[PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[Huacai Chen]

CP0.Config6 is a Vendor-defined register whose bits definitions are
different from one to another. Recently, Xuerui's Loongson-3 patch and
Serge's P5600 patch make the definitions inconsistency and unclear.

To make life easy, this patch tidy the definition up:
1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
3, Add bit6/bit7 definition for Loongson-3 which will be used later.

All existing users of these macros are updated.

Cc: WANG Xuerui <git@xen0n.name>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/mipsregs.h | 37 ++++++++++++++++++++++++-------------
 arch/mips/kernel/cpu-probe.c     | 12 ++++++------
 arch/mips/mm/c-r4k.c             |  4 ++--
 3 files changed, 32 insertions(+), 21 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fe6293f..796dbb8 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -686,27 +686,38 @@
 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
 #define MIPS_CONF5_K		(_ULCAST_(1) << 30)
 
+/* Config6 feature bits for proAptiv/P5600 */
+
 /* Jump register cache prediction disable */
-#define MIPS_CONF6_JRCD		(_ULCAST_(1) << 0)
+#define MIPS_CONF6_MTI_JRCD		(_ULCAST_(1) << 0)
 /* MIPSr6 extensions enable */
-#define MIPS_CONF6_R6		(_ULCAST_(1) << 2)
+#define MIPS_CONF6_MTI_R6		(_ULCAST_(1) << 2)
 /* IFU Performance Control */
-#define MIPS_CONF6_IFUPERFCTL	(_ULCAST_(3) << 10)
-#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
+#define MIPS_CONF6_MTI_IFUPERFCTL	(_ULCAST_(3) << 10)
+#define MIPS_CONF6_MTI_SYND		(_ULCAST_(1) << 13)
 /* Sleep state performance counter disable */
-#define MIPS_CONF6_SPCD		(_ULCAST_(1) << 14)
+#define MIPS_CONF6_MTI_SPCD		(_ULCAST_(1) << 14)
 /* proAptiv FTLB on/off bit */
-#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
+#define MIPS_CONF6_MTI_FTLBEN		(_ULCAST_(1) << 15)
 /* Disable load/store bonding */
-#define MIPS_CONF6_DLSB		(_ULCAST_(1) << 21)
-/* Loongson-3 FTLB on/off bit */
-#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
+#define MIPS_CONF6_MTI_DLSB		(_ULCAST_(1) << 21)
 /* FTLB probability bits */
-#define MIPS_CONF6_FTLBP_SHIFT	(16)
-/* Loongson-3 feature bits */
-#define MIPS_CONF6_LOONGSON_SCRAND	(_ULCAST_(1) << 17)
+#define MIPS_CONF6_MTI_FTLBP_SHIFT	(16)
+
+/* Config6 feature bits for Loongson-3 */
+
+/* Loongson-3 internal timer bit */
+#define MIPS_CONF6_LOONGSON_INTIMER	(_ULCAST_(1) << 6)
+/* Loongson-3 external timer bit */
+#define MIPS_CONF6_LOONGSON_EXTIMER	(_ULCAST_(1) << 7)
+/* Loongson-3 SFB on/off bit, STFill in manual */
+#define MIPS_CONF6_LOONGSON_SFBEN	(_ULCAST_(1) << 8)
+/* Loongson-3's LL on exclusive cacheline */
 #define MIPS_CONF6_LOONGSON_LLEXC	(_ULCAST_(1) << 16)
-#define MIPS_CONF6_LOONGSON_STFILL	(_ULCAST_(1) << 8)
+/* Loongson-3's SC has a random delay */
+#define MIPS_CONF6_LOONGSON_SCRAND	(_ULCAST_(1) << 17)
+/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
+#define MIPS_CONF6_LOONGSON_FTLBDIS	(_ULCAST_(1) << 22)
 
 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b8ec357..f7c4b1d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -633,14 +633,14 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 		config = read_c0_config6();
 
 		if (flags & FTLB_EN)
-			config |= MIPS_CONF6_FTLBEN;
+			config |= MIPS_CONF6_MTI_FTLBEN;
 		else
-			config &= ~MIPS_CONF6_FTLBEN;
+			config &= ~MIPS_CONF6_MTI_FTLBEN;
 
 		if (flags & FTLB_SET_PROB) {
-			config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
+			config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT);
 			config |= calculate_ftlb_probability(c)
-				  << MIPS_CONF6_FTLBP_SHIFT;
+				  << MIPS_CONF6_MTI_FTLBP_SHIFT;
 		}
 
 		write_c0_config6(config);
@@ -660,10 +660,10 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 		config = read_c0_config6();
 		if (flags & FTLB_EN)
 			/* Enable FTLB */
-			write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
+			write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS);
 		else
 			/* Disable FTLB */
-			write_c0_config6(config | MIPS_CONF6_FTLBDIS);
+			write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS);
 		break;
 	default:
 		return 1;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a9f55bf..6fb83ac 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1073,12 +1073,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c)
 		if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
 			present = 1;
 		if (rev == PRID_REV_ENCODE_332(2, 4, 0))
-			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
 		break;
 	case PRID_IMP_1074K:
 		if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
 			present = 1;
-			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
 		}
 		break;
 	default:
-- 
2.7.0

Re: [PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[Thomas Bogendoerfer]

On Sat, May 23, 2020 at 03:51:45PM +0800, Huacai Chen wrote:
> CP0.Config6 is a Vendor-defined register whose bits definitions are
> different from one to another. Recently, Xuerui's Loongson-3 patch and
> Serge's P5600 patch make the definitions inconsistency and unclear.
> 
> To make life easy, this patch tidy the definition up:
> 1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
> 2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
> 3, Add bit6/bit7 definition for Loongson-3 which will be used later.
> 
> All existing users of these macros are updated.
> 
> Cc: WANG Xuerui <git@xen0n.name>
> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
>  arch/mips/include/asm/mipsregs.h | 37 ++++++++++++++++++++++++-------------
>  arch/mips/kernel/cpu-probe.c     | 12 ++++++------
>  arch/mips/mm/c-r4k.c             |  4 ++--
>  3 files changed, 32 insertions(+), 21 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[Maciej W. Rozycki]

On Sat, 23 May 2020, Huacai Chen wrote:

> CP0.Config6 is a Vendor-defined register whose bits definitions are
> different from one to another. Recently, Xuerui's Loongson-3 patch and
> Serge's P5600 patch make the definitions inconsistency and unclear.
> 
> To make life easy, this patch tidy the definition up:
> 1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
> 2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
> 3, Add bit6/bit7 definition for Loongson-3 which will be used later.

 What a mess!  We use *prefixes* for vendor- or processor-specific names, 
e.g.:

#define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
#define R4K_CONF_SW		(_ULCAST_(1) << 20)
#define MTI_CONF7_PTC		(_ULCAST_(1) << 19)

etc. and MIPS_ denotes a MIPS architectural (as in R1, R2, etc., i.e. not 
legacy) definition, e.g.:

#define MIPS_CONF_VI		(_ULCAST_(1) <<  3)

 So to be consistent these would have to be:

> +/* Config6 feature bits for proAptiv/P5600 */
> +
>  /* Jump register cache prediction disable */
> -#define MIPS_CONF6_JRCD		(_ULCAST_(1) << 0)
> +#define MIPS_CONF6_MTI_JRCD		(_ULCAST_(1) << 0)

#define MTI_CONF6_JRCD		(_ULCAST_(1) << 0)

etc.

> +/* Config6 feature bits for Loongson-3 */
> +
> +/* Loongson-3 internal timer bit */
> +#define MIPS_CONF6_LOONGSON_INTIMER	(_ULCAST_(1) << 6)

#define LOONGSON_CONF6_INTIMER	(_ULCAST_(1) << 6)

etc.

  Maciej

Re: [PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[Huacai Chen]

OK, let me fix it.

Huacai

On Mon, Jun 1, 2020 at 10:13 AM Maciej W. Rozycki <macro@wdc.com> wrote:
>
> On Sat, 23 May 2020, Huacai Chen wrote:
>
> > CP0.Config6 is a Vendor-defined register whose bits definitions are
> > different from one to another. Recently, Xuerui's Loongson-3 patch and
> > Serge's P5600 patch make the definitions inconsistency and unclear.
> >
> > To make life easy, this patch tidy the definition up:
> > 1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
> > 2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
> > 3, Add bit6/bit7 definition for Loongson-3 which will be used later.
>
>  What a mess!  We use *prefixes* for vendor- or processor-specific names,
> e.g.:
>
> #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
> #define R4K_CONF_SW             (_ULCAST_(1) << 20)
> #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
>
> etc. and MIPS_ denotes a MIPS architectural (as in R1, R2, etc., i.e. not
> legacy) definition, e.g.:
>
> #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
>
>  So to be consistent these would have to be:
>
> > +/* Config6 feature bits for proAptiv/P5600 */
> > +
> >  /* Jump register cache prediction disable */
> > -#define MIPS_CONF6_JRCD              (_ULCAST_(1) << 0)
> > +#define MIPS_CONF6_MTI_JRCD          (_ULCAST_(1) << 0)
>
> #define MTI_CONF6_JRCD          (_ULCAST_(1) << 0)
>
> etc.
>
> > +/* Config6 feature bits for Loongson-3 */
> > +
> > +/* Loongson-3 internal timer bit */
> > +#define MIPS_CONF6_LOONGSON_INTIMER  (_ULCAST_(1) << 6)
>
> #define LOONGSON_CONF6_INTIMER  (_ULCAST_(1) << 6)
>
> etc.
>
>   Maciej