* [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-15 18:22 ` Martin Blumenstingl
0 siblings, 0 replies; 10+ messages in thread
From: Martin Blumenstingl @ 2020-08-15 18:22 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index eadb0832bcfc..7649dd1e0b9e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,13 +11,6 @@ / {
#size-cells = <1>;
interrupt-parent = <&gic>;
- L2: cache-controller@c4200000 {
- compatible = "arm,pl310-cache";
- reg = <0xc4200000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
};
};
+ L2: cache-controller@c4200000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xc4200000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
periph: bus@c4300000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;
--
2.28.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-15 18:22 ` Martin Blumenstingl
0 siblings, 0 replies; 10+ messages in thread
From: Martin Blumenstingl @ 2020-08-15 18:22 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index eadb0832bcfc..7649dd1e0b9e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,13 +11,6 @@ / {
#size-cells = <1>;
interrupt-parent = <&gic>;
- L2: cache-controller@c4200000 {
- compatible = "arm,pl310-cache";
- reg = <0xc4200000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
};
};
+ L2: cache-controller@c4200000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xc4200000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
periph: bus@c4300000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;
--
2.28.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
2020-08-15 18:22 ` Martin Blumenstingl
(?)
(?)
@ 2020-08-24 8:05 ` Neil Armstrong
-1 siblings, 0 replies; 10+ messages in thread
From: Neil Armstrong @ 2020-08-24 8:05 UTC (permalink / raw)
To: linux-amlogic
On 15/08/2020 20:22, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index eadb0832bcfc..7649dd1e0b9e 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -11,13 +11,6 @@ / {
> #size-cells = <1>;
> interrupt-parent = <&gic>;
>
> - L2: cache-controller@c4200000 {
> - compatible = "arm,pl310-cache";
> - reg = <0xc4200000 0x1000>;
> - cache-unified;
> - cache-level = <2>;
> - };
> -
> soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
> };
> };
>
> + L2: cache-controller@c4200000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xc4200000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> periph: bus@c4300000 {
> compatible = "simple-bus";
> reg = <0xc4300000 0x10000>;
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
2020-08-15 18:22 ` Martin Blumenstingl
(?)
@ 2020-08-24 21:15 ` Kevin Hilman
-1 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:15 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Boot tested on meson8b-odroidc1
Tested-by: Kevin Hilman <khilman@baylibre.com>
Queuing for v5.10.
Thanks,
Kevin
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-24 21:15 ` Kevin Hilman
0 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:15 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Boot tested on meson8b-odroidc1
Tested-by: Kevin Hilman <khilman@baylibre.com>
Queuing for v5.10.
Thanks,
Kevin
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-24 21:15 ` Kevin Hilman
0 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:15 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Boot tested on meson8b-odroidc1
Tested-by: Kevin Hilman <khilman@baylibre.com>
Queuing for v5.10.
Thanks,
Kevin
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
2020-08-15 18:22 ` Martin Blumenstingl
(?)
@ 2020-08-24 21:16 ` Kevin Hilman
-1 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:16 UTC (permalink / raw)
To: linux-amlogic, Martin Blumenstingl; +Cc: linux-arm-kernel, linux-kernel
On Sat, 15 Aug 2020 20:22:23 +0200, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
Applied, thanks!
[1/1] ARM: dts: meson: move the L2 cache-controller inside the SoC node
commit: 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-24 21:16 ` Kevin Hilman
0 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:16 UTC (permalink / raw)
To: linux-amlogic, Martin Blumenstingl; +Cc: linux-kernel, linux-arm-kernel
On Sat, 15 Aug 2020 20:22:23 +0200, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
Applied, thanks!
[1/1] ARM: dts: meson: move the L2 cache-controller inside the SoC node
commit: 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
@ 2020-08-24 21:16 ` Kevin Hilman
0 siblings, 0 replies; 10+ messages in thread
From: Kevin Hilman @ 2020-08-24 21:16 UTC (permalink / raw)
To: linux-amlogic, Martin Blumenstingl; +Cc: linux-kernel, linux-arm-kernel
On Sat, 15 Aug 2020 20:22:23 +0200, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
Applied, thanks!
[1/1] ARM: dts: meson: move the L2 cache-controller inside the SoC node
commit: 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 10+ messages in thread