* [PATCH v2 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 @ 2020-07-23 0:36 ` Khaled Almahallawy 0 siblings, 0 replies; 20+ messages in thread From: Khaled Almahallawy @ 2020-07-23 0:36 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: manasi.d.navare, animesh.manna, Khaled Almahallawy Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..fbf83f207b15 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 @ 2020-07-23 0:36 ` Khaled Almahallawy 0 siblings, 0 replies; 20+ messages in thread From: Khaled Almahallawy @ 2020-07-23 0:36 UTC (permalink / raw) To: intel-gfx, dri-devel Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..fbf83f207b15 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy @ 2020-07-23 0:36 ` Khaled Almahallawy -1 siblings, 0 replies; 20+ messages in thread From: Khaled Almahallawy @ 2020-07-23 0:36 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: manasi.d.navare, animesh.manna, Khaled Almahallawy Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: uniform bit names TP4a/b/c (Manasi) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d6295eb20b63..4b74b2ec5665 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 pattern_val; + u32 pattern_val, dp_tp_ctl; switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_PHY_TEST_PATTERN_CP2520_PAT3: + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a0d31f3bf634..c586595b9e76 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9982,6 +9982,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support @ 2020-07-23 0:36 ` Khaled Almahallawy 0 siblings, 0 replies; 20+ messages in thread From: Khaled Almahallawy @ 2020-07-23 0:36 UTC (permalink / raw) To: intel-gfx, dri-devel Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: uniform bit names TP4a/b/c (Manasi) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d6295eb20b63..4b74b2ec5665 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 pattern_val; + u32 pattern_val, dp_tp_ctl; switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_PHY_TEST_PATTERN_CP2520_PAT3: + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a0d31f3bf634..c586595b9e76 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9982,6 +9982,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy @ 2020-08-18 21:29 ` Navare, Manasi -1 siblings, 0 replies; 20+ messages in thread From: Navare, Manasi @ 2020-08-18 21:29 UTC (permalink / raw) To: Khaled Almahallawy; +Cc: intel-gfx, animesh.manna, dri-devel On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. > > v2: uniform bit names TP4a/b/c (Manasi) > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Looks good to me, Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Khaled, could you also give a tested by here? Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index d6295eb20b63..4b74b2ec5665 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > &intel_dp->compliance.test_data.phytest; > struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > - u32 pattern_val; > + u32 pattern_val, dp_tp_ctl; > > switch (data->phy_pattern) { > case DP_PHY_TEST_PATTERN_NONE: > @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > DDI_DP_COMP_CTL_ENABLE | > DDI_DP_COMP_CTL_CUSTOM80); > break; > - case DP_PHY_TEST_PATTERN_CP2520: > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > /* > * FIXME: Ideally pattern should come from DPCD 0x24A. As > * current firmware of DPR-100 could not set it, so hardcoding > @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | > pattern_val); > break; > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); > + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); > + break; > default: > WARN(1, "Invalid Phy Test Pattern\n"); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a0d31f3bf634..c586595b9e76 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > #define DP_TP_CTL_MODE_SST (0 << 27) > #define DP_TP_CTL_MODE_MST (1 << 27) > #define DP_TP_CTL_FORCE_ACT (1 << 25) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > -- > 2.17.1 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support @ 2020-08-18 21:29 ` Navare, Manasi 0 siblings, 0 replies; 20+ messages in thread From: Navare, Manasi @ 2020-08-18 21:29 UTC (permalink / raw) To: Khaled Almahallawy; +Cc: intel-gfx, dri-devel On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. > > v2: uniform bit names TP4a/b/c (Manasi) > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Looks good to me, Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Khaled, could you also give a tested by here? Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index d6295eb20b63..4b74b2ec5665 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > &intel_dp->compliance.test_data.phytest; > struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > - u32 pattern_val; > + u32 pattern_val, dp_tp_ctl; > > switch (data->phy_pattern) { > case DP_PHY_TEST_PATTERN_NONE: > @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > DDI_DP_COMP_CTL_ENABLE | > DDI_DP_COMP_CTL_CUSTOM80); > break; > - case DP_PHY_TEST_PATTERN_CP2520: > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > /* > * FIXME: Ideally pattern should come from DPCD 0x24A. As > * current firmware of DPR-100 could not set it, so hardcoding > @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | > pattern_val); > break; > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); > + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); > + break; > default: > WARN(1, "Invalid Phy Test Pattern\n"); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a0d31f3bf634..c586595b9e76 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > #define DP_TP_CTL_MODE_SST (0 << 27) > #define DP_TP_CTL_MODE_MST (1 << 27) > #define DP_TP_CTL_FORCE_ACT (1 << 25) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support 2020-08-18 21:29 ` [Intel-gfx] " Navare, Manasi @ 2020-08-19 1:47 ` Almahallawy, Khaled -1 siblings, 0 replies; 20+ messages in thread From: Almahallawy, Khaled @ 2020-08-19 1:47 UTC (permalink / raw) To: Navare, Manasi D; +Cc: intel-gfx, Manna, Animesh, dri-devel On Tue, 2020-08-18 at 14:29 -0700, Navare, Manasi wrote: > On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source > > tests. > > > > v2: uniform bit names TP4a/b/c (Manasi) > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > > Looks good to me, > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Khaled, could you also give a tested by here? > > Manasi Passed all TPS4 tests on DP Compliance scope with DPoC1.4a test specification Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > 2 files changed, 16 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index d6295eb20b63..4b74b2ec5665 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5371,7 +5371,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > &intel_dp->compliance.test_data.phytest; > > struct intel_crtc *crtc = to_intel_crtc(dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 pattern_val; > > + u32 pattern_val, dp_tp_ctl; > > > > switch (data->phy_pattern) { > > case DP_PHY_TEST_PATTERN_NONE: > > @@ -5411,7 +5411,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_CUSTOM80); > > break; > > - case DP_PHY_TEST_PATTERN_CP2520: > > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > > /* > > * FIXME: Ideally pattern should come from DPCD 0x24A. > > As > > * current firmware of DPR-100 could not set it, so > > hardcoding > > @@ -5423,6 +5423,16 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_HBR2 | > > pattern_val); > > break; > > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > > 0x0); > > + dp_tp_ctl = intel_de_read(dev_priv, > > TGL_DP_TP_CTL(pipe)); > > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), > > dp_tp_ctl); > > + break; > > default: > > WARN(1, "Invalid Phy Test Pattern\n"); > > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index a0d31f3bf634..c586595b9e76 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > > #define DP_TP_CTL_MODE_SST (0 << 27) > > #define DP_TP_CTL_MODE_MST (1 << 27) > > #define DP_TP_CTL_FORCE_ACT (1 << 25) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > > -- > > 2.17.1 > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support @ 2020-08-19 1:47 ` Almahallawy, Khaled 0 siblings, 0 replies; 20+ messages in thread From: Almahallawy, Khaled @ 2020-08-19 1:47 UTC (permalink / raw) To: Navare, Manasi D; +Cc: intel-gfx, dri-devel On Tue, 2020-08-18 at 14:29 -0700, Navare, Manasi wrote: > On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source > > tests. > > > > v2: uniform bit names TP4a/b/c (Manasi) > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > > Looks good to me, > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Khaled, could you also give a tested by here? > > Manasi Passed all TPS4 tests on DP Compliance scope with DPoC1.4a test specification Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > 2 files changed, 16 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index d6295eb20b63..4b74b2ec5665 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5371,7 +5371,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > &intel_dp->compliance.test_data.phytest; > > struct intel_crtc *crtc = to_intel_crtc(dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 pattern_val; > > + u32 pattern_val, dp_tp_ctl; > > > > switch (data->phy_pattern) { > > case DP_PHY_TEST_PATTERN_NONE: > > @@ -5411,7 +5411,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_CUSTOM80); > > break; > > - case DP_PHY_TEST_PATTERN_CP2520: > > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > > /* > > * FIXME: Ideally pattern should come from DPCD 0x24A. > > As > > * current firmware of DPR-100 could not set it, so > > hardcoding > > @@ -5423,6 +5423,16 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_HBR2 | > > pattern_val); > > break; > > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > > 0x0); > > + dp_tp_ctl = intel_de_read(dev_priv, > > TGL_DP_TP_CTL(pipe)); > > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), > > dp_tp_ctl); > > + break; > > default: > > WARN(1, "Invalid Phy Test Pattern\n"); > > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index a0d31f3bf634..c586595b9e76 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > > #define DP_TP_CTL_MODE_SST (0 << 27) > > #define DP_TP_CTL_MODE_MST (1 << 27) > > #define DP_TP_CTL_FORCE_ACT (1 << 25) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > > -- > > 2.17.1 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy (?) (?) @ 2020-07-23 0:46 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2020-07-23 0:46 UTC (permalink / raw) To: Khaled Almahallawy; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 URL : https://patchwork.freedesktop.org/series/79779/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy ` (2 preceding siblings ...) (?) @ 2020-07-23 1:06 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2020-07-23 1:06 UTC (permalink / raw) To: Khaled Almahallawy; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6429 bytes --] == Series Details == Series: series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 URL : https://patchwork.freedesktop.org/series/79779/ State : success == Summary == CI Bug Log - changes from CI_DRM_8776 -> Patchwork_18227 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/index.html Known issues ------------ Here are the changes found in Patchwork_18227 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html * igt@gem_flink_basic@flink-lifetime: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html * igt@i915_pm_rpm@module-reload: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html * igt@i915_module_load@reload: - fi-apl-guc: [DMESG-WARN][9] ([i915#1635] / [i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-apl-guc/igt@i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-apl-guc/igt@i915_module_load@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@kms_busy@basic@flip: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-y/igt@kms_busy@basic@flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-y/igt@kms_busy@basic@flip.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html * igt@vgem_basic@setversion: - fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-y/igt@vgem_basic@setversion.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-y/igt@vgem_basic@setversion.html #### Warnings #### * igt@i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][19] ([i915#1982]) -> [DMESG-WARN][20] ([i915#402]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-tgl-u2/igt@i915_module_load@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-tgl-u2/igt@i915_module_load@reload.html * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 40) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8776 -> Patchwork_18227 CI-20190529: 20190529 CI_DRM_8776: 74b7f6c16ef8b25eeced90397c82376071d3a12a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5744: 89ef04d90cf2b96c72820c1927034cf716ea37f7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18227: 7fc758af76ae1d7866b036555852c7e16e562ff5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7fc758af76ae drm/i915/dp: TPS4 PHY test pattern compliance support c8b06244cf84 drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/index.html [-- Attachment #1.2: Type: text/html, Size: 8327 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy ` (3 preceding siblings ...) (?) @ 2020-07-23 2:44 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2020-07-23 2:44 UTC (permalink / raw) To: Khaled Almahallawy; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 14228 bytes --] == Series Details == Series: series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 URL : https://patchwork.freedesktop.org/series/79779/ State : success == Summary == CI Bug Log - changes from CI_DRM_8776_full -> Patchwork_18227_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18227_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_create@madvise: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-glk5/igt@gem_exec_create@madvise.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-glk9/igt@gem_exec_create@madvise.html * igt@kms_big_fb@x-tiled-8bpp-rotate-180: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-apl1/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-apl2/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#129]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl10/igt@kms_color@pipe-c-ctm-green-to-red.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl3/igt@kms_color@pipe-c-ctm-green-to-red.html * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl6/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl3/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#57]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][11] -> [FAIL][12] ([IGT#5]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-hsw6/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-vga1: - shard-snb: [PASS][17] -> [DMESG-WARN][18] ([i915#42]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +16 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl10/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl8/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html * igt@perf_pmu@semaphore-busy@rcs0: - shard-kbl: [PASS][27] -> [FAIL][28] ([i915#1820]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl4/igt@perf_pmu@semaphore-busy@rcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html #### Possible fixes #### * igt@gem_ctx_engines@idempotent: - shard-skl: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30] +7 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl6/igt@gem_ctx_engines@idempotent.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl4/igt@gem_ctx_engines@idempotent.html * igt@gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][31] ([i915#1930]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-glk6/igt@gem_exec_reloc@basic-concurrent0.html * igt@gem_exec_whisper@basic-queues: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-glk3/igt@gem_exec_whisper@basic-queues.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-glk3/igt@gem_exec_whisper@basic-queues.html * igt@gem_workarounds@suspend-resume: - shard-skl: [INCOMPLETE][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl10/igt@gem_workarounds@suspend-resume.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl8/igt@gem_workarounds@suspend-resume.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][37] ([i915#454]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-iclb8/igt@i915_pm_dc@dc6-psr.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-iclb8/igt@i915_pm_dc@dc6-psr.html * igt@kms_addfb_basic@bad-pitch-0: - shard-tglb: [DMESG-WARN][39] ([i915#402]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-tglb6/igt@kms_addfb_basic@bad-pitch-0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-tglb2/igt@kms_addfb_basic@bad-pitch-0.html * igt@kms_flip@plain-flip-fb-recreate@a-edp1: - shard-skl: [DMESG-FAIL][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-kbl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl6/igt@kms_flip_tiling@flip-changes-tiling-yf.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl3/igt@kms_flip_tiling@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack: - shard-tglb: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html * igt@kms_hdr@bpc-switch: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl9/igt@kms_hdr@bpc-switch.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl9/igt@kms_hdr@bpc-switch.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html #### Warnings #### * igt@gem_exec_reloc@basic-concurrent16: - shard-glk: [TIMEOUT][55] ([i915#1958] / [i915#2119]) -> [INCOMPLETE][56] ([i915#1958]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-glk8/igt@gem_exec_reloc@basic-concurrent16.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-glk4/igt@gem_exec_reloc@basic-concurrent16.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][57] ([i915#1515]) -> [FAIL][58] ([i915#1515]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_content_protection@srm: - shard-kbl: [TIMEOUT][59] ([i915#1319] / [i915#1958] / [i915#2119]) -> [TIMEOUT][60] ([i915#1319] / [i915#2119]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-kbl6/igt@kms_content_protection@srm.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-kbl1/igt@kms_content_protection@srm.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [FAIL][62] ([fdo#108145] / [i915#265]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8776/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#129]: https://gitlab.freedesktop.org/drm/intel/issues/129 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8776 -> Patchwork_18227 CI-20190529: 20190529 CI_DRM_8776: 74b7f6c16ef8b25eeced90397c82376071d3a12a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5744: 89ef04d90cf2b96c72820c1927034cf716ea37f7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18227: 7fc758af76ae1d7866b036555852c7e16e562ff5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18227/index.html [-- Attachment #1.2: Type: text/html, Size: 16994 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy @ 2020-09-04 4:25 ` Vidya Srinivas -1 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Khaled Almahallawy From: Khaled Almahallawy <khaled.almahallawy@intel.com> Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 @ 2020-09-04 4:25 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel From: Khaled Almahallawy <khaled.almahallawy@intel.com> Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support 2020-09-04 4:25 ` [Intel-gfx] " Vidya Srinivas @ 2020-09-04 4:25 ` Vidya Srinivas -1 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Khaled Almahallawy From: Khaled Almahallawy <khaled.almahallawy@intel.com> Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: uniform bit names TP4a/b/c (Manasi) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 04231ca5643b..a8a3ffcef5dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 pattern_val; + u32 pattern_val, dp_tp_ctl; switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: @@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding @@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_PHY_TEST_PATTERN_CP2520_PAT3: + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab4b1abd4364..4850890918dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9974,6 +9974,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support @ 2020-09-04 4:25 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel From: Khaled Almahallawy <khaled.almahallawy@intel.com> Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: uniform bit names TP4a/b/c (Manasi) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 04231ca5643b..a8a3ffcef5dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 pattern_val; + u32 pattern_val, dp_tp_ctl; switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: @@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding @@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_PHY_TEST_PATTERN_CP2520_PAT3: + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab4b1abd4364..4850890918dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9974,6 +9974,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL 2020-09-04 4:25 ` [Intel-gfx] " Vidya Srinivas @ 2020-09-04 4:25 ` Vidya Srinivas -1 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Vidya Srinivas, Khaled Almahallawy Please Note: Comment from Ville could not be addressed as his comments are with respect to base implementation (design) which are already merged. We need JSL changes for compliance. Hence pushing the required changes on top of existing design. Apoligies for that. v2: Rebased patch on top of Khaled's (yet to be merged): https://patchwork.freedesktop.org/series/79779/ Fixed phy patterns for JSL/EHL Add TPS4 support for JSL/EHL Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++-- 2 files changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a8a3ffcef5dc..1773f3d5d0f4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) enum pipe pipe = crtc->pipe; u32 pattern_val, dp_tp_ctl; + i915_reg_t dp_comp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) + dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port); + else if (IS_TIGERLAKE(dev_priv)) + dp_comp_reg = DDI_DP_COMP_CTL(pipe); + switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_write(dev_priv, dp_comp_reg, 0x0); break; case DP_PHY_TEST_PATTERN_D10_2: DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; case DP_PHY_TEST_PATTERN_PRBS7: DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: @@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) * current firmware of DPR-100 could not set it, so hardcoding * now for complaince test. */ - DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \ + 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); pattern_val = 0x3e0f83e0; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); pattern_val = 0x0f83e0f8; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); pattern_val = 0x0000f83e; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; @@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) */ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); pattern_val = 0xFB; - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; @@ -5478,22 +5498,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_port_mask; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(dig_port->base.port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5505,20 +5535,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5565,6 +5604,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5590,6 +5630,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4850890918dc..7d3b6779661f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10026,10 +10026,16 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* EHL/JSL DP compliance control */ +#define _EHL_DDI_DP_COMP_CTL_A 0x640F0 +#define _EHL_DDI_DP_COMP_CTL_B 0x641F0 +#define EHL_DDI_DP_COMP_CTL(port) \ + _MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B) + /* DDI DP Compliance Control */ -#define _DDI_DP_COMP_CTL_A 0x605F0 -#define _DDI_DP_COMP_CTL_B 0x615F0 -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) #define DDI_DP_COMP_CTL_ENABLE (1 << 31) #define DDI_DP_COMP_CTL_D10_2 (0 << 28) #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) @@ -10039,6 +10045,12 @@ enum skl_power_gate { #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) +/* EHL */ +#define _EHL_DDI_DP_COMP_PAT_A 0x640F4 +#define _EHL_DDI_DP_COMP_PAT_B 0x641F4 +#define EHL_DDI_DP_COMP_PAT(port, i) \ + _MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4) + /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A 0x605F4 #define _DDI_DP_COMP_PAT_B 0x615F4 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL @ 2020-09-04 4:25 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:25 UTC (permalink / raw) To: intel-gfx, dri-devel Please Note: Comment from Ville could not be addressed as his comments are with respect to base implementation (design) which are already merged. We need JSL changes for compliance. Hence pushing the required changes on top of existing design. Apoligies for that. v2: Rebased patch on top of Khaled's (yet to be merged): https://patchwork.freedesktop.org/series/79779/ Fixed phy patterns for JSL/EHL Add TPS4 support for JSL/EHL Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++-- 2 files changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a8a3ffcef5dc..1773f3d5d0f4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) enum pipe pipe = crtc->pipe; u32 pattern_val, dp_tp_ctl; + i915_reg_t dp_comp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) + dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port); + else if (IS_TIGERLAKE(dev_priv)) + dp_comp_reg = DDI_DP_COMP_CTL(pipe); + switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_write(dev_priv, dp_comp_reg, 0x0); break; case DP_PHY_TEST_PATTERN_D10_2: DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; case DP_PHY_TEST_PATTERN_PRBS7: DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: @@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) * current firmware of DPR-100 could not set it, so hardcoding * now for complaince test. */ - DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \ + 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); pattern_val = 0x3e0f83e0; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); pattern_val = 0x0f83e0f8; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); pattern_val = 0x0000f83e; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; @@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) */ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); pattern_val = 0xFB; - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; @@ -5478,22 +5498,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_port_mask; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(dig_port->base.port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5505,20 +5535,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5565,6 +5604,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5590,6 +5630,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4850890918dc..7d3b6779661f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10026,10 +10026,16 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* EHL/JSL DP compliance control */ +#define _EHL_DDI_DP_COMP_CTL_A 0x640F0 +#define _EHL_DDI_DP_COMP_CTL_B 0x641F0 +#define EHL_DDI_DP_COMP_CTL(port) \ + _MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B) + /* DDI DP Compliance Control */ -#define _DDI_DP_COMP_CTL_A 0x605F0 -#define _DDI_DP_COMP_CTL_B 0x615F0 -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) #define DDI_DP_COMP_CTL_ENABLE (1 << 31) #define DDI_DP_COMP_CTL_D10_2 (0 << 28) #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) @@ -10039,6 +10045,12 @@ enum skl_power_gate { #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) +/* EHL */ +#define _EHL_DDI_DP_COMP_PAT_A 0x640F4 +#define _EHL_DDI_DP_COMP_PAT_B 0x641F4 +#define EHL_DDI_DP_COMP_PAT(port, i) \ + _MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4) + /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A 0x605F4 #define _DDI_DP_COMP_PAT_B 0x615F4 -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 @ 2020-09-04 4:21 Vidya Srinivas 2020-09-04 4:21 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 0 siblings, 1 reply; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:21 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Khaled Almahallawy From: Khaled Almahallawy <khaled.almahallawy@intel.com> Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL 2020-09-04 4:21 [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas @ 2020-09-04 4:21 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:21 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Vidya Srinivas, Khaled Almahallawy Please Note: Comment from Ville could not be addressed as his comments are with respect to base implementation (design) which are already merged. We need JSL changes for compliance. Hence pushing the required changes on top of existing design. Apoligies for that. v2: Rebased patch on top of Khaled's (yet to be merged): https://patchwork.freedesktop.org/series/79779/ Fixed phy patterns for JSL/EHL Add TPS4 support for JSL/EHL Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++-- 2 files changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a8a3ffcef5dc..1773f3d5d0f4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) enum pipe pipe = crtc->pipe; u32 pattern_val, dp_tp_ctl; + i915_reg_t dp_comp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) + dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port); + else if (IS_TIGERLAKE(dev_priv)) + dp_comp_reg = DDI_DP_COMP_CTL(pipe); + switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_write(dev_priv, dp_comp_reg, 0x0); break; case DP_PHY_TEST_PATTERN_D10_2: DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; case DP_PHY_TEST_PATTERN_PRBS7: DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: @@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) * current firmware of DPR-100 could not set it, so hardcoding * now for complaince test. */ - DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \ + 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); pattern_val = 0x3e0f83e0; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); pattern_val = 0x0f83e0f8; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); pattern_val = 0x0000f83e; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; @@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) */ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); pattern_val = 0xFB; - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; @@ -5478,22 +5498,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_port_mask; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(dig_port->base.port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5505,20 +5535,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5565,6 +5604,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5590,6 +5630,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4850890918dc..7d3b6779661f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10026,10 +10026,16 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* EHL/JSL DP compliance control */ +#define _EHL_DDI_DP_COMP_CTL_A 0x640F0 +#define _EHL_DDI_DP_COMP_CTL_B 0x641F0 +#define EHL_DDI_DP_COMP_CTL(port) \ + _MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B) + /* DDI DP Compliance Control */ -#define _DDI_DP_COMP_CTL_A 0x605F0 -#define _DDI_DP_COMP_CTL_B 0x615F0 -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) #define DDI_DP_COMP_CTL_ENABLE (1 << 31) #define DDI_DP_COMP_CTL_D10_2 (0 << 28) #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) @@ -10039,6 +10045,12 @@ enum skl_power_gate { #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) +/* EHL */ +#define _EHL_DDI_DP_COMP_PAT_A 0x640F4 +#define _EHL_DDI_DP_COMP_PAT_B 0x641F4 +#define EHL_DDI_DP_COMP_PAT(port, i) \ + _MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4) + /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A 0x605F4 #define _DDI_DP_COMP_PAT_B 0x615F4 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH] drm/i915/dp: DP PHY compliance for JSL @ 2020-06-04 5:03 Vidya Srinivas 2020-09-04 4:13 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 2020-09-04 4:14 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 0 siblings, 2 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-06-04 5:03 UTC (permalink / raw) To: intel-gfx, dri-devel Cc: Vidya Srinivas, animesh.manna, manasi.d.navare, uma.shankar, shawn.c.lee, Khaled Almahallawy Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 40 ++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7223367171d1..44663e8ac9a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_port_mask; + enum port port = intel_dig_port->base.port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = intel_dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5557,6 +5575,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5582,6 +5601,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) || !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-06-04 5:03 [PATCH] drm/i915/dp: DP PHY compliance for JSL Vidya Srinivas @ 2020-09-04 4:13 ` Vidya Srinivas 2020-09-04 4:13 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 2020-09-04 4:14 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 1 sibling, 1 reply; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:13 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Khaled Almahallawy From: Khaled Almahallawy <khaled.almahallawy@intel.com> Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL 2020-09-04 4:13 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas @ 2020-09-04 4:13 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:13 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Vidya Srinivas, Khaled Almahallawy Please Note: Comment from Ville could not be addressed as his comments are with respect to base implementation (design) which are already merged. We need JSL changes for compliance. Hence pushing the required changes on top of existing design. Apoligies for that. v2: Rebased patch on top of Khaled's (yet to be merged): https://patchwork.freedesktop.org/series/79779/ Fixed phy patterns for JSL/EHL Add TPS4 support for JSL/EHL Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++-- 2 files changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a8a3ffcef5dc..1773f3d5d0f4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) enum pipe pipe = crtc->pipe; u32 pattern_val, dp_tp_ctl; + i915_reg_t dp_comp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) + dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port); + else if (IS_TIGERLAKE(dev_priv)) + dp_comp_reg = DDI_DP_COMP_CTL(pipe); + switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_write(dev_priv, dp_comp_reg, 0x0); break; case DP_PHY_TEST_PATTERN_D10_2: DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; case DP_PHY_TEST_PATTERN_PRBS7: DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: @@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) * current firmware of DPR-100 could not set it, so hardcoding * now for complaince test. */ - DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \ + 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); pattern_val = 0x3e0f83e0; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); pattern_val = 0x0f83e0f8; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); pattern_val = 0x0000f83e; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; @@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) */ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); pattern_val = 0xFB; - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; @@ -5478,22 +5498,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_port_mask; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(dig_port->base.port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5505,20 +5535,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5565,6 +5604,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5590,6 +5630,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4850890918dc..7d3b6779661f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10026,10 +10026,16 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* EHL/JSL DP compliance control */ +#define _EHL_DDI_DP_COMP_CTL_A 0x640F0 +#define _EHL_DDI_DP_COMP_CTL_B 0x641F0 +#define EHL_DDI_DP_COMP_CTL(port) \ + _MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B) + /* DDI DP Compliance Control */ -#define _DDI_DP_COMP_CTL_A 0x605F0 -#define _DDI_DP_COMP_CTL_B 0x615F0 -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) #define DDI_DP_COMP_CTL_ENABLE (1 << 31) #define DDI_DP_COMP_CTL_D10_2 (0 << 28) #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) @@ -10039,6 +10045,12 @@ enum skl_power_gate { #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) +/* EHL */ +#define _EHL_DDI_DP_COMP_PAT_A 0x640F4 +#define _EHL_DDI_DP_COMP_PAT_B 0x641F4 +#define EHL_DDI_DP_COMP_PAT(port, i) \ + _MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4) + /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A 0x605F4 #define _DDI_DP_COMP_PAT_B 0x615F4 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 2020-06-04 5:03 [PATCH] drm/i915/dp: DP PHY compliance for JSL Vidya Srinivas 2020-09-04 4:13 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas @ 2020-09-04 4:14 ` Vidya Srinivas 2020-09-04 4:14 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 1 sibling, 1 reply; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:14 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Khaled Almahallawy From: Khaled Almahallawy <khaled.almahallawy@intel.com> Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> (v1) Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, &data->hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL 2020-09-04 4:14 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas @ 2020-09-04 4:14 ` Vidya Srinivas 0 siblings, 0 replies; 20+ messages in thread From: Vidya Srinivas @ 2020-09-04 4:14 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Vidya Srinivas, Khaled Almahallawy Please Note: Comment from Ville could not be addressed as his comments are with respect to base implementation (design) which are already merged. We need JSL changes for compliance. Hence pushing the required changes on top of existing design. Apoligies for that. v2: Rebased patch on top of Khaled's (yet to be merged): https://patchwork.freedesktop.org/series/79779/ Fixed phy patterns for JSL/EHL Add TPS4 support for JSL/EHL Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++-- 2 files changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a8a3ffcef5dc..1773f3d5d0f4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) enum pipe pipe = crtc->pipe; u32 pattern_val, dp_tp_ctl; + i915_reg_t dp_comp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) + dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port); + else if (IS_TIGERLAKE(dev_priv)) + dp_comp_reg = DDI_DP_COMP_CTL(pipe); + switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_write(dev_priv, dp_comp_reg, 0x0); break; case DP_PHY_TEST_PATTERN_D10_2: DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; case DP_PHY_TEST_PATTERN_PRBS7: DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: @@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) * current firmware of DPR-100 could not set it, so hardcoding * now for complaince test. */ - DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \ + 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); pattern_val = 0x3e0f83e0; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); pattern_val = 0x0f83e0f8; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); pattern_val = 0x0000f83e; - intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + if (IS_ELKHARTLAKE(dev_priv)) + intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2), + pattern_val); + else + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; @@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) */ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); pattern_val = 0xFB; - intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), + intel_de_write(dev_priv, dp_comp_reg, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; @@ -5478,22 +5498,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_port_mask; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(dig_port->base.port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5505,20 +5535,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, + dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5565,6 +5604,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5590,6 +5630,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4850890918dc..7d3b6779661f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10026,10 +10026,16 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* EHL/JSL DP compliance control */ +#define _EHL_DDI_DP_COMP_CTL_A 0x640F0 +#define _EHL_DDI_DP_COMP_CTL_B 0x641F0 +#define EHL_DDI_DP_COMP_CTL(port) \ + _MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B) + /* DDI DP Compliance Control */ -#define _DDI_DP_COMP_CTL_A 0x605F0 -#define _DDI_DP_COMP_CTL_B 0x615F0 -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) #define DDI_DP_COMP_CTL_ENABLE (1 << 31) #define DDI_DP_COMP_CTL_D10_2 (0 << 28) #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) @@ -10039,6 +10045,12 @@ enum skl_power_gate { #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) +/* EHL */ +#define _EHL_DDI_DP_COMP_PAT_A 0x640F4 +#define _EHL_DDI_DP_COMP_PAT_B 0x641F4 +#define EHL_DDI_DP_COMP_PAT(port, i) \ + _MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4) + /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A 0x605F4 #define _DDI_DP_COMP_PAT_B 0x615F4 -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-09-04 4:30 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-23 0:36 [PATCH v2 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Khaled Almahallawy 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy 2020-07-23 0:36 ` [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Khaled Almahallawy 2020-07-23 0:36 ` [Intel-gfx] " Khaled Almahallawy 2020-08-18 21:29 ` Navare, Manasi 2020-08-18 21:29 ` [Intel-gfx] " Navare, Manasi 2020-08-19 1:47 ` Almahallawy, Khaled 2020-08-19 1:47 ` [Intel-gfx] " Almahallawy, Khaled 2020-07-23 0:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Patchwork 2020-07-23 1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-07-23 2:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-09-04 4:25 ` [PATCH 1/3] " Vidya Srinivas 2020-09-04 4:25 ` [Intel-gfx] " Vidya Srinivas 2020-09-04 4:25 ` [PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support Vidya Srinivas 2020-09-04 4:25 ` [Intel-gfx] " Vidya Srinivas 2020-09-04 4:25 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 2020-09-04 4:25 ` [Intel-gfx] " Vidya Srinivas -- strict thread matches above, loose matches on Subject: below -- 2020-09-04 4:21 [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 2020-09-04 4:21 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 2020-06-04 5:03 [PATCH] drm/i915/dp: DP PHY compliance for JSL Vidya Srinivas 2020-09-04 4:13 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 2020-09-04 4:13 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas 2020-09-04 4:14 ` [PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Vidya Srinivas 2020-09-04 4:14 ` [PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL Vidya Srinivas
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