From: Sumit Garg <sumit.garg@linaro.org> To: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, jason@lakedaemon.net, mark.rutland@arm.com, julien.thierry.kdev@gmail.com, dianders@chromium.org, daniel.thompson@linaro.org, jason.wessel@windriver.com, kgdb-bugreport@lists.sourceforge.net, linux-kernel@vger.kernel.org, Sumit Garg <sumit.garg@linaro.org> Subject: [PATCH v4 1/5] arm64: Add framework to turn IPI as NMI Date: Fri, 11 Sep 2020 18:58:40 +0530 [thread overview] Message-ID: <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> (raw) In-Reply-To: <1599830924-13990-1-git-send-email-sumit.garg@linaro.org> Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a particular platform doesn't support pseudo NMIs, then request IPI as a regular IRQ. The main motivation for this feature is to have an IPI that can be leveraged to invoke NMI functions on other CPUs. And current prospective users are NMI backtrace and KGDB CPUs round-up whose support is added via future patches. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- arch/arm64/include/asm/nmi.h | 16 +++++++++ arch/arm64/kernel/Makefile | 2 +- arch/arm64/kernel/ipi_nmi.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/nmi.h create mode 100644 arch/arm64/kernel/ipi_nmi.c diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h new file mode 100644 index 0000000..3433c55 --- /dev/null +++ b/arch/arm64/include/asm/nmi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_NMI_H +#define __ASM_NMI_H + +#ifndef __ASSEMBLER__ + +#include <linux/cpumask.h> + +extern void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask); + +void set_smp_ipi_nmi(int ipi); +void ipi_nmi_setup(int cpu); +void ipi_nmi_teardown(int cpu); + +#endif /* !__ASSEMBLER__ */ +#endif diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index a561cbb..022c26b 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -19,7 +19,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ return_address.o cpuinfo.o cpu_errata.o \ cpufeature.o alternative.o cacheinfo.o \ smp.o smp_spin_table.o topology.o smccc-call.o \ - syscall.o + syscall.o ipi_nmi.o targets += efi-entry.o diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c new file mode 100644 index 0000000..355ef92 --- /dev/null +++ b/arch/arm64/kernel/ipi_nmi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * NMI support for IPIs + * + * Copyright (C) 2020 Linaro Limited + * Author: Sumit Garg <sumit.garg@linaro.org> + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/smp.h> + +#include <asm/nmi.h> + +static struct irq_desc *ipi_desc __read_mostly; +static int ipi_id __read_mostly; +static bool is_nmi __read_mostly; + +void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask) +{ + if (WARN_ON_ONCE(!ipi_desc)) + return; + + __ipi_send_mask(ipi_desc, mask); +} + +static irqreturn_t ipi_nmi_handler(int irq, void *data) +{ + /* nop, NMI handlers for special features can be added here. */ + + return IRQ_HANDLED; +} + +void ipi_nmi_setup(int cpu) +{ + if (!ipi_desc) + return; + + if (is_nmi) { + if (!prepare_percpu_nmi(ipi_id)) + enable_percpu_nmi(ipi_id, 0); + } else { + enable_percpu_irq(ipi_id, 0); + } +} + +void ipi_nmi_teardown(int cpu) +{ + if (!ipi_desc) + return; + + if (is_nmi) { + disable_percpu_nmi(ipi_id); + teardown_percpu_nmi(ipi_id); + } else { + disable_percpu_irq(ipi_id); + } +} + +void __init set_smp_ipi_nmi(int ipi) +{ + int err; + + err = request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number); + if (err) { + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", + &cpu_number); + WARN_ON(err); + is_nmi = false; + } else { + is_nmi = true; + } + + ipi_desc = irq_to_desc(ipi); + irq_set_status_flags(ipi, IRQ_HIDDEN); + ipi_id = ipi; + + /* Setup the boot CPU immediately */ + ipi_nmi_setup(smp_processor_id()); +} -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sumit Garg <sumit.garg@linaro.org> To: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org Cc: mark.rutland@arm.com, Sumit Garg <sumit.garg@linaro.org>, daniel.thompson@linaro.org, jason@lakedaemon.net, kgdb-bugreport@lists.sourceforge.net, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jason.wessel@windriver.com, tglx@linutronix.de, julien.thierry.kdev@gmail.com Subject: [PATCH v4 1/5] arm64: Add framework to turn IPI as NMI Date: Fri, 11 Sep 2020 18:58:40 +0530 [thread overview] Message-ID: <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> (raw) In-Reply-To: <1599830924-13990-1-git-send-email-sumit.garg@linaro.org> Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a particular platform doesn't support pseudo NMIs, then request IPI as a regular IRQ. The main motivation for this feature is to have an IPI that can be leveraged to invoke NMI functions on other CPUs. And current prospective users are NMI backtrace and KGDB CPUs round-up whose support is added via future patches. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- arch/arm64/include/asm/nmi.h | 16 +++++++++ arch/arm64/kernel/Makefile | 2 +- arch/arm64/kernel/ipi_nmi.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/nmi.h create mode 100644 arch/arm64/kernel/ipi_nmi.c diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h new file mode 100644 index 0000000..3433c55 --- /dev/null +++ b/arch/arm64/include/asm/nmi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_NMI_H +#define __ASM_NMI_H + +#ifndef __ASSEMBLER__ + +#include <linux/cpumask.h> + +extern void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask); + +void set_smp_ipi_nmi(int ipi); +void ipi_nmi_setup(int cpu); +void ipi_nmi_teardown(int cpu); + +#endif /* !__ASSEMBLER__ */ +#endif diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index a561cbb..022c26b 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -19,7 +19,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ return_address.o cpuinfo.o cpu_errata.o \ cpufeature.o alternative.o cacheinfo.o \ smp.o smp_spin_table.o topology.o smccc-call.o \ - syscall.o + syscall.o ipi_nmi.o targets += efi-entry.o diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c new file mode 100644 index 0000000..355ef92 --- /dev/null +++ b/arch/arm64/kernel/ipi_nmi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * NMI support for IPIs + * + * Copyright (C) 2020 Linaro Limited + * Author: Sumit Garg <sumit.garg@linaro.org> + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/smp.h> + +#include <asm/nmi.h> + +static struct irq_desc *ipi_desc __read_mostly; +static int ipi_id __read_mostly; +static bool is_nmi __read_mostly; + +void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask) +{ + if (WARN_ON_ONCE(!ipi_desc)) + return; + + __ipi_send_mask(ipi_desc, mask); +} + +static irqreturn_t ipi_nmi_handler(int irq, void *data) +{ + /* nop, NMI handlers for special features can be added here. */ + + return IRQ_HANDLED; +} + +void ipi_nmi_setup(int cpu) +{ + if (!ipi_desc) + return; + + if (is_nmi) { + if (!prepare_percpu_nmi(ipi_id)) + enable_percpu_nmi(ipi_id, 0); + } else { + enable_percpu_irq(ipi_id, 0); + } +} + +void ipi_nmi_teardown(int cpu) +{ + if (!ipi_desc) + return; + + if (is_nmi) { + disable_percpu_nmi(ipi_id); + teardown_percpu_nmi(ipi_id); + } else { + disable_percpu_irq(ipi_id); + } +} + +void __init set_smp_ipi_nmi(int ipi) +{ + int err; + + err = request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number); + if (err) { + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", + &cpu_number); + WARN_ON(err); + is_nmi = false; + } else { + is_nmi = true; + } + + ipi_desc = irq_to_desc(ipi); + irq_set_status_flags(ipi, IRQ_HIDDEN); + ipi_id = ipi; + + /* Setup the boot CPU immediately */ + ipi_nmi_setup(smp_processor_id()); +} -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-11 16:25 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-11 13:28 [PATCH v4 0/5] arm64: Add framework to turn an IPI as NMI Sumit Garg 2020-09-11 13:28 ` Sumit Garg 2020-09-11 13:28 ` Sumit Garg [this message] 2020-09-11 13:28 ` [PATCH v4 1/5] arm64: Add framework to turn " Sumit Garg 2020-10-10 1:58 ` Masayoshi Mizuma 2020-10-10 1:58 ` Masayoshi Mizuma 2020-10-10 9:34 ` Marc Zyngier 2020-10-10 9:34 ` Marc Zyngier 2020-10-10 15:13 ` Masayoshi Mizuma 2020-10-10 15:13 ` Masayoshi Mizuma 2020-10-12 12:19 ` Sumit Garg 2020-10-12 12:19 ` Sumit Garg 2020-10-13 3:23 ` Masayoshi Mizuma 2020-10-13 3:23 ` Masayoshi Mizuma 2020-10-12 12:21 ` Sumit Garg 2020-10-12 12:21 ` Sumit Garg 2020-09-11 13:28 ` [PATCH v4 2/5] irqchip/gic-v3: Enable support for SGIs to act as NMIs Sumit Garg 2020-09-11 13:28 ` Sumit Garg 2020-09-11 13:28 ` [PATCH v4 3/5] arm64: smp: Allocate and setup IPI as NMI Sumit Garg 2020-09-11 13:28 ` Sumit Garg 2020-09-11 13:28 ` [PATCH v4 4/5] arm64: kgdb: Round up cpus using " Sumit Garg 2020-09-11 13:28 ` Sumit Garg 2020-09-11 13:28 ` [PATCH v4 5/5] arm64: ipi_nmi: Add support for NMI backtrace Sumit Garg 2020-09-11 13:28 ` Sumit Garg
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