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* [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
@ 2020-10-06 11:53 Imre Deak
  2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Imre Deak @ 2020-10-06 11:53 UTC (permalink / raw)
  To: intel-gfx

Add the MISSING_CASE() for the p0, p2 decoding during WRPLL HW readout
and move the corresponding check for p1 next to where it's read out.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2cc0e84e41ea..27a8c281382c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2662,6 +2662,8 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	else
 		p1 = 1;
 
+	if (drm_WARN_ON(&dev_priv->drm, p1 == 0))
+		return 0;
 
 	switch (p0) {
 	case DPLL_CFGCR1_PDIV_2:
@@ -2676,6 +2678,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	case DPLL_CFGCR1_PDIV_7:
 		p0 = 7;
 		break;
+	default:
+		MISSING_CASE(p0);
+		return 0;
 	}
 
 	switch (p2) {
@@ -2688,6 +2693,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	case DPLL_CFGCR1_KDIV_3:
 		p2 = 3;
 		break;
+	default:
+		MISSING_CASE(p2);
+		return 0;
 	}
 
 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
@@ -2701,9 +2709,6 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 
 	dco_freq += (dco_fraction * ref_clock) / 0x8000;
 
-	if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
-		return 0;
-
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
-- 
2.25.1

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-06 14:55 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection Imre Deak
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork

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