* [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
@ 2020-10-06 11:53 Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Imre Deak @ 2020-10-06 11:53 UTC (permalink / raw)
To: intel-gfx
Add the MISSING_CASE() for the p0, p2 decoding during WRPLL HW readout
and move the corresponding check for p1 next to where it's read out.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2cc0e84e41ea..27a8c281382c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2662,6 +2662,8 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
else
p1 = 1;
+ if (drm_WARN_ON(&dev_priv->drm, p1 == 0))
+ return 0;
switch (p0) {
case DPLL_CFGCR1_PDIV_2:
@@ -2676,6 +2678,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case DPLL_CFGCR1_PDIV_7:
p0 = 7;
break;
+ default:
+ MISSING_CASE(p0);
+ return 0;
}
switch (p2) {
@@ -2688,6 +2693,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case DPLL_CFGCR1_KDIV_3:
p2 = 3;
break;
+ default:
+ MISSING_CASE(p2);
+ return 0;
}
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
@@ -2701,9 +2709,6 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
dco_freq += (dco_fraction * ref_clock) / 0x8000;
- if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
- return 0;
-
return dco_freq / (p0 * p1 * p2 * 5);
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
@ 2020-10-06 11:54 ` Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection Imre Deak
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Imre Deak @ 2020-10-06 11:54 UTC (permalink / raw)
To: intel-gfx
Move the check of p1 divider value next to where it's read out.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 27a8c281382c..2a411dd46769 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1591,6 +1591,8 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
else
p1 = 1;
+ if (drm_WARN_ON(&i915->drm, p1 == 0))
+ return 0;
switch (p0) {
case DPLL_CFGCR2_PDIV_1:
@@ -1641,9 +1643,6 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
ref_clock / 0x8000;
- if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
- return 0;
-
return dco_freq / (p0 * p1 * p2 * 5);
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
@ 2020-10-06 11:54 ` Imre Deak
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Imre Deak @ 2020-10-06 11:54 UTC (permalink / raw)
To: intel-gfx
The p0 divider (aka PDIV) doesn't support the div-by-5 configuration, so
in case the effective divider (p0*p1*p2) value is 5, either p1 (QDIV) or
p2 (KDIV) must be used. p1 can't be used either since it must match p0
if p0 is 1, so using p2 is the only possibility.
This didn't cause an actual problem, since the HDMI port clock is
limited to 300MHz on SKL, which means the minimum effective divider is 6
there, but let's still fix the logic (instead of removing dividers
smaller than 6 from the effective divider list).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2a411dd46769..eabe63716eb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1367,8 +1367,12 @@ static void skl_wrpll_get_multipliers(unsigned int p,
*p0 = 3;
*p1 = 1;
*p2 = p / 3;
- } else if (p == 5 || p == 7) {
- *p0 = p;
+ } else if (p == 5) {
+ *p0 = 1;
+ *p1 = 1;
+ *p2 = 5;
+ } else if (p == 7) {
+ *p0 = 7;
*p1 = 1;
*p2 = 1;
} else if (p == 15) {
--
2.25.1
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection Imre Deak
@ 2020-10-06 14:55 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-10-06 14:55 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7016 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
URL : https://patchwork.freedesktop.org/series/82406/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18635
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18635 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18635, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18635:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@execlists:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-cml-u2/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-cml-u2/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_18635 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][11] ([i915#2203]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-skl-guc/igt@vgem_basic@unload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-skl-guc/igt@vgem_basic@unload.html
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@vgem_basic@unload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-kbl-x1275/igt@vgem_basic@unload.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][15] ([i915#62] / [i915#95]) -> [DMESG-FAIL][16] ([i915#62])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][21] ([i915#2029] / [i915#2439]) -> [FAIL][22] ([i915#2029])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-bdw-5557u/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/fi-bdw-5557u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_9104 -> Patchwork_18635
CI-20190529: 20190529
CI_DRM_9104: 9cca7a33b0ebfaa5e0e86098b38eb7508097936a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5802: 0e4fbc60ca5ad6585e642d2ddf8313f3c738426e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18635: e1ae8586c5a6987b5f3782d1314c434ba4ddc4f8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e1ae8586c5a6 drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection
bfec4adf5449 drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out
331c31b5e812 drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18635/index.html
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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-06 14:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection Imre Deak
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork
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