* [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 22:11 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/ Ville Syrjala
` (23 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the DSC stuff out from the middle of the ICP HPD register
definitions. The location seems to have been selected by a
dice roll.
SHPD_FILTER_CNT addition also went astray due to the DSC
mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
1 file changed, 107 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ad9ee4243a0..efe51a4ef719 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4618,6 +4618,110 @@ enum {
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT 10
+#define RC_MAX_QP_SHIFT 5
+#define RC_MIN_QP_SHIFT 0
+
+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
+
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA _MMIO(0xe1100)
@@ -8305,117 +8409,12 @@ enum {
#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
-
-#define SHPD_FILTER_CNT _MMIO(0xc4038)
-#define SHPD_FILTER_CNT_500_ADJ 0x001D9
-
-/* Icelake DSC Rate Control Range Parameter Registers */
-#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
-#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
-#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define RC_BPG_OFFSET_SHIFT 10
-#define RC_MAX_QP_SHIFT 5
-#define RC_MIN_QP_SHIFT 0
-
-#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
-#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
-#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
-#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
-#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
-#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
-#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
-
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
+#define SHPD_FILTER_CNT _MMIO(0xc4038)
+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
+
#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
2020-10-06 14:33 ` [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs Ville Syrjala
@ 2020-10-07 22:11 ` Lucas De Marchi
2020-10-22 23:22 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 22:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Move the DSC stuff out from the middle of the ICP HPD register
>definitions. The location seems to have been selected by a
>dice roll.
>
>SHPD_FILTER_CNT addition also went astray due to the DSC
>mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
> 1 file changed, 107 insertions(+), 108 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 6ad9ee4243a0..efe51a4ef719 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4618,6 +4618,110 @@ enum {
> #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
>
>+/* Icelake DSC Rate Control Range Parameter Registers */
>+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>+#define RC_BPG_OFFSET_SHIFT 10
>+#define RC_MAX_QP_SHIFT 5
>+#define RC_MIN_QP_SHIFT 0
>+
>+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>+
>+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>+
>+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>+
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
>@@ -8305,117 +8409,12 @@ enum {
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
>-
>-#define SHPD_FILTER_CNT _MMIO(0xc4038)
>-#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>-
>-/* Icelake DSC Rate Control Range Parameter Registers */
>-#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>-#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>-#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>-#define RC_BPG_OFFSET_SHIFT 10
>-#define RC_MAX_QP_SHIFT 5
>-#define RC_MIN_QP_SHIFT 0
>-
>-#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>-#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>-#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>-
>-#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>-#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>-#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>-
>-#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>-#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>-#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>-
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
>+#define SHPD_FILTER_CNT _MMIO(0xc4038)
>+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>+
that is a weird choice git 2.26 made for the diff, but looks correct. With
--color-moved (and not sure if the version made any difference, but mine
is 2.28) I could check this is plain move.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
2020-10-07 22:11 ` Lucas De Marchi
@ 2020-10-22 23:22 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-22 23:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Wed, Oct 07, 2020 at 03:11:56PM -0700, Lucas De Marchi wrote:
>On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
>>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>Move the DSC stuff out from the middle of the ICP HPD register
>>definitions. The location seems to have been selected by a
>>dice roll.
>>
>>SHPD_FILTER_CNT addition also went astray due to the DSC
>>mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
>>
>>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>---
>>drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
>>1 file changed, 107 insertions(+), 108 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 6ad9ee4243a0..efe51a4ef719 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -4618,6 +4618,110 @@ enum {
>>#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
>>#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
>>
>>+/* Icelake DSC Rate Control Range Parameter Registers */
>>+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>>+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>>+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>>+#define RC_BPG_OFFSET_SHIFT 10
>>+#define RC_MAX_QP_SHIFT 5
>>+#define RC_MIN_QP_SHIFT 0
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>>+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>>+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>>+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>>+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>>+
>>+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>>+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>>+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>>+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>>+
>>/* VGA port control */
>>#define ADPA _MMIO(0x61100)
>>#define PCH_ADPA _MMIO(0xe1100)
>>@@ -8305,117 +8409,12 @@ enum {
>>
>>#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
>>#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
>>-
>>-#define SHPD_FILTER_CNT _MMIO(0xc4038)
>>-#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>>-
>>-/* Icelake DSC Rate Control Range Parameter Registers */
>>-#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>>-#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>>-#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>>-#define RC_BPG_OFFSET_SHIFT 10
>>-#define RC_MAX_QP_SHIFT 5
>>-#define RC_MIN_QP_SHIFT 0
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>>-#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>>-#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>>-#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>>-#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>>-
>>-#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>>-#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>>-#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>>-#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>>-
>>#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
>>#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>>
>>+#define SHPD_FILTER_CNT _MMIO(0xc4038)
>>+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>>+
>
>that is a weird choice git 2.26 made for the diff, but looks correct. With
>--color-moved (and not sure if the version made any difference, but mine
>is 2.28) I could check this is plain move.
>
>Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Let's see if patchwork now accepts the comment without the email header
to ignore.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Lucas De Marchi
>
>>#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>>#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
>>--
>>2.26.2
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 22:22 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
` (22 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 78 ++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 60 +++++++--------
5 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 907e1d155443..32d24c60ff96 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7367,7 +7367,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
{
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
- return PORT_TC_NONE;
+ return TC_PORT_NONE;
if (INTEL_GEN(dev_priv) >= 12)
return port - PORT_D;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d10b7c8cde3f..8c93253cbd95 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -243,14 +243,14 @@ static inline const char *port_identifier(enum port port)
}
enum tc_port {
- PORT_TC_NONE = -1,
+ TC_PORT_NONE = -1,
- PORT_TC1 = 0,
- PORT_TC2,
- PORT_TC3,
- PORT_TC4,
- PORT_TC5,
- PORT_TC6,
+ TC_PORT_TC1 = 0,
+ TC_PORT_TC2,
+ TC_PORT_TC3,
+ TC_PORT_TC4,
+ TC_PORT_TC5,
+ TC_PORT_TC6,
I915_MAX_TC_PORTS
};
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..1cb548d757e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(i915, port);
- if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
+ if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
return;
snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..d9438194c2f0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
- [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
- [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
- [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
- [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
- [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
- [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_TC1) | GEN11_TBT_HOTPLUG(TC_PORT_TC1),
+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_TC2) | GEN11_TBT_HOTPLUG(TC_PORT_TC2),
+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_TC3) | GEN11_TBT_HOTPLUG(TC_PORT_TC3),
+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_TC4) | GEN11_TBT_HOTPLUG(TC_PORT_TC4),
+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_TC5) | GEN11_TBT_HOTPLUG(TC_PORT_TC5),
+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_TC6) | GEN11_TBT_HOTPLUG(TC_PORT_TC6),
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
- [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
- [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
- [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
- [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
- [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
- [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC4),
+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC5),
+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC6),
};
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1035,17 +1035,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC1);
case HPD_PORT_TC2:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC2);
case HPD_PORT_TC3:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC3);
case HPD_PORT_TC4:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC4);
case HPD_PORT_TC5:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC5);
case HPD_PORT_TC6:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC6);
default:
return false;
}
@@ -1083,17 +1083,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC1);
case HPD_PORT_TC2:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC2);
case HPD_PORT_TC3:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC3);
case HPD_PORT_TC4:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC4);
case HPD_PORT_TC5:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC5);
case HPD_PORT_TC6:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC6);
default:
return false;
}
@@ -1872,7 +1872,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_TC1);
} else {
drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
"Unrecognized PCH type 0x%x\n",
@@ -3238,7 +3238,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
}
/*
@@ -3257,21 +3257,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
u32 hotplug;
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
}
@@ -3652,7 +3652,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
} else if (HAS_PCH_MCC(dev_priv)) {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
} else {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efe51a4ef719..2e378d9b21c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7865,19 +7865,19 @@ enum {
#define GEN11_DE_HPD_IIR _MMIO(0x44478)
#define GEN11_DE_HPD_IER _MMIO(0x4447c)
#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \
- GEN11_TC_HOTPLUG(PORT_TC5) | \
- GEN11_TC_HOTPLUG(PORT_TC4) | \
- GEN11_TC_HOTPLUG(PORT_TC3) | \
- GEN11_TC_HOTPLUG(PORT_TC2) | \
- GEN11_TC_HOTPLUG(PORT_TC1))
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_TC6) | \
+ GEN11_TC_HOTPLUG(TC_PORT_TC5) | \
+ GEN11_TC_HOTPLUG(TC_PORT_TC4) | \
+ GEN11_TC_HOTPLUG(TC_PORT_TC3) | \
+ GEN11_TC_HOTPLUG(TC_PORT_TC2) | \
+ GEN11_TC_HOTPLUG(TC_PORT_TC1))
#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \
- GEN11_TBT_HOTPLUG(PORT_TC5) | \
- GEN11_TBT_HOTPLUG(PORT_TC4) | \
- GEN11_TBT_HOTPLUG(PORT_TC3) | \
- GEN11_TBT_HOTPLUG(PORT_TC2) | \
- GEN11_TBT_HOTPLUG(PORT_TC1))
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_TC6) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_TC5) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_TC4) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_TC3) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_TC2) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_TC1))
#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
@@ -8320,19 +8320,19 @@ enum {
#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
SDE_DDI_HOTPLUG_ICP(PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8417,15 +8417,15 @@ enum {
#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
- ICP_TC_HPD_ENABLE(PORT_TC3) | \
- ICP_TC_HPD_ENABLE(PORT_TC2) | \
- ICP_TC_HPD_ENABLE(PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_TC1))
#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
- ICP_TC_HPD_ENABLE(PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
#define _PCH_DPLL_A 0xc6014
@@ -10283,9 +10283,9 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_TC4 ? \
(tc_port) + 12 : \
- (tc_port) - PORT_TC4 + 21))
+ (tc_port) - TC_PORT_TC4 + 21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/
2020-10-06 14:33 ` [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/ Ville Syrjala
@ 2020-10-07 22:22 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 22:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:31PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Make the namespacing for enum tc_port better by adding
>the TC_ to the actual enum values.
I like having the constants with the same name as the enum but with
capital letters, but then we have TC_PORT_TC<n> which doesn't sound great.
Maybe TC_PORT_1, TC_PORT_2, TC_PORT_3, ...?
When we added enum tc_port we didn't have enum phy. Maybe now we can
actually remove tc_port.
Lucas De Marchi
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
> drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 78 ++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h | 60 +++++++--------
> 5 files changed, 78 insertions(+), 78 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 907e1d155443..32d24c60ff96 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -7367,7 +7367,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> {
> if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>- return PORT_TC_NONE;
>+ return TC_PORT_NONE;
>
> if (INTEL_GEN(dev_priv) >= 12)
> return port - PORT_D;
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index d10b7c8cde3f..8c93253cbd95 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -243,14 +243,14 @@ static inline const char *port_identifier(enum port port)
> }
>
> enum tc_port {
>- PORT_TC_NONE = -1,
>+ TC_PORT_NONE = -1,
>
>- PORT_TC1 = 0,
>- PORT_TC2,
>- PORT_TC3,
>- PORT_TC4,
>- PORT_TC5,
>- PORT_TC6,
>+ TC_PORT_TC1 = 0,
>+ TC_PORT_TC2,
>+ TC_PORT_TC3,
>+ TC_PORT_TC4,
>+ TC_PORT_TC5,
>+ TC_PORT_TC6,
>
> I915_MAX_TC_PORTS
> };
>diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>index 8f67aef18b2d..1cb548d757e1 100644
>--- a/drivers/gpu/drm/i915/display/intel_tc.c
>+++ b/drivers/gpu/drm/i915/display/intel_tc.c
>@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
> enum port port = dig_port->base.port;
> enum tc_port tc_port = intel_port_to_tc(i915, port);
>
>- if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
>+ if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
> return;
>
> snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b753c77c9a77..d9438194c2f0 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_gen11[HPD_NUM_PINS] = {
>- [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
>- [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
>- [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
>- [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
>- [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
>- [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
>+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_TC1) | GEN11_TBT_HOTPLUG(TC_PORT_TC1),
>+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_TC2) | GEN11_TBT_HOTPLUG(TC_PORT_TC2),
>+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_TC3) | GEN11_TBT_HOTPLUG(TC_PORT_TC3),
>+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_TC4) | GEN11_TBT_HOTPLUG(TC_PORT_TC4),
>+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_TC5) | GEN11_TBT_HOTPLUG(TC_PORT_TC5),
>+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_TC6) | GEN11_TBT_HOTPLUG(TC_PORT_TC6),
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
> [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
>- [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
>- [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
>- [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
>- [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
>- [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
>- [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
>+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1),
>+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2),
>+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3),
>+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC4),
>+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC5),
>+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC6),
> };
>
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>@@ -1035,17 +1035,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_TC1:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC1);
> case HPD_PORT_TC2:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC2);
> case HPD_PORT_TC3:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC3);
> case HPD_PORT_TC4:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC4);
> case HPD_PORT_TC5:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC5);
> case HPD_PORT_TC6:
>- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC6);
> default:
> return false;
> }
>@@ -1083,17 +1083,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_TC1:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC1);
> case HPD_PORT_TC2:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC2);
> case HPD_PORT_TC3:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC3);
> case HPD_PORT_TC4:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC4);
> case HPD_PORT_TC5:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC5);
> case HPD_PORT_TC6:
>- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
>+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC6);
> default:
> return false;
> }
>@@ -1872,7 +1872,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> tc_hotplug_trigger = 0;
> } else if (HAS_PCH_MCC(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
>+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_TC1);
> } else {
> drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
> "Unrecognized PCH type 0x%x\n",
>@@ -3238,7 +3238,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
> static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> icp_hpd_irq_setup(dev_priv,
>- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
>+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
> }
>
> /*
>@@ -3257,21 +3257,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> u32 hotplug;
>
> hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
>- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
>+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
> I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
>
> hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
>- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
>- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
>+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
>+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
> I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
> }
>
>@@ -3652,7 +3652,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> } else if (HAS_PCH_MCC(dev_priv)) {
> icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
>- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
>+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
> } else {
> icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index efe51a4ef719..2e378d9b21c5 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7865,19 +7865,19 @@ enum {
> #define GEN11_DE_HPD_IIR _MMIO(0x44478)
> #define GEN11_DE_HPD_IER _MMIO(0x4447c)
> #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
>-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \
>- GEN11_TC_HOTPLUG(PORT_TC5) | \
>- GEN11_TC_HOTPLUG(PORT_TC4) | \
>- GEN11_TC_HOTPLUG(PORT_TC3) | \
>- GEN11_TC_HOTPLUG(PORT_TC2) | \
>- GEN11_TC_HOTPLUG(PORT_TC1))
>+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_TC6) | \
>+ GEN11_TC_HOTPLUG(TC_PORT_TC5) | \
>+ GEN11_TC_HOTPLUG(TC_PORT_TC4) | \
>+ GEN11_TC_HOTPLUG(TC_PORT_TC3) | \
>+ GEN11_TC_HOTPLUG(TC_PORT_TC2) | \
>+ GEN11_TC_HOTPLUG(TC_PORT_TC1))
> #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
>-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \
>- GEN11_TBT_HOTPLUG(PORT_TC5) | \
>- GEN11_TBT_HOTPLUG(PORT_TC4) | \
>- GEN11_TBT_HOTPLUG(PORT_TC3) | \
>- GEN11_TBT_HOTPLUG(PORT_TC2) | \
>- GEN11_TBT_HOTPLUG(PORT_TC1))
>+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_TC6) | \
>+ GEN11_TBT_HOTPLUG(TC_PORT_TC5) | \
>+ GEN11_TBT_HOTPLUG(TC_PORT_TC4) | \
>+ GEN11_TBT_HOTPLUG(TC_PORT_TC3) | \
>+ GEN11_TBT_HOTPLUG(TC_PORT_TC2) | \
>+ GEN11_TBT_HOTPLUG(TC_PORT_TC1))
>
> #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
> #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
>@@ -8320,19 +8320,19 @@ enum {
> #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
> #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> SDE_DDI_HOTPLUG_ICP(PORT_A))
>-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
> #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> SDE_DDI_HOTPLUG_ICP(PORT_A))
>-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>- SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
>+ SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
>
> #define SDEISR _MMIO(0xc4000)
> #define SDEIMR _MMIO(0xc4004)
>@@ -8417,15 +8417,15 @@ enum {
>
> #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
>- ICP_TC_HPD_ENABLE(PORT_TC3) | \
>- ICP_TC_HPD_ENABLE(PORT_TC2) | \
>- ICP_TC_HPD_ENABLE(PORT_TC1))
>+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \
>+ ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \
>+ ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \
>+ ICP_TC_HPD_ENABLE(TC_PORT_TC1))
> #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
>- ICP_TC_HPD_ENABLE(PORT_TC5) | \
>+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \
>+ ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \
> ICP_TC_HPD_ENABLE_MASK)
>
> #define _PCH_DPLL_A 0xc6014
>@@ -10283,9 +10283,9 @@ enum skl_power_gate {
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
> #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
>-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
>+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_TC4 ? \
> (tc_port) + 12 : \
>- (tc_port) - PORT_TC4 + 21))
>+ (tc_port) - TC_PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/ Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 22:28 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names Ville Syrjala
` (21 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 10 +++----
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++
4 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4716484af62d..179029c3d3d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1660,17 +1660,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
};
/*
- * Bspec lists the ports as A, B, C, D - however internally in our
- * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
- * registers in Display Engine match the right offsets. Apply the
- * mapping here to translate from VBT to internal convention.
+ * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+ * map to DDI A,B,TC1,TC2 respectively.
*/
static const int rkl_port_mapping[][3] = {
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
[PORT_C] = { -1 },
- [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
if (IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6f7bd67732f2..d1e4cb04e90d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5075,8 +5075,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
{
- if (port >= PORT_D)
- return HPD_PORT_TC1 + port - PORT_D;
+ if (port >= PORT_TC1)
+ return HPD_PORT_TC1 + port - PORT_TC1;
else
return HPD_PORT_A + port - PORT_A;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 32d24c60ff96..e073b862b282 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7356,12 +7356,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
- return (enum phy)port - 1;
+ if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+ return PHY_C + port - PORT_TC1;
else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
- return (enum phy)port;
+ return PHY_A + port - PORT_A;
}
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
@@ -7370,9 +7370,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
return TC_PORT_NONE;
if (INTEL_GEN(dev_priv) >= 12)
- return port - PORT_D;
-
- return port - PORT_C;
+ return TC_PORT_TC1 + port - PORT_TC1;
+ else
+ return TC_PORT_TC1 + port - PORT_C;
}
enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -17104,17 +17104,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D);
- intel_ddi_init(dev_priv, PORT_E);
- intel_ddi_init(dev_priv, PORT_F);
- intel_ddi_init(dev_priv, PORT_G);
- intel_ddi_init(dev_priv, PORT_H);
- intel_ddi_init(dev_priv, PORT_I);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC4);
+ intel_ddi_init(dev_priv, PORT_TC5);
+ intel_ddi_init(dev_priv, PORT_TC6);
icl_dsi_init(dev_priv);
} else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8c93253cbd95..a39be3c9e0cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -207,6 +207,14 @@ enum port {
PORT_H,
PORT_I,
+ /* tgl+ */
+ PORT_TC1 = PORT_D,
+ PORT_TC2,
+ PORT_TC3,
+ PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
+
I915_MAX_PORTS
};
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port
2020-10-06 14:33 ` [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
@ 2020-10-07 22:28 ` Lucas De Marchi
2020-10-08 8:34 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 22:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:32PM +0300, Ville Syrjälä wrote:
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index 8c93253cbd95..a39be3c9e0cf 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -207,6 +207,14 @@ enum port {
> PORT_H,
> PORT_I,
>
>+ /* tgl+ */
>+ PORT_TC1 = PORT_D,
ICL also uses TC ports but there PORT_TC1 would be PORT_C. Just ignore
that and only add the aliases for tgl+ or should we also add for ICL to
avoid confusion?
Lucas De Marchi
>+ PORT_TC2,
>+ PORT_TC3,
>+ PORT_TC4,
>+ PORT_TC5,
>+ PORT_TC6,
>+
> I915_MAX_PORTS
> };
>
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port
2020-10-07 22:28 ` Lucas De Marchi
@ 2020-10-08 8:34 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-08 8:34 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Oct 07, 2020 at 03:28:48PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 06, 2020 at 05:33:32PM +0300, Ville Syrjälä wrote:
> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >index 8c93253cbd95..a39be3c9e0cf 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display.h
> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
> >@@ -207,6 +207,14 @@ enum port {
> > PORT_H,
> > PORT_I,
> >
> >+ /* tgl+ */
> >+ PORT_TC1 = PORT_D,
>
> ICL also uses TC ports but there PORT_TC1 would be PORT_C. Just ignore
> that and only add the aliases for tgl+ or should we also add for ICL to
> avoid confusion?
The spec still uses the DDI C-F names on icl for the TC DDIs.
My idea here is to match the spec terminology.
However, it's going to get annoying in the future because some
of the TC DDIs revert back to alphabetic names in the future,
and in a way that doesn't match the original alphabetic names.
Not quite sure how to deal with that. Probably more aliases,
but this time with a platform specific suffix :(
>
> Lucas De Marchi
>
> >+ PORT_TC2,
> >+ PORT_TC3,
> >+ PORT_TC4,
> >+ PORT_TC5,
> >+ PORT_TC6,
> >+
> > I915_MAX_PORTS
> > };
> >
> >--
> >2.26.2
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (2 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 22:36 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
` (20 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.
ICL is a bit special since it already has the two different types
of DDIs (combo or TC) but it still calls them just DDI A-F regarless
of the type. For that let's add an extra "(TC)" note to remind
is which type of DDI it really is.
The code is darn ugly, but not sure there's much we can do about it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d1e4cb04e90d..5a30bc6a6c49 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5171,8 +5171,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
- drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
- DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %s%c/PHY %s%c",
+ port >= PORT_TC1 ? "TC" : "",
+ port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
+ tc_port != TC_PORT_NONE ? "TC" : "",
+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
+ } else if (INTEL_GEN(dev_priv) >= 11) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %c%s/PHY %s%c",
+ port_name(port),
+ port >= PORT_C ? " (TC)" : "",
+ tc_port != TC_PORT_NONE ? "TC" : "",
+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
+ } else {
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %c/PHY %c", port_name(port), phy_name(phy));
+ }
mutex_init(&dig_port->hdcp_mutex);
dig_port->num_hdcp_streams = 0;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names
2020-10-06 14:33 ` [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names Ville Syrjala
@ 2020-10-07 22:36 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 22:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:33PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's pimp the DDI encoder->name to reflect what the spec calls them.
>Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
>
>Also since each encoder is really a combination of the DDI and the PHY
>we include the PHY name as well.
>
>ICL is a bit special since it already has the two different types
>of DDIs (combo or TC) but it still calls them just DDI A-F regarless
>of the type. For that let's add an extra "(TC)" note to remind
>is which type of DDI it really is.
>
>The code is darn ugly, but not sure there's much we can do about it.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
this also achieves one of the goals of my old series I never
completed (https://patchwork.freedesktop.org/series/71330/).
I'm ok going this direction instead.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index d1e4cb04e90d..5a30bc6a6c49 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -5171,8 +5171,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>
> encoder = &dig_port->base;
>
>- drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
>- DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>+
>+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
>+ DRM_MODE_ENCODER_TMDS,
>+ "DDI %s%c/PHY %s%c",
>+ port >= PORT_TC1 ? "TC" : "",
>+ port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
>+ tc_port != TC_PORT_NONE ? "TC" : "",
>+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
>+ } else if (INTEL_GEN(dev_priv) >= 11) {
>+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>+
>+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
>+ DRM_MODE_ENCODER_TMDS,
>+ "DDI %c%s/PHY %s%c",
>+ port_name(port),
>+ port >= PORT_C ? " (TC)" : "",
>+ tc_port != TC_PORT_NONE ? "TC" : "",
>+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
>+ } else {
>+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
>+ DRM_MODE_ENCODER_TMDS,
>+ "DDI %c/PHY %c", port_name(port), phy_name(phy));
>+ }
>
> mutex_init(&dig_port->hdcp_mutex);
> dig_port->num_hdcp_streams = 0;
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (3 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 22:51 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names Ville Syrjala
` (19 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 8 +++
drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index a39be3c9e0cf..cba876721ea0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -290,6 +290,14 @@ enum aux_ch {
AUX_CH_G,
AUX_CH_H,
AUX_CH_I,
+
+ /* tgl+ */
+ AUX_CH_USBC1 = AUX_CH_D,
+ AUX_CH_USBC2,
+ AUX_CH_USBC3,
+ AUX_CH_USBC4,
+ AUX_CH_USBC5,
+ AUX_CH_USBC6,
};
#define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 239016dcd544..a73c354c920e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
- case AUX_CH_G:
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
- case AUX_CH_G:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = skl_aux_data_reg;
} else if (HAS_PCH_SPLIT(dev_priv)) {
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-06 14:33 ` [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
@ 2020-10-07 22:51 ` Lucas De Marchi
2020-10-08 8:40 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 22:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Just like with the DDIs tgl+ renamed the AUX CHs to reflect
>the type of the DDI. Let's add the aliasing enum values for
>the type-C AUX CHs.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
> 2 files changed, 58 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index a39be3c9e0cf..cba876721ea0 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -290,6 +290,14 @@ enum aux_ch {
> AUX_CH_G,
> AUX_CH_H,
> AUX_CH_I,
>+
>+ /* tgl+ */
>+ AUX_CH_USBC1 = AUX_CH_D,
>+ AUX_CH_USBC2,
>+ AUX_CH_USBC3,
>+ AUX_CH_USBC4,
>+ AUX_CH_USBC5,
>+ AUX_CH_USBC6,
> };
>
> #define aux_ch_name(a) ((a) + 'A')
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>index 239016dcd544..a73c354c920e 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.c
>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
> case AUX_CH_D:
> case AUX_CH_E:
> case AUX_CH_F:
>- case AUX_CH_G:
> return DP_AUX_CH_CTL(aux_ch);
> default:
> MISSING_CASE(aux_ch);
>@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
> case AUX_CH_D:
> case AUX_CH_E:
> case AUX_CH_F:
>- case AUX_CH_G:
>+ return DP_AUX_CH_DATA(aux_ch, index);
>+ default:
>+ MISSING_CASE(aux_ch);
>+ return DP_AUX_CH_DATA(AUX_CH_A, index);
>+ }
>+}
>+
>+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
>+{
>+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+ enum aux_ch aux_ch = dig_port->aux_ch;
>+
>+ switch (aux_ch) {
>+ case AUX_CH_A:
>+ case AUX_CH_B:
>+ case AUX_CH_C:
>+ case AUX_CH_USBC1:
>+ case AUX_CH_USBC2:
>+ case AUX_CH_USBC3:
>+ case AUX_CH_USBC4:
>+ case AUX_CH_USBC5:
>+ case AUX_CH_USBC6:
>+ return DP_AUX_CH_CTL(aux_ch);
>+ default:
>+ MISSING_CASE(aux_ch);
>+ return DP_AUX_CH_CTL(AUX_CH_A);
>+ }
>+}
>+
>+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
>+{
>+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+ enum aux_ch aux_ch = dig_port->aux_ch;
>+
>+ switch (aux_ch) {
>+ case AUX_CH_A:
>+ case AUX_CH_B:
>+ case AUX_CH_C:
>+ case AUX_CH_USBC1:
>+ case AUX_CH_USBC2:
>+ case AUX_CH_USBC3:
>+ case AUX_CH_USBC4:
>+ case AUX_CH_USBC5:
>+ case AUX_CH_USBC6:
> return DP_AUX_CH_DATA(aux_ch, index);
> default:
> MISSING_CASE(aux_ch);
>@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &dig_port->base;
>
>- if (INTEL_GEN(dev_priv) >= 9) {
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
why is this even a function pointer rather than just the reg? AFAICS it
only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
but could be orthogonal to the change here.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
>+ } else if (INTEL_GEN(dev_priv) >= 9) {
> intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
> intel_dp->aux_ch_data_reg = skl_aux_data_reg;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-07 22:51 ` Lucas De Marchi
@ 2020-10-08 8:40 ` Ville Syrjälä
2020-10-08 8:52 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-08 8:40 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
> >the type of the DDI. Let's add the aliasing enum values for
> >the type-C AUX CHs.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
> > 2 files changed, 58 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >index a39be3c9e0cf..cba876721ea0 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display.h
> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
> >@@ -290,6 +290,14 @@ enum aux_ch {
> > AUX_CH_G,
> > AUX_CH_H,
> > AUX_CH_I,
> >+
> >+ /* tgl+ */
> >+ AUX_CH_USBC1 = AUX_CH_D,
> >+ AUX_CH_USBC2,
> >+ AUX_CH_USBC3,
> >+ AUX_CH_USBC4,
> >+ AUX_CH_USBC5,
> >+ AUX_CH_USBC6,
> > };
> >
> > #define aux_ch_name(a) ((a) + 'A')
> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >index 239016dcd544..a73c354c920e 100644
> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
> > case AUX_CH_D:
> > case AUX_CH_E:
> > case AUX_CH_F:
> >- case AUX_CH_G:
> > return DP_AUX_CH_CTL(aux_ch);
> > default:
> > MISSING_CASE(aux_ch);
> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
> > case AUX_CH_D:
> > case AUX_CH_E:
> > case AUX_CH_F:
> >- case AUX_CH_G:
> >+ return DP_AUX_CH_DATA(aux_ch, index);
> >+ default:
> >+ MISSING_CASE(aux_ch);
> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
> >+ }
> >+}
> >+
> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> >+{
> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >+
> >+ switch (aux_ch) {
> >+ case AUX_CH_A:
> >+ case AUX_CH_B:
> >+ case AUX_CH_C:
> >+ case AUX_CH_USBC1:
> >+ case AUX_CH_USBC2:
> >+ case AUX_CH_USBC3:
> >+ case AUX_CH_USBC4:
> >+ case AUX_CH_USBC5:
> >+ case AUX_CH_USBC6:
> >+ return DP_AUX_CH_CTL(aux_ch);
> >+ default:
> >+ MISSING_CASE(aux_ch);
> >+ return DP_AUX_CH_CTL(AUX_CH_A);
> >+ }
> >+}
> >+
> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> >+{
> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >+
> >+ switch (aux_ch) {
> >+ case AUX_CH_A:
> >+ case AUX_CH_B:
> >+ case AUX_CH_C:
> >+ case AUX_CH_USBC1:
> >+ case AUX_CH_USBC2:
> >+ case AUX_CH_USBC3:
> >+ case AUX_CH_USBC4:
> >+ case AUX_CH_USBC5:
> >+ case AUX_CH_USBC6:
> > return DP_AUX_CH_DATA(aux_ch, index);
> > default:
> > MISSING_CASE(aux_ch);
> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct intel_encoder *encoder = &dig_port->base;
> >
> >- if (INTEL_GEN(dev_priv) >= 9) {
> >+ if (INTEL_GEN(dev_priv) >= 12) {
> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
>
> why is this even a function pointer rather than just the reg? AFAICS it
> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
Just for consistency with .aux_ch_data_reg() I guess. Can't remember
a more specific reason at least.
>
> but could be orthogonal to the change here.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Lucas De Marchi
>
> >+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> >+ } else if (INTEL_GEN(dev_priv) >= 9) {
> > intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
> > intel_dp->aux_ch_data_reg = skl_aux_data_reg;
> > } else if (HAS_PCH_SPLIT(dev_priv)) {
> >--
> >2.26.2
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-08 8:40 ` Ville Syrjälä
@ 2020-10-08 8:52 ` Lucas De Marchi
2020-10-22 23:56 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-08 8:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
>On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
>> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
>> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
>> >the type of the DDI. Let's add the aliasing enum values for
>> >the type-C AUX CHs.
>> >
>> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >---
>> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
>> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
>> > 2 files changed, 58 insertions(+), 3 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> >index a39be3c9e0cf..cba876721ea0 100644
>> >--- a/drivers/gpu/drm/i915/display/intel_display.h
>> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
>> >@@ -290,6 +290,14 @@ enum aux_ch {
>> > AUX_CH_G,
>> > AUX_CH_H,
>> > AUX_CH_I,
>> >+
>> >+ /* tgl+ */
>> >+ AUX_CH_USBC1 = AUX_CH_D,
>> >+ AUX_CH_USBC2,
>> >+ AUX_CH_USBC3,
>> >+ AUX_CH_USBC4,
>> >+ AUX_CH_USBC5,
>> >+ AUX_CH_USBC6,
>> > };
>> >
>> > #define aux_ch_name(a) ((a) + 'A')
>> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> >index 239016dcd544..a73c354c920e 100644
>> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
>> > case AUX_CH_D:
>> > case AUX_CH_E:
>> > case AUX_CH_F:
>> >- case AUX_CH_G:
>> > return DP_AUX_CH_CTL(aux_ch);
>> > default:
>> > MISSING_CASE(aux_ch);
>> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
>> > case AUX_CH_D:
>> > case AUX_CH_E:
>> > case AUX_CH_F:
>> >- case AUX_CH_G:
>> >+ return DP_AUX_CH_DATA(aux_ch, index);
>> >+ default:
>> >+ MISSING_CASE(aux_ch);
>> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
>> >+ }
>> >+}
>> >+
>> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
>> >+{
>> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >+
>> >+ switch (aux_ch) {
>> >+ case AUX_CH_A:
>> >+ case AUX_CH_B:
>> >+ case AUX_CH_C:
>> >+ case AUX_CH_USBC1:
>> >+ case AUX_CH_USBC2:
>> >+ case AUX_CH_USBC3:
>> >+ case AUX_CH_USBC4:
>> >+ case AUX_CH_USBC5:
>> >+ case AUX_CH_USBC6:
>> >+ return DP_AUX_CH_CTL(aux_ch);
>> >+ default:
>> >+ MISSING_CASE(aux_ch);
>> >+ return DP_AUX_CH_CTL(AUX_CH_A);
>> >+ }
>> >+}
>> >+
>> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
>> >+{
>> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >+
>> >+ switch (aux_ch) {
>> >+ case AUX_CH_A:
>> >+ case AUX_CH_B:
>> >+ case AUX_CH_C:
>> >+ case AUX_CH_USBC1:
>> >+ case AUX_CH_USBC2:
>> >+ case AUX_CH_USBC3:
>> >+ case AUX_CH_USBC4:
>> >+ case AUX_CH_USBC5:
>> >+ case AUX_CH_USBC6:
>> > return DP_AUX_CH_DATA(aux_ch, index);
>> > default:
>> > MISSING_CASE(aux_ch);
>> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > struct intel_encoder *encoder = &dig_port->base;
>> >
>> >- if (INTEL_GEN(dev_priv) >= 9) {
>> >+ if (INTEL_GEN(dev_priv) >= 12) {
>> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
>>
>> why is this even a function pointer rather than just the reg? AFAICS it
>> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
>
>Just for consistency with .aux_ch_data_reg() I guess. Can't remember
>a more specific reason at least.
even that may be overkill since all the users just use index to
do `+ index * 4`
Lucas De Marchi
>
>>
>> but could be orthogonal to the change here.
>>
>>
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>> Lucas De Marchi
>>
>> >+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
>> >+ } else if (INTEL_GEN(dev_priv) >= 9) {
>> > intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
>> > intel_dp->aux_ch_data_reg = skl_aux_data_reg;
>> > } else if (HAS_PCH_SPLIT(dev_priv)) {
>> >--
>> >2.26.2
>> >
>> >_______________________________________________
>> >Intel-gfx mailing list
>> >Intel-gfx@lists.freedesktop.org
>> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-08 8:52 ` Lucas De Marchi
@ 2020-10-22 23:56 ` Ville Syrjälä
2020-10-23 0:01 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-22 23:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
> On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
> >On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
> >> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
> >> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
> >> >the type of the DDI. Let's add the aliasing enum values for
> >> >the type-C AUX CHs.
> >> >
> >> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >---
> >> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> >> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
> >> > 2 files changed, 58 insertions(+), 3 deletions(-)
> >> >
> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> >index a39be3c9e0cf..cba876721ea0 100644
> >> >--- a/drivers/gpu/drm/i915/display/intel_display.h
> >> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> >@@ -290,6 +290,14 @@ enum aux_ch {
> >> > AUX_CH_G,
> >> > AUX_CH_H,
> >> > AUX_CH_I,
> >> >+
> >> >+ /* tgl+ */
> >> >+ AUX_CH_USBC1 = AUX_CH_D,
> >> >+ AUX_CH_USBC2,
> >> >+ AUX_CH_USBC3,
> >> >+ AUX_CH_USBC4,
> >> >+ AUX_CH_USBC5,
> >> >+ AUX_CH_USBC6,
> >> > };
> >> >
> >> > #define aux_ch_name(a) ((a) + 'A')
> >> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >index 239016dcd544..a73c354c920e 100644
> >> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
> >> > case AUX_CH_D:
> >> > case AUX_CH_E:
> >> > case AUX_CH_F:
> >> >- case AUX_CH_G:
> >> > return DP_AUX_CH_CTL(aux_ch);
> >> > default:
> >> > MISSING_CASE(aux_ch);
> >> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
> >> > case AUX_CH_D:
> >> > case AUX_CH_E:
> >> > case AUX_CH_F:
> >> >- case AUX_CH_G:
> >> >+ return DP_AUX_CH_DATA(aux_ch, index);
> >> >+ default:
> >> >+ MISSING_CASE(aux_ch);
> >> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
> >> >+ }
> >> >+}
> >> >+
> >> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> >> >+{
> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >> >+
> >> >+ switch (aux_ch) {
> >> >+ case AUX_CH_A:
> >> >+ case AUX_CH_B:
> >> >+ case AUX_CH_C:
> >> >+ case AUX_CH_USBC1:
> >> >+ case AUX_CH_USBC2:
> >> >+ case AUX_CH_USBC3:
> >> >+ case AUX_CH_USBC4:
> >> >+ case AUX_CH_USBC5:
> >> >+ case AUX_CH_USBC6:
> >> >+ return DP_AUX_CH_CTL(aux_ch);
> >> >+ default:
> >> >+ MISSING_CASE(aux_ch);
> >> >+ return DP_AUX_CH_CTL(AUX_CH_A);
> >> >+ }
> >> >+}
> >> >+
> >> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> >> >+{
> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >> >+
> >> >+ switch (aux_ch) {
> >> >+ case AUX_CH_A:
> >> >+ case AUX_CH_B:
> >> >+ case AUX_CH_C:
> >> >+ case AUX_CH_USBC1:
> >> >+ case AUX_CH_USBC2:
> >> >+ case AUX_CH_USBC3:
> >> >+ case AUX_CH_USBC4:
> >> >+ case AUX_CH_USBC5:
> >> >+ case AUX_CH_USBC6:
> >> > return DP_AUX_CH_DATA(aux_ch, index);
> >> > default:
> >> > MISSING_CASE(aux_ch);
> >> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> >> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> > struct intel_encoder *encoder = &dig_port->base;
> >> >
> >> >- if (INTEL_GEN(dev_priv) >= 9) {
> >> >+ if (INTEL_GEN(dev_priv) >= 12) {
> >> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> >>
> >> why is this even a function pointer rather than just the reg? AFAICS it
> >> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
> >
> >Just for consistency with .aux_ch_data_reg() I guess. Can't remember
> >a more specific reason at least.
>
> even that may be overkill since all the users just use index to
> do `+ index * 4`
The code used to do that but we got rid of it when the i915_reg
stuff was introduced to discourage people from doing hand rolled
arithmetic on register offsets. I think the tradeoff has been
generally worth it because I can't remeber the last time someone
messed up the register offsets. Before type safety it was a
somewhat regular occurance.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
2020-10-22 23:56 ` Ville Syrjälä
@ 2020-10-23 0:01 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-23 0:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Oct 23, 2020 at 02:56:21AM +0300, Ville Syrjälä wrote:
>On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
>> On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
>> >On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
>> >> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
>> >> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >
>> >> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
>> >> >the type of the DDI. Let's add the aliasing enum values for
>> >> >the type-C AUX CHs.
>> >> >
>> >> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >---
>> >> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
>> >> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++--
>> >> > 2 files changed, 58 insertions(+), 3 deletions(-)
>> >> >
>> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> >> >index a39be3c9e0cf..cba876721ea0 100644
>> >> >--- a/drivers/gpu/drm/i915/display/intel_display.h
>> >> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
>> >> >@@ -290,6 +290,14 @@ enum aux_ch {
>> >> > AUX_CH_G,
>> >> > AUX_CH_H,
>> >> > AUX_CH_I,
>> >> >+
>> >> >+ /* tgl+ */
>> >> >+ AUX_CH_USBC1 = AUX_CH_D,
>> >> >+ AUX_CH_USBC2,
>> >> >+ AUX_CH_USBC3,
>> >> >+ AUX_CH_USBC4,
>> >> >+ AUX_CH_USBC5,
>> >> >+ AUX_CH_USBC6,
>> >> > };
>> >> >
>> >> > #define aux_ch_name(a) ((a) + 'A')
>> >> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> >index 239016dcd544..a73c354c920e 100644
>> >> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
>> >> > case AUX_CH_D:
>> >> > case AUX_CH_E:
>> >> > case AUX_CH_F:
>> >> >- case AUX_CH_G:
>> >> > return DP_AUX_CH_CTL(aux_ch);
>> >> > default:
>> >> > MISSING_CASE(aux_ch);
>> >> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
>> >> > case AUX_CH_D:
>> >> > case AUX_CH_E:
>> >> > case AUX_CH_F:
>> >> >- case AUX_CH_G:
>> >> >+ return DP_AUX_CH_DATA(aux_ch, index);
>> >> >+ default:
>> >> >+ MISSING_CASE(aux_ch);
>> >> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
>> >> >+ }
>> >> >+}
>> >> >+
>> >> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
>> >> >+{
>> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >> >+
>> >> >+ switch (aux_ch) {
>> >> >+ case AUX_CH_A:
>> >> >+ case AUX_CH_B:
>> >> >+ case AUX_CH_C:
>> >> >+ case AUX_CH_USBC1:
>> >> >+ case AUX_CH_USBC2:
>> >> >+ case AUX_CH_USBC3:
>> >> >+ case AUX_CH_USBC4:
>> >> >+ case AUX_CH_USBC5:
>> >> >+ case AUX_CH_USBC6:
>> >> >+ return DP_AUX_CH_CTL(aux_ch);
>> >> >+ default:
>> >> >+ MISSING_CASE(aux_ch);
>> >> >+ return DP_AUX_CH_CTL(AUX_CH_A);
>> >> >+ }
>> >> >+}
>> >> >+
>> >> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
>> >> >+{
>> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >> >+
>> >> >+ switch (aux_ch) {
>> >> >+ case AUX_CH_A:
>> >> >+ case AUX_CH_B:
>> >> >+ case AUX_CH_C:
>> >> >+ case AUX_CH_USBC1:
>> >> >+ case AUX_CH_USBC2:
>> >> >+ case AUX_CH_USBC3:
>> >> >+ case AUX_CH_USBC4:
>> >> >+ case AUX_CH_USBC5:
>> >> >+ case AUX_CH_USBC6:
>> >> > return DP_AUX_CH_DATA(aux_ch, index);
>> >> > default:
>> >> > MISSING_CASE(aux_ch);
>> >> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>> >> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> > struct intel_encoder *encoder = &dig_port->base;
>> >> >
>> >> >- if (INTEL_GEN(dev_priv) >= 9) {
>> >> >+ if (INTEL_GEN(dev_priv) >= 12) {
>> >> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
>> >>
>> >> why is this even a function pointer rather than just the reg? AFAICS it
>> >> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
>> >
>> >Just for consistency with .aux_ch_data_reg() I guess. Can't remember
>> >a more specific reason at least.
>>
>> even that may be overkill since all the users just use index to
>> do `+ index * 4`
>
>The code used to do that but we got rid of it when the i915_reg
>stuff was introduced to discourage people from doing hand rolled
>arithmetic on register offsets. I think the tradeoff has been
>generally worth it because I can't remeber the last time someone
>messed up the register offsets. Before type safety it was a
>somewhat regular occurance.
ok. Just so patchwork gets it now:
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (4 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 23:01 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
` (18 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a73c354c920e..299dc444a777 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1877,6 +1877,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
+ enum aux_ch aux_ch = dig_port->aux_ch;
if (INTEL_GEN(dev_priv) >= 12) {
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
@@ -1909,9 +1910,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(&intel_dp->aux);
/* Failure to allocate our preferred name is not critical */
- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
- aux_ch_name(dig_port->aux_ch),
- port_name(encoder->port));
+ if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+ aux_ch - AUX_CH_USBC1 + '1',
+ encoder->base.name);
+ else
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch),
+ encoder->base.name);
+
intel_dp->aux.transfer = intel_dp_aux_transfer;
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names
2020-10-06 14:33 ` [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names Ville Syrjala
@ 2020-10-07 23:01 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 23:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:35PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
>AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
>the full encoder name in the AUX CH name as well (as opposed to
>just using port_name() which wouldn't give us the right thing on
>tgl+).
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>index a73c354c920e..299dc444a777 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.c
>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>@@ -1877,6 +1877,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &dig_port->base;
>+ enum aux_ch aux_ch = dig_port->aux_ch;
>
> if (INTEL_GEN(dev_priv) >= 12) {
> intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
>@@ -1909,9 +1910,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> drm_dp_aux_init(&intel_dp->aux);
>
> /* Failure to allocate our preferred name is not critical */
>- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
>- aux_ch_name(dig_port->aux_ch),
>- port_name(encoder->port));
>+ if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
>+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
>+ aux_ch - AUX_CH_USBC1 + '1',
>+ encoder->base.name);
>+ else
>+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
>+ aux_ch_name(aux_ch),
>+ encoder->base.name);
>+
> intel_dp->aux.transfer = intel_dp_aux_transfer;
> }
>
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (5 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 23:11 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
` (17 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 179029c3d3d5..77c86f51c36d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2636,10 +2636,14 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ /*
+ * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+ * map to DDI A,B,TC1,TC2 respectively.
+ */
+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC1 : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC2 : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
2020-10-06 14:33 ` [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
@ 2020-10-07 23:11 ` Lucas De Marchi
2020-10-08 8:43 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 23:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:36PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>As with the VBT DVO port, RKL uses PHY based mapping for the
>VBT AUX CH. Adjust the code to use the new AUX_USBCn names
>and add a comment to explain the situation.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>index 179029c3d3d5..77c86f51c36d 100644
>--- a/drivers/gpu/drm/i915/display/intel_bios.c
>+++ b/drivers/gpu/drm/i915/display/intel_bios.c
>@@ -2636,10 +2636,14 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> aux_ch = AUX_CH_B;
> break;
> case DP_AUX_C:
>- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
>+ /*
>+ * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
>+ * map to DDI A,B,TC1,TC2 respectively.
This will conflict with DG1 that was just merged and use the same
mapping as RKL. Change here LGTM.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+ */
>+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC1 : AUX_CH_C;
> break;
> case DP_AUX_D:
>- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
>+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC2 : AUX_CH_D;
> break;
> case DP_AUX_E:
> aux_ch = AUX_CH_E;
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
2020-10-07 23:11 ` Lucas De Marchi
@ 2020-10-08 8:43 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-08 8:43 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Oct 07, 2020 at 04:11:45PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 06, 2020 at 05:33:36PM +0300, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >As with the VBT DVO port, RKL uses PHY based mapping for the
> >VBT AUX CH. Adjust the code to use the new AUX_USBCn names
> >and add a comment to explain the situation.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> >index 179029c3d3d5..77c86f51c36d 100644
> >--- a/drivers/gpu/drm/i915/display/intel_bios.c
> >+++ b/drivers/gpu/drm/i915/display/intel_bios.c
> >@@ -2636,10 +2636,14 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> > aux_ch = AUX_CH_B;
> > break;
> > case DP_AUX_C:
> >- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
> >+ /*
> >+ * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
> >+ * map to DDI A,B,TC1,TC2 respectively.
>
> This will conflict with DG1 that was just merged and use the same
> mapping as RKL. Change here LGTM.
Aye. I'm still pondering how to make this VBT port stuf not
suck so badly. I guess some kind of platform dependent
i915->VBT enum mapping function(s) could work, but not sure.
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Lucas De Marchi
>
> >+ */
> >+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC1 : AUX_CH_C;
> > break;
> > case DP_AUX_D:
> >- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
> >+ aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC2 : AUX_CH_D;
> > break;
> > case DP_AUX_E:
> > aux_ch = AUX_CH_E;
> >--
> >2.26.2
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (6 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 16:25 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
` (16 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d9438194c2f0..9b92b95f7a6f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
};
static const u32 hpd_bxt[HPD_NUM_PINS] = {
- [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
- [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
- [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+ [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
+ [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
+ [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
* For BXT invert bit has to be set based on AOB design
* for HPD detection logic, update it based on VBT fields.
*/
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
hotplug |= BXT_DDIC_HPD_INVERT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e378d9b21c5..72f93ec38aea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7786,6 +7786,8 @@ enum {
(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
GEN11_PIPE_PLANE5_FAULT)
+#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
+
#define GEN8_DE_PORT_ISR _MMIO(0x44440)
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
@@ -7799,12 +7801,10 @@ enum {
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define DSI1_TE (1 << 24)
#define DSI0_TE (1 << 23)
-#define BXT_DE_PORT_HP_DDIC (1 << 5)
-#define BXT_DE_PORT_HP_DDIB (1 << 4)
-#define BXT_DE_PORT_HP_DDIA (1 << 3)
-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
- BXT_DE_PORT_HP_DDIB | \
- BXT_DE_PORT_HP_DDIC)
+#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
+ BXT_DE_PORT_HP_DDI(HPD_PORT_C))
#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH v2 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
2020-10-06 14:33 ` [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
@ 2020-10-06 16:25 ` Ville Syrjala
2020-10-07 23:17 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 16:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.
v2: Remember the gvt
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/display.c | 13 +++++++------
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 7ba16ddfe75f..c124734e114c 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
int pipe;
if (IS_BROXTON(dev_priv)) {
- vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
- BXT_DE_PORT_HP_DDIB |
- BXT_DE_PORT_HP_DDIC);
+ vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+ ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
+ BXT_DE_PORT_HP_DDI(HPD_PORT_C));
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDIA;
+ BXT_DE_PORT_HP_DDI(HPD_PORT_A);
}
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDIB;
+ BXT_DE_PORT_HP_DDI(HPD_PORT_B);
}
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDIC;
+ BXT_DE_PORT_HP_DDI(HPD_PORT_C);
}
return;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d9438194c2f0..9b92b95f7a6f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
};
static const u32 hpd_bxt[HPD_NUM_PINS] = {
- [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
- [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
- [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+ [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
+ [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
+ [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
* For BXT invert bit has to be set based on AOB design
* for HPD detection logic, update it based on VBT fields.
*/
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
hotplug |= BXT_DDIC_HPD_INVERT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e378d9b21c5..72f93ec38aea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7786,6 +7786,8 @@ enum {
(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
GEN11_PIPE_PLANE5_FAULT)
+#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
+
#define GEN8_DE_PORT_ISR _MMIO(0x44440)
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
@@ -7799,12 +7801,10 @@ enum {
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define DSI1_TE (1 << 24)
#define DSI0_TE (1 << 23)
-#define BXT_DE_PORT_HP_DDIC (1 << 5)
-#define BXT_DE_PORT_HP_DDIB (1 << 4)
-#define BXT_DE_PORT_HP_DDIA (1 << 3)
-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
- BXT_DE_PORT_HP_DDIB | \
- BXT_DE_PORT_HP_DDIC)
+#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
+ BXT_DE_PORT_HP_DDI(HPD_PORT_C))
#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH v2 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
2020-10-06 16:25 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2020-10-07 23:17 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 23:17 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 07:25:22PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
>these have nothing to do with DDI ports or PHYs as such. The only
>thing that matters is the HPD pin assignment.
>
>v2: Remember the gvt
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/gvt/display.c | 13 +++++++------
> drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> 3 files changed, 19 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
>index 7ba16ddfe75f..c124734e114c 100644
>--- a/drivers/gpu/drm/i915/gvt/display.c
>+++ b/drivers/gpu/drm/i915/gvt/display.c
>@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> int pipe;
>
> if (IS_BROXTON(dev_priv)) {
>- vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
>- BXT_DE_PORT_HP_DDIB |
>- BXT_DE_PORT_HP_DDIC);
>+ vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
>+ ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_C));
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDIA;
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_A);
> }
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDIB;
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_B);
> }
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDIC;
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_C);
> }
>
> return;
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index d9438194c2f0..9b92b95f7a6f 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_bxt[HPD_NUM_PINS] = {
>- [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
>- [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
>- [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
>+ [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
>+ [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
>+ [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
> };
>
> static const u32 hpd_gen11[HPD_NUM_PINS] = {
>@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> * For BXT invert bit has to be set based on AOB design
> * for HPD detection logic, update it based on VBT fields.
> */
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
>+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
> hotplug |= BXT_DDIA_HPD_INVERT;
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
>+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
> hotplug |= BXT_DDIB_HPD_INVERT;
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
>+ if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
> hotplug |= BXT_DDIC_HPD_INVERT;
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 2e378d9b21c5..72f93ec38aea 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7786,6 +7786,8 @@ enum {
> (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
> GEN11_PIPE_PLANE5_FAULT)
>
>+#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
>+
> #define GEN8_DE_PORT_ISR _MMIO(0x44440)
> #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>@@ -7799,12 +7801,10 @@ enum {
> #define GEN9_AUX_CHANNEL_B (1 << 25)
> #define DSI1_TE (1 << 24)
> #define DSI0_TE (1 << 23)
>-#define BXT_DE_PORT_HP_DDIC (1 << 5)
>-#define BXT_DE_PORT_HP_DDIB (1 << 4)
>-#define BXT_DE_PORT_HP_DDIA (1 << 3)
>-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
>- BXT_DE_PORT_HP_DDIB | \
>- BXT_DE_PORT_HP_DDIC)
>+#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
>+#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
>+ BXT_DE_PORT_HP_DDI(HPD_PORT_C))
> #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
> #define BXT_DE_PORT_GMBUS (1 << 1)
> #define GEN8_AUX_CHANNEL_A (1 << 0)
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (7 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 16:25 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
` (15 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9b92b95f7a6f..6b824db1424a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
};
static const u32 hpd_bdw[HPD_NUM_PINS] = {
- [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
};
static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
};
static const u32 hpd_bxt[HPD_NUM_PINS] = {
- [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
- [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
- [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+ [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+ [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2367,7 +2367,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
- tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+ tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
ilk_hpd_irq_handler(dev_priv, tmp_mask);
found = true;
@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
* For BXT invert bit has to be set based on AOB design
* for HPD detection logic, update it based on VBT fields.
*/
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
hotplug |= BXT_DDIC_HPD_INVERT;
@@ -3574,7 +3574,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
else if (IS_BROADWELL(dev_priv))
- de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
+ de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
if (INTEL_GEN(dev_priv) >= 12) {
enum transcoder trans;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72f93ec38aea..969266e59f56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7801,11 +7801,11 @@ enum {
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define DSI1_TE (1 << 24)
#define DSI0_TE (1 << 23)
-#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
- BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
- BXT_DE_PORT_HP_DDI(HPD_PORT_C))
-#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
+#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH v2 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
2020-10-06 14:33 ` [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
@ 2020-10-06 16:25 ` Ville Syrjala
2020-10-07 23:17 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 16:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.
v2: Remember the gvt
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/display.c | 14 +++++++-------
drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index c124734e114c..5b5c71a0b4af 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
if (IS_BROXTON(dev_priv)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
- ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
- BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
- BXT_DE_PORT_HP_DDI(HPD_PORT_C));
+ ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDI(HPD_PORT_A);
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
}
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDI(HPD_PORT_B);
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
}
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- BXT_DE_PORT_HP_DDI(HPD_PORT_C);
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
}
return;
@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
if (IS_BROADWELL(dev_priv))
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
- GEN8_PORT_DP_A_HOTPLUG;
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
else
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9b92b95f7a6f..6b824db1424a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
};
static const u32 hpd_bdw[HPD_NUM_PINS] = {
- [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
};
static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
};
static const u32 hpd_bxt[HPD_NUM_PINS] = {
- [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
- [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
- [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+ [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+ [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2367,7 +2367,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
- tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+ tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
ilk_hpd_irq_handler(dev_priv, tmp_mask);
found = true;
@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
* For BXT invert bit has to be set based on AOB design
* for HPD detection logic, update it based on VBT fields.
*/
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
hotplug |= BXT_DDIC_HPD_INVERT;
@@ -3574,7 +3574,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
else if (IS_BROADWELL(dev_priv))
- de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
+ de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
if (INTEL_GEN(dev_priv) >= 12) {
enum transcoder trans;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72f93ec38aea..969266e59f56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7801,11 +7801,11 @@ enum {
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define DSI1_TE (1 << 24)
#define DSI0_TE (1 << 23)
-#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
- BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
- BXT_DE_PORT_HP_DDI(HPD_PORT_C))
-#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
+#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
2020-10-06 16:25 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2020-10-07 23:17 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 23:17 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 07:25:43PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Unify the BDW/BXT hotplug bits. BDW only has port A, but that
>matches BXT port A so we can shar the same macro for both.
>
>v2: Remember the gvt
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/gvt/display.c | 14 +++++++-------
> drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> 3 files changed, 21 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
>index c124734e114c..5b5c71a0b4af 100644
>--- a/drivers/gpu/drm/i915/gvt/display.c
>+++ b/drivers/gpu/drm/i915/gvt/display.c
>@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>
> if (IS_BROXTON(dev_priv)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
>- ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
>- BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
>- BXT_DE_PORT_HP_DDI(HPD_PORT_C));
>+ ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDI(HPD_PORT_A);
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
> }
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDI(HPD_PORT_B);
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
> }
>
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- BXT_DE_PORT_HP_DDI(HPD_PORT_C);
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
> }
>
> return;
>@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
> if (IS_BROADWELL(dev_priv))
> vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
>- GEN8_PORT_DP_A_HOTPLUG;
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
> else
> vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 9b92b95f7a6f..6b824db1424a 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_bdw[HPD_NUM_PINS] = {
>- [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
>+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
> };
>
> static const u32 hpd_ibx[HPD_NUM_PINS] = {
>@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_bxt[HPD_NUM_PINS] = {
>- [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
>- [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
>- [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
>+ [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
>+ [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
>+ [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
> };
>
> static const u32 hpd_gen11[HPD_NUM_PINS] = {
>@@ -2367,7 +2367,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> found = true;
> }
> } else if (IS_BROADWELL(dev_priv)) {
>- tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
>+ tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
> if (tmp_mask) {
> ilk_hpd_irq_handler(dev_priv, tmp_mask);
> found = true;
>@@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> * For BXT invert bit has to be set based on AOB design
> * for HPD detection logic, update it based on VBT fields.
> */
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
>+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
> hotplug |= BXT_DDIA_HPD_INVERT;
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
>+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
> hotplug |= BXT_DDIB_HPD_INVERT;
>- if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
>+ if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
> intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
> hotplug |= BXT_DDIC_HPD_INVERT;
>
>@@ -3574,7 +3574,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> if (IS_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> else if (IS_BROADWELL(dev_priv))
>- de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
>+ de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
>
> if (INTEL_GEN(dev_priv) >= 12) {
> enum transcoder trans;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 72f93ec38aea..969266e59f56 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7801,11 +7801,11 @@ enum {
> #define GEN9_AUX_CHANNEL_B (1 << 25)
> #define DSI1_TE (1 << 24)
> #define DSI0_TE (1 << 23)
>-#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
>-#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
>- BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
>- BXT_DE_PORT_HP_DDI(HPD_PORT_C))
>-#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
>+#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
>+#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
>+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
>+#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
> #define BXT_DE_PORT_GMBUS (1 << 1)
> #define GEN8_AUX_CHANNEL_A (1 << 0)
> #define TGL_DE_PORT_AUX_USBC6 (1 << 13)
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (8 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-07 23:22 ` Lucas De Marchi
2020-10-06 14:33 ` [Intel-gfx] [PATCH 11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
` (14 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++++++-----------------
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6b824db1424a..b64f83f3d686 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
- [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
- [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
- [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1),
[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2),
[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3),
@@ -1069,11 +1069,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_A:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
case HPD_PORT_B:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
case HPD_PORT_C:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
default:
return false;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 969266e59f56..206e8ab64bd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8317,16 +8317,16 @@ enum {
/* south display engine interrupt: ICP/TGP */
#define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
-#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
- SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
-#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
- SDE_DDI_HOTPLUG_ICP(PORT_B) | \
- SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
@@ -8400,12 +8400,12 @@ enum {
*/
#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
-#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port)))
-#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port)))
-#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port)))
-#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port)))
-#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port)))
-#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
@@ -8415,15 +8415,15 @@ enum {
#define SHPD_FILTER_CNT _MMIO(0xc4038)
#define SHPD_FILTER_CNT_500_ADJ 0x001D9
-#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \
ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \
ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \
ICP_TC_HPD_ENABLE(TC_PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \
ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
2020-10-06 14:33 ` [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
@ 2020-10-07 23:22 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2020-10-07 23:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:39PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
>macros. Makes it clear what these refer to.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++++++-----------------
> 2 files changed, 23 insertions(+), 23 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 6b824db1424a..b64f83f3d686 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
>- [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
>- [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
>- [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
>+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
>+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
>+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
> [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1),
> [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2),
> [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3),
>@@ -1069,11 +1069,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_A:
>- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
>+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
> case HPD_PORT_B:
>- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
>+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
> case HPD_PORT_C:
>- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
>+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
> default:
> return false;
> }
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 969266e59f56..206e8ab64bd4 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8317,16 +8317,16 @@ enum {
> /* south display engine interrupt: ICP/TGP */
> #define SDE_GMBUS_ICP (1 << 23)
> #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
>-#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
>-#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
>- SDE_DDI_HOTPLUG_ICP(PORT_A))
>+#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>+#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
> #define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
> SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
> SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
> SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
>-#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
>- SDE_DDI_HOTPLUG_ICP(PORT_B) | \
>- SDE_DDI_HOTPLUG_ICP(PORT_A))
>+#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
>+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> #define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \
> SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \
> SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
>@@ -8400,12 +8400,12 @@ enum {
> */
>
> #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
>-#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port)))
>-#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port)))
>-#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port)))
>-#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port)))
>-#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port)))
>-#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port)))
>+#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
>+#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
>+#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
>+#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
>+#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
>+#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
>@@ -8415,15 +8415,15 @@ enum {
> #define SHPD_FILTER_CNT _MMIO(0xc4038)
> #define SHPD_FILTER_CNT_500_ADJ 0x001D9
>
>-#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>+#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
>+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
> #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \
> ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \
> ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \
> ICP_TC_HPD_ENABLE(TC_PORT_TC1))
>-#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
>- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>- SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>+#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
>+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
>+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \
> ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \
> ICP_TC_HPD_ENABLE_MASK)
>--
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (9 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
` (13 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++-----------------
drivers/gpu/drm/i915/i915_reg.h | 37 ++++++++++++-------------
2 files changed, 43 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b64f83f3d686..ac82ed3873db 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
- [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_TC1) | GEN11_TBT_HOTPLUG(TC_PORT_TC1),
- [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_TC2) | GEN11_TBT_HOTPLUG(TC_PORT_TC2),
- [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_TC3) | GEN11_TBT_HOTPLUG(TC_PORT_TC3),
- [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_TC4) | GEN11_TBT_HOTPLUG(TC_PORT_TC4),
- [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_TC5) | GEN11_TBT_HOTPLUG(TC_PORT_TC5),
- [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_TC6) | GEN11_TBT_HOTPLUG(TC_PORT_TC6),
+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
@@ -1035,17 +1035,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC1);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC2);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC3);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC4);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC5);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC6);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
default:
return false;
}
@@ -3257,21 +3257,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
u32 hotplug;
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 206e8ab64bd4..ab4b31cb50f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7787,6 +7787,7 @@ enum {
GEN11_PIPE_PLANE5_FAULT)
#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
+#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
#define GEN8_DE_PORT_ISR _MMIO(0x44440)
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
@@ -7864,27 +7865,27 @@ enum {
#define GEN11_DE_HPD_IMR _MMIO(0x44474)
#define GEN11_DE_HPD_IIR _MMIO(0x44478)
#define GEN11_DE_HPD_IER _MMIO(0x4447c)
-#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_TC6) | \
- GEN11_TC_HOTPLUG(TC_PORT_TC5) | \
- GEN11_TC_HOTPLUG(TC_PORT_TC4) | \
- GEN11_TC_HOTPLUG(TC_PORT_TC3) | \
- GEN11_TC_HOTPLUG(TC_PORT_TC2) | \
- GEN11_TC_HOTPLUG(TC_PORT_TC1))
-#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_TC6) | \
- GEN11_TBT_HOTPLUG(TC_PORT_TC5) | \
- GEN11_TBT_HOTPLUG(TC_PORT_TC4) | \
- GEN11_TBT_HOTPLUG(TC_PORT_TC3) | \
- GEN11_TBT_HOTPLUG(TC_PORT_TC2) | \
- GEN11_TBT_HOTPLUG(TC_PORT_TC1))
+#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC1))
+#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
-#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
-#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
-#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
+#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
#define GEN11_CSME (31)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (10 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
` (12 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++-------------
drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++-----------------
2 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ac82ed3873db..63322160e248 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
- [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1),
- [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2),
- [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3),
- [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC4),
- [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC5),
- [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC6),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
};
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1083,17 +1083,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC1);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC2);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC3);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC4);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC5);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
- return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC6);
+ return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
default:
return false;
}
@@ -1872,7 +1872,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_TC1);
+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
} else {
drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
"Unrecognized PCH type 0x%x\n",
@@ -3238,7 +3238,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
}
/*
@@ -3652,7 +3652,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
} else if (HAS_PCH_MCC(dev_priv)) {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_TC1));
+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
} else {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b31cb50f2..b3ae002bf628 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8317,23 +8317,23 @@ enum {
/* south display engine interrupt: ICP/TGP */
#define SDE_GMBUS_ICP (1 << 23)
-#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
+#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(TC_PORT_TC1))
+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8409,24 +8409,24 @@ enum {
#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
-#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
-#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
-#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
+#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
#define SHPD_FILTER_CNT _MMIO(0xc4038)
#define SHPD_FILTER_CNT_500_ADJ 0x001D9
#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \
- ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \
- ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \
- ICP_TC_HPD_ENABLE(TC_PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \
- ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
#define _PCH_DPLL_A 0xc6014
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (11 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
` (11 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++++-----------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 63322160e248..87ccc82bf21d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1196,6 +1196,31 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
}
+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+ const u32 hpd[HPD_NUM_PINS])
+{
+ struct intel_encoder *encoder;
+ u32 enabled_irqs = 0;
+
+ for_each_intel_encoder(&dev_priv->drm, encoder)
+ if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+ enabled_irqs |= hpd[encoder->hpd_pin];
+
+ return enabled_irqs;
+}
+
+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+ const u32 hpd[HPD_NUM_PINS])
+{
+ struct intel_encoder *encoder;
+ u32 hotplug_irqs = 0;
+
+ for_each_intel_encoder(&dev_priv->drm, encoder)
+ hotplug_irqs |= hpd[encoder->hpd_pin];
+
+ return hotplug_irqs;
+}
+
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3131,31 +3156,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
- const u32 hpd[HPD_NUM_PINS])
-{
- struct intel_encoder *encoder;
- u32 enabled_irqs = 0;
-
- for_each_intel_encoder(&dev_priv->drm, encoder)
- if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
- enabled_irqs |= hpd[encoder->hpd_pin];
-
- return enabled_irqs;
-}
-
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
- const u32 hpd[HPD_NUM_PINS])
-{
- struct intel_encoder *encoder;
- u32 hotplug_irqs = 0;
-
- for_each_intel_encoder(&dev_priv->drm, encoder)
- hotplug_irqs |= hpd[encoder->hpd_pin];
-
- return hotplug_irqs;
-}
-
static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (12 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
` (10 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 87ccc82bf21d..0886369e3890 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3252,7 +3252,7 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3264,6 +3264,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug;
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
@@ -3289,7 +3294,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_DE_HPD_IMR, val);
POSTING_READ(GEN11_DE_HPD_IMR);
- gen11_hpd_detection_setup(dev_priv);
+ gen11_tc_hpd_detection_setup(dev_priv);
+ gen11_tbt_hpd_detection_setup(dev_priv);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
icp_hpd_irq_setup(dev_priv,
@@ -3612,7 +3618,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
de_hpd_enables);
- gen11_hpd_detection_setup(dev_priv);
+ gen11_tc_hpd_detection_setup(dev_priv);
+ gen11_tbt_hpd_detection_setup(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_hpd_detection_setup(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall()
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (13 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 16:20 ` Imre Deak
2020-10-06 14:33 ` [Intel-gfx] [PATCH 16/20] drm/i915: Rename 'tmp_mask' Ville Syrjala
` (9 subsequent siblings)
24 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
well. Let's just eliminate the redundant early setup.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 38 +++------------------------------
1 file changed, 3 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0886369e3890..b1c56a29376c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3378,8 +3378,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_irq_setup(dev_priv);
}
-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enabled_irqs)
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
+ u32 enabled_irqs)
{
u32 hotplug;
@@ -3410,11 +3410,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
-}
-
static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
@@ -3424,7 +3419,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
- __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+ bxt_hpd_detection_setup(dev_priv, enabled_irqs);
}
static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3443,12 +3438,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
- if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
- HAS_PCH_LPT(dev_priv))
- ibx_hpd_detection_setup(dev_priv);
- else
- spt_hpd_detection_setup(dev_priv);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3485,8 +3474,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
gen5_gt_irq_postinstall(&dev_priv->gt);
- ilk_hpd_detection_setup(dev_priv);
-
ibx_irq_postinstall(dev_priv);
if (IS_IRONLAKE_M(dev_priv)) {
@@ -3618,12 +3605,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
de_hpd_enables);
- gen11_tc_hpd_detection_setup(dev_priv);
- gen11_tbt_hpd_detection_setup(dev_priv);
- } else if (IS_GEN9_LP(dev_priv)) {
- bxt_hpd_detection_setup(dev_priv);
- } else if (IS_BROADWELL(dev_priv)) {
- ilk_hpd_detection_setup(dev_priv);
}
}
@@ -3651,19 +3632,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
- if (HAS_PCH_TGP(dev_priv)) {
- icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
- } else if (HAS_PCH_JSP(dev_priv)) {
- icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
- } else if (HAS_PCH_MCC(dev_priv)) {
- icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
- } else {
- icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
- }
}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall()
2020-10-06 14:33 ` [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
@ 2020-10-06 16:20 ` Imre Deak
2020-10-06 16:43 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-06 16:20 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 05:33:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No reason that I can see why we should enable the hpd detection logic
> already during irq postinstall phase. We don't even do this on all
> the platforms. We just need it before we actually enable the hotplug
> interrupts in .hpd_irq_setup(), and in fact we already do it there as
> well. Let's just eliminate the redundant early setup.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
It's needed by LSPCON resume, which happens before initing HPD
interrupts. I suppose that could be done later, after HPD interrupt init,
I don't see now why it would need to be done at encoder->reset() time.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 38 +++------------------------------
> 1 file changed, 3 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0886369e3890..b1c56a29376c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3378,8 +3378,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_hpd_irq_setup(dev_priv);
> }
>
> -static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> - u32 enabled_irqs)
> +static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> + u32 enabled_irqs)
> {
> u32 hotplug;
>
> @@ -3410,11 +3410,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> }
>
> -static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> -{
> - __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
> -}
> -
> static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug_irqs, enabled_irqs;
> @@ -3424,7 +3419,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
>
> bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
> - __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> + bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> }
>
> static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3443,12 +3438,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> I915_WRITE(SDEIMR, ~mask);
> -
> - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> - HAS_PCH_LPT(dev_priv))
> - ibx_hpd_detection_setup(dev_priv);
> - else
> - spt_hpd_detection_setup(dev_priv);
> }
>
> static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3485,8 +3474,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen5_gt_irq_postinstall(&dev_priv->gt);
>
> - ilk_hpd_detection_setup(dev_priv);
> -
> ibx_irq_postinstall(dev_priv);
>
> if (IS_IRONLAKE_M(dev_priv)) {
> @@ -3618,12 +3605,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
> de_hpd_enables);
> - gen11_tc_hpd_detection_setup(dev_priv);
> - gen11_tbt_hpd_detection_setup(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_hpd_detection_setup(dev_priv);
> - } else if (IS_BROADWELL(dev_priv)) {
> - ilk_hpd_detection_setup(dev_priv);
> }
> }
>
> @@ -3651,19 +3632,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> I915_WRITE(SDEIMR, ~mask);
> -
> - if (HAS_PCH_TGP(dev_priv)) {
> - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> - icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
> - } else if (HAS_PCH_JSP(dev_priv)) {
> - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> - } else if (HAS_PCH_MCC(dev_priv)) {
> - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
> - } else {
> - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
> - }
> }
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall()
2020-10-06 16:20 ` Imre Deak
@ 2020-10-06 16:43 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-06 16:43 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 07:20:46PM +0300, Imre Deak wrote:
> On Tue, Oct 06, 2020 at 05:33:44PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > No reason that I can see why we should enable the hpd detection logic
> > already during irq postinstall phase. We don't even do this on all
> > the platforms. We just need it before we actually enable the hotplug
> > interrupts in .hpd_irq_setup(), and in fact we already do it there as
> > well. Let's just eliminate the redundant early setup.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> It's needed by LSPCON resume, which happens before initing HPD
> interrupts. I suppose that could be done later, after HPD interrupt init,
> I don't see now why it would need to be done at encoder->reset() time.
Hmm. The ordering of the .reset() hooks vs. other init/resume stuff
looks somewhat random. Might need to think how to make this consistent.
At init time we no longer have the early lspcon probe, exept Uma
probably has to add it back for the HDR stuff. This looks like it
might need some actual thought :(
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 38 +++------------------------------
> > 1 file changed, 3 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 0886369e3890..b1c56a29376c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3378,8 +3378,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > ibx_hpd_irq_setup(dev_priv);
> > }
> >
> > -static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> > - u32 enabled_irqs)
> > +static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> > + u32 enabled_irqs)
> > {
> > u32 hotplug;
> >
> > @@ -3410,11 +3410,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> > I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> > }
> >
> > -static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> > -{
> > - __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
> > -}
> > -
> > static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > {
> > u32 hotplug_irqs, enabled_irqs;
> > @@ -3424,7 +3419,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> >
> > bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > - __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> > + bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> > }
> >
> > static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> > @@ -3443,12 +3438,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> >
> > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> > I915_WRITE(SDEIMR, ~mask);
> > -
> > - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> > - HAS_PCH_LPT(dev_priv))
> > - ibx_hpd_detection_setup(dev_priv);
> > - else
> > - spt_hpd_detection_setup(dev_priv);
> > }
> >
> > static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> > @@ -3485,8 +3474,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> >
> > gen5_gt_irq_postinstall(&dev_priv->gt);
> >
> > - ilk_hpd_detection_setup(dev_priv);
> > -
> > ibx_irq_postinstall(dev_priv);
> >
> > if (IS_IRONLAKE_M(dev_priv)) {
> > @@ -3618,12 +3605,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> >
> > GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
> > de_hpd_enables);
> > - gen11_tc_hpd_detection_setup(dev_priv);
> > - gen11_tbt_hpd_detection_setup(dev_priv);
> > - } else if (IS_GEN9_LP(dev_priv)) {
> > - bxt_hpd_detection_setup(dev_priv);
> > - } else if (IS_BROADWELL(dev_priv)) {
> > - ilk_hpd_detection_setup(dev_priv);
> > }
> > }
> >
> > @@ -3651,19 +3632,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> >
> > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> > I915_WRITE(SDEIMR, ~mask);
> > -
> > - if (HAS_PCH_TGP(dev_priv)) {
> > - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> > - icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
> > - } else if (HAS_PCH_JSP(dev_priv)) {
> > - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> > - } else if (HAS_PCH_MCC(dev_priv)) {
> > - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> > - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
> > - } else {
> > - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> > - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
> > - }
> > }
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > --
> > 2.26.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 16/20] drm/i915: Rename 'tmp_mask'
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (14 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 17/20] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
` (8 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1c56a29376c..1fa880272d88 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2374,7 +2374,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (master_ctl & GEN8_DE_PORT_IRQ) {
iir = I915_READ(GEN8_DE_PORT_IIR);
if (iir) {
- u32 tmp_mask;
bool found = false;
I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2386,15 +2385,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
if (IS_GEN9_LP(dev_priv)) {
- tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
- if (tmp_mask) {
- bxt_hpd_irq_handler(dev_priv, tmp_mask);
+ u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
+
+ if (hotplug_trigger) {
+ bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
- tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
- if (tmp_mask) {
- ilk_hpd_irq_handler(dev_priv, tmp_mask);
+ u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
+
+ if (hotplug_trigger) {
+ ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
found = true;
}
}
@@ -2405,9 +2406,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
if (INTEL_GEN(dev_priv) >= 11) {
- tmp_mask = iir & (DSI0_TE | DSI1_TE);
- if (tmp_mask) {
- gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+ u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
+
+ if (te_trigger) {
+ gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
found = true;
}
}
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 17/20] drm/i915: Remove the per-plaform IIR HPD masking
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (15 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 16/20] drm/i915: Rename 'tmp_mask' Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 18/20] drm/i915: Enable hpd logic only for ports that are present Ville Syrjala
` (7 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
2 files changed, 4 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1fa880272d88..dd6a8d2690f6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1886,27 +1886,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
- u32 ddi_hotplug_trigger, tc_hotplug_trigger;
+ u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
u32 pin_mask = 0, long_mask = 0;
- if (HAS_PCH_TGP(dev_priv)) {
- ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
- tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
- } else if (HAS_PCH_JSP(dev_priv)) {
- ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
- tc_hotplug_trigger = 0;
- } else if (HAS_PCH_MCC(dev_priv)) {
- ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
- } else {
- drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
- "Unrecognized PCH type 0x%x\n",
- INTEL_PCH_TYPE(dev_priv));
-
- ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
- }
-
if (ddi_hotplug_trigger) {
u32 dig_hotplug_reg;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b3ae002bf628..d2175faf7d34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8319,16 +8319,10 @@ enum {
#define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
-#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
- SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 18/20] drm/i915: Enable hpd logic only for ports that are present
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (16 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 17/20] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
` (6 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's enable the hardware hpd logic only for the ports we
can actually use.
In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports being present on each SKU.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 301 ++++++++++++++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 13 --
2 files changed, 205 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dd6a8d2690f6..222d2e6d7ee4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
*/
typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+ enum hpd_pin pin);
static const u32 hpd_ilk[HPD_NUM_PINS] = {
[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -1221,6 +1223,18 @@ static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
return hotplug_irqs;
}
+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+ hotplug_enables_func hotplug_enables)
+{
+ struct intel_encoder *encoder;
+ u32 hotplug = 0;
+
+ for_each_intel_encoder(&i915->drm, encoder)
+ hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+ return hotplug;
+}
+
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3141,6 +3155,31 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ /*
+ * When CPU and PCH are on the same package, port A
+ * HPD must be enabled in both north and south.
+ */
+ return HAS_PCH_LPT_LP(i915) ?
+ PORTA_HOTPLUG_ENABLE : 0;
+ case HPD_PORT_B:
+ return PORTB_HOTPLUG_ENABLE |
+ PORTB_PULSE_DURATION_2ms;
+ case HPD_PORT_C:
+ return PORTC_HOTPLUG_ENABLE |
+ PORTC_PULSE_DURATION_2ms;
+ case HPD_PORT_D:
+ return PORTD_HOTPLUG_ENABLE |
+ PORTD_PULSE_DURATION_2ms;
+ default:
+ return 0;
+ }
+}
+
static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3151,18 +3190,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
* The pulse duration bits are reserved on LPT+.
*/
hotplug = I915_READ(PCH_PORT_HOTPLUG);
- hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+ hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+ PORTB_HOTPLUG_ENABLE |
+ PORTC_HOTPLUG_ENABLE |
+ PORTD_HOTPLUG_ENABLE |
+ PORTB_PULSE_DURATION_MASK |
PORTC_PULSE_DURATION_MASK |
PORTD_PULSE_DURATION_MASK);
- hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
- hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
- hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
- /*
- * When CPU and PCH are on the same package, port A
- * HPD must be enabled in both north and south.
- */
- if (HAS_PCH_LPT_LP(dev_priv))
- hotplug |= PORTA_HOTPLUG_ENABLE;
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}
@@ -3178,28 +3213,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_detection_setup(dev_priv);
}
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ case HPD_PORT_B:
+ case HPD_PORT_C:
+ return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+ default:
+ return 0;
+ }
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_TC1:
+ case HPD_PORT_TC2:
+ case HPD_PORT_TC3:
+ case HPD_PORT_TC4:
+ case HPD_PORT_TC5:
+ case HPD_PORT_TC6:
+ return ICP_TC_HPD_ENABLE(pin);
+ default:
+ return 0;
+ }
+}
+
+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
hotplug = I915_READ(SHOTPLUG_CTL_DDI);
- hotplug |= enable_mask;
+ hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
}
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enable_mask)
+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
hotplug = I915_READ(SHOTPLUG_CTL_TC);
- hotplug |= enable_mask;
+ hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
}
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
- u32 ddi_enable_mask, u32 tc_enable_mask)
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
@@ -3211,30 +3281,24 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
- if (tc_enable_mask)
- icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
+ icp_ddi_hpd_detection_setup(dev_priv);
+ icp_tc_hpd_detection_setup(dev_priv);
}
-/*
- * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
- * equivalent of SDE.
- */
-static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
{
- icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-}
-
-/*
- * JSP behaves exactly the same as MCC above except that port C is mapped to
- * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
- * masks & tables rather than ICP's masks & tables.
- */
-static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
- icp_hpd_irq_setup(dev_priv,
- TGP_DDI_HPD_ENABLE_MASK, 0);
+ switch (pin) {
+ case HPD_PORT_TC1:
+ case HPD_PORT_TC2:
+ case HPD_PORT_TC3:
+ case HPD_PORT_TC4:
+ case HPD_PORT_TC5:
+ case HPD_PORT_TC6:
+ return GEN11_HOTPLUG_CTL_ENABLE(pin);
+ default:
+ return 0;
+ }
}
static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3242,12 +3306,13 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
u32 hotplug;
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+ hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
}
@@ -3256,12 +3321,13 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
u32 hotplug;
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+ hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+ GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
}
@@ -3282,12 +3348,36 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
gen11_tc_hpd_detection_setup(dev_priv);
gen11_tbt_hpd_detection_setup(dev_priv);
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
- icp_hpd_irq_setup(dev_priv,
- TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_hpd_irq_setup(dev_priv);
+}
+
+static u32 spt_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return PORTA_HOTPLUG_ENABLE;
+ case HPD_PORT_B:
+ return PORTB_HOTPLUG_ENABLE;
+ case HPD_PORT_C:
+ return PORTC_HOTPLUG_ENABLE;
+ case HPD_PORT_D:
+ return PORTD_HOTPLUG_ENABLE;
+ default:
+ return 0;
+ }
+}
+
+static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_E:
+ return PORTE_HOTPLUG_ENABLE;
+ default:
+ return 0;
+ }
}
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3304,14 +3394,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
/* Enable digital hotplug on the PCH */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
- hotplug |= PORTA_HOTPLUG_ENABLE |
- PORTB_HOTPLUG_ENABLE |
- PORTC_HOTPLUG_ENABLE |
- PORTD_HOTPLUG_ENABLE;
+ hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+ PORTB_HOTPLUG_ENABLE |
+ PORTC_HOTPLUG_ENABLE |
+ PORTD_HOTPLUG_ENABLE);
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
hotplug = I915_READ(PCH_PORT_HOTPLUG2);
- hotplug |= PORTE_HOTPLUG_ENABLE;
+ hotplug &= ~PORTE_HOTPLUG_ENABLE;
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
}
@@ -3330,6 +3422,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
spt_hpd_detection_setup(dev_priv);
}
+static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return DIGITAL_PORTA_HOTPLUG_ENABLE |
+ DIGITAL_PORTA_PULSE_DURATION_2ms;
+ default:
+ return 0;
+ }
+}
+
static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3340,9 +3444,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
* The pulse duration bits are reserved on HSW+.
*/
hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
- hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
- hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
- DIGITAL_PORTA_PULSE_DURATION_2ms;
+ hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
+ DIGITAL_PORTA_PULSE_DURATION_MASK);
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
}
@@ -3363,35 +3467,44 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_irq_setup(dev_priv);
}
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enabled_irqs)
+static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ u32 hotplug;
+
+ switch (pin) {
+ case HPD_PORT_A:
+ hotplug = PORTA_HOTPLUG_ENABLE;
+ if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
+ hotplug |= BXT_DDIA_HPD_INVERT;
+ return hotplug;
+ case HPD_PORT_B:
+ hotplug = PORTB_HOTPLUG_ENABLE;
+ if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
+ hotplug |= BXT_DDIB_HPD_INVERT;
+ return hotplug;
+ case HPD_PORT_C:
+ hotplug = PORTC_HOTPLUG_ENABLE;
+ if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
+ hotplug |= BXT_DDIC_HPD_INVERT;
+ return hotplug;
+ default:
+ return 0;
+ }
+}
+
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
hotplug = I915_READ(PCH_PORT_HOTPLUG);
- hotplug |= PORTA_HOTPLUG_ENABLE |
- PORTB_HOTPLUG_ENABLE |
- PORTC_HOTPLUG_ENABLE;
-
- drm_dbg_kms(&dev_priv->drm,
- "Invert bit setting: hp_ctl:%x hp_port:%x\n",
- hotplug, enabled_irqs);
- hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
-
- /*
- * For BXT invert bit has to be set based on AOB design
- * for HPD detection logic, update it based on VBT fields.
- */
- if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
- intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
- hotplug |= BXT_DDIA_HPD_INVERT;
- if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
- intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
- hotplug |= BXT_DDIB_HPD_INVERT;
- if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
- intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
- hotplug |= BXT_DDIC_HPD_INVERT;
-
+ hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+ PORTB_HOTPLUG_ENABLE |
+ PORTC_HOTPLUG_ENABLE |
+ BXT_DDIA_HPD_INVERT |
+ BXT_DDIB_HPD_INVERT |
+ BXT_DDIC_HPD_INVERT);
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}
@@ -3404,7 +3517,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
- bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+ bxt_hpd_detection_setup(dev_priv);
}
static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4122,11 +4235,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_JSP(dev_priv))
- dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
- else if (HAS_PCH_MCC(dev_priv))
- dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
- else if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2175faf7d34..75c45fda0f85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8410,19 +8410,6 @@ enum {
#define SHPD_FILTER_CNT _MMIO(0xc4038)
#define SHPD_FILTER_CNT_500_ADJ 0x001D9
-#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
- ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
- ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
- ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
- ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
- ICP_TC_HPD_ENABLE_MASK)
-
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (17 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 18/20] drm/i915: Enable hpd logic only for ports that are present Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 14:33 ` [Intel-gfx] [PATCH 20/20] drm/i915: Get rid of ibx_irq_pre_postinstall() Ville Syrjala
` (5 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
No reason not to use GEN3_IRQ_INIT() on icp+.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 222d2e6d7ee4..63ae60ec2324 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3722,14 +3722,10 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 mask = SDE_GMBUS_ICP;
- drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
- I915_WRITE(SDEIER, 0xffffffff);
- POSTING_READ(SDEIER);
-
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
- I915_WRITE(SDEIMR, ~mask);
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] [PATCH 20/20] drm/i915: Get rid of ibx_irq_pre_postinstall()
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (18 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
@ 2020-10-06 14:33 ` Ville Syrjala
2020-10-06 15:21 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher cleanup around hpd pins and port identfiers Patchwork
` (4 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjala @ 2020-10-06 14:33 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in place. That is, safe with MSI but racy with
shared legacy interrupts. Fortunately we should have MSI on all ilk+.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++---------------------
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 63ae60ec2324..39927b71982e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2901,24 +2901,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
I915_WRITE(SERR_INT, 0xffffffff);
}
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled -
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_NOP(dev_priv))
- return;
-
- drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
- I915_WRITE(SDEIER, 0xffffffff);
- POSTING_READ(SDEIER);
-}
-
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3520,8 +3502,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
bxt_hpd_detection_setup(dev_priv);
}
+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled -
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 mask;
if (HAS_PCH_NOP(dev_priv))
@@ -3534,8 +3528,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
else
mask = SDE_GMBUS_CPT;
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
- I915_WRITE(SDEIMR, ~mask);
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3565,15 +3558,13 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~display_mask;
- ibx_irq_pre_postinstall(dev_priv);
+ ibx_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
display_mask | extra_mask);
gen5_gt_irq_postinstall(&dev_priv->gt);
- ibx_irq_postinstall(dev_priv);
-
if (IS_IRONLAKE_M(dev_priv)) {
/* Enable PCU event interrupts
*
@@ -3708,15 +3699,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_pre_postinstall(dev_priv);
-
- gen8_gt_irq_postinstall(&dev_priv->gt);
- gen8_de_irq_postinstall(dev_priv);
-
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
+ gen8_gt_irq_postinstall(&dev_priv->gt);
+ gen8_de_irq_postinstall(dev_priv);
+
gen8_master_intr_enable(dev_priv->uncore.regs);
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher cleanup around hpd pins and port identfiers
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (19 preceding siblings ...)
2020-10-06 14:33 ` [Intel-gfx] [PATCH 20/20] drm/i915: Get rid of ibx_irq_pre_postinstall() Ville Syrjala
@ 2020-10-06 15:21 ` Patchwork
2020-10-06 17:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3) Patchwork
` (3 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 15:21 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers
URL : https://patchwork.freedesktop.org/series/82411/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gvt/display.o
drivers/gpu/drm/i915/gvt/display.c: In function ‘emulate_monitor_status_change’:
drivers/gpu/drm/i915/gvt/display.c:176:44: error: ‘BXT_DE_PORT_HP_DDIA’ undeclared (first use in this function); did you mean ‘TGL_DE_PORT_AUX_DDIA’?
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
^~~~~~~~~~~~~~~~~~~
TGL_DE_PORT_AUX_DDIA
drivers/gpu/drm/i915/gvt/display.c:176:44: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gvt/display.c:177:4: error: ‘BXT_DE_PORT_HP_DDIB’ undeclared (first use in this function); did you mean ‘BXT_DE_PORT_HP_DDIA’?
BXT_DE_PORT_HP_DDIB |
^~~~~~~~~~~~~~~~~~~
BXT_DE_PORT_HP_DDIA
drivers/gpu/drm/i915/gvt/display.c:178:4: error: ‘BXT_DE_PORT_HP_DDIC’ undeclared (first use in this function); did you mean ‘BXT_DE_PORT_HP_DDIB’?
BXT_DE_PORT_HP_DDIC);
^~~~~~~~~~~~~~~~~~~
BXT_DE_PORT_HP_DDIB
drivers/gpu/drm/i915/gvt/display.c:330:5: error: ‘GEN8_PORT_DP_A_HOTPLUG’ undeclared (first use in this function); did you mean ‘DE_DP_A_HOTPLUG’?
GEN8_PORT_DP_A_HOTPLUG;
^~~~~~~~~~~~~~~~~~~~~~
DE_DP_A_HOTPLUG
scripts/Makefile.build:283: recipe for target 'drivers/gpu/drm/i915/gvt/display.o' failed
make[4]: *** [drivers/gpu/drm/i915/gvt/display.o] Error 1
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1784: recipe for target 'drivers' failed
make: *** [drivers] Error 2
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^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (20 preceding siblings ...)
2020-10-06 15:21 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher cleanup around hpd pins and port identfiers Patchwork
@ 2020-10-06 17:07 ` Patchwork
2020-10-06 17:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
24 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 17:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac8d5caeb9e4 drm/i915: Sort the mess around ICP TC hotplugs regs
c825eca75000 drm/i915: s/PORT_TC/TC_PORT_TC/
-:310: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#310: FILE: drivers/gpu/drm/i915/i915_reg.h:10286:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_TC4 ? \
(tc_port) + 12 : \
+ (tc_port) - TC_PORT_TC4 + 21))
total: 0 errors, 0 warnings, 1 checks, 269 lines checked
febabec5fc30 drm/i915: Add PORT_TCn aliases to enum port
0fd1b45546eb drm/i915: Give DDI encoders even better names
-:43: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5183:
+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
-:53: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5193:
+ tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1');
total: 0 errors, 2 warnings, 0 checks, 33 lines checked
944768cafe11 drm/i915: Introduce AUX_CH_USBCn
79ead29c1550 drm/i915: Pimp AUX CH names
b5d260d99ea5 drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
609d459a8656 drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
504b3a46f276 drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
a0f5f533ef42 drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
e280cadea053 drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
58484246fe9e drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
2cf3a3a5de78 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
2f1980b7acec drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
913dadb8c216 drm/i915: Don't enable hpd detection logic from irq_postinstall()
e17684d1f041 drm/i915: Rename 'tmp_mask'
ff428055fb0d drm/i915: Remove the per-plaform IIR HPD masking
-:68: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#68: FILE: drivers/gpu/drm/i915/i915_reg.h:8325:
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
total: 1 errors, 0 warnings, 0 checks, 47 lines checked
6dc728777193 drm/i915: Enable hpd logic only for ports that are present
54780a93e89d drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
d239f4c5ab84 drm/i915: Get rid of ibx_irq_pre_postinstall()
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^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (21 preceding siblings ...)
2020-10-06 17:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3) Patchwork
@ 2020-10-06 17:08 ` Patchwork
2020-10-06 17:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 21:52 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
24 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 17:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
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^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (22 preceding siblings ...)
2020-10-06 17:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-06 17:29 ` Patchwork
2020-10-06 21:52 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
24 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 17:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5847 bytes --]
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18640
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/index.html
Known issues
------------
Here are the changes found in Patchwork_18640 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][7] ([i915#2203]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-skl-guc/igt@vgem_basic@unload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-skl-guc/igt@vgem_basic@unload.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_9104 -> Patchwork_18640
CI-20190529: 20190529
CI_DRM_9104: 9cca7a33b0ebfaa5e0e86098b38eb7508097936a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5802: 0e4fbc60ca5ad6585e642d2ddf8313f3c738426e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18640: d239f4c5ab844c0c026616f66649fd9ab9ccde9d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d239f4c5ab84 drm/i915: Get rid of ibx_irq_pre_postinstall()
54780a93e89d drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
6dc728777193 drm/i915: Enable hpd logic only for ports that are present
ff428055fb0d drm/i915: Remove the per-plaform IIR HPD masking
e17684d1f041 drm/i915: Rename 'tmp_mask'
913dadb8c216 drm/i915: Don't enable hpd detection logic from irq_postinstall()
2f1980b7acec drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
2cf3a3a5de78 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
58484246fe9e drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
e280cadea053 drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
a0f5f533ef42 drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
504b3a46f276 drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
609d459a8656 drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
b5d260d99ea5 drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
79ead29c1550 drm/i915: Pimp AUX CH names
944768cafe11 drm/i915: Introduce AUX_CH_USBCn
0fd1b45546eb drm/i915: Give DDI encoders even better names
febabec5fc30 drm/i915: Add PORT_TCn aliases to enum port
c825eca75000 drm/i915: s/PORT_TC/TC_PORT_TC/
ac8d5caeb9e4 drm/i915: Sort the mess around ICP TC hotplugs regs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
2020-10-06 14:33 [Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
` (23 preceding siblings ...)
2020-10-06 17:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-06 21:52 ` Patchwork
24 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 21:52 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18640_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18640_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18640_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18640_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_vblank@pipe-a-query-forked-hang:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-hsw5/igt@kms_vblank@pipe-a-query-forked-hang.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-hsw2/igt@kms_vblank@pipe-a-query-forked-hang.html
#### Warnings ####
* igt@gem_exec_create@madvise:
- shard-hsw: [FAIL][3] ([i915#1888]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-hsw8/igt@gem_exec_create@madvise.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-hsw6/igt@gem_exec_create@madvise.html
### Piglit changes ###
#### Possible regressions ####
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-ivec4-ivec4 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][5] +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-ivec4-ivec4.html
New tests
---------
New tests have been introduced between CI_DRM_9104_full and Patchwork_18640_full:
### New Piglit tests (8) ###
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-greaterthan-ivec4-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-neg-int-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-ivec4-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitxor-abs-neg-ivec4-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-neg-ivec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-mat2x3-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-mat3-mat3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-pow-float-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18640_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2389]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-glk5/igt@gem_exec_reloc@basic-many-active@vecs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-glk3/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-glk6/igt@gem_exec_whisper@basic-contexts-forked.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1436] / [i915#716])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl4/igt@gen9_exec_parse@allowed-all.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl9/igt@gen9_exec_parse@allowed-all.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-kbl: [PASS][12] -> [INCOMPLETE][13] ([i915#155] / [i915#794])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-kbl2/igt@i915_suspend@fence-restore-tiled2untiled.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-kbl1/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-kbl7/igt@kms_big_fb@linear-8bpp-rotate-180.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-kbl1/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-hsw: [PASS][16] -> [DMESG-WARN][17] ([i915#1982])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-hsw7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [PASS][18] -> [INCOMPLETE][19] ([i915#198])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl9/igt@kms_flip@flip-vs-suspend@c-edp1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl6/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][20] -> [FAIL][21] ([i915#2122])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-tglb: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
- shard-iclb: [PASS][24] -> [DMESG-WARN][25] ([i915#1982])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#49])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +7 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#49])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl3/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl3/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#1188])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#648])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][36] -> [FAIL][37] ([fdo#108145] / [i915#265]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][38] -> [SKIP][39] ([fdo#109441]) +4 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-iclb2/igt@kms_psr@psr2_dpms.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-iclb5/igt@kms_psr@psr2_dpms.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][40] ([i915#658]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-iclb8/igt@feature_discovery@psr2.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@file:
- shard-skl: [TIMEOUT][42] ([i915#2544]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl5/igt@gem_ctx_persistence@file.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl8/igt@gem_ctx_persistence@file.html
* igt@gem_ctx_shared@q-independent@vecs0:
- shard-skl: [DMESG-WARN][44] ([i915#2544]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl5/igt@gem_ctx_shared@q-independent@vecs0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl8/igt@gem_ctx_shared@q-independent@vecs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][46] ([i915#454]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* {igt@kms_async_flips@alternate-sync-async-flip}:
- shard-apl: [FAIL][48] ([i915#1635] / [i915#2521]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-apl: [DMESG-WARN][50] ([i915#1635] / [i915#1982]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-apl6/igt@kms_big_fb@linear-8bpp-rotate-180.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-apl6/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- shard-skl: [DMESG-WARN][52] ([i915#1982]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl5/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl8/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][54] ([i915#79]) -> [PASS][55] +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1:
- shard-kbl: [FAIL][56] ([i915#2122]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-kbl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@b-edp1:
- shard-skl: [FAIL][58] ([i915#2122]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl1/igt@kms_flip@plain-flip-ts-check@b-edp1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl1/igt@kms_flip@plain-flip-ts-check@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-tglb: [DMESG-WARN][60] ([i915#1982]) -> [PASS][61] +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [INCOMPLETE][62] ([i915#198]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [DMESG-WARN][64] ([i915#180]) -> [PASS][65] +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][66] ([fdo#109441]) -> [PASS][67] +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][68] ([i915#1542]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl2/igt@perf@polling-parameterized.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl9/igt@perf@polling-parameterized.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][70] ([i915#1731]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-skl7/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-skl10/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-tglb: [INCOMPLETE][72] ([i915#2411]) -> [DMESG-WARN][73] ([i915#2411])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-tglb6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-tglb5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_suspend@forcewake:
- shard-tglb: [DMESG-WARN][74] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411]) -> [INCOMPLETE][75] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411] / [i915#456])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-tglb2/igt@i915_suspend@forcewake.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-tglb1/igt@i915_suspend@forcewake.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [DMESG-WARN][76] ([i915#2411]) -> [INCOMPLETE][77] ([i915#1436] / [i915#1982])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9104/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2544]: https://gitlab.freedesktop.org/drm/intel/issues/2544
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9104 -> Patchwork_18640
CI-20190529: 20190529
CI_DRM_9104: 9cca7a33b0ebfaa5e0e86098b38eb7508097936a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5802: 0e4fbc60ca5ad6585e642d2ddf8313f3c738426e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18640: d239f4c5ab844c0c026616f66649fd9ab9ccde9d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18640/index.html
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