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From: Yong Wu <yong.wu@mediatek.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Joerg Roedel <joro@8bytes.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	Will Deacon <will@kernel.org>, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>, <youlin.pei@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
	<chao.hao@mediatek.com>, <ming-fan.chen@mediatek.com>,
	Greg Kroah-Hartman <gregkh@google.com>, <kernel-team@android.com>
Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Mon, 26 Oct 2020 15:41:23 +0800	[thread overview]
Message-ID: <1603698083.26323.87.camel@mhfsdcap03> (raw)
In-Reply-To: <a5713949-1d95-40f1-d35d-d99735b48294@arm.com>

On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> >   drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> >   drivers/iommu/mtk_iommu.c          |  2 +-
> >   2 files changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> >    */
> >   #define ARM_V7S_ADDR_BITS		32
> >   #define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
> > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> > +#define _ARM_V7S_LVL_BITS_MTK(lvl)	(20 - (lvl) * 6)
> 
> This should defined in terms of both lvl and cfg->ias. The formula here 
> is nothing more than a disgusting trick I made up since a linear 
> interpolation happened to fit the required numbers. That said, all of 
> these bits pretending that short-descriptor is a well-defined recursive 
> format only served to allow the rest of the code to look more like the 
> LPAE code - IIRC they've already diverged a fair bit since then, so 
> frankly a lot of this could stand to be unpicked and made considerably 
> clearer by simply accepting that level 1 and level 2 are different from 
> each other.

If the formula is not good and make it clearer, How about this?


/*
 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
2,
-* and 12 bits in a page. With some carefully-chosen coefficients we can
-* hide the ugly inconsistencies behind these macros and at least let
the
-* rest of the code pretend to be somewhat sane.
+* and 12 bits in a page.
+*
+* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
at lvl2.
 */

-#define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
+#define _ARM_V7S_LVL1_BITS_NR(cfg)     (((cfg)->ias == 32) ? 12 : 14)
+#define _ARM_V7S_LVL2_BITS_NR		8
+
+#define _ARM_V7S_LVL_BITS(lvl, cfg)    \
+      (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)

> Robin.
> 
> >   #define ARM_V7S_LVL_SHIFT(lvl)		(ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> >   #define ARM_V7S_TABLE_SHIFT		10
> >   
> > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	(1 << _ARM_V7S_LVL_BITS(lvl))
> > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	({				\
> > +	int _lvl = lvl;							\
> > +	!arm_v7s_is_mtk_enabled(cfg) ?					\
> > +	 (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> > +})
> > +
> >   #define ARM_V7S_TABLE_SIZE(lvl, cfg)					\
> >   	(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
> >   
> > @@ -63,7 +70,7 @@
> >   #define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> >   #define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({			\
> >   	int _l = lvl;							\
> > -	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > +	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> >   })
> >   
> >   /*
> > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> >   {
> >   	struct arm_v7s_io_pgtable *data;
> >   
> > -	if (cfg->ias > ARM_V7S_ADDR_BITS)
> > +	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> >   		return NULL;
> >   
> >   	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index f6a2e3eb59d2..6e85c9976a33 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> >   			IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> >   			IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> >   		.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> > -		.ias = 32,
> > +		.ias = 34,
> >   		.oas = 35,
> >   		.tlb = &mtk_iommu_flush_ops,
> >   		.iommu_dev = data->dev,
> > 


WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream@mediatek.com, chao.hao@mediatek.com,
	kernel-team@android.com, Greg Kroah-Hartman <gregkh@google.com>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Mon, 26 Oct 2020 15:41:23 +0800	[thread overview]
Message-ID: <1603698083.26323.87.camel@mhfsdcap03> (raw)
In-Reply-To: <a5713949-1d95-40f1-d35d-d99735b48294@arm.com>

On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> >   drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> >   drivers/iommu/mtk_iommu.c          |  2 +-
> >   2 files changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> >    */
> >   #define ARM_V7S_ADDR_BITS		32
> >   #define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
> > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> > +#define _ARM_V7S_LVL_BITS_MTK(lvl)	(20 - (lvl) * 6)
> 
> This should defined in terms of both lvl and cfg->ias. The formula here 
> is nothing more than a disgusting trick I made up since a linear 
> interpolation happened to fit the required numbers. That said, all of 
> these bits pretending that short-descriptor is a well-defined recursive 
> format only served to allow the rest of the code to look more like the 
> LPAE code - IIRC they've already diverged a fair bit since then, so 
> frankly a lot of this could stand to be unpicked and made considerably 
> clearer by simply accepting that level 1 and level 2 are different from 
> each other.

If the formula is not good and make it clearer, How about this?


/*
 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
2,
-* and 12 bits in a page. With some carefully-chosen coefficients we can
-* hide the ugly inconsistencies behind these macros and at least let
the
-* rest of the code pretend to be somewhat sane.
+* and 12 bits in a page.
+*
+* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
at lvl2.
 */

-#define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
+#define _ARM_V7S_LVL1_BITS_NR(cfg)     (((cfg)->ias == 32) ? 12 : 14)
+#define _ARM_V7S_LVL2_BITS_NR		8
+
+#define _ARM_V7S_LVL_BITS(lvl, cfg)    \
+      (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)

> Robin.
> 
> >   #define ARM_V7S_LVL_SHIFT(lvl)		(ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> >   #define ARM_V7S_TABLE_SHIFT		10
> >   
> > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	(1 << _ARM_V7S_LVL_BITS(lvl))
> > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	({				\
> > +	int _lvl = lvl;							\
> > +	!arm_v7s_is_mtk_enabled(cfg) ?					\
> > +	 (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> > +})
> > +
> >   #define ARM_V7S_TABLE_SIZE(lvl, cfg)					\
> >   	(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
> >   
> > @@ -63,7 +70,7 @@
> >   #define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> >   #define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({			\
> >   	int _l = lvl;							\
> > -	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > +	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> >   })
> >   
> >   /*
> > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> >   {
> >   	struct arm_v7s_io_pgtable *data;
> >   
> > -	if (cfg->ias > ARM_V7S_ADDR_BITS)
> > +	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> >   		return NULL;
> >   
> >   	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index f6a2e3eb59d2..6e85c9976a33 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> >   			IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> >   			IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> >   		.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> > -		.ias = 32,
> > +		.ias = 34,
> >   		.oas = 35,
> >   		.tlb = &mtk_iommu_flush_ops,
> >   		.iommu_dev = data->dev,
> > 

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream@mediatek.com, chao.hao@mediatek.com,
	kernel-team@android.com, Joerg Roedel <joro@8bytes.org>,
	Greg Kroah-Hartman <gregkh@google.com>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Mon, 26 Oct 2020 15:41:23 +0800	[thread overview]
Message-ID: <1603698083.26323.87.camel@mhfsdcap03> (raw)
In-Reply-To: <a5713949-1d95-40f1-d35d-d99735b48294@arm.com>

On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> >   drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> >   drivers/iommu/mtk_iommu.c          |  2 +-
> >   2 files changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> >    */
> >   #define ARM_V7S_ADDR_BITS		32
> >   #define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
> > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> > +#define _ARM_V7S_LVL_BITS_MTK(lvl)	(20 - (lvl) * 6)
> 
> This should defined in terms of both lvl and cfg->ias. The formula here 
> is nothing more than a disgusting trick I made up since a linear 
> interpolation happened to fit the required numbers. That said, all of 
> these bits pretending that short-descriptor is a well-defined recursive 
> format only served to allow the rest of the code to look more like the 
> LPAE code - IIRC they've already diverged a fair bit since then, so 
> frankly a lot of this could stand to be unpicked and made considerably 
> clearer by simply accepting that level 1 and level 2 are different from 
> each other.

If the formula is not good and make it clearer, How about this?


/*
 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
2,
-* and 12 bits in a page. With some carefully-chosen coefficients we can
-* hide the ugly inconsistencies behind these macros and at least let
the
-* rest of the code pretend to be somewhat sane.
+* and 12 bits in a page.
+*
+* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
at lvl2.
 */

-#define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
+#define _ARM_V7S_LVL1_BITS_NR(cfg)     (((cfg)->ias == 32) ? 12 : 14)
+#define _ARM_V7S_LVL2_BITS_NR		8
+
+#define _ARM_V7S_LVL_BITS(lvl, cfg)    \
+      (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)

> Robin.
> 
> >   #define ARM_V7S_LVL_SHIFT(lvl)		(ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> >   #define ARM_V7S_TABLE_SHIFT		10
> >   
> > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	(1 << _ARM_V7S_LVL_BITS(lvl))
> > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	({				\
> > +	int _lvl = lvl;							\
> > +	!arm_v7s_is_mtk_enabled(cfg) ?					\
> > +	 (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> > +})
> > +
> >   #define ARM_V7S_TABLE_SIZE(lvl, cfg)					\
> >   	(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
> >   
> > @@ -63,7 +70,7 @@
> >   #define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> >   #define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({			\
> >   	int _l = lvl;							\
> > -	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > +	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> >   })
> >   
> >   /*
> > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> >   {
> >   	struct arm_v7s_io_pgtable *data;
> >   
> > -	if (cfg->ias > ARM_V7S_ADDR_BITS)
> > +	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> >   		return NULL;
> >   
> >   	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index f6a2e3eb59d2..6e85c9976a33 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> >   			IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> >   			IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> >   		.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> > -		.ias = 32,
> > +		.ias = 34,
> >   		.oas = 35,
> >   		.tlb = &mtk_iommu_flush_ops,
> >   		.iommu_dev = data->dev,
> > 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream@mediatek.com, chao.hao@mediatek.com,
	kernel-team@android.com, Joerg Roedel <joro@8bytes.org>,
	Greg Kroah-Hartman <gregkh@google.com>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Mon, 26 Oct 2020 15:41:23 +0800	[thread overview]
Message-ID: <1603698083.26323.87.camel@mhfsdcap03> (raw)
In-Reply-To: <a5713949-1d95-40f1-d35d-d99735b48294@arm.com>

On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> >   drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> >   drivers/iommu/mtk_iommu.c          |  2 +-
> >   2 files changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> >    */
> >   #define ARM_V7S_ADDR_BITS		32
> >   #define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
> > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> > +#define _ARM_V7S_LVL_BITS_MTK(lvl)	(20 - (lvl) * 6)
> 
> This should defined in terms of both lvl and cfg->ias. The formula here 
> is nothing more than a disgusting trick I made up since a linear 
> interpolation happened to fit the required numbers. That said, all of 
> these bits pretending that short-descriptor is a well-defined recursive 
> format only served to allow the rest of the code to look more like the 
> LPAE code - IIRC they've already diverged a fair bit since then, so 
> frankly a lot of this could stand to be unpicked and made considerably 
> clearer by simply accepting that level 1 and level 2 are different from 
> each other.

If the formula is not good and make it clearer, How about this?


/*
 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
2,
-* and 12 bits in a page. With some carefully-chosen coefficients we can
-* hide the ugly inconsistencies behind these macros and at least let
the
-* rest of the code pretend to be somewhat sane.
+* and 12 bits in a page.
+*
+* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
at lvl2.
 */

-#define _ARM_V7S_LVL_BITS(lvl)		(16 - (lvl) * 4)
+#define _ARM_V7S_LVL1_BITS_NR(cfg)     (((cfg)->ias == 32) ? 12 : 14)
+#define _ARM_V7S_LVL2_BITS_NR		8
+
+#define _ARM_V7S_LVL_BITS(lvl, cfg)    \
+      (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)

> Robin.
> 
> >   #define ARM_V7S_LVL_SHIFT(lvl)		(ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> >   #define ARM_V7S_TABLE_SHIFT		10
> >   
> > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	(1 << _ARM_V7S_LVL_BITS(lvl))
> > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg)	({				\
> > +	int _lvl = lvl;							\
> > +	!arm_v7s_is_mtk_enabled(cfg) ?					\
> > +	 (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> > +})
> > +
> >   #define ARM_V7S_TABLE_SIZE(lvl, cfg)					\
> >   	(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
> >   
> > @@ -63,7 +70,7 @@
> >   #define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> >   #define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({			\
> >   	int _l = lvl;							\
> > -	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > +	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> >   })
> >   
> >   /*
> > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> >   {
> >   	struct arm_v7s_io_pgtable *data;
> >   
> > -	if (cfg->ias > ARM_V7S_ADDR_BITS)
> > +	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> >   		return NULL;
> >   
> >   	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index f6a2e3eb59d2..6e85c9976a33 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> >   			IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> >   			IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> >   		.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> > -		.ias = 32,
> > +		.ias = 34,
> >   		.oas = 35,
> >   		.tlb = &mtk_iommu_flush_ops,
> >   		.iommu_dev = data->dev,
> > 

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  reply	other threads:[~2020-10-26  7:42 UTC|newest]

Thread overview: 213+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-30  7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
2020-09-30  7:06 ` Yong Wu
2020-09-30  7:06 ` Yong Wu
2020-09-30  7:06 ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-02 10:58   ` Krzysztof Kozlowski
2020-10-02 10:58     ` Krzysztof Kozlowski
2020-10-02 10:58     ` Krzysztof Kozlowski
2020-10-02 10:58     ` Krzysztof Kozlowski
2020-10-30  9:47     ` Yong Wu
2020-10-02 11:07   ` Krzysztof Kozlowski
2020-10-02 11:07     ` Krzysztof Kozlowski
2020-10-02 11:07     ` Krzysztof Kozlowski
2020-10-02 11:07     ` Krzysztof Kozlowski
2020-10-06  4:26     ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-12 17:08       ` Krzysztof Kozlowski
2020-10-12 17:08         ` Krzysztof Kozlowski
2020-10-12 17:08         ` Krzysztof Kozlowski
2020-10-12 17:08         ` Krzysztof Kozlowski
2020-10-13  7:53         ` Yong Wu
2020-10-13  7:53           ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-02 11:04   ` Krzysztof Kozlowski
2020-10-02 11:04     ` Krzysztof Kozlowski
2020-10-02 11:04     ` Krzysztof Kozlowski
2020-10-02 11:04     ` Krzysztof Kozlowski
2020-10-02 11:08   ` Krzysztof Kozlowski
2020-10-02 11:08     ` Krzysztof Kozlowski
2020-10-02 11:08     ` Krzysztof Kozlowski
2020-10-02 11:08     ` Krzysztof Kozlowski
2020-10-06  4:27     ` Yong Wu
2020-10-06  4:27       ` Yong Wu
2020-10-06  4:27       ` Yong Wu
2020-10-06  4:27       ` Yong Wu
2020-10-06  7:15       ` Krzysztof Kozlowski
2020-10-06  7:15         ` Krzysztof Kozlowski
2020-10-06  7:15         ` Krzysztof Kozlowski
2020-10-06  7:15         ` Krzysztof Kozlowski
2020-10-10  6:18         ` Yong Wu
2020-10-10  6:18           ` Yong Wu
2020-10-10  6:18           ` Yong Wu
2020-10-10  6:18           ` Yong Wu
2020-10-12  7:18           ` Krzysztof Kozlowski
2020-10-12  7:18             ` Krzysztof Kozlowski
2020-10-12  7:18             ` Krzysztof Kozlowski
2020-10-12  7:18             ` Krzysztof Kozlowski
2020-10-12 12:01             ` Yong Wu
2020-10-12 12:01               ` Yong Wu
2020-10-12 12:01               ` Yong Wu
2020-10-12 12:01               ` Yong Wu
2020-10-12 13:26               ` Krzysztof Kozlowski
2020-10-12 13:26                 ` Krzysztof Kozlowski
2020-10-12 13:26                 ` Krzysztof Kozlowski
2020-10-12 13:26                 ` Krzysztof Kozlowski
2020-10-13  7:53                 ` Yong Wu
2020-10-13  7:53                   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 03/24] dt-bindings: memory: mediatek: Add a common larb-port header file Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 04/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 05/24] dt-bindings: memory: mediatek: Add domain definition Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-02 11:10   ` Krzysztof Kozlowski
2020-10-02 11:10     ` Krzysztof Kozlowski
2020-10-02 11:10     ` Krzysztof Kozlowski
2020-10-02 11:10     ` Krzysztof Kozlowski
2020-10-06  4:26     ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-06  4:26       ` Yong Wu
2020-10-06  7:19       ` Krzysztof Kozlowski
2020-10-06  7:19         ` Krzysztof Kozlowski
2020-10-06  7:19         ` Krzysztof Kozlowski
2020-10-06  7:19         ` Krzysztof Kozlowski
2020-09-30  7:06 ` [PATCH v3 07/24] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-23 11:17   ` Will Deacon
2020-10-23 11:17     ` Will Deacon
2020-10-23 11:17     ` Will Deacon
2020-10-23 11:17     ` Will Deacon
2020-10-26  7:49     ` Yong Wu
2020-10-26  7:49       ` Yong Wu
2020-10-26  7:49       ` Yong Wu
2020-10-26  7:49       ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-23 11:22   ` Will Deacon
2020-10-23 11:22     ` Will Deacon
2020-10-23 11:22     ` Will Deacon
2020-10-23 11:22     ` Will Deacon
2020-09-30  7:06 ` [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-23 11:23   ` Will Deacon
2020-10-23 11:23     ` Will Deacon
2020-10-23 11:23     ` Will Deacon
2020-10-23 11:23     ` Will Deacon
2020-09-30  7:06 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-23 11:21   ` Will Deacon
2020-10-23 11:21     ` Will Deacon
2020-10-23 11:21     ` Will Deacon
2020-10-23 11:21     ` Will Deacon
2020-10-26  7:45     ` Yong Wu
2020-10-26  7:45       ` Yong Wu
2020-10-26  7:45       ` Yong Wu
2020-10-26  7:45       ` Yong Wu
2020-10-23 14:10   ` Robin Murphy
2020-10-23 14:10     ` Robin Murphy
2020-10-23 14:10     ` Robin Murphy
2020-10-23 14:10     ` Robin Murphy
2020-10-26  7:41     ` Yong Wu [this message]
2020-10-26  7:41       ` Yong Wu
2020-10-26  7:41       ` Yong Wu
2020-10-26  7:41       ` Yong Wu
2020-10-26 11:35       ` Robin Murphy
2020-10-26 11:35         ` Robin Murphy
2020-10-26 11:35         ` Robin Murphy
2020-10-26 11:35         ` Robin Murphy
2020-09-30  7:06 ` [PATCH v3 12/24] iommu/mediatek: Move hw_init into attach_device Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 13/24] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 14/24] iommu/mediatek: Add pm runtime callback Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 15/24] iommu/mediatek: Add power-domain operation Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 16/24] iommu/mediatek: Add iova reserved function Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 17/24] iommu/mediatek: Add single domain Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-06  7:18   ` Krzysztof Kozlowski
2020-10-06  7:18     ` Krzysztof Kozlowski
2020-10-06  7:18     ` Krzysztof Kozlowski
2020-10-06  7:18     ` Krzysztof Kozlowski
2020-09-30  7:06 ` [PATCH v3 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 21/24] iommu/mediatek: Add support for multi domain Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 22/24] iommu/mediatek: Adjust the structure Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 23/24] iommu/mediatek: Add mt8192 support Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06 ` [PATCH v3 24/24] memory: mtk-smi: " Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-09-30  7:06   ` Yong Wu
2020-10-02 11:15   ` Krzysztof Kozlowski
2020-10-02 11:15     ` Krzysztof Kozlowski
2020-10-02 11:15     ` Krzysztof Kozlowski
2020-10-02 11:15     ` Krzysztof Kozlowski
2020-10-26 20:08 ` [PATCH v3 00/24] MT8192 IOMMU support Krzysztof Kozlowski
2020-10-26 20:08   ` Krzysztof Kozlowski
2020-10-26 20:08   ` Krzysztof Kozlowski
2020-10-26 20:08   ` Krzysztof Kozlowski

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