* [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Start board support by adding initial support for the SiFive FU740 SoC
and the first development board that uses it, the SiFive HiFive
Unmatched A00.
Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
U-boot and OpenSBI.
This patch series is dependent on Zong's Patchset[0]. The patchset also
adds two new nodes in dtsi file. The binding documentation patch
for these nodes are already posted on the mailing list[1][2].
[0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
[1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
[2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
Changes in v2:
- The dt bindings patch is split into several individual patches.
- Expand the full list for compatible strings in i2c-ocores.txt
Yash Shah (9):
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: serial: Update DT binding docs to support SiFive FU740
SoC
dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
riscv: dts: add initial support for the SiFive FU740-C000 SoC
dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
board
riscv: dts: add initial board data for the SiFive HiFive Unmatched
.../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
.../devicetree/bindings/i2c/i2c-ocores.txt | 8 +-
.../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
.../devicetree/bindings/riscv/sifive.yaml | 17 +-
.../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
.../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
arch/riscv/boot/dts/sifive/Makefile | 3 +-
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
10 files changed, 590 insertions(+), 17 deletions(-)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv # Simulator only
description:
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv # Simulator only
description:
--
2.7.4
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:55 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:55 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, broonie, linux-riscv, linux-i2c,
lee.jones, linux-kernel, palmer, linux-gpio, peter, robh+dt,
paul.walmsley, aou, u.kleine-koenig, bgolaszewski, gregkh,
thierry.reding, linux-pwm, linus.walleij, andrew, devicetree
On Tue, 08 Dec 2020 10:25:33 +0530, Yash Shah wrote:
> Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
> cores ("harts") that are present on FU740-C000 SoC.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 3:55 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:55 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, peter, aou, bgolaszewski, gregkh, linus.walleij,
u.kleine-koenig, linux-kernel, robh+dt, linux-spi, andrew,
linux-gpio, devicetree, broonie, palmer, linux-i2c, linux-serial,
paul.walmsley, thierry.reding, linux-riscv, lee.jones
On Tue, 08 Dec 2020 10:25:33 +0530, Yash Shah wrote:
> Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
> cores ("harts") that are present on FU740-C000 SoC.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 13:34 ` Bin Meng
-1 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley,
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
> cores ("harts") that are present on FU740-C000 SoC.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 13:34 ` Bin Meng
0 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley,
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
> cores ("harts") that are present on FU740-C000 SoC.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 56dcf1d..6e7e394 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -17,15 +17,17 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-spi
+ - enum:
+ - sifive,fu540-c000-spi
+ - sifive,fu740-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
- "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
- onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
- SPI v0 IP block with no chip integration tweaks.
+ "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
+ as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
+ for the SiFive SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 56dcf1d..6e7e394 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -17,15 +17,17 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-spi
+ - enum:
+ - sifive,fu540-c000-spi
+ - sifive,fu740-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
- "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
- onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
- SPI v0 IP block with no chip integration tweaks.
+ "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
+ as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
+ for the SiFive SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v2 3/9] dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 5ac2527..84e6691 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- - const: sifive,fu540-c000-pwm
+ - enum:
+ - sifive,fu540-c000-pwm
+ - sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
- compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
- as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ compatible strings are "sifive,fu540-c000-pwm" and
+ "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
+ SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 3/9] dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 5ac2527..84e6691 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- - const: sifive,fu540-c000-pwm
+ - enum:
+ - sifive,fu540-c000-pwm
+ - sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
- compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
- as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ compatible strings are "sifive,fu540-c000-pwm" and
+ "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
+ SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 3/9] dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:56 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:56 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, gregkh, aou,
lee.jones, u.kleine-koenig, thierry.reding, andrew, peter,
paul.walmsley, palmer, bgolaszewski, linus.walleij
On Tue, Dec 08, 2020 at 10:25:35AM +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> index 5ac2527..84e6691 100644
> --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> @@ -25,12 +25,15 @@ description:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-pwm
> + - enum:
> + - sifive,fu540-c000-pwm
> + - sifive,fu740-c000-pwm
> - const: sifive,pwm0
> description:
> Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
> - compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
> - as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
> + compatible strings are "sifive,fu540-c000-pwm" and
> + "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
> + SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
Better if you reword this so we don't have to update it for every new
compatible.
> SiFive PWM v0 IP block with no chip integration tweaks.
> Please refer to sifive-blocks-ip-versioning.txt for details.
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 3:56 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:56 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, peter, aou, devicetree, gregkh, bgolaszewski,
paul.walmsley, linux-kernel, linux-spi, andrew, linux-gpio,
broonie, thierry.reding, linux-i2c, linux-serial,
u.kleine-koenig, palmer, linux-riscv, lee.jones, linus.walleij
On Tue, Dec 08, 2020 at 10:25:35AM +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> index 5ac2527..84e6691 100644
> --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> @@ -25,12 +25,15 @@ description:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-pwm
> + - enum:
> + - sifive,fu540-c000-pwm
> + - sifive,fu740-c000-pwm
> - const: sifive,pwm0
> description:
> Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
> - compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
> - as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
> + compatible strings are "sifive,fu540-c000-pwm" and
> + "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
> + SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
Better if you reword this so we don't have to update it for every new
compatible.
> SiFive PWM v0 IP block with no chip integration tweaks.
> Please refer to sifive-blocks-ip-versioning.txt for details.
>
> --
> 2.7.4
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 4/9] dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
index 92283f6..3ac5c7f 100644
--- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
+++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-uart
+ - enum:
+ - sifive,fu540-c000-uart
+ - sifive,fu740-c000-uart
- const: sifive,uart0
description:
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 4/9] dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
index 92283f6..3ac5c7f 100644
--- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
+++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-uart
+ - enum:
+ - sifive,fu540-c000-uart
+ - sifive,fu740-c000-uart
- const: sifive,uart0
description:
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 4/9] dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:56 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:56 UTC (permalink / raw)
To: Yash Shah
Cc: broonie, linux-kernel, linus.walleij, u.kleine-koenig, aou,
bgolaszewski, gregkh, peter, lee.jones, palmer, linux-pwm,
paul.walmsley, linux-serial, linux-spi, robh+dt, andrew,
devicetree, linux-riscv, linux-gpio, linux-i2c, thierry.reding
On Tue, 08 Dec 2020 10:25:36 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 4/9] dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 3:56 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:56 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, peter, aou, andrew, gregkh, linus.walleij,
paul.walmsley, linux-kernel, robh+dt, linux-spi, bgolaszewski,
devicetree, broonie, palmer, linux-i2c, linux-serial,
u.kleine-koenig, thierry.reding, linux-riscv, lee.jones,
linux-gpio
On Tue, 08 Dec 2020 10:25:36 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 5/9] dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
index a0efd8d..ab22056 100644
--- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
@@ -13,7 +13,9 @@ maintainers:
properties:
compatible:
items:
- - const: sifive,fu540-c000-gpio
+ - enum:
+ - sifive,fu540-c000-gpio
+ - sifive,fu740-c000-gpio
- const: sifive,gpio0
reg:
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 5/9] dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
index a0efd8d..ab22056 100644
--- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
@@ -13,7 +13,9 @@ maintainers:
properties:
compatible:
items:
- - const: sifive,fu540-c000-gpio
+ - enum:
+ - sifive,fu540-c000-gpio
+ - sifive,fu740-c000-gpio
- const: sifive,gpio0
reg:
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 5/9] dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:57 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:57 UTC (permalink / raw)
To: Yash Shah
Cc: thierry.reding, linux-i2c, gregkh, palmer, linux-spi, linux-pwm,
u.kleine-koenig, linux-kernel, robh+dt, broonie, bgolaszewski,
aou, paul.walmsley, linus.walleij, peter, andrew, linux-riscv,
devicetree, linux-serial, lee.jones, linux-gpio
On Tue, 08 Dec 2020 10:25:37 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 3:57 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:57 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, peter, aou, andrew, gregkh, broonie, paul.walmsley,
linux-kernel, robh+dt, linux-spi, bgolaszewski, devicetree,
thierry.reding, palmer, linux-i2c, linux-serial, u.kleine-koenig,
linux-riscv, lee.jones, linus.walleij, linux-gpio
On Tue, 08 Dec 2020 10:25:37 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 6b25a80..a37c945 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -5,8 +5,12 @@ Required properties:
"aeroflexgaisler,i2cmst"
"sifive,fu540-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
- FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
- for additional details.
+ FU540-C000 SoC.
+ "sifive,fu740-c000-i2c", "sifive,i2c0"
+ For Opencore based I2C IP block reimplemented in
+ FU740-C000 SoC.
+ Please refer to sifive-blocks-ip-versioning.txt for
+ additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
Mutually exclusive with opencores,ip-clock-frequency
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 6b25a80..a37c945 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -5,8 +5,12 @@ Required properties:
"aeroflexgaisler,i2cmst"
"sifive,fu540-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
- FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
- for additional details.
+ FU540-C000 SoC.
+ "sifive,fu740-c000-i2c", "sifive,i2c0"
+ For Opencore based I2C IP block reimplemented in
+ FU740-C000 SoC.
+ Please refer to sifive-blocks-ip-versioning.txt for
+ additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
Mutually exclusive with opencores,ip-clock-frequency
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:59 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:59 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, broonie, gregkh, linux-spi, robh+dt, u.kleine-koenig,
linux-kernel, lee.jones, linus.walleij, paul.walmsley,
devicetree, linux-serial, linux-riscv, peter, andrew, palmer,
linux-i2c, bgolaszewski, aou, thierry.reding, linux-gpio
On Tue, 08 Dec 2020 10:25:38 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-10 3:59 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:59 UTC (permalink / raw)
To: Yash Shah
Cc: thierry.reding, linux-pwm, peter, aou, devicetree, gregkh,
linus.walleij, paul.walmsley, linux-kernel, robh+dt, linux-spi,
bgolaszewski, broonie, andrew, linux-i2c, linux-serial,
u.kleine-koenig, palmer, linux-riscv, lee.jones, linux-gpio
On Tue, 08 Dec 2020 10:25:38 +0530, Yash Shah wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-22 3:23 ` Palmer Dabbelt
-1 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2020-12-22 3:23 UTC (permalink / raw)
To: yash.shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, Greg KH, aou,
lee.jones, u.kleine-koenig, thierry.reding, andrew, peter,
Paul Walmsley, robh+dt, bgolaszewski, linus.walleij, yash.shah
On Mon, 07 Dec 2020 20:55:38 PST (-0800), yash.shah@sifive.com wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> index 6b25a80..a37c945 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> @@ -5,8 +5,12 @@ Required properties:
> "aeroflexgaisler,i2cmst"
> "sifive,fu540-c000-i2c", "sifive,i2c0"
> For Opencore based I2C IP block reimplemented in
> - FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
> - for additional details.
> + FU540-C000 SoC.
> + "sifive,fu740-c000-i2c", "sifive,i2c0"
> + For Opencore based I2C IP block reimplemented in
> + FU740-C000 SoC.
> + Please refer to sifive-blocks-ip-versioning.txt for
> + additional details.
> - reg : bus address start and address range size of device
> - clocks : handle to the controller clock; see the note below.
> Mutually exclusive with opencores,ip-clock-frequency
Presumably this new one no longer has the interrupt bug? The current
implementation turns the errata off (it's only enabled for the fu540), so if
that's the case we should be good to go.
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
@ 2020-12-22 3:23 ` Palmer Dabbelt
0 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2020-12-22 3:23 UTC (permalink / raw)
To: yash.shah
Cc: linux-pwm, peter, aou, devicetree, Greg KH, linus.walleij,
Paul Walmsley, linux-kernel, robh+dt, linux-spi, andrew,
linux-gpio, yash.shah, broonie, thierry.reding, linux-i2c,
linux-serial, u.kleine-koenig, bgolaszewski, linux-riscv,
lee.jones
On Mon, 07 Dec 2020 20:55:38 PST (-0800), yash.shah@sifive.com wrote:
> Add new compatible strings to the DT binding documents to support SiFive
> FU740-C000.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> index 6b25a80..a37c945 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> @@ -5,8 +5,12 @@ Required properties:
> "aeroflexgaisler,i2cmst"
> "sifive,fu540-c000-i2c", "sifive,i2c0"
> For Opencore based I2C IP block reimplemented in
> - FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
> - for additional details.
> + FU540-C000 SoC.
> + "sifive,fu740-c000-i2c", "sifive,i2c0"
> + For Opencore based I2C IP block reimplemented in
> + FU740-C000 SoC.
> + Please refer to sifive-blocks-ip-versioning.txt for
> + additional details.
> - reg : bus address start and address range size of device
> - clocks : handle to the controller clock; see the note below.
> Mutually exclusive with opencores,ip-clock-frequency
Presumably this new one no longer has the interrupt bug? The current
implementation turns the errata off (it's only enabled for the fu540), so if
that's the case we should be good to go.
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
1 file changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
new file mode 100644
index 0000000..eeb4f8c3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&ccache>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <69>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu740-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <39>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <40>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ i2c1: i2c@10031000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10031000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <41>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ spi0: spi@10050000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <43>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <55>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <44>, <45>, <46>, <47>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <48>, <49>, <50>, <51>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ ccache: cache-controller@2010000 {
+ compatible = "sifive,fu740-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <19 20 21 22>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>, <31>, <32>, <33>, <34>, <35>, <36>,
+ <37>, <38>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
1 file changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
new file mode 100644
index 0000000..eeb4f8c3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&ccache>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <69>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu740-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <39>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <40>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ i2c1: i2c@10031000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10031000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <41>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ spi0: spi@10050000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <43>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <55>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <44>, <45>, <46>, <47>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <48>, <49>, <50>, <51>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ ccache: cache-controller@2010000 {
+ compatible = "sifive,fu740-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <19 20 21 22>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>, <31>, <32>, <33>, <34>, <35>, <36>,
+ <37>, <38>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 13:34 ` Bin Meng
-1 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley,
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
FU740-C000 Soc
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
> 1 file changed, 293 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> new file mode 100644
> index 0000000..eeb4f8c3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -0,0 +1,293 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sifive-fu740-prci.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu740-c000", "sifive,fu740";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + ethernet0 = ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,bullet0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + next-level-cache = <&ccache>;
> + reg = <0x0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x3>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu4: cpu@4 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x4>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> + plic0: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev = <69>;
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff
> + &cpu1_intc 0xffffffff &cpu1_intc 9
> + &cpu2_intc 0xffffffff &cpu2_intc 9
> + &cpu3_intc 0xffffffff &cpu3_intc 9
> + &cpu4_intc 0xffffffff &cpu4_intc 9>;
> + };
> + prci: clock-controller@10000000 {
> + compatible = "sifive,fu740-c000-prci";
> + reg = <0x0 0x10000000 0x0 0x1000>;
> + clocks = <&hfclk>, <&rtcclk>;
> + #clock-cells = <1>;
> + };
> + uart0: serial@10010000 {
> + compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10010000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <39>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + uart1: serial@10011000 {
> + compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10011000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <40>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + i2c0: i2c@10030000 {
> + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
> + reg = <0x0 0x10030000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <52>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + reg-shift = <2>;
> + reg-io-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + i2c1: i2c@10031000 {
> + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
> + reg = <0x0 0x10031000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <53>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + reg-shift = <2>;
> + reg-io-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + qspi0: spi@10040000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10040000 0x0 0x1000>,
> + <0x0 0x20000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <41>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + qspi1: spi@10041000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10041000 0x0 0x1000>,
> + <0x0 0x30000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <42>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + spi0: spi@10050000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10050000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <43>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + eth0: ethernet@10090000 {
> + compatible = "sifive,fu540-c000-gem";
"sifive,fu740-c000-gem"?
> + interrupt-parent = <&plic0>;
> + interrupts = <55>;
> + reg = <0x0 0x10090000 0x0 0x2000>,
> + <0x0 0x100a0000 0x0 0x1000>;
> + local-mac-address = [00 00 00 00 00 00];
> + clock-names = "pclk", "hclk";
> + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> + <&prci PRCI_CLK_GEMGXLPLL>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + pwm0: pwm@10020000 {
> + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> + reg = <0x0 0x10020000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <44>, <45>, <46>, <47>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> + pwm1: pwm@10021000 {
> + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> + reg = <0x0 0x10021000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <48>, <49>, <50>, <51>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> + ccache: cache-controller@2010000 {
> + compatible = "sifive,fu740-c000-ccache", "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + interrupt-parent = <&plic0>;
> + interrupts = <19 20 21 22>;
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + };
> + gpio: gpio@10060000 {
> + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
> + interrupt-parent = <&plic0>;
> + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> + <30>, <31>, <32>, <33>, <34>, <35>, <36>,
> + <37>, <38>;
> + reg = <0x0 0x10060000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + };
> +};
Regards,
Bin
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2020-12-10 13:34 ` Bin Meng
0 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley,
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
FU740-C000 Soc
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
> 1 file changed, 293 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> new file mode 100644
> index 0000000..eeb4f8c3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -0,0 +1,293 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sifive-fu740-prci.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu740-c000", "sifive,fu740";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + ethernet0 = ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,bullet0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + next-level-cache = <&ccache>;
> + reg = <0x0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x3>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu4: cpu@4 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x4>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> + plic0: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev = <69>;
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff
> + &cpu1_intc 0xffffffff &cpu1_intc 9
> + &cpu2_intc 0xffffffff &cpu2_intc 9
> + &cpu3_intc 0xffffffff &cpu3_intc 9
> + &cpu4_intc 0xffffffff &cpu4_intc 9>;
> + };
> + prci: clock-controller@10000000 {
> + compatible = "sifive,fu740-c000-prci";
> + reg = <0x0 0x10000000 0x0 0x1000>;
> + clocks = <&hfclk>, <&rtcclk>;
> + #clock-cells = <1>;
> + };
> + uart0: serial@10010000 {
> + compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10010000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <39>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + uart1: serial@10011000 {
> + compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10011000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <40>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + i2c0: i2c@10030000 {
> + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
> + reg = <0x0 0x10030000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <52>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + reg-shift = <2>;
> + reg-io-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + i2c1: i2c@10031000 {
> + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
> + reg = <0x0 0x10031000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <53>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + reg-shift = <2>;
> + reg-io-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + qspi0: spi@10040000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10040000 0x0 0x1000>,
> + <0x0 0x20000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <41>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + qspi1: spi@10041000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10041000 0x0 0x1000>,
> + <0x0 0x30000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <42>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + spi0: spi@10050000 {
> + compatible = "sifive,fu740-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10050000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <43>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + eth0: ethernet@10090000 {
> + compatible = "sifive,fu540-c000-gem";
"sifive,fu740-c000-gem"?
> + interrupt-parent = <&plic0>;
> + interrupts = <55>;
> + reg = <0x0 0x10090000 0x0 0x2000>,
> + <0x0 0x100a0000 0x0 0x1000>;
> + local-mac-address = [00 00 00 00 00 00];
> + clock-names = "pclk", "hclk";
> + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> + <&prci PRCI_CLK_GEMGXLPLL>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + pwm0: pwm@10020000 {
> + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> + reg = <0x0 0x10020000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <44>, <45>, <46>, <47>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> + pwm1: pwm@10021000 {
> + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> + reg = <0x0 0x10021000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <48>, <49>, <50>, <51>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> + ccache: cache-controller@2010000 {
> + compatible = "sifive,fu740-c000-ccache", "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + interrupt-parent = <&plic0>;
> + interrupts = <19 20 21 22>;
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + };
> + gpio: gpio@10060000 {
> + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
> + interrupt-parent = <&plic0>;
> + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> + <30>, <31>, <32>, <33>, <34>, <35>, <36>,
> + <37>, <38>;
> + reg = <0x0 0x10060000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&prci PRCI_CLK_PCLK>;
> + status = "disabled";
> + };
> + };
> +};
Regards,
Bin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-10 13:34 ` Bin Meng
@ 2020-12-16 5:24 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-16 5:24 UTC (permalink / raw)
To: Bin Meng
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley ( Sifive),
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 10 December 2020 19:05
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
> >
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
>
> FU740-C000 Soc
>
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > +++++++++++++++++++++++++++++
> > 1 file changed, 293 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > new file mode 100644
> > index 0000000..eeb4f8c3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
...
> > + plic0: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + #address-cells = <0>;
> > + compatible = "sifive,fu540-c000-plic",
> > + "sifive,plic-1.0.0";
>
> I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
That's because it is not required. There won't be any difference in driver code for FU740 plic.
...
> > + eth0: ethernet@10090000 {
> > + compatible = "sifive,fu540-c000-gem";
>
> "sifive,fu740-c000-gem"?
>
Same reason as above.
Thanks for your review.
- Yash
> > + interrupt-parent = <&plic0>;
> > + interrupts = <55>;
> > + reg = <0x0 0x10090000 0x0 0x2000>,
> > + <0x0 0x100a0000 0x0 0x1000>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + clock-names = "pclk", "hclk";
> > + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> > + <&prci PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > + pwm0: pwm@10020000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10020000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <44>, <45>, <46>, <47>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + pwm1: pwm@10021000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10021000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <48>, <49>, <50>, <51>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + ccache: cache-controller@2010000 {
> > + compatible = "sifive,fu740-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <2048>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <19 20 21 22>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > + gpio: gpio@10060000 {
> > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
> > + interrupt-parent = <&plic0>;
> > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> > + <30>, <31>, <32>, <33>, <34>, <35>, <36>,
> > + <37>, <38>;
> > + reg = <0x0 0x10060000 0x0 0x1000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + status = "disabled";
> > + };
> > + };
> > +};
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 58+ messages in thread* RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2020-12-16 5:24 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-16 5:24 UTC (permalink / raw)
To: Bin Meng
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley ( Sifive),
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 10 December 2020 19:05
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
> >
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
>
> FU740-C000 Soc
>
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > +++++++++++++++++++++++++++++
> > 1 file changed, 293 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > new file mode 100644
> > index 0000000..eeb4f8c3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
...
> > + plic0: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + #address-cells = <0>;
> > + compatible = "sifive,fu540-c000-plic",
> > + "sifive,plic-1.0.0";
>
> I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
That's because it is not required. There won't be any difference in driver code for FU740 plic.
...
> > + eth0: ethernet@10090000 {
> > + compatible = "sifive,fu540-c000-gem";
>
> "sifive,fu740-c000-gem"?
>
Same reason as above.
Thanks for your review.
- Yash
> > + interrupt-parent = <&plic0>;
> > + interrupts = <55>;
> > + reg = <0x0 0x10090000 0x0 0x2000>,
> > + <0x0 0x100a0000 0x0 0x1000>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + clock-names = "pclk", "hclk";
> > + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> > + <&prci PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > + pwm0: pwm@10020000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10020000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <44>, <45>, <46>, <47>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + pwm1: pwm@10021000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10021000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <48>, <49>, <50>, <51>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + ccache: cache-controller@2010000 {
> > + compatible = "sifive,fu740-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <2048>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <19 20 21 22>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > + gpio: gpio@10060000 {
> > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
> > + interrupt-parent = <&plic0>;
> > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> > + <30>, <31>, <32>, <33>, <34>, <35>, <36>,
> > + <37>, <38>;
> > + reg = <0x0 0x10060000 0x0 0x1000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + status = "disabled";
> > + };
> > + };
> > +};
>
> Regards,
> Bin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-16 5:24 ` Yash Shah
@ 2020-12-16 6:06 ` Bin Meng
-1 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-16 6:06 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley ( Sifive),
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
Hi Yash,
On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> wrote:
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 10 December 2020 19:05
> > To: Yash Shah <yash.shah@openfive.com>
> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> > <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> > Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> > C000 SoC
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
> > >
> > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> >
> > FU740-C000 Soc
> >
> > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > >
> > > This file is expected to grow as more device drivers are added to the
> > > kernel.
> > >
> > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > > ---
> > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > +++++++++++++++++++++++++++++
> > > 1 file changed, 293 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > new file mode 100644
> > > index 0000000..eeb4f8c3
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > @@ -0,0 +1,293 @@
>
> ...
>
> > > + plic0: interrupt-controller@c000000 {
> > > + #interrupt-cells = <1>;
> > > + #address-cells = <0>;
> > > + compatible = "sifive,fu540-c000-plic",
> > > + "sifive,plic-1.0.0";
> >
> > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
>
> That's because it is not required. There won't be any difference in driver code for FU740 plic.
Are there any driver changes for the drivers that have an updated
fu640-c000-* bindings? I don't see them in the linux-riscv list.
>
> ...
>
> > > + eth0: ethernet@10090000 {
> > > + compatible = "sifive,fu540-c000-gem";
> >
> > "sifive,fu740-c000-gem"?
> >
>
> Same reason as above.
>
> Thanks for your review.
Regards,
Bin
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2020-12-16 6:06 ` Bin Meng
0 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-16 6:06 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley ( Sifive),
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
Hi Yash,
On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> wrote:
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 10 December 2020 19:05
> > To: Yash Shah <yash.shah@openfive.com>
> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> > <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> > Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> > C000 SoC
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
> > >
> > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> >
> > FU740-C000 Soc
> >
> > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > >
> > > This file is expected to grow as more device drivers are added to the
> > > kernel.
> > >
> > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > > ---
> > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > +++++++++++++++++++++++++++++
> > > 1 file changed, 293 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > new file mode 100644
> > > index 0000000..eeb4f8c3
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > @@ -0,0 +1,293 @@
>
> ...
>
> > > + plic0: interrupt-controller@c000000 {
> > > + #interrupt-cells = <1>;
> > > + #address-cells = <0>;
> > > + compatible = "sifive,fu540-c000-plic",
> > > + "sifive,plic-1.0.0";
> >
> > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
>
> That's because it is not required. There won't be any difference in driver code for FU740 plic.
Are there any driver changes for the drivers that have an updated
fu640-c000-* bindings? I don't see them in the linux-riscv list.
>
> ...
>
> > > + eth0: ethernet@10090000 {
> > > + compatible = "sifive,fu540-c000-gem";
> >
> > "sifive,fu740-c000-gem"?
> >
>
> Same reason as above.
>
> Thanks for your review.
Regards,
Bin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-16 6:06 ` Bin Meng
@ 2020-12-16 6:12 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-16 6:12 UTC (permalink / raw)
To: Bin Meng
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley ( Sifive),
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 16 December 2020 11:36
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Yash,
>
> On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com>
> wrote:
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 10 December 2020 19:05
> > > To: Yash Shah <yash.shah@openfive.com>
> > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> > > kernel@vger.kernel.org>; linux-riscv
> > > <linux-riscv@lists.infradead.org>;
> > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM
> > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg
> > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou
> > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org;
> > > u.kleine-koenig@pengutronix.de; Thierry Reding
> > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> > > <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> Rob
> > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> > > <bgolaszewski@baylibre.com>; Linus Walleij
> > > <linus.walleij@linaro.org>
> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the
> > > SiFive FU740-
> > > C000 SoC
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com>
> wrote:
> > > >
> > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is
> > > > built
> > >
> > > FU740-C000 Soc
> > >
> > > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > > >
> > > > This file is expected to grow as more device drivers are added to
> > > > the kernel.
> > > >
> > > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > > > ---
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > > +++++++++++++++++++++++++++++
> > > > 1 file changed, 293 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > new file mode 100644
> > > > index 0000000..eeb4f8c3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > @@ -0,0 +1,293 @@
> >
> > ...
> >
> > > > + plic0: interrupt-controller@c000000 {
> > > > + #interrupt-cells = <1>;
> > > > + #address-cells = <0>;
> > > > + compatible = "sifive,fu540-c000-plic",
> > > > + "sifive,plic-1.0.0";
> > >
> > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
> >
> > That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
>
> Are there any driver changes for the drivers that have an updated
> fu640-c000-* bindings? I don't see them in the linux-riscv list.
Yes, they will be posted soon.
- Yash
>
> >
> > ...
> >
> > > > + eth0: ethernet@10090000 {
> > > > + compatible = "sifive,fu540-c000-gem";
> > >
> > > "sifive,fu740-c000-gem"?
> > >
> >
> > Same reason as above.
> >
> > Thanks for your review.
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 58+ messages in thread* RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2020-12-16 6:12 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-16 6:12 UTC (permalink / raw)
To: Bin Meng
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley ( Sifive),
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 16 December 2020 11:36
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>;
> devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux-
> gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>;
> lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding
> <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob
> Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Yash,
>
> On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com>
> wrote:
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 10 December 2020 19:05
> > > To: Yash Shah <yash.shah@openfive.com>
> > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux-
> > > kernel@vger.kernel.org>; linux-riscv
> > > <linux-riscv@lists.infradead.org>;
> > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM
> > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg
> > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou
> > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org;
> > > u.kleine-koenig@pengutronix.de; Thierry Reding
> > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard
> > > <peter@korsgaard.com>; Paul Walmsley ( Sifive)
> > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> Rob
> > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski
> > > <bgolaszewski@baylibre.com>; Linus Walleij
> > > <linus.walleij@linaro.org>
> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the
> > > SiFive FU740-
> > > C000 SoC
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com>
> wrote:
> > > >
> > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is
> > > > built
> > >
> > > FU740-C000 Soc
> > >
> > > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > > >
> > > > This file is expected to grow as more device drivers are added to
> > > > the kernel.
> > > >
> > > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > > > ---
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > > +++++++++++++++++++++++++++++
> > > > 1 file changed, 293 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > new file mode 100644
> > > > index 0000000..eeb4f8c3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > @@ -0,0 +1,293 @@
> >
> > ...
> >
> > > > + plic0: interrupt-controller@c000000 {
> > > > + #interrupt-cells = <1>;
> > > > + #address-cells = <0>;
> > > > + compatible = "sifive,fu540-c000-plic",
> > > > + "sifive,plic-1.0.0";
> > >
> > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
> >
> > That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
>
> Are there any driver changes for the drivers that have an updated
> fu640-c000-* bindings? I don't see them in the linux-riscv list.
Yes, they will be posted soon.
- Yash
>
> >
> > ...
> >
> > > > + eth0: ethernet@10090000 {
> > > > + compatible = "sifive,fu540-c000-gem";
> > >
> > > "sifive,fu740-c000-gem"?
> > >
> >
> > Same reason as above.
> >
> > Thanks for your review.
>
> Regards,
> Bin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-08 4:55 ` Yash Shah
@ 2021-07-16 12:49 ` Geert Uytterhoeven
-1 siblings, 0 replies; 58+ messages in thread
From: Geert Uytterhoeven @ 2021-07-16 12:49 UTC (permalink / raw)
To: Yash Shah
Cc: Linux Kernel Mailing List, linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Paul Walmsley, Rob Herring, Thierry Reding, Palmer Dabbelt
Hi Yash,
On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote:
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks for your patch, which became commit 57985788158a5a6b ("riscv:
dts: add initial support for the SiFive FU740-C000 SoC").
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -0,0 +1,293 @@
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,bullet0", "riscv";
I'm wondering why you're using
compatible = "sifive,bullet0", "riscv";
According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv:
Update DT binding docs to support SiFive FU740 SoC"), it should be
compatible = "sifive,u74-mc", "riscv";
instead.
Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
compatible = "sifive,e51", "sifive,rocket0", "riscv";
and
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
but according to the DT bindings the rocket part should not be present.
Is there any specific reason for that?
Should the DT bindings and/or the DTS files be fixed?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2021-07-16 12:49 ` Geert Uytterhoeven
0 siblings, 0 replies; 58+ messages in thread
From: Geert Uytterhoeven @ 2021-07-16 12:49 UTC (permalink / raw)
To: Yash Shah
Cc: Linux Kernel Mailing List, linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Paul Walmsley, Rob Herring, Thierry Reding, Palmer Dabbelt
Hi Yash,
On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote:
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks for your patch, which became commit 57985788158a5a6b ("riscv:
dts: add initial support for the SiFive FU740-C000 SoC").
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -0,0 +1,293 @@
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,bullet0", "riscv";
I'm wondering why you're using
compatible = "sifive,bullet0", "riscv";
According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv:
Update DT binding docs to support SiFive FU740 SoC"), it should be
compatible = "sifive,u74-mc", "riscv";
instead.
Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
compatible = "sifive,e51", "sifive,rocket0", "riscv";
and
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
but according to the DT bindings the rocket part should not be present.
Is there any specific reason for that?
Should the DT bindings and/or the DTS files be fixed?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2021-07-16 12:49 ` Geert Uytterhoeven
@ 2021-07-19 17:12 ` David Abdurachmanov
-1 siblings, 0 replies; 58+ messages in thread
From: David Abdurachmanov @ 2021-07-19 17:12 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yash Shah, Linux Kernel Mailing List, linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Paul Walmsley, Rob Herring, Thierry Reding, Palmer Dabbelt
On Fri, Jul 16, 2021 at 3:51 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Yash,
>
> On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote:
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> Thanks for your patch, which became commit 57985788158a5a6b ("riscv:
> dts: add initial support for the SiFive FU740-C000 SoC").
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
>
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cpu0: cpu@0 {
> > + compatible = "sifive,bullet0", "riscv";
>
> I'm wondering why you're using
>
> compatible = "sifive,bullet0", "riscv";
>
> According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv:
> Update DT binding docs to support SiFive FU740 SoC"), it should be
>
> compatible = "sifive,u74-mc", "riscv";
>
> instead.
I plan to send out new DT for the Rev3A and Rev3B (the final board
customers can buy) boards.
This is already fixed in meta-sifive.
In general bullet here is micro architecture, but it's less
descriptive in /proc/cpuinfo.
>
> Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
>
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
>
> and
>
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>
> but according to the DT bindings the rocket part should not be present.
>
> Is there any specific reason for that?
> Should the DT bindings and/or the DTS files be fixed?
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
@ 2021-07-19 17:12 ` David Abdurachmanov
0 siblings, 0 replies; 58+ messages in thread
From: David Abdurachmanov @ 2021-07-19 17:12 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yash Shah, Linux Kernel Mailing List, linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Paul Walmsley, Rob Herring, Thierry Reding, Palmer Dabbelt
On Fri, Jul 16, 2021 at 3:51 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Yash,
>
> On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote:
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> Thanks for your patch, which became commit 57985788158a5a6b ("riscv:
> dts: add initial support for the SiFive FU740-C000 SoC").
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
>
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cpu0: cpu@0 {
> > + compatible = "sifive,bullet0", "riscv";
>
> I'm wondering why you're using
>
> compatible = "sifive,bullet0", "riscv";
>
> According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv:
> Update DT binding docs to support SiFive FU740 SoC"), it should be
>
> compatible = "sifive,u74-mc", "riscv";
>
> instead.
I plan to send out new DT for the Rev3A and Rev3B (the final board
customers can buy) boards.
This is already fixed in meta-sifive.
In general bullet here is micro architecture, but it's less
descriptive in /proc/cpuinfo.
>
> Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
>
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
>
> and
>
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>
> but according to the DT bindings the rocket part should not be present.
>
> Is there any specific reason for that?
> Should the DT bindings and/or the DTS files be fixed?
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add new compatible strings to the YAML DT binding document to support
SiFive's HiFive Unmatched board
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
index 3a8647d..ee0a239 100644
--- a/Documentation/devicetree/bindings/riscv/sifive.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
@@ -17,11 +17,18 @@ properties:
$nodename:
const: '/'
compatible:
- items:
- - enum:
- - sifive,hifive-unleashed-a00
- - const: sifive,fu540-c000
- - const: sifive,fu540
+ oneOf:
+ - items:
+ - enum:
+ - sifive,hifive-unleashed-a00
+ - const: sifive,fu540-c000
+ - const: sifive,fu540
+
+ - items:
+ - enum:
+ - sifive,hifive-unmatched-a00
+ - const: sifive,fu740-c000
+ - const: sifive,fu740
additionalProperties: true
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add new compatible strings to the YAML DT binding document to support
SiFive's HiFive Unmatched board
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
index 3a8647d..ee0a239 100644
--- a/Documentation/devicetree/bindings/riscv/sifive.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
@@ -17,11 +17,18 @@ properties:
$nodename:
const: '/'
compatible:
- items:
- - enum:
- - sifive,hifive-unleashed-a00
- - const: sifive,fu540-c000
- - const: sifive,fu540
+ oneOf:
+ - items:
+ - enum:
+ - sifive,hifive-unleashed-a00
+ - const: sifive,fu540-c000
+ - const: sifive,fu540
+
+ - items:
+ - enum:
+ - sifive,hifive-unmatched-a00
+ - const: sifive,fu740-c000
+ - const: sifive,fu740
additionalProperties: true
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 3:59 ` Rob Herring
-1 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:59 UTC (permalink / raw)
To: Yash Shah
Cc: gregkh, devicetree, paul.walmsley, peter, lee.jones,
linux-serial, thierry.reding, linux-i2c, linux-gpio,
bgolaszewski, aou, linux-kernel, palmer, u.kleine-koenig,
broonie, linus.walleij, linux-spi, linux-riscv, andrew,
linux-pwm, robh+dt
On Tue, 08 Dec 2020 10:25:40 +0530, Yash Shah wrote:
> Add new compatible strings to the YAML DT binding document to support
> SiFive's HiFive Unmatched board
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
@ 2020-12-10 3:59 ` Rob Herring
0 siblings, 0 replies; 58+ messages in thread
From: Rob Herring @ 2020-12-10 3:59 UTC (permalink / raw)
To: Yash Shah
Cc: devicetree, peter, aou, robh+dt, bgolaszewski, gregkh, broonie,
u.kleine-koenig, linux-kernel, linux-pwm, linux-spi, andrew,
linux-gpio, thierry.reding, palmer, linux-i2c, linux-serial,
paul.walmsley, linux-riscv, lee.jones, linus.walleij
On Tue, 08 Dec 2020 10:25:40 +0530, Yash Shah wrote:
> Add new compatible strings to the YAML DT binding document to support
> SiFive's HiFive Unmatched board
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 13:34 ` Bin Meng
-1 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley,
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
On Tue, Dec 8, 2020 at 3:05 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add new compatible strings to the YAML DT binding document to support
> SiFive's HiFive Unmatched board
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
@ 2020-12-10 13:34 ` Bin Meng
0 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley,
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
On Tue, Dec 8, 2020 at 3:05 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add new compatible strings to the YAML DT binding document to support
> SiFive's HiFive Unmatched board
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 4:55 ` Yash Shah
-1 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, Yash Shah
Add initial board data for the SiFive HiFive Unmatched A00.
This patch is dependent on Zong's Patchset[0].
[0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/Makefile | 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++
2 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
index 6d6189e..74c47fe 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
+ hifive-unmatched-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
new file mode 100644
index 0000000..b1c3c59
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <1500000>;
+ regulator-max-microamp = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ld09: ldo9 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched
@ 2020-12-08 4:55 ` Yash Shah
0 siblings, 0 replies; 58+ messages in thread
From: Yash Shah @ 2020-12-08 4:55 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: andrew, peter, aou, gregkh, broonie, paul.walmsley, robh+dt,
bgolaszewski, Yash Shah, thierry.reding, palmer, u.kleine-koenig,
lee.jones, linus.walleij
Add initial board data for the SiFive HiFive Unmatched A00.
This patch is dependent on Zong's Patchset[0].
[0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/Makefile | 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++
2 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
index 6d6189e..74c47fe 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
+ hifive-unmatched-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
new file mode 100644
index 0000000..b1c3c59
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <1500000>;
+ regulator-max-microamp = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ld09: ldo9 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
--
2.7.4
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched
2020-12-08 4:55 ` Yash Shah
@ 2020-12-10 13:34 ` Bin Meng
-1 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, open list:GPIO SUBSYSTEM, broonie,
Greg Kroah-Hartman, Albert Ou, lee.jones, u.kleine-koenig,
Thierry Reding, andrew, Peter Korsgaard, Paul Walmsley,
Palmer Dabbelt, Rob Herring, Bartosz Golaszewski, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add initial board data for the SiFive HiFive Unmatched A00.
> This patch is dependent on Zong's Patchset[0].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
I think the dependency should be put below --, not in the commit message itself
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++
> 2 files changed, 255 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
>
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> index 6d6189e..74c47fe 100644
> --- a/arch/riscv/boot/dts/sifive/Makefile
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
> +dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
> + hifive-unmatched-a00.dtb
Otherwise LGTM:
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched
@ 2020-12-10 13:34 ` Bin Meng
0 siblings, 0 replies; 58+ messages in thread
From: Bin Meng @ 2020-12-10 13:34 UTC (permalink / raw)
To: Yash Shah
Cc: linux-pwm, Peter Korsgaard, Albert Ou, devicetree,
Greg Kroah-Hartman, Bartosz Golaszewski, Paul Walmsley,
linux-kernel, Rob Herring, linux-spi, andrew,
open list:GPIO SUBSYSTEM, broonie, Thierry Reding, linux-i2c,
linux-serial, u.kleine-koenig, Palmer Dabbelt, linux-riscv,
lee.jones, Linus Walleij
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> Add initial board data for the SiFive HiFive Unmatched A00.
> This patch is dependent on Zong's Patchset[0].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
I think the dependency should be put below --, not in the commit message itself
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++
> 2 files changed, 255 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
>
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> index 6d6189e..74c47fe 100644
> --- a/arch/riscv/boot/dts/sifive/Makefile
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
> +dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
> + hifive-unmatched-a00.dtb
Otherwise LGTM:
Reviewed-by: Bin Meng <bin.meng@windriver.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: (subset) [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
2020-12-08 4:55 ` Yash Shah
@ 2020-12-08 17:11 ` Mark Brown
-1 siblings, 0 replies; 58+ messages in thread
From: Mark Brown @ 2020-12-08 17:11 UTC (permalink / raw)
To: linux-i2c, linux-serial, linux-spi, linux-pwm, linux-riscv,
Yash Shah, linux-kernel, linux-gpio, devicetree
Cc: aou, peter, paul.walmsley, u.kleine-koenig, linus.walleij,
bgolaszewski, gregkh, palmer, andrew, thierry.reding, lee.jones,
robh+dt
On Tue, 8 Dec 2020 10:25:32 +0530, Yash Shah wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
commit: 76347344c522da78be29403dda81463ffae2bc99
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: (subset) [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
@ 2020-12-08 17:11 ` Mark Brown
0 siblings, 0 replies; 58+ messages in thread
From: Mark Brown @ 2020-12-08 17:11 UTC (permalink / raw)
To: linux-i2c, linux-serial, linux-spi, linux-pwm, linux-riscv,
Yash Shah, linux-kernel, linux-gpio, devicetree
Cc: andrew, peter, aou, gregkh, linus.walleij, paul.walmsley,
robh+dt, bgolaszewski, thierry.reding, palmer, u.kleine-koenig,
lee.jones
On Tue, 8 Dec 2020 10:25:32 +0530, Yash Shah wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
commit: 76347344c522da78be29403dda81463ffae2bc99
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
2020-12-08 4:55 ` Yash Shah
@ 2020-12-22 4:38 ` Palmer Dabbelt
-1 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2020-12-22 4:38 UTC (permalink / raw)
To: yash.shah, robh+dt
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, Greg KH, aou,
lee.jones, u.kleine-koenig, thierry.reding, andrew, peter,
Paul Walmsley, bgolaszewski, linus.walleij, yash.shah
On Mon, 07 Dec 2020 20:55:32 PST (-0800), yash.shah@sifive.com wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> This patch series is dependent on Zong's Patchset[0]. The patchset also
> adds two new nodes in dtsi file. The binding documentation patch
> for these nodes are already posted on the mailing list[1][2].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
> [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
> [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
>
> Changes in v2:
> - The dt bindings patch is split into several individual patches.
> - Expand the full list for compatible strings in i2c-ocores.txt
>
> Yash Shah (9):
> dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: serial: Update DT binding docs to support SiFive FU740
> SoC
> dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
> riscv: dts: add initial support for the SiFive FU740-C000 SoC
> dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
> board
> riscv: dts: add initial board data for the SiFive HiFive Unmatched
>
> .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
> .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +-
> .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
> .../devicetree/bindings/riscv/sifive.yaml | 17 +-
> .../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
> .../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
> 10 files changed, 590 insertions(+), 17 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
Aside from that question about the i2c bug these look good to me. I don't see
any Ack/Review on the DT side of things, though. If you want to take them
through a DT tree that's fine for me, I'll leave them in my inbox for now and
if nobody says anything I'll look a bit more and take them for 5.12.
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
@ 2020-12-22 4:38 ` Palmer Dabbelt
0 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2020-12-22 4:38 UTC (permalink / raw)
To: yash.shah, robh+dt
Cc: linux-pwm, peter, aou, devicetree, Greg KH, linus.walleij,
Paul Walmsley, linux-kernel, linux-spi, andrew, linux-gpio,
yash.shah, broonie, thierry.reding, linux-i2c, linux-serial,
u.kleine-koenig, bgolaszewski, linux-riscv, lee.jones
On Mon, 07 Dec 2020 20:55:32 PST (-0800), yash.shah@sifive.com wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> This patch series is dependent on Zong's Patchset[0]. The patchset also
> adds two new nodes in dtsi file. The binding documentation patch
> for these nodes are already posted on the mailing list[1][2].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
> [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
> [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
>
> Changes in v2:
> - The dt bindings patch is split into several individual patches.
> - Expand the full list for compatible strings in i2c-ocores.txt
>
> Yash Shah (9):
> dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: serial: Update DT binding docs to support SiFive FU740
> SoC
> dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
> riscv: dts: add initial support for the SiFive FU740-C000 SoC
> dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
> board
> riscv: dts: add initial board data for the SiFive HiFive Unmatched
>
> .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
> .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +-
> .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
> .../devicetree/bindings/riscv/sifive.yaml | 17 +-
> .../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
> .../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
> 10 files changed, 590 insertions(+), 17 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
Aside from that question about the i2c bug these look good to me. I don't see
any Ack/Review on the DT side of things, though. If you want to take them
through a DT tree that's fine for me, I'll leave them in my inbox for now and
if nobody says anything I'll look a bit more and take them for 5.12.
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
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^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
2020-12-08 4:55 ` Yash Shah
@ 2021-01-08 3:12 ` Palmer Dabbelt
-1 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2021-01-08 3:12 UTC (permalink / raw)
To: yash.shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, Greg KH, aou,
lee.jones, u.kleine-koenig, thierry.reding, andrew, peter,
Paul Walmsley, robh+dt, bgolaszewski, linus.walleij, yash.shah
On Mon, 07 Dec 2020 20:55:32 PST (-0800), yash.shah@sifive.com wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> This patch series is dependent on Zong's Patchset[0]. The patchset also
> adds two new nodes in dtsi file. The binding documentation patch
> for these nodes are already posted on the mailing list[1][2].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
> [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
> [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
>
> Changes in v2:
> - The dt bindings patch is split into several individual patches.
> - Expand the full list for compatible strings in i2c-ocores.txt
>
> Yash Shah (9):
> dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: serial: Update DT binding docs to support SiFive FU740
> SoC
> dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
> riscv: dts: add initial support for the SiFive FU740-C000 SoC
> dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
> board
> riscv: dts: add initial board data for the SiFive HiFive Unmatched
>
> .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
> .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +-
> .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
> .../devicetree/bindings/riscv/sifive.yaml | 17 +-
> .../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
> .../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
> 10 files changed, 590 insertions(+), 17 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
Thanks, these are on for-next. There was one checkpatch warning about the
missing ISSI device tree entry, but we already had that in the FU540 so I'm OK
letting it slide.
I'm also not really sure this is the right way to do this sort of thing: most
of the patches here really aren't RISC-V things, they're SiFive SOC things.
Some of these patches have been picked up by other trees, but I just took the
rest. I'm not all that happy about taking DT bindings for things like GPIO or
PWM bindings, but as they're pretty small I'm OK doing it in this instance.
In the future it would really be better to split these up and land them via
their respectitve trees, rather than trying to do all the SOC stuff over here.
I know that can be a headache, but we have that SOC group for this purpose to
try and keep things a bit more together -- I know it was a while ago and there
really hasn't been much SOC activity on the RISC-V side of things so maybe it
hasn't been that widley discussed, but that was really designed to solve these
sorts of problems.
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v2 0/9] arch: riscv: add board and SoC DT file support
@ 2021-01-08 3:12 ` Palmer Dabbelt
0 siblings, 0 replies; 58+ messages in thread
From: Palmer Dabbelt @ 2021-01-08 3:12 UTC (permalink / raw)
To: yash.shah
Cc: linux-pwm, peter, aou, devicetree, Greg KH, linus.walleij,
Paul Walmsley, linux-kernel, robh+dt, linux-spi, andrew,
linux-gpio, yash.shah, broonie, thierry.reding, linux-i2c,
linux-serial, u.kleine-koenig, bgolaszewski, linux-riscv,
lee.jones
On Mon, 07 Dec 2020 20:55:32 PST (-0800), yash.shah@sifive.com wrote:
> Start board support by adding initial support for the SiFive FU740 SoC
> and the first development board that uses it, the SiFive HiFive
> Unmatched A00.
>
> Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
> U-boot and OpenSBI.
>
> This patch series is dependent on Zong's Patchset[0]. The patchset also
> adds two new nodes in dtsi file. The binding documentation patch
> for these nodes are already posted on the mailing list[1][2].
>
> [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
> [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
> [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
>
> Changes in v2:
> - The dt bindings patch is split into several individual patches.
> - Expand the full list for compatible strings in i2c-ocores.txt
>
> Yash Shah (9):
> dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: serial: Update DT binding docs to support SiFive FU740
> SoC
> dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
> dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
> riscv: dts: add initial support for the SiFive FU740-C000 SoC
> dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
> board
> riscv: dts: add initial board data for the SiFive HiFive Unmatched
>
> .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
> .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +-
> .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
> .../devicetree/bindings/riscv/sifive.yaml | 17 +-
> .../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
> .../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
> arch/riscv/boot/dts/sifive/Makefile | 3 +-
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
> .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
> 10 files changed, 590 insertions(+), 17 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
Thanks, these are on for-next. There was one checkpatch warning about the
missing ISSI device tree entry, but we already had that in the FU540 so I'm OK
letting it slide.
I'm also not really sure this is the right way to do this sort of thing: most
of the patches here really aren't RISC-V things, they're SiFive SOC things.
Some of these patches have been picked up by other trees, but I just took the
rest. I'm not all that happy about taking DT bindings for things like GPIO or
PWM bindings, but as they're pretty small I'm OK doing it in this instance.
In the future it would really be better to split these up and land them via
their respectitve trees, rather than trying to do all the SOC stuff over here.
I know that can be a headache, but we have that SOC group for this purpose to
try and keep things a bit more together -- I know it was a while ago and there
really hasn't been much SOC activity on the RISC-V side of things so maybe it
hasn't been that widley discussed, but that was really designed to solve these
sorts of problems.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 58+ messages in thread