From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, mike.leach@linaro.org, Anshuman Khandual <anshuman.khandual@arm.com>, Linu Cherian <lcherian@marvell.com>, linux-kernel@vger.kernel.org Subject: [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Date: Wed, 13 Jan 2021 09:48:08 +0530 [thread overview] Message-ID: <1610511498-4058-2-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1610511498-4058-1-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose <suzuki.poulose@arm.com> When there are multiple sinks on the system, in the absence of a specified sink, it is quite possible that a default sink for an ETM could be different from that of another ETM. However we do not support having multiple sinks for an event yet. This patch allows the event to use the default sinks on the ETMs where they are scheduled as long as the sinks are of the same type. e.g, if we have 1x1 topology with per-CPU ETRs, the event can use the per-CPU ETR for the session. However, if the sinks are of different type, e.g TMC-ETR on one and a custom sink on another, the event will only trace on the first detected sink. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Tested-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++----- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bdc34ca..eb9e7e9 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -204,6 +204,13 @@ static void etm_free_aux(void *data) schedule_work(&event_data->work); } +static bool sinks_match(struct coresight_device *a, struct coresight_device *b) +{ + if (!a || !b) + return false; + return (sink_ops(a) == sink_ops(b)); +} + static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, cpumask_t *mask; struct coresight_device *sink = NULL; struct etm_event_data *event_data = NULL; + bool sink_forced = false; event_data = alloc_event_data(cpu); if (!event_data) @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (event->attr.config2) { id = (u32)event->attr.config2; sink = coresight_get_sink_by_id(id); + sink_forced = true; } mask = &event_data->mask; @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, */ for_each_cpu(cpu, mask) { struct list_head *path; - struct coresight_device *csdev; + struct coresight_device *csdev, *new_sink; csdev = per_cpu(csdev_src, cpu); /* @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, } /* - * No sink provided - look for a default sink for one of the - * devices. At present we only support topology where all CPUs - * use the same sink [N:1], so only need to find one sink. The - * coresight_build_path later will remove any CPU that does not - * attach to the sink, or if we have not found a sink. + * No sink provided - look for a default sink for all the devices. + * We only support multiple sinks, only if all the default sinks + * are of the same type, so that the sink buffer can be shared + * as the event moves around. We don't trace on a CPU if it can't + * */ - if (!sink) - sink = coresight_find_default_sink(csdev); + if (!sink_forced) { + new_sink = coresight_find_default_sink(csdev); + if (!new_sink) { + cpumask_clear_cpu(cpu, mask); + continue; + } + /* Skip checks for the first sink */ + if (!sink) { + sink = new_sink; + } else if (!sinks_match(new_sink, sink)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + } else { + new_sink = sink; + } /* * Building a path doesn't enable it, it simply builds a * list of devices from source to sink that can be * referenced later when the path is actually needed. */ - path = coresight_build_path(csdev, sink); + path = coresight_build_path(csdev, new_sink); if (IS_ERR(path)) { cpumask_clear_cpu(cpu, mask); continue; @@ -284,7 +307,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer) goto err; - /* Allocate the sink buffer for this session */ + /* + * Allocate the sink buffer for this session. All the sinks + * where this event can be scheduled are ensured to be of the + * same type. Thus the same sink configuration is used by the + * sinks. + */ event_data->snk_config = sink_ops(sink)->alloc_buffer(sink, event, pages, nr_pages, overwrite); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: mathieu.poirier@linaro.org, Anshuman Khandual <anshuman.khandual@arm.com>, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org, Linu Cherian <lcherian@marvell.com>, mike.leach@linaro.org Subject: [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Date: Wed, 13 Jan 2021 09:48:08 +0530 [thread overview] Message-ID: <1610511498-4058-2-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1610511498-4058-1-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose <suzuki.poulose@arm.com> When there are multiple sinks on the system, in the absence of a specified sink, it is quite possible that a default sink for an ETM could be different from that of another ETM. However we do not support having multiple sinks for an event yet. This patch allows the event to use the default sinks on the ETMs where they are scheduled as long as the sinks are of the same type. e.g, if we have 1x1 topology with per-CPU ETRs, the event can use the per-CPU ETR for the session. However, if the sinks are of different type, e.g TMC-ETR on one and a custom sink on another, the event will only trace on the first detected sink. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Tested-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++----- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bdc34ca..eb9e7e9 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -204,6 +204,13 @@ static void etm_free_aux(void *data) schedule_work(&event_data->work); } +static bool sinks_match(struct coresight_device *a, struct coresight_device *b) +{ + if (!a || !b) + return false; + return (sink_ops(a) == sink_ops(b)); +} + static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, cpumask_t *mask; struct coresight_device *sink = NULL; struct etm_event_data *event_data = NULL; + bool sink_forced = false; event_data = alloc_event_data(cpu); if (!event_data) @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (event->attr.config2) { id = (u32)event->attr.config2; sink = coresight_get_sink_by_id(id); + sink_forced = true; } mask = &event_data->mask; @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, */ for_each_cpu(cpu, mask) { struct list_head *path; - struct coresight_device *csdev; + struct coresight_device *csdev, *new_sink; csdev = per_cpu(csdev_src, cpu); /* @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, } /* - * No sink provided - look for a default sink for one of the - * devices. At present we only support topology where all CPUs - * use the same sink [N:1], so only need to find one sink. The - * coresight_build_path later will remove any CPU that does not - * attach to the sink, or if we have not found a sink. + * No sink provided - look for a default sink for all the devices. + * We only support multiple sinks, only if all the default sinks + * are of the same type, so that the sink buffer can be shared + * as the event moves around. We don't trace on a CPU if it can't + * */ - if (!sink) - sink = coresight_find_default_sink(csdev); + if (!sink_forced) { + new_sink = coresight_find_default_sink(csdev); + if (!new_sink) { + cpumask_clear_cpu(cpu, mask); + continue; + } + /* Skip checks for the first sink */ + if (!sink) { + sink = new_sink; + } else if (!sinks_match(new_sink, sink)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + } else { + new_sink = sink; + } /* * Building a path doesn't enable it, it simply builds a * list of devices from source to sink that can be * referenced later when the path is actually needed. */ - path = coresight_build_path(csdev, sink); + path = coresight_build_path(csdev, new_sink); if (IS_ERR(path)) { cpumask_clear_cpu(cpu, mask); continue; @@ -284,7 +307,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer) goto err; - /* Allocate the sink buffer for this session */ + /* + * Allocate the sink buffer for this session. All the sinks + * where this event can be scheduled are ensured to be of the + * same type. Thus the same sink configuration is used by the + * sinks. + */ event_data->snk_config = sink_ops(sink)->alloc_buffer(sink, event, pages, nr_pages, overwrite); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-13 4:19 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-13 4:18 [PATCH V2 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual [this message] 2021-01-13 4:18 ` [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-25 19:22 ` Rob Herring 2021-01-25 19:22 ` Rob Herring 2021-01-25 22:20 ` Suzuki K Poulose 2021-01-25 22:20 ` Suzuki K Poulose 2021-01-25 23:28 ` Suzuki K Poulose 2021-01-25 23:28 ` Suzuki K Poulose 2021-01-13 4:18 ` [PATCH V2 07/11] arm64: Add TRBE definitions Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 9:21 ` Suzuki K Poulose 2021-01-13 9:21 ` Suzuki K Poulose 2021-01-15 1:52 ` Anshuman Khandual 2021-01-15 1:52 ` Anshuman Khandual 2021-02-22 13:55 ` Catalin Marinas 2021-02-22 13:55 ` Catalin Marinas 2021-02-22 13:59 ` Catalin Marinas 2021-02-22 13:59 ` Catalin Marinas 2021-01-13 4:18 ` [PATCH V2 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 9:43 ` Suzuki K Poulose 2021-01-13 9:43 ` Suzuki K Poulose 2021-01-15 2:36 ` Anshuman Khandual 2021-01-15 2:36 ` Anshuman Khandual 2021-01-15 12:31 ` Suzuki K Poulose 2021-01-15 12:31 ` Suzuki K Poulose 2021-01-13 4:18 ` [PATCH V2 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 9:48 ` Suzuki K Poulose 2021-01-13 9:48 ` Suzuki K Poulose 2021-01-13 4:18 ` [PATCH V2 10/11] coresight: sink: Add TRBE driver Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 15:28 ` Suzuki K Poulose 2021-01-13 15:28 ` Suzuki K Poulose 2021-01-15 5:29 ` Anshuman Khandual 2021-01-15 5:29 ` Anshuman Khandual 2021-01-15 12:43 ` Suzuki K Poulose 2021-01-15 12:43 ` Suzuki K Poulose 2021-01-17 12:10 ` Anshuman Khandual 2021-01-17 12:10 ` Anshuman Khandual 2021-01-13 4:18 ` [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual 2021-01-13 4:18 ` Anshuman Khandual 2021-01-13 15:45 ` Rob Herring 2021-01-13 15:45 ` Rob Herring 2021-01-14 10:17 ` Suzuki K Poulose 2021-01-14 10:17 ` Suzuki K Poulose 2021-01-14 14:07 ` Rob Herring 2021-01-14 14:07 ` Rob Herring 2021-01-14 14:47 ` Suzuki K Poulose 2021-01-14 14:47 ` Suzuki K Poulose
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