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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Rob Herring <robh@kernel.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	Linu Cherian <lcherian@marvell.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE
Date: Thu, 14 Jan 2021 14:47:37 +0000	[thread overview]
Message-ID: <54b49858-3475-f3db-7c81-f0a251a261af@arm.com> (raw)
In-Reply-To: <20210114140754.GA2816889@robh.at.kernel.org>

On 1/14/21 2:07 PM, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 09:48:18AM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Document the device tree bindings for Trace Buffer Extension (TRBE).
>>
>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   Documentation/devicetree/bindings/arm/trbe.yaml | 46 +++++++++++++++++++++++++
>>   1 file changed, 46 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml
>> new file mode 100644
>> index 0000000..2258595
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/trbe.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +# Copyright 2021, Arm Ltd
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: ARM Trace Buffer Extensions
>> +
>> +maintainers:
>> +  - Anshuman Khandual <anshuman.khandual@arm.com>
>> +
>> +description: |
>> +  Description of TRBE hw
> 
> Huh?
> 

Doh ! That was due to a miscommunication between us.
This should be :

description: |
   Arm Trace Buffer Extension (TRBE) is a per CPU component
   for storing trace generated on the CPU to memory. It is
   accessed via CPU system registers. The software can verify
   if it is permitted to use the component by checking the
   TRBIDR register.

>> +
>> +properties:
>> +  $nodename:
>> +    pattern: "trbe"
> 
> const: trbe
> 
>> +  compatible:
>> +    items:
>> +      - const: arm,trace-buffer-extension
> 
> Any versioning to this? Or is that discoverable?
> 

It must be discoverable via ID_AA64DFR0_EL1.TraceBuffer.
The IP is entirely accessed by the CPU system registers. So, any
further changes can be interpreted from the system registers
(including if the access is blocked by a higher exception level).

>> +
>> +  interrupts:
>> +    description: |
>> +       Exactly 1 PPI must be listed. For heterogeneous systems where
>> +       TRBE is only supported on a subset of the CPUs, please consult
>> +       the arm,gic-v3 binding for details on describing a PPI partition.
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - interrupts
>> +
>> +additionalProperties: false
>> +
>> +
> 
> Extra blank line.

Removed.

Cheers

Suzuki

WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Rob Herring <robh@kernel.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>
Cc: devicetree@vger.kernel.org, mathieu.poirier@linaro.org,
	coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Linu Cherian <lcherian@marvell.com>,
	mike.leach@linaro.org
Subject: Re: [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE
Date: Thu, 14 Jan 2021 14:47:37 +0000	[thread overview]
Message-ID: <54b49858-3475-f3db-7c81-f0a251a261af@arm.com> (raw)
In-Reply-To: <20210114140754.GA2816889@robh.at.kernel.org>

On 1/14/21 2:07 PM, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 09:48:18AM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Document the device tree bindings for Trace Buffer Extension (TRBE).
>>
>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   Documentation/devicetree/bindings/arm/trbe.yaml | 46 +++++++++++++++++++++++++
>>   1 file changed, 46 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml
>> new file mode 100644
>> index 0000000..2258595
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/trbe.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +# Copyright 2021, Arm Ltd
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: ARM Trace Buffer Extensions
>> +
>> +maintainers:
>> +  - Anshuman Khandual <anshuman.khandual@arm.com>
>> +
>> +description: |
>> +  Description of TRBE hw
> 
> Huh?
> 

Doh ! That was due to a miscommunication between us.
This should be :

description: |
   Arm Trace Buffer Extension (TRBE) is a per CPU component
   for storing trace generated on the CPU to memory. It is
   accessed via CPU system registers. The software can verify
   if it is permitted to use the component by checking the
   TRBIDR register.

>> +
>> +properties:
>> +  $nodename:
>> +    pattern: "trbe"
> 
> const: trbe
> 
>> +  compatible:
>> +    items:
>> +      - const: arm,trace-buffer-extension
> 
> Any versioning to this? Or is that discoverable?
> 

It must be discoverable via ID_AA64DFR0_EL1.TraceBuffer.
The IP is entirely accessed by the CPU system registers. So, any
further changes can be interpreted from the system registers
(including if the access is blocked by a higher exception level).

>> +
>> +  interrupts:
>> +    description: |
>> +       Exactly 1 PPI must be listed. For heterogeneous systems where
>> +       TRBE is only supported on a subset of the CPUs, please consult
>> +       the arm,gic-v3 binding for details on describing a PPI partition.
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - interrupts
>> +
>> +additionalProperties: false
>> +
>> +
> 
> Extra blank line.

Removed.

Cheers

Suzuki

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-01-14 14:48 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13  4:18 [PATCH V2 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-13  4:18 ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-25 19:22   ` Rob Herring
2021-01-25 19:22     ` Rob Herring
2021-01-25 22:20     ` Suzuki K Poulose
2021-01-25 22:20       ` Suzuki K Poulose
2021-01-25 23:28       ` Suzuki K Poulose
2021-01-25 23:28         ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 07/11] arm64: Add TRBE definitions Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:21   ` Suzuki K Poulose
2021-01-13  9:21     ` Suzuki K Poulose
2021-01-15  1:52     ` Anshuman Khandual
2021-01-15  1:52       ` Anshuman Khandual
2021-02-22 13:55   ` Catalin Marinas
2021-02-22 13:55     ` Catalin Marinas
2021-02-22 13:59     ` Catalin Marinas
2021-02-22 13:59       ` Catalin Marinas
2021-01-13  4:18 ` [PATCH V2 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:43   ` Suzuki K Poulose
2021-01-13  9:43     ` Suzuki K Poulose
2021-01-15  2:36     ` Anshuman Khandual
2021-01-15  2:36       ` Anshuman Khandual
2021-01-15 12:31       ` Suzuki K Poulose
2021-01-15 12:31         ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:48   ` Suzuki K Poulose
2021-01-13  9:48     ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 10/11] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13 15:28   ` Suzuki K Poulose
2021-01-13 15:28     ` Suzuki K Poulose
2021-01-15  5:29     ` Anshuman Khandual
2021-01-15  5:29       ` Anshuman Khandual
2021-01-15 12:43       ` Suzuki K Poulose
2021-01-15 12:43         ` Suzuki K Poulose
2021-01-17 12:10         ` Anshuman Khandual
2021-01-17 12:10           ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13 15:45   ` Rob Herring
2021-01-13 15:45     ` Rob Herring
2021-01-14 10:17     ` Suzuki K Poulose
2021-01-14 10:17       ` Suzuki K Poulose
2021-01-14 14:07   ` Rob Herring
2021-01-14 14:07     ` Rob Herring
2021-01-14 14:47     ` Suzuki K Poulose [this message]
2021-01-14 14:47       ` Suzuki K Poulose

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