[Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess

[Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDI clock routing code has turned into proper spaghetti.
Attempt to clean it up by introducing some new vfuncs.

Ville Syrjälä (15):
  drm/i915: Extract icl_dpclka_cfgcr0_reg()
  drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
  drm/i915: Introduce .{enable,disable}_clock() encoder vfuncs
  drm/i915: Extract hsw_ddi_{enable,disable}_clock()
  drm/i915: Extract skl_ddi_{enable,disable}_clock()
  drm/i195: Extract cnl_ddi_{enable,disable}_clock()
  drm/i915: Convert DG1 over to .{enable,disable}_clock()
  drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
  drm/i915: Use intel_de_rmw() for DDI clock routing
  drm/i915: Sprinkle a few missing locks around shared DDI clock
    registers
  drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
  drm/i915: Extract _cnl_ddi_{enable,disable}_clock()
  drm/i915: Split alds/rkl from icl_ddi_combo_{enable,disable}_clock()
  drm/i915: Use .disable_clock() for pll sanitation
  drm/i915: Relocate icl_sanitize_encoder_pll_mapping()

 drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 536 ++++++++++--------
 .../drm/i915/display/intel_display_types.h    |   6 +
 3 files changed, 295 insertions(+), 248 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH 01/15] drm/i915: Extract icl_dpclka_cfgcr0_reg()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code to determine the DPCLK_CFGCR register
to use.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++--------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5bc5033a2dea..a3aeb1c2821c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,6 +3127,15 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
+					enum phy phy)
+{
+	if (IS_ALDERLAKE_S(i915))
+		return ADLS_DPCLKA_CFGCR(phy);
+	else
+		return ICL_DPCLKA_CFGCR0;
+}
+
 static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -3167,19 +3176,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 	u32 val, mask, sel;
-	i915_reg_t reg;
 
 	if (IS_ALDERLAKE_S(dev_priv)) {
-		reg = ADLS_DPCLKA_CFGCR(phy);
 		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
 		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
 	} else if (IS_ROCKETLAKE(dev_priv)) {
-		reg = ICL_DPCLKA_CFGCR0;
 		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	} else {
-		reg = ICL_DPCLKA_CFGCR0;
 		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
@@ -3230,16 +3236,11 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 	u32 val;
-	i915_reg_t reg;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	if (IS_ALDERLAKE_S(dev_priv))
-		reg = ADLS_DPCLKA_CFGCR(phy);
-	else
-		reg = ICL_DPCLKA_CFGCR0;
-
 	val = intel_de_read(dev_priv, reg);
 	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 
@@ -3285,15 +3286,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 	enum port port;
 	bool ddi_clk_off;
 	u32 val;
-	i915_reg_t reg;
 
 	for_each_port_masked(port, port_mask) {
 		enum phy phy = intel_port_to_phy(dev_priv, port);
-
-		if (IS_ALDERLAKE_S(dev_priv))
-			reg = ADLS_DPCLKA_CFGCR(phy);
-		else
-			reg = ICL_DPCLKA_CFGCR0;
+		i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 
 		val = intel_de_read(dev_priv, reg);
 		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
-- 
2.26.2

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[Intel-gfx] [PATCH 02/15] drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract some helpers to calculate the correct CLK_SEL values
for DPCLKA_CFGCR.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++++++++++++---------
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a3aeb1c2821c..23fbb9013e09 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,6 +3127,28 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
+				     enum intel_dpll_id id, enum phy phy)
+{
+	if (IS_ALDERLAKE_S(dev_priv))
+		return id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
+	else if (IS_ROCKETLAKE(dev_priv))
+		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
+	else
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
+}
+
+static u32 icl_dpclka_cfgcr0_clk_sel_mask(struct drm_i915_private *dev_priv,
+					  enum phy phy)
+{
+	if (IS_ALDERLAKE_S(dev_priv))
+		return ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+	else if (IS_ROCKETLAKE(dev_priv))
+		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+	else
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+}
+
 static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
 					enum phy phy)
 {
@@ -3177,18 +3199,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-	u32 val, mask, sel;
-
-	if (IS_ALDERLAKE_S(dev_priv)) {
-		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
-		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
-	} else if (IS_ROCKETLAKE(dev_priv)) {
-		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	} else {
-		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	}
+	u32 val;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
@@ -3207,8 +3218,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		 *   Clock Select chooses the PLL for both DDIA and DDID and
 		 *   drives port A in all cases."
 		 */
-		val &= ~mask;
-		val |= sel;
+		val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
+		val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
 		intel_de_write(dev_priv, reg, val);
 		intel_de_posting_read(dev_priv, reg);
 	}
-- 
2.26.2

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[Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.

We leave them initially unimplemented, falling back to the old
if-else approach.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 29 +++++++++++++++----
 .../drm/i915/display/intel_display_types.h    |  6 ++++
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 23fbb9013e09..da8bb9a2de0b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3464,6 +3464,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	}
 }
 
+static void intel_ddi_enable_clock(struct intel_encoder *encoder,
+				   const struct intel_crtc_state *crtc_state)
+{
+	if (encoder->enable_clock)
+		encoder->enable_clock(encoder, crtc_state);
+	else
+		intel_ddi_clk_select(encoder, crtc_state);
+}
+
+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	if (encoder->disable_clock)
+		encoder->disable_clock(encoder);
+	else
+		intel_ddi_clk_disable(encoder);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
@@ -3708,7 +3725,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
 	 * configure the PLL to port mapping here.
 	 */
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
 	if (!intel_phy_is_tc(dev_priv, phy) ||
@@ -3829,7 +3846,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
 	intel_pps_on(intel_dp);
 
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	if (!intel_phy_is_tc(dev_priv, phy) ||
 	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
@@ -3904,7 +3921,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
-	intel_ddi_clk_select(encoder, crtc_state);
+	intel_ddi_enable_clock(encoder, crtc_state);
 
 	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 	dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
@@ -4056,7 +4073,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 					dig_port->ddi_io_power_domain,
 					fetch_and_zero(&dig_port->ddi_io_wakeref));
 
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 }
 
 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
@@ -4079,7 +4096,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
 				dig_port->ddi_io_power_domain,
 				fetch_and_zero(&dig_port->ddi_io_wakeref));
 
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 }
@@ -4179,7 +4196,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
 
 	intel_disable_ddi_buf(encoder, old_crtc_state);
-	intel_ddi_clk_disable(encoder);
+	intel_ddi_disable_clock(encoder);
 
 	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39397748b4b0..085162616112 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -219,6 +219,12 @@ struct intel_encoder {
 	 * encoders have been disabled and suspended.
 	 */
 	void (*shutdown)(struct intel_encoder *encoder);
+	/*
+	 * Enable/disable the clock to the port.
+	 */
+	void (*enable_clock)(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state);
+	void (*disable_clock)(struct intel_encoder *encoder);
 	enum hpd_pin hpd_pin;
 	enum intel_display_power_domain power_domain;
 	/* for communication with audio component; protected by av_mutex */
-- 
2.26.2

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[Intel-gfx] [PATCH 04/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++-----
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index da8bb9a2de0b..b46d7be1996b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3433,9 +3433,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		intel_de_write(dev_priv, DPLL_CTRL2, val);
 
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       hsw_pll_to_ddi_pll_sel(pll));
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -3458,12 +3455,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	} else if (IS_GEN9_BC(dev_priv)) {
 		intel_de_write(dev_priv, DPLL_CTRL2,
 			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       PORT_CLK_SEL_NONE);
 	}
 }
 
+static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	intel_de_write(dev_priv, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+}
+
+static void hsw_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(dev_priv, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+}
+
 static void intel_ddi_enable_clock(struct intel_encoder *encoder,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -5610,6 +5625,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
+	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+		encoder->enable_clock = hsw_ddi_enable_clock;
+		encoder->disable_clock = hsw_ddi_disable_clock;
+	}
+
 	if (IS_DG1(dev_priv))
 		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
 	else if (IS_ROCKETLAKE(dev_priv))
-- 
2.26.2

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[Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DDI clock routing clode for skl/derivatives
into the new encoder vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 53 +++++++++++++++++-------
 1 file changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b46d7be1996b..c50b20f5b3b6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3422,17 +3422,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
 		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
-	} else if (IS_GEN9_BC(dev_priv)) {
-		/* DDI -> PLL mapping  */
-		val = intel_de_read(dev_priv, DPLL_CTRL2);
-
-		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-		intel_de_write(dev_priv, DPLL_CTRL2, val);
-
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -3452,12 +3441,43 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		intel_de_write(dev_priv, DPCLKA_CFGCR0,
 			       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-	} else if (IS_GEN9_BC(dev_priv)) {
-		intel_de_write(dev_priv, DPLL_CTRL2,
-			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
 	}
 }
 
+static void skl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+	u32 val;
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	val = intel_de_read(dev_priv, DPLL_CTRL2);
+
+	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
+		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
+	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
+
+	intel_de_write(dev_priv, DPLL_CTRL2, val);
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
+static void skl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(dev_priv, DPLL_CTRL2,
+		       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+}
+
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -5625,7 +5645,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv)) {
+		encoder->enable_clock = skl_ddi_enable_clock;
+		encoder->disable_clock = skl_ddi_disable_clock;
+	} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
 		encoder->enable_clock = hsw_ddi_enable_clock;
 		encoder->disable_clock = hsw_ddi_disable_clock;
 	}
-- 
2.26.2

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[Intel-gfx] [PATCH 06/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DDI clock routing for CNL into the new vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 62 ++++++++++++++++--------
 1 file changed, 42 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c50b20f5b3b6..611495a78494 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3388,7 +3388,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
-	u32 val;
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
@@ -3407,21 +3406,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 			 */
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       DDI_CLK_SEL_MG);
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
-		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
-
-		/*
-		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
-		 * This step and the step before must be done with separate
-		 * register writes.
-		 */
-		val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-		intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -3438,12 +3422,47 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       DDI_CLK_SEL_NONE);
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		intel_de_write(dev_priv, DPCLKA_CFGCR0,
-			       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 	}
 }
 
+static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+	u32 val;
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
+	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+
+	/*
+	 * "This step and the step before must be
+	 *  done with separate register writes."
+	 */
+	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
+	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
+static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(dev_priv, DPCLKA_CFGCR0,
+		       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+}
+
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -5645,7 +5664,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		encoder->enable_clock = cnl_ddi_enable_clock;
+		encoder->disable_clock = cnl_ddi_disable_clock;
+	} else if (IS_GEN9_BC(dev_priv)) {
 		encoder->enable_clock = skl_ddi_enable_clock;
 		encoder->disable_clock = skl_ddi_disable_clock;
 	} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH 07/15] drm/i915: Convert DG1 over to .{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 611495a78494..39cbaa03d261 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3158,8 +3158,8 @@ static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
 		return ICL_DPCLKA_CFGCR0;
 }
 
-static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *crtc_state)
+static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -3192,6 +3192,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -3230,19 +3243,6 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
-}
-
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -4014,9 +4014,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (IS_DG1(dev_priv))
-		dg1_map_plls_to_ports(encoder, crtc_state);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_map_plls_to_ports(encoder, crtc_state);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -4217,9 +4215,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (IS_DG1(dev_priv))
-		dg1_unmap_plls_to_ports(encoder);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_unmap_plls_to_ports(encoder);
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
@@ -5664,7 +5660,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		encoder->enable_clock = dg1_ddi_enable_clock;
+		encoder->disable_clock = dg1_ddi_disable_clock;
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		encoder->enable_clock = cnl_ddi_enable_clock;
 		encoder->disable_clock = cnl_ddi_disable_clock;
 	} else if (IS_GEN9_BC(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH 08/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
   -> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
   and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
   -> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
   -> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
   the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
   -> these use both TC and combo DDIs with combo PHYs, however they
   always use the full combo style clock selection as per
   icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
   thus get treated the same as 2)

We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 149 +++++++++++++++--------
 1 file changed, 95 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 39cbaa03d261..aac85e86d776 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3205,8 +3205,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void icl_map_plls_to_ports(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *crtc_state)
+static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -3220,22 +3220,20 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	drm_WARN_ON(&dev_priv->drm,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
-	if (intel_phy_is_combo(dev_priv, phy)) {
-		/*
-		 * Even though this register references DDIs, note that we
-		 * want to pass the PHY rather than the port (DDI).  For
-		 * ICL, port=phy in all cases so it doesn't matter, but for
-		 * EHL the bspec notes the following:
-		 *
-		 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-		 *   Clock Select chooses the PLL for both DDIA and DDID and
-		 *   drives port A in all cases."
-		 */
-		val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
-		val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
-		intel_de_write(dev_priv, reg, val);
-		intel_de_posting_read(dev_priv, reg);
-	}
+	/*
+	 * Even though this register references DDIs, note that we
+	 * want to pass the PHY rather than the port (DDI).  For
+	 * ICL, port=phy in all cases so it doesn't matter, but for
+	 * EHL the bspec notes the following:
+	 *
+	 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+	 *   Clock Select chooses the PLL for both DDIA and DDID and
+	 *   drives port A in all cases."
+	 */
+	val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
+	val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
+	intel_de_write(dev_priv, reg, val);
+	intel_de_posting_read(dev_priv, reg);
 
 	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	intel_de_write(dev_priv, reg, val);
@@ -3243,7 +3241,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
+static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
@@ -3382,47 +3380,71 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
 }
 
-static void intel_ddi_clk_select(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *crtc_state)
+static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	/*
+	 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
+	 *  MG does not exist, but the programming is required to ungate DDIC and DDID."
+	 */
+	intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
+
+	icl_ddi_combo_enable_clock(encoder, crtc_state);
+}
+
+static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	icl_ddi_combo_disable_clock(encoder);
+
+	intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+}
+
+static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
+	enum port port = encoder->port;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
+	intel_de_write(dev_priv, DDI_CLK_SEL(port),
+		       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
+
 	mutex_lock(&dev_priv->dpll.lock);
 
-	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_phy_is_combo(dev_priv, phy))
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
-		else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
-			/*
-			 * MG does not exist but the programming is required
-			 * to ungate DDIC and DDID
-			 */
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       DDI_CLK_SEL_MG);
-	}
+	intel_de_rmw(dev_priv, ICL_DPCLKA_CFGCR0,
+		     ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void intel_ddi_clk_disable(struct intel_encoder *encoder)
+static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	enum port port = encoder->port;
-	enum phy phy = intel_port_to_phy(dev_priv, port);
-
-	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_phy_is_combo(dev_priv, phy) ||
-		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
-			intel_de_write(dev_priv, DDI_CLK_SEL(port),
-				       DDI_CLK_SEL_NONE);
-	}
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	intel_de_rmw(dev_priv, ICL_DPCLKA_CFGCR0,
+		     0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
+
+	mutex_unlock(&dev_priv->dpll.lock);
+
+	intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 }
 
 static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3523,16 +3545,12 @@ static void intel_ddi_enable_clock(struct intel_encoder *encoder,
 {
 	if (encoder->enable_clock)
 		encoder->enable_clock(encoder, crtc_state);
-	else
-		intel_ddi_clk_select(encoder, crtc_state);
 }
 
 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
 {
 	if (encoder->disable_clock)
 		encoder->disable_clock(encoder);
-	else
-		intel_ddi_clk_disable(encoder);
 }
 
 static void
@@ -4014,9 +4032,6 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
-		icl_map_plls_to_ports(encoder, crtc_state);
-
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -4215,9 +4230,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
-		icl_unmap_plls_to_ports(encoder);
-
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
 		intel_display_power_put(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port),
@@ -5556,6 +5568,16 @@ static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
 	return HPD_PORT_A + port - PORT_A;
 }
 
+static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
+{
+	if (INTEL_GEN(i915) >= 12)
+		return port >= PORT_TC1;
+	else if (INTEL_GEN(i915) >= 11)
+		return port >= PORT_C;
+	else
+		return false;
+}
+
 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
 
@@ -5660,9 +5682,28 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+		encoder->enable_clock = icl_ddi_combo_enable_clock;
+		encoder->disable_clock = icl_ddi_combo_disable_clock;
+	} else if (IS_DG1(dev_priv)) {
 		encoder->enable_clock = dg1_ddi_enable_clock;
 		encoder->disable_clock = dg1_ddi_disable_clock;
+	} else if (IS_JSL_EHL(dev_priv)) {
+		if (intel_ddi_is_tc(dev_priv, port)) {
+			encoder->enable_clock = jsl_ddi_tc_enable_clock;
+			encoder->disable_clock = jsl_ddi_tc_disable_clock;
+		} else {
+			encoder->enable_clock = icl_ddi_combo_enable_clock;
+			encoder->disable_clock = icl_ddi_combo_disable_clock;
+		}
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		if (intel_ddi_is_tc(dev_priv, port)) {
+			encoder->enable_clock = icl_ddi_tc_enable_clock;
+			encoder->disable_clock = icl_ddi_tc_disable_clock;
+		} else {
+			encoder->enable_clock = icl_ddi_combo_enable_clock;
+			encoder->disable_clock = icl_ddi_combo_disable_clock;
+		}
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		encoder->enable_clock = cnl_ddi_enable_clock;
 		encoder->disable_clock = cnl_ddi_disable_clock;
-- 
2.26.2

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[Intel-gfx] [PATCH 09/15] drm/i915: Use intel_de_rmw() for DDI clock routing

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 78 +++++++++---------------
 1 file changed, 28 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aac85e86d776..7137929f58bd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3164,7 +3164,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
@@ -3177,17 +3176,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
 
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-	val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3199,8 +3193,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3212,14 +3206,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-	u32 val;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
-
 	/*
 	 * Even though this register references DDIs, note that we
 	 * want to pass the PHY rather than the port (DDI).  For
@@ -3230,13 +3219,12 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	 *   Clock Select chooses the PLL for both DDIA and DDID and
 	 *   drives port A in all cases."
 	 */
-	val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
-	val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
-	intel_de_write(dev_priv, reg, val);
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
+		     icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy));
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3246,14 +3234,11 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-	u32 val;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3453,25 +3438,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
 
 	/*
 	 * "This step and the step before must be
 	 *  done with separate register writes."
 	 */
-	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3481,8 +3463,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(dev_priv, DPCLKA_CFGCR0,
-		       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3491,21 +3473,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DPLL_CTRL2);
-
-	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-	intel_de_write(dev_priv, DPLL_CTRL2, val);
+	intel_de_rmw(dev_priv, DPLL_CTRL2,
+		     DPLL_CTRL2_DDI_CLK_OFF(port) |
+		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
+		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3515,8 +3493,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(dev_priv, DPLL_CTRL2,
-		       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+	intel_de_rmw(dev_priv, DPLL_CTRL2,
+		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
 }
 
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH 10/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code attempts to protect the RMWs into global
clock routing registers with a mutex, but forgets to do so
in a few places. Let's remedy that.

Note that at the moment we serialize all modesets onto single
wq, so this shouldn't actually matter. But maybe one day we
wish to attempt parallel modesets again...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7137929f58bd..93552f3c2c43 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3463,8 +3463,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&dev_priv->dpll.lock);
+
 	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
 		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+
+	mutex_unlock(&dev_priv->dpll.lock);
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3493,8 +3497,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
+	mutex_lock(&dev_priv->dpll.lock);
+
 	intel_de_rmw(dev_priv, DPLL_CTRL2,
 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
+
+	mutex_unlock(&dev_priv->dpll.lock);
 }
 
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH 11/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the shared_dpll code (not sure it wouldn't
oops elsewhere though). So let's unify it all and sprinkle in
the missing WARNs for icl/dg1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 93552f3c2c43..b4984bbd7817 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3165,6 +3165,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
 	 * used by first 2 phys and last 2 PLLs by last phys
@@ -3207,6 +3210,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
 	mutex_lock(&dev_priv->dpll.lock);
 
 	/*
-- 
2.26.2

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[Intel-gfx] [PATCH 12/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the DPCLKA_CFGCR handling follows a common pattern. Let's
extract that to a small helper that just takes a few parameters
each caller can customize.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 112 ++++++++++-------------
 1 file changed, 46 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4984bbd7817..1bd2aa86183d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3158,11 +3158,37 @@ static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
 		return ICL_DPCLKA_CFGCR0;
 }
 
+static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
+{
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
+
+	/*
+	 * "This step and the step before must be
+	 *  done with separate register writes."
+	 */
+	intel_de_rmw(i915, reg, clk_off, 0);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
+static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+				   u32 clk_off)
+{
+	mutex_lock(&i915->dpll.lock);
+
+	intel_de_rmw(i915, reg, 0, clk_off);
+
+	mutex_unlock(&i915->dpll.lock);
+}
+
 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
@@ -3177,16 +3203,10 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
@@ -3194,59 +3214,33 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	/*
-	 * Even though this register references DDIs, note that we
-	 * want to pass the PHY rather than the port (DDI).  For
-	 * ICL, port=phy in all cases so it doesn't matter, but for
-	 * EHL the bspec notes the following:
-	 *
-	 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-	 *   Clock Select chooses the PLL for both DDIA and DDID and
-	 *   drives port A in all cases."
-	 */
-	intel_de_rmw(dev_priv, reg,
-		     icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
-		     icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy));
-
-	intel_de_rmw(dev_priv, reg,
-		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_enable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
+			      icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
+			      icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy),
+			      icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 }
 
 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, reg,
-		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_disable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
+			       icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 }
 
 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
@@ -3448,20 +3442,10 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
-		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
-		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
-
-	/*
-	 * "This step and the step before must be
-	 *  done with separate register writes."
-	 */
-	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
-		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_enable_clock(dev_priv, DPCLKA_CFGCR0,
+			      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+			      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
+			      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
@@ -3469,12 +3453,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
-		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-
-	mutex_unlock(&dev_priv->dpll.lock);
+	_cnl_ddi_disable_clock(dev_priv, DPCLKA_CFGCR0,
+			       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
have if-ladders inside them. Just provide specialized version for adlp
and rkl so we don't need any of that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++++++++++++++++--------
 1 file changed, 62 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1bd2aa86183d..bafb754d1b66 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,28 +3127,6 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
-				     enum intel_dpll_id id, enum phy phy)
-{
-	if (IS_ALDERLAKE_S(dev_priv))
-		return id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
-	else if (IS_ROCKETLAKE(dev_priv))
-		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
-	else
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
-}
-
-static u32 icl_dpclka_cfgcr0_clk_sel_mask(struct drm_i915_private *dev_priv,
-					  enum phy phy)
-{
-	if (IS_ALDERLAKE_S(dev_priv))
-		return ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
-	else if (IS_ROCKETLAKE(dev_priv))
-		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-	else
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-}
-
 static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
 					enum phy phy)
 {
@@ -3184,6 +3162,56 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
 	mutex_unlock(&i915->dpll.lock);
 }
 
+static void adls_ddi_enable_clock(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	_cnl_ddi_enable_clock(dev_priv, ADLS_DPCLKA_CFGCR(phy),
+			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
+			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void adls_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	_cnl_ddi_disable_clock(dev_priv, ADLS_DPCLKA_CFGCR(phy),
+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
+
+	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -3228,10 +3256,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
-			      icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
-			      icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy),
-			      icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
+	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
@@ -3239,8 +3267,8 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	_cnl_ddi_disable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
-			       icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
+	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
@@ -5654,9 +5682,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
-		encoder->enable_clock = icl_ddi_combo_enable_clock;
-		encoder->disable_clock = icl_ddi_combo_disable_clock;
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		encoder->enable_clock = adls_ddi_enable_clock;
+		encoder->disable_clock = adls_ddi_disable_clock;
+	} else if (IS_ROCKETLAKE(dev_priv)) {
+		encoder->enable_clock = rkl_ddi_enable_clock;
+		encoder->disable_clock = rkl_ddi_disable_clock;
 	} else if (IS_DG1(dev_priv)) {
 		encoder->enable_clock = dg1_ddi_enable_clock;
 		encoder->disable_clock = dg1_ddi_disable_clock;
-- 
2.26.2

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[Intel-gfx] [PATCH 14/15] drm/i915: Use .disable_clock() for pll sanitation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Instead of every new platform having yet another masive
copy of the whole PLL sanitation code, let's just reuse the
.disable_clock() hook for this purpose. We do need to plug
this into the ICL+ DSI code for that, but fortunately it
already has a suitable function we can use.

We do lose the debug message though on account of not bothering
to check if the clock is actually enabled or not before turning
it off. We could introduce yet another vfunc to query the current
state, but not sure it's worth the hassle?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c   |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c | 96 +-----------------------
 2 files changed, 3 insertions(+), 94 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9d245a689323..a7edfaa09035 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1940,6 +1940,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->pipe_mask = ~0;
 	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
 	encoder->get_power_domains = gen11_dsi_get_power_domains;
+	encoder->disable_clock = gen11_dsi_gate_clocks;
 
 	/* register DSI connector with DRM subsystem */
 	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bafb754d1b66..a619afde1ad0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3110,32 +3110,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
-static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-				     enum phy phy)
-{
-	if (IS_ROCKETLAKE(dev_priv)) {
-		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	} else if (intel_phy_is_combo(dev_priv, phy)) {
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	} else if (intel_phy_is_tc(dev_priv, phy)) {
-		enum tc_port tc_port = intel_port_to_tc(dev_priv,
-							(enum port)phy);
-
-		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
-	}
-
-	return 0;
-}
-
-static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
-					enum phy phy)
-{
-	if (IS_ALDERLAKE_S(i915))
-		return ADLS_DPCLKA_CFGCR(phy);
-	else
-		return ICL_DPCLKA_CFGCR0;
-}
-
 static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
 				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
 {
@@ -3271,70 +3245,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
-static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
-				      u32 port_mask, bool ddi_clk_needed)
-{
-	enum port port;
-	u32 val;
-
-	for_each_port_masked(port, port_mask) {
-		enum phy phy = intel_port_to_phy(dev_priv, port);
-		bool ddi_clk_off;
-
-		val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-		ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-
-		if (ddi_clk_needed == !ddi_clk_off)
-			continue;
-
-		/*
-		 * Punt on the case now where clock is gated, but it would
-		 * be needed by the port. Something else is really broken then.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
-			continue;
-
-		drm_notice(&dev_priv->drm,
-			   "PHY %c is disabled with an ungated DDI clock, gate it\n",
-			   phy_name(phy));
-		val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-		intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	}
-}
-
-static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
-				      u32 port_mask, bool ddi_clk_needed)
-{
-	enum port port;
-	bool ddi_clk_off;
-	u32 val;
-
-	for_each_port_masked(port, port_mask) {
-		enum phy phy = intel_port_to_phy(dev_priv, port);
-		i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-
-		val = intel_de_read(dev_priv, reg);
-		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
-							      phy);
-
-		if (ddi_clk_needed == !ddi_clk_off)
-			continue;
-
-		/*
-		 * Punt on the case now where clock is gated, but it would
-		 * be needed by the port. Something else is really broken then.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
-			continue;
-
-		drm_notice(&dev_priv->drm,
-			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
-			   phy_name(phy));
-		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-		intel_de_write(dev_priv, reg, val);
-	}
-}
-
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3387,10 +3297,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		ddi_clk_needed = false;
 	}
 
-	if (IS_DG1(dev_priv))
-		dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
-	else
-		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+	if (!ddi_clk_needed && encoder->disable_clock)
+		encoder->disable_clock(encoder);
 }
 
 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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[Intel-gfx] [PATCH 15/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move icl_sanitize_encoder_pll_mapping() out from the middle
of the .{enable,disable}_clock() functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++++++++++------------
 1 file changed, 56 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a619afde1ad0..95c5c8eea94a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3245,62 +3245,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
-void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u32 port_mask;
-	bool ddi_clk_needed;
-
-	/*
-	 * In case of DP MST, we sanitize the primary encoder only, not the
-	 * virtual ones.
-	 */
-	if (encoder->type == INTEL_OUTPUT_DP_MST)
-		return;
-
-	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
-		u8 pipe_mask;
-		bool is_mst;
-
-		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
-		/*
-		 * In the unlikely case that BIOS enables DP in MST mode, just
-		 * warn since our MST HW readout is incomplete.
-		 */
-		if (drm_WARN_ON(&dev_priv->drm, is_mst))
-			return;
-	}
-
-	port_mask = BIT(encoder->port);
-	ddi_clk_needed = encoder->base.crtc;
-
-	if (encoder->type == INTEL_OUTPUT_DSI) {
-		struct intel_encoder *other_encoder;
-
-		port_mask = intel_dsi_encoder_ports(encoder);
-		/*
-		 * Sanity check that we haven't incorrectly registered another
-		 * encoder using any of the ports of this DSI encoder.
-		 */
-		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
-			if (other_encoder == encoder)
-				continue;
-
-			if (drm_WARN_ON(&dev_priv->drm,
-					port_mask & BIT(other_encoder->port)))
-				return;
-		}
-		/*
-		 * For DSI we keep the ddi clocks gated
-		 * except during enable/disable sequence.
-		 */
-		ddi_clk_needed = false;
-	}
-
-	if (!ddi_clk_needed && encoder->disable_clock)
-		encoder->disable_clock(encoder);
-}
-
 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -3461,6 +3405,62 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
 		encoder->disable_clock(encoder);
 }
 
+void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	u32 port_mask;
+	bool ddi_clk_needed;
+
+	/*
+	 * In case of DP MST, we sanitize the primary encoder only, not the
+	 * virtual ones.
+	 */
+	if (encoder->type == INTEL_OUTPUT_DP_MST)
+		return;
+
+	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
+		u8 pipe_mask;
+		bool is_mst;
+
+		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
+		/*
+		 * In the unlikely case that BIOS enables DP in MST mode, just
+		 * warn since our MST HW readout is incomplete.
+		 */
+		if (drm_WARN_ON(&dev_priv->drm, is_mst))
+			return;
+	}
+
+	port_mask = BIT(encoder->port);
+	ddi_clk_needed = encoder->base.crtc;
+
+	if (encoder->type == INTEL_OUTPUT_DSI) {
+		struct intel_encoder *other_encoder;
+
+		port_mask = intel_dsi_encoder_ports(encoder);
+		/*
+		 * Sanity check that we haven't incorrectly registered another
+		 * encoder using any of the ports of this DSI encoder.
+		 */
+		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
+			if (other_encoder == encoder)
+				continue;
+
+			if (drm_WARN_ON(&dev_priv->drm,
+					port_mask & BIT(other_encoder->port)))
+				return;
+		}
+		/*
+		 * For DSI we keep the ddi clocks gated
+		 * except during enable/disable sequence.
+		 */
+		ddi_clk_needed = false;
+	}
+
+	if (!ddi_clk_needed && encoder->disable_clock)
+		encoder->disable_clock(encoder);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 01/15] drm/i915: Extract icl_dpclka_cfgcr0_reg()

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:29PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Extract the code to determine the DPCLK_CFGCR register
>to use.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++--------------
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 5bc5033a2dea..a3aeb1c2821c 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3127,6 +3127,15 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> 	return 0;
> }
>
>+static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
>+					enum phy phy)
>+{
>+	if (IS_ALDERLAKE_S(i915))
>+		return ADLS_DPCLKA_CFGCR(phy);
>+	else
>+		return ICL_DPCLKA_CFGCR0;
>+}
>+
> static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
> 				  const struct intel_crtc_state *crtc_state)
> {
>@@ -3167,19 +3176,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
> 	u32 val, mask, sel;
>-	i915_reg_t reg;
>
> 	if (IS_ALDERLAKE_S(dev_priv)) {
>-		reg = ADLS_DPCLKA_CFGCR(phy);
> 		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> 		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
> 	} else if (IS_ROCKETLAKE(dev_priv)) {
>-		reg = ICL_DPCLKA_CFGCR0;
> 		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> 		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> 	} else {
>-		reg = ICL_DPCLKA_CFGCR0;
> 		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> 		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> 	}
>@@ -3230,16 +3236,11 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
> 	u32 val;
>-	i915_reg_t reg;
>
> 	mutex_lock(&dev_priv->dpll.lock);
>
>-	if (IS_ALDERLAKE_S(dev_priv))
>-		reg = ADLS_DPCLKA_CFGCR(phy);
>-	else
>-		reg = ICL_DPCLKA_CFGCR0;
>-
> 	val = intel_de_read(dev_priv, reg);
> 	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>
>@@ -3285,15 +3286,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
> 	enum port port;
> 	bool ddi_clk_off;
> 	u32 val;
>-	i915_reg_t reg;
>
> 	for_each_port_masked(port, port_mask) {
> 		enum phy phy = intel_port_to_phy(dev_priv, port);
>-
>-		if (IS_ALDERLAKE_S(dev_priv))
>-			reg = ADLS_DPCLKA_CFGCR(phy);
>-		else
>-			reg = ICL_DPCLKA_CFGCR0;
>+		i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
>
> 		val = intel_de_read(dev_priv, reg);
> 		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 02/15] drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:30PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Extract some helpers to calculate the correct CLK_SEL values
>for DPCLKA_CFGCR.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++++++++++++---------
> 1 file changed, 25 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index a3aeb1c2821c..23fbb9013e09 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3127,6 +3127,28 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> 	return 0;
> }
>
>+static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
>+				     enum intel_dpll_id id, enum phy phy)
>+{
>+	if (IS_ALDERLAKE_S(dev_priv))
>+		return id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);

for consistency we should actually have a _SEL macro like below, or....

>+	else if (IS_ROCKETLAKE(dev_priv))
>+		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
>+	else
>+		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
>+}
>+
>+static u32 icl_dpclka_cfgcr0_clk_sel_mask(struct drm_i915_private *dev_priv,
>+					  enum phy phy)
>+{
>+	if (IS_ALDERLAKE_S(dev_priv))
>+		return ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
>+	else if (IS_ROCKETLAKE(dev_priv))
>+		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>+	else
>+		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>+}

since now we have a separate function for that, do we even need the
macro definitions? We could very well just nuke them.

anyway, for this mechanical move


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>+
> static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
> 					enum phy phy)
> {
>@@ -3177,18 +3199,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
>-	u32 val, mask, sel;
>-
>-	if (IS_ALDERLAKE_S(dev_priv)) {
>-		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
>-		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
>-	} else if (IS_ROCKETLAKE(dev_priv)) {
>-		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>-		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>-	} else {
>-		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>-		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>-	}
>+	u32 val;
>
> 	mutex_lock(&dev_priv->dpll.lock);
>
>@@ -3207,8 +3218,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> 		 *   Clock Select chooses the PLL for both DDIA and DDID and
> 		 *   drives port A in all cases."
> 		 */
>-		val &= ~mask;
>-		val |= sel;
>+		val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
>+		val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
> 		intel_de_write(dev_priv, reg, val);
> 		intel_de_posting_read(dev_priv, reg);
> 	}
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:31PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The current code dealing with the clock routing for DDI encoders
>is a maintenance nightmare. Let's start cleaning it up by allowing
>the encoder to provide vfuncs for enablign/disabling the clock.
>
>We leave them initially unimplemented, falling back to the old
>if-else approach.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c      | 29 +++++++++++++++----
> .../drm/i915/display/intel_display_types.h    |  6 ++++
> 2 files changed, 29 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 23fbb9013e09..da8bb9a2de0b 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3464,6 +3464,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> 	}
> }
>
>+static void intel_ddi_enable_clock(struct intel_encoder *encoder,
>+				   const struct intel_crtc_state *crtc_state)
>+{
>+	if (encoder->enable_clock)
>+		encoder->enable_clock(encoder, crtc_state);
>+	else
>+		intel_ddi_clk_select(encoder, crtc_state);
>+}
>+
>+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
>+{
>+	if (encoder->disable_clock)
>+		encoder->disable_clock(encoder);
>+	else
>+		intel_ddi_clk_disable(encoder);

intel_ddi_disable_clock  vs  intel_ddi_clk_disable

I think the names here is very prone to mistake. Maybe we should come
back with better names?  We could have renamed intel_ddi_clk_disable to
__ddi_clk_disable in this patch, since we are going to remove the
function once everything is converted.

Lucas De Marchi


>+}
>+
> static void
> icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> 		       const struct intel_crtc_state *crtc_state)
>@@ -3708,7 +3725,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> 	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
> 	 * configure the PLL to port mapping here.
> 	 */
>-	intel_ddi_clk_select(encoder, crtc_state);
>+	intel_ddi_enable_clock(encoder, crtc_state);
>
> 	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
> 	if (!intel_phy_is_tc(dev_priv, phy) ||
>@@ -3829,7 +3846,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>
> 	intel_pps_on(intel_dp);
>
>-	intel_ddi_clk_select(encoder, crtc_state);
>+	intel_ddi_enable_clock(encoder, crtc_state);
>
> 	if (!intel_phy_is_tc(dev_priv, phy) ||
> 	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
>@@ -3904,7 +3921,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
>-	intel_ddi_clk_select(encoder, crtc_state);
>+	intel_ddi_enable_clock(encoder, crtc_state);
>
> 	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
> 	dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
>@@ -4056,7 +4073,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> 					dig_port->ddi_io_power_domain,
> 					fetch_and_zero(&dig_port->ddi_io_wakeref));
>
>-	intel_ddi_clk_disable(encoder);
>+	intel_ddi_disable_clock(encoder);
> }
>
> static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
>@@ -4079,7 +4096,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
> 				dig_port->ddi_io_power_domain,
> 				fetch_and_zero(&dig_port->ddi_io_wakeref));
>
>-	intel_ddi_clk_disable(encoder);
>+	intel_ddi_disable_clock(encoder);
>
> 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
> }
>@@ -4179,7 +4196,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
> 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
>
> 	intel_disable_ddi_buf(encoder, old_crtc_state);
>-	intel_ddi_clk_disable(encoder);
>+	intel_ddi_disable_clock(encoder);
>
> 	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>index 39397748b4b0..085162616112 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_types.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>@@ -219,6 +219,12 @@ struct intel_encoder {
> 	 * encoders have been disabled and suspended.
> 	 */
> 	void (*shutdown)(struct intel_encoder *encoder);
>+	/*
>+	 * Enable/disable the clock to the port.
>+	 */
>+	void (*enable_clock)(struct intel_encoder *encoder,
>+			     const struct intel_crtc_state *crtc_state);
>+	void (*disable_clock)(struct intel_encoder *encoder);
> 	enum hpd_pin hpd_pin;
> 	enum intel_display_power_domain power_domain;
> 	/* for communication with audio component; protected by av_mutex */
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 04/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:32PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
>and put it into the new encoder .{enable,disable}_clock() vfuncs.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++-----
> 1 file changed, 26 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index da8bb9a2de0b..b46d7be1996b 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3433,9 +3433,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>
> 		intel_de_write(dev_priv, DPLL_CTRL2, val);
>
>-	} else if (INTEL_GEN(dev_priv) < 9) {
>-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
>-			       hsw_pll_to_ddi_pll_sel(pll));
> 	}
>
> 	mutex_unlock(&dev_priv->dpll.lock);
>@@ -3458,12 +3455,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> 	} else if (IS_GEN9_BC(dev_priv)) {
> 		intel_de_write(dev_priv, DPLL_CTRL2,
> 			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
>-	} else if (INTEL_GEN(dev_priv) < 9) {
>-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
>-			       PORT_CLK_SEL_NONE);
> 	}
> }
>
>+static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
>+				 const struct intel_crtc_state *crtc_state)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

since we are adding this new function, better to use i915 rather than
dev_priv.

Lucas De Marchi
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Re: [Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 11:04:40AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:31PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >The current code dealing with the clock routing for DDI encoders
> >is a maintenance nightmare. Let's start cleaning it up by allowing
> >the encoder to provide vfuncs for enablign/disabling the clock.
> >
> >We leave them initially unimplemented, falling back to the old
> >if-else approach.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c      | 29 +++++++++++++++----
> > .../drm/i915/display/intel_display_types.h    |  6 ++++
> > 2 files changed, 29 insertions(+), 6 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index 23fbb9013e09..da8bb9a2de0b 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -3464,6 +3464,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> > 	}
> > }
> >
> >+static void intel_ddi_enable_clock(struct intel_encoder *encoder,
> >+				   const struct intel_crtc_state *crtc_state)
> >+{
> >+	if (encoder->enable_clock)
> >+		encoder->enable_clock(encoder, crtc_state);
> >+	else
> >+		intel_ddi_clk_select(encoder, crtc_state);
> >+}
> >+
> >+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
> >+{
> >+	if (encoder->disable_clock)
> >+		encoder->disable_clock(encoder);
> >+	else
> >+		intel_ddi_clk_disable(encoder);
> 
> intel_ddi_disable_clock  vs  intel_ddi_clk_disable
> 
> I think the names here is very prone to mistake. Maybe we should come
> back with better names?  We could have renamed intel_ddi_clk_disable to
> __ddi_clk_disable in this patch, since we are going to remove the
> function once everything is converted.

It's a dead man walking anyway. Don't see much point in renaming it.

> 
> Lucas De Marchi
> 
> 
> >+}
> >+
> > static void
> > icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> > 		       const struct intel_crtc_state *crtc_state)
> >@@ -3708,7 +3725,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > 	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
> > 	 * configure the PLL to port mapping here.
> > 	 */
> >-	intel_ddi_clk_select(encoder, crtc_state);
> >+	intel_ddi_enable_clock(encoder, crtc_state);
> >
> > 	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
> > 	if (!intel_phy_is_tc(dev_priv, phy) ||
> >@@ -3829,7 +3846,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >
> > 	intel_pps_on(intel_dp);
> >
> >-	intel_ddi_clk_select(encoder, crtc_state);
> >+	intel_ddi_enable_clock(encoder, crtc_state);
> >
> > 	if (!intel_phy_is_tc(dev_priv, phy) ||
> > 	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
> >@@ -3904,7 +3921,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> > 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >
> > 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> >-	intel_ddi_clk_select(encoder, crtc_state);
> >+	intel_ddi_enable_clock(encoder, crtc_state);
> >
> > 	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
> > 	dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
> >@@ -4056,7 +4073,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> > 					dig_port->ddi_io_power_domain,
> > 					fetch_and_zero(&dig_port->ddi_io_wakeref));
> >
> >-	intel_ddi_clk_disable(encoder);
> >+	intel_ddi_disable_clock(encoder);
> > }
> >
> > static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
> >@@ -4079,7 +4096,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
> > 				dig_port->ddi_io_power_domain,
> > 				fetch_and_zero(&dig_port->ddi_io_wakeref));
> >
> >-	intel_ddi_clk_disable(encoder);
> >+	intel_ddi_disable_clock(encoder);
> >
> > 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
> > }
> >@@ -4179,7 +4196,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
> > 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> >
> > 	intel_disable_ddi_buf(encoder, old_crtc_state);
> >-	intel_ddi_clk_disable(encoder);
> >+	intel_ddi_disable_clock(encoder);
> >
> > 	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
> > 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >index 39397748b4b0..085162616112 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >@@ -219,6 +219,12 @@ struct intel_encoder {
> > 	 * encoders have been disabled and suspended.
> > 	 */
> > 	void (*shutdown)(struct intel_encoder *encoder);
> >+	/*
> >+	 * Enable/disable the clock to the port.
> >+	 */
> >+	void (*enable_clock)(struct intel_encoder *encoder,
> >+			     const struct intel_crtc_state *crtc_state);
> >+	void (*disable_clock)(struct intel_encoder *encoder);
> > 	enum hpd_pin hpd_pin;
> > 	enum intel_display_power_domain power_domain;
> > 	/* for communication with audio component; protected by av_mutex */
> >-- 
> >2.26.2
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 10/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:38PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The current code attempts to protect the RMWs into global
>clock routing registers with a mutex, but forgets to do so
>in a few places. Let's remedy that.

Forgets or doesn't do on purpose? In the first patches in this series I
was actually wondering why do we even have to take the lock you were
adding for some platforms.

>
>Note that at the moment we serialize all modesets onto single
>wq, so this shouldn't actually matter. But maybe one day we
>wish to attempt parallel modesets again...

and this answers that. But why don't we just stop getting the lock and
reintroduce them if/when we attempt parallel modeset?

Lucas De Marchi

>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 7137929f58bd..93552f3c2c43 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3463,8 +3463,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>
>+	mutex_lock(&dev_priv->dpll.lock);
>+
> 	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
> 		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
>+
>+	mutex_unlock(&dev_priv->dpll.lock);
> }
>
> static void skl_ddi_enable_clock(struct intel_encoder *encoder,
>@@ -3493,8 +3497,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>
>+	mutex_lock(&dev_priv->dpll.lock);
>+
> 	intel_de_rmw(dev_priv, DPLL_CTRL2,
> 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
>+
>+	mutex_unlock(&dev_priv->dpll.lock);
> }
>
> static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 11/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:39PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The other DDI .enable_clock() functions are trying to protect us
>against pll==NULL. A bit tempted to throw out all the WARNs as
>just unnecessary noise, but I guess they might have some use
>when poking around the shared_dpll code (not sure it wouldn't
>oops elsewhere though). So let's unify it all and sprinkle in
>the missing WARNs for icl/dg1.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 93552f3c2c43..b4984bbd7817 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3165,6 +3165,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
>+	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+		return;
>+
> 	/*
> 	 * If we fail this, something went very wrong: first 2 PLLs should be
> 	 * used by first 2 phys and last 2 PLLs by last phys
>@@ -3207,6 +3210,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
>
>+	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+		return;
>+
> 	mutex_lock(&dev_priv->dpll.lock);
>
> 	/*
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 04/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 11:07:20AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:32PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
> >and put it into the new encoder .{enable,disable}_clock() vfuncs.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++-----
> > 1 file changed, 26 insertions(+), 6 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index da8bb9a2de0b..b46d7be1996b 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -3433,9 +3433,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> >
> > 		intel_de_write(dev_priv, DPLL_CTRL2, val);
> >
> >-	} else if (INTEL_GEN(dev_priv) < 9) {
> >-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
> >-			       hsw_pll_to_ddi_pll_sel(pll));
> > 	}
> >
> > 	mutex_unlock(&dev_priv->dpll.lock);
> >@@ -3458,12 +3455,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> > 	} else if (IS_GEN9_BC(dev_priv)) {
> > 		intel_de_write(dev_priv, DPLL_CTRL2,
> > 			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
> >-	} else if (INTEL_GEN(dev_priv) < 9) {
> >-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
> >-			       PORT_CLK_SEL_NONE);
> > 	}
> > }
> >
> >+static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> >+				 const struct intel_crtc_state *crtc_state)
> >+{
> >+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
> since we are adding this new function, better to use i915 rather than
> dev_priv.

Hmm. Yeah, looks like we can do that in this case since
PORT_CLK_SEL() doesn't depend on 'dev_priv'. I'm just too lazy
to always check for that, and so I tend to do the rename only
when there are no register accesses in the function.

-- 
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Re: [Intel-gfx] [PATCH 10/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 11:15:01AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:38PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >The current code attempts to protect the RMWs into global
> >clock routing registers with a mutex, but forgets to do so
> >in a few places. Let's remedy that.
> 
> Forgets or doesn't do on purpose? In the first patches in this series I
> was actually wondering why do we even have to take the lock you were
> adding for some platforms.
> 
> >
> >Note that at the moment we serialize all modesets onto single
> >wq, so this shouldn't actually matter. But maybe one day we
> >wish to attempt parallel modesets again...
> 
> and this answers that. But why don't we just stop getting the lock and
> reintroduce them if/when we attempt parallel modeset?

I suspect that will pretty much guarantee that it'll never
happen, because last time it was tried no one bothered to
do any kind of code review for these kinds of problems. So
I think we'll just have to keep sprinkling the locks as we
find such code, and then maybe one day we can attempt to
throw the switch again.

> 
> Lucas De Marchi
> 
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index 7137929f58bd..93552f3c2c43 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -3463,8 +3463,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
> > 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > 	enum port port = encoder->port;
> >
> >+	mutex_lock(&dev_priv->dpll.lock);
> >+
> > 	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
> > 		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> >+
> >+	mutex_unlock(&dev_priv->dpll.lock);
> > }
> >
> > static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> >@@ -3493,8 +3497,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
> > 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > 	enum port port = encoder->port;
> >
> >+	mutex_lock(&dev_priv->dpll.lock);
> >+
> > 	intel_de_rmw(dev_priv, DPLL_CTRL2,
> > 		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
> >+
> >+	mutex_unlock(&dev_priv->dpll.lock);
> > }
> >
> > static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> >-- 
> >2.26.2
> >
> >_______________________________________________
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> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
>have if-ladders inside them. Just provide specialized version for adlp
>and rkl so we don't need any of that.

s/alds/adl-s/

s/adlp/adl-s/


>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++++++++++++++++--------
> 1 file changed, 62 insertions(+), 31 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 1bd2aa86183d..bafb754d1b66 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3127,28 +3127,6 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> 	return 0;
> }
>
>-static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
>-				     enum intel_dpll_id id, enum phy phy)

ok, but why do we even add them in this series if we are going to
remove. Just makes it harder to review.

For this end state:


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>-{
>-	if (IS_ALDERLAKE_S(dev_priv))
>-		return id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
>-	else if (IS_ROCKETLAKE(dev_priv))
>-		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
>-	else
>-		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy);
>-}
>-
>-static u32 icl_dpclka_cfgcr0_clk_sel_mask(struct drm_i915_private *dev_priv,
>-					  enum phy phy)
>-{
>-	if (IS_ALDERLAKE_S(dev_priv))
>-		return ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
>-	else if (IS_ROCKETLAKE(dev_priv))
>-		return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>-	else
>-		return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>-}
>-
> static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
> 					enum phy phy)
> {
>@@ -3184,6 +3162,56 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
> 	mutex_unlock(&i915->dpll.lock);
> }
>
>+static void adls_ddi_enable_clock(struct intel_encoder *encoder,
>+				  const struct intel_crtc_state *crtc_state)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+		return;
>+
>+	_cnl_ddi_enable_clock(dev_priv, ADLS_DPCLKA_CFGCR(phy),
>+			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
>+			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
>+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>+}
>+
>+static void adls_ddi_disable_clock(struct intel_encoder *encoder)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+	_cnl_ddi_disable_clock(dev_priv, ADLS_DPCLKA_CFGCR(phy),
>+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>+}
>+
>+static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
>+				 const struct intel_crtc_state *crtc_state)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+	if (drm_WARN_ON(&dev_priv->drm, !pll))
>+		return;
>+
>+	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>+			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
>+			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>+}
>+
>+static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>+}
>+
> static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> 				 const struct intel_crtc_state *crtc_state)
> {
>@@ -3228,10 +3256,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> 	if (drm_WARN_ON(&dev_priv->drm, !pll))
> 		return;
>
>-	_cnl_ddi_enable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
>-			      icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
>-			      icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy),
>-			      icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
>+	_cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>+			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
>+			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
>@@ -3239,8 +3267,8 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
>-	_cnl_ddi_disable_clock(dev_priv, icl_dpclka_cfgcr0_reg(dev_priv, phy),
>-			       icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
>+	_cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
>+			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
>@@ -5654,9 +5682,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> 	encoder->cloneable = 0;
> 	encoder->pipe_mask = ~0;
>
>-	if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
>-		encoder->enable_clock = icl_ddi_combo_enable_clock;
>-		encoder->disable_clock = icl_ddi_combo_disable_clock;
>+	if (IS_ALDERLAKE_S(dev_priv)) {
>+		encoder->enable_clock = adls_ddi_enable_clock;
>+		encoder->disable_clock = adls_ddi_disable_clock;
>+	} else if (IS_ROCKETLAKE(dev_priv)) {
>+		encoder->enable_clock = rkl_ddi_enable_clock;
>+		encoder->disable_clock = rkl_ddi_disable_clock;
> 	} else if (IS_DG1(dev_priv)) {
> 		encoder->enable_clock = dg1_ddi_enable_clock;
> 		encoder->disable_clock = dg1_ddi_disable_clock;
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess

[Lucas De Marchi]

On Mon, Feb 01, 2021 at 08:33:28PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The DDI clock routing code has turned into proper spaghetti.
>Attempt to clean it up by introducing some new vfuncs.

A few minors I replied in the series. The move back and forth from one
approach to the other IMO makes it harder to review, but after looking
that the complete set:

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>
>Ville Syrjälä (15):
>  drm/i915: Extract icl_dpclka_cfgcr0_reg()
>  drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
>  drm/i915: Introduce .{enable,disable}_clock() encoder vfuncs
>  drm/i915: Extract hsw_ddi_{enable,disable}_clock()
>  drm/i915: Extract skl_ddi_{enable,disable}_clock()
>  drm/i195: Extract cnl_ddi_{enable,disable}_clock()
>  drm/i915: Convert DG1 over to .{enable,disable}_clock()
>  drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
>  drm/i915: Use intel_de_rmw() for DDI clock routing
>  drm/i915: Sprinkle a few missing locks around shared DDI clock
>    registers
>  drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
>  drm/i915: Extract _cnl_ddi_{enable,disable}_clock()
>  drm/i915: Split alds/rkl from icl_ddi_combo_{enable,disable}_clock()
>  drm/i915: Use .disable_clock() for pll sanitation
>  drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
>
> drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
> drivers/gpu/drm/i915/display/intel_ddi.c      | 536 ++++++++++--------
> .../drm/i915/display/intel_display_types.h    |   6 +
> 3 files changed, 295 insertions(+), 248 deletions(-)
>
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 11:22:39AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
> >have if-ladders inside them. Just provide specialized version for adlp
> >and rkl so we don't need any of that.
> 
> s/alds/adl-s/
> 
> s/adlp/adl-s/
> 
> 
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++++++++++++++++--------
> > 1 file changed, 62 insertions(+), 31 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index 1bd2aa86183d..bafb754d1b66 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -3127,28 +3127,6 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> > 	return 0;
> > }
> >
> >-static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
> >-				     enum intel_dpll_id id, enum phy phy)
> 
> ok, but why do we even add them in this series if we are going to
> remove. Just makes it harder to review.

I had to increase the SNR before I could see what the code was
trying to do. I guess I could now go back and drop the first
two patches.

-- 
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Re: [Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 09:31:49PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 01, 2021 at 11:22:39AM -0800, Lucas De Marchi wrote:
> > On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
> > >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > >Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
> > >have if-ladders inside them. Just provide specialized version for adlp
> > >and rkl so we don't need any of that.
> > 
> > s/alds/adl-s/
> > 
> > s/adlp/adl-s/
> > 
> > 
> > >
> > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++++++++++++++++--------
> > > 1 file changed, 62 insertions(+), 31 deletions(-)
> > >
> > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >index 1bd2aa86183d..bafb754d1b66 100644
> > >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >@@ -3127,28 +3127,6 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> > > 	return 0;
> > > }
> > >
> > >-static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv,
> > >-				     enum intel_dpll_id id, enum phy phy)
> > 
> > ok, but why do we even add them in this series if we are going to
> > remove. Just makes it harder to review.
> 
> I had to increase the SNR before I could see what the code was
> trying to do. I guess I could now go back and drop the first
> two patches.

One counter argument would be that we already had
icl_dpclka_cfgcr0_clk_off(), so not unifying the approach first
means the other refactorings have to deal with two different
styles, and thus could end up looking even more confusing.

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess
URL   : https://patchwork.freedesktop.org/series/86544/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
83a4bb6e6220 drm/i915: Extract icl_dpclka_cfgcr0_reg()
55c608204619 drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
896a544d3328 drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
732fae08fafa drm/i915: Extract hsw_ddi_{enable, disable}_clock()
e75c39a95d43 drm/i915: Extract skl_ddi_{enable, disable}_clock()
26c2a16ac8ae drm/i195: Extract cnl_ddi_{enable, disable}_clock()
d9f0d9ea2d01 drm/i915: Convert DG1 over to .{enable, disable}_clock()
aa859cf415e0 drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12: 
   and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()

total: 0 errors, 1 warnings, 0 checks, 227 lines checked
e9b82425593e drm/i915: Use intel_de_rmw() for DDI clock routing
acdaeff0d22f drm/i915: Sprinkle a few missing locks around shared DDI clock registers
fa3178994587 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
1f48cc5cbdb8 drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
7c936097f280 drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()
5f0caa42e34a drm/i915: Use .disable_clock() for pll sanitation
a5c9c286cd25 drm/i915: Relocate icl_sanitize_encoder_pll_mapping()


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up the DDI clock routing mess

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess
URL   : https://patchwork.freedesktop.org/series/86544/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing mess

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 5876 bytes --]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess
URL   : https://patchwork.freedesktop.org/series/86544/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19556 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19556, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19556:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_19556 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@prime_self_import@basic-with_two_bos:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@gem_mmap_gtt@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@gem_mmap_gtt@basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-cfl-8109u:       [DMESG-WARN][9] ([i915#203]) -> [PASS][10] +27 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@execlists:
    - fi-cfl-8109u:       [DMESG-WARN][11] ([i915#1037]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_engines:
    - fi-cfl-8109u:       [DMESG-WARN][13] -> [PASS][14] +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7500u:       [DMESG-WARN][15] ([i915#2605]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html

  
  [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 39)
------------------------------

  Missing    (6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9713 -> Patchwork_19556

  CI-20190529: 20190529
  CI_DRM_9713: cc7b6cbff2a0a75ad4fe84d055ee1a762f0ce64b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5984: ccfc101419c1e233f87ca509781c5f8e09a2f3ae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19556: a5c9c286cd254d7ea6cf92303ecd91b8918a7945 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a5c9c286cd25 drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
5f0caa42e34a drm/i915: Use .disable_clock() for pll sanitation
7c936097f280 drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()
1f48cc5cbdb8 drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
fa3178994587 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
acdaeff0d22f drm/i915: Sprinkle a few missing locks around shared DDI clock registers
e9b82425593e drm/i915: Use intel_de_rmw() for DDI clock routing
aa859cf415e0 drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
d9f0d9ea2d01 drm/i915: Convert DG1 over to .{enable, disable}_clock()
26c2a16ac8ae drm/i195: Extract cnl_ddi_{enable, disable}_clock()
e75c39a95d43 drm/i915: Extract skl_ddi_{enable, disable}_clock()
732fae08fafa drm/i915: Extract hsw_ddi_{enable, disable}_clock()
896a544d3328 drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
55c608204619 drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
83a4bb6e6220 drm/i915: Extract icl_dpclka_cfgcr0_reg()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html

[-- Attachment #1.2: Type: text/html, Size: 6932 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing mess

[Ville Syrjälä]

On Mon, Feb 01, 2021 at 08:12:11PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Clean up the DDI clock routing mess
> URL   : https://patchwork.freedesktop.org/series/86544/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_19556 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_19556, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_19556:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
>     - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

<3> [153.691774] i915 0000:00:02.0: [drm] *ERROR* Failed to read DPCD register 0x92

Seems to be
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
except not yet tracked for icl.

That register seems to be related to the HDMI 2.1 PCON stuff.

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up the DDI clock routing mess

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 5478 bytes --]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess
URL   : https://patchwork.freedesktop.org/series/86544/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html

Known issues
------------

  Here are the changes found in Patchwork_19556 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#2411] / [i915#402])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [PASS][3] -> [DMESG-WARN][4] ([i915#2868])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@prime_self_import@basic-with_two_bos:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-tgl-y/igt@gem_mmap_gtt@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-tgl-y/igt@gem_mmap_gtt@basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-cfl-8109u:       [DMESG-WARN][9] ([i915#203]) -> [PASS][10] +27 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@execlists:
    - fi-cfl-8109u:       [DMESG-WARN][11] ([i915#1037]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_engines:
    - fi-cfl-8109u:       [DMESG-WARN][13] -> [PASS][14] +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7500u:       [DMESG-WARN][15] ([i915#2605]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html

  
  [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 39)
------------------------------

  Missing    (6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9713 -> Patchwork_19556

  CI-20190529: 20190529
  CI_DRM_9713: cc7b6cbff2a0a75ad4fe84d055ee1a762f0ce64b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5984: ccfc101419c1e233f87ca509781c5f8e09a2f3ae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19556: a5c9c286cd254d7ea6cf92303ecd91b8918a7945 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a5c9c286cd25 drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
5f0caa42e34a drm/i915: Use .disable_clock() for pll sanitation
7c936097f280 drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock()
1f48cc5cbdb8 drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
fa3178994587 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
acdaeff0d22f drm/i915: Sprinkle a few missing locks around shared DDI clock registers
e9b82425593e drm/i915: Use intel_de_rmw() for DDI clock routing
aa859cf415e0 drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
d9f0d9ea2d01 drm/i915: Convert DG1 over to .{enable, disable}_clock()
26c2a16ac8ae drm/i195: Extract cnl_ddi_{enable, disable}_clock()
e75c39a95d43 drm/i915: Extract skl_ddi_{enable, disable}_clock()
732fae08fafa drm/i915: Extract hsw_ddi_{enable, disable}_clock()
896a544d3328 drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
55c608204619 drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
83a4bb6e6220 drm/i915: Extract icl_dpclka_cfgcr0_reg()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html

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_______________________________________________
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing mess

[Vudum, Lakshminarayana]

Re-reported.

-----Original Message-----
From: Ville Syrjälä <ville.syrjala@linux.intel.com> 
Sent: Monday, February 1, 2021 12:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing mess

On Mon, Feb 01, 2021 at 08:12:11PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Clean up the DDI clock routing mess
> URL   : https://patchwork.freedesktop.org/series/86544/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556 
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_19556 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_19556, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_19556:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
>     - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-icl-u2/igt
> @kms_chamelium@common-hpd-after-suspend.html

<3> [153.691774] i915 0000:00:02.0: [drm] *ERROR* Failed to read DPCD register 0x92

Seems to be
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
except not yet tracked for icl.

That register seems to be related to the HDMI 2.1 PCON stuff.

--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up the DDI clock routing mess

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30268 bytes --]

== Series Details ==

Series: drm/i915: Clean up the DDI clock routing mess
URL   : https://patchwork.freedesktop.org/series/86544/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9713_full -> Patchwork_19556_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19556_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19556_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19556_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@u-fairslice@rcs0:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl2/igt@gem_exec_schedule@u-fairslice@rcs0.html

  
#### Warnings ####

  * igt@gem_exec_balancer@hang:
    - shard-iclb:         [INCOMPLETE][3] ([i915#3031]) -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb4/igt@gem_exec_balancer@hang.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb2/igt@gem_exec_balancer@hang.html

  
Known issues
------------

  Here are the changes found in Patchwork_19556_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@reset-stress:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([i915#2771])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl1/igt@gem_eio@reset-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl3/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl6/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl6/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-skl:          NOTRUN -> [SKIP][13] ([fdo#109271]) +90 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl10/igt@gem_exec_params@no-vebox.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
    - shard-skl:          NOTRUN -> [FAIL][14] ([i915#2389]) +3 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl10/igt@gem_exec_reloc@basic-wide-active@bcs0.html

  * igt@gem_exec_schedule@u-fairslice@bcs0:
    - shard-iclb:         [PASS][15] -> [DMESG-WARN][16] ([i915#2803])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb6/igt@gem_exec_schedule@u-fairslice@bcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb8/igt@gem_exec_schedule@u-fairslice@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][17] -> [SKIP][18] ([i915#2190])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb1/igt@gem_huc_copy@huc-copy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([fdo#110426] / [i915#1704])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([fdo#109289])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@gen7_exec_parse@basic-allocation.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [PASS][21] -> [INCOMPLETE][22] ([i915#2880])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-hsw:          [PASS][23] -> [FAIL][24] ([i915#1860])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-hsw2/igt@i915_pm_rc6_residency@rc6-idle.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-hsw6/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_selftest@live@gt_pm:
    - shard-skl:          NOTRUN -> [DMESG-FAIL][25] ([i915#1886] / [i915#2291])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl10/igt@i915_selftest@live@gt_pm.html

  * igt@i915_suspend@sysfs-reader:
    - shard-skl:          [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl6/igt@i915_suspend@sysfs-reader.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl6/igt@i915_suspend@sysfs-reader.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c:
    - shard-kbl:          [PASS][28] -> [DMESG-WARN][29] ([i915#165] / [i915#180] / [i915#78]) +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([fdo#111614])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([fdo#111615]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html

  * igt@kms_color_chamelium@pipe-b-degamma:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@kms_color_chamelium@pipe-b-degamma.html

  * igt@kms_color_chamelium@pipe-c-degamma:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@kms_color_chamelium@pipe-c-degamma.html
    - shard-kbl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@kms_color_chamelium@pipe-c-degamma.html

  * igt@kms_color_chamelium@pipe-d-degamma:
    - shard-skl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl6/igt@kms_color_chamelium@pipe-d-degamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
    - shard-kbl:          NOTRUN -> [SKIP][36] ([fdo#109271]) +35 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#109279])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen:
    - shard-skl:          NOTRUN -> [FAIL][38] ([i915#54]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([i915#54]) +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-d-256x256-top-edge:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#109278])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb6/igt@kms_cursor_edge_walk@pipe-d-256x256-top-edge.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
    - shard-glk:          [PASS][42] -> [FAIL][43] ([i915#79])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][44] -> [FAIL][45] ([i915#79])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-rmfb@b-dp1:
    - shard-kbl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180] / [i915#78])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl4/igt@kms_flip@flip-vs-rmfb@b-dp1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl2/igt@kms_flip@flip-vs-rmfb@b-dp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible@b-dp1:
    - shard-kbl:          [PASS][48] -> [DMESG-WARN][49] ([i915#165] / [i915#180])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl6/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-dp1.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl2/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-dp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([fdo#111825]) +11 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109280]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-apl:          [PASS][52] -> [DMESG-WARN][53] ([i915#180]) +3 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl3/igt@kms_hdr@bpc-switch-suspend.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@kms_hdr@bpc-switch-suspend.html
    - shard-skl:          [PASS][54] -> [FAIL][55] ([i915#1188])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl8/igt@kms_pipe_crc_basic@read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][62] -> [SKIP][63] ([fdo#109441]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271]) +9 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_vblank@pipe-b-accuracy-idle:
    - shard-skl:          [PASS][65] -> [FAIL][66] ([i915#43])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl4/igt@kms_vblank@pipe-b-accuracy-idle.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl6/igt@kms_vblank@pipe-b-accuracy-idle.html

  * igt@nouveau_crc@pipe-c-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#2530])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@nouveau_crc@pipe-c-source-outp-inactive.html

  * igt@prime_nv_pcopy@test3_5:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109291])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@prime_nv_pcopy@test3_5.html

  * igt@prime_vgem@fence-read-hang:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([fdo#109295])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@prime_vgem@fence-read-hang.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-glk:          [TIMEOUT][70] ([i915#2918]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-glk1/igt@gem_ctx_persistence@close-replace-race.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-glk4/igt@gem_ctx_persistence@close-replace-race.html

  * {igt@gem_ctx_persistence@many-contexts}:
    - shard-iclb:         [INCOMPLETE][72] -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb5/igt@gem_ctx_persistence@many-contexts.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb6/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [FAIL][74] ([i915#2842]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [FAIL][76] ([i915#2842]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [FAIL][78] ([i915#2842]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-glk:          [FAIL][80] ([i915#2389]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-glk3/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-glk7/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@bcs0:
    - shard-tglb:         [DMESG-WARN][82] ([i915#2803]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb8/igt@gem_exec_schedule@u-fairslice@bcs0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb2/igt@gem_exec_schedule@u-fairslice@bcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
    - shard-kbl:          [DMESG-WARN][84] ([i915#1610] / [i915#2803]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl6/igt@gem_exec_schedule@u-fairslice@rcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl4/igt@gem_exec_schedule@u-fairslice@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@vecs0:
    - shard-iclb:         [DMESG-WARN][86] ([i915#2803]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb6/igt@gem_exec_schedule@u-fairslice@vecs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb8/igt@gem_exec_schedule@u-fairslice@vecs0.html

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [INCOMPLETE][88] ([i915#146] / [i915#198]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl6/igt@gem_workarounds@suspend-resume.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl6/igt@gem_workarounds@suspend-resume.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-skl:          [INCOMPLETE][90] ([i915#198] / [i915#2295]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_suspend@debugfs-reader:
    - shard-skl:          [INCOMPLETE][92] ([i915#198]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl5/igt@i915_suspend@debugfs-reader.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl8/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-random:
    - shard-skl:          [FAIL][94] ([i915#54]) -> [PASS][95] +5 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [FAIL][96] ([i915#2346]) -> [PASS][97] +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-tglb:         [FAIL][98] ([i915#2598]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-skl:          [FAIL][100] ([i915#2122]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [DMESG-WARN][102] ([i915#180]) -> [PASS][103] +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-skl:          [DMESG-WARN][104] ([i915#1982]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][106] ([fdo#108145] / [i915#265]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][108] ([fdo#109441]) -> [PASS][109] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          [FAIL][110] ([i915#454]) -> [INCOMPLETE][111] ([i915#198])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-skl1/igt@i915_pm_dc@dc6-psr.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-skl3/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][112] ([i915#1804] / [i915#2684]) -> [WARN][113] ([i915#2681] / [i915#2684])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][114] ([i915#2684]) -> [WARN][115] ([i915#1804] / [i915#2684])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][116] ([i915#2920]) -> [SKIP][117] ([i915#658]) +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-iclb:         [SKIP][118] ([i915#658]) -> [SKIP][119] ([i915#2920]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#2295] / [i915#2426] / [i915#2505] / [i915#3002]) -> ([FAIL][124], [FAIL][125], [FAIL][126]) ([i915#2295] / [i915#3002])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl7/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl7/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl6/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-kbl4/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl2/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl1/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-kbl7/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#2295] / [i915#2426] / [i915#2722] / [i915#2724] / [i915#3002]) -> ([FAIL][131], [FAIL][132], [FAIL][133]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb6/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb4/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb3/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-iclb5/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb8/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb1/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-iclb4/igt@runner@aborted.html
    - shard-apl:          ([FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([fdo#109271] / [i915#1814] / [i915#2295] / [i915#3002]) -> ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#1610] / [i915#1814] / [i915#2295] / [i915#3002])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl7/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl8/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl1/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl4/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl1/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-apl1/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl8/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl3/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl4/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl8/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl8/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl7/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-apl2/igt@runner@aborted.html
    - shard-tglb:         ([FAIL][148], [FAIL][149], [FAIL][150]) ([i915#2295] / [i915#2426] / [i915#2803] / [i915#3002]) -> ([FAIL][151], [FAIL][152]) ([i915#2295] / [i915#3002])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb3/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb2/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/shard-tglb8/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb5/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/shard-tglb1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110426]: https://bugs.freedesktop.org/show_bug.cgi?id=110426
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1704]: https://gitlab.freedesktop.org/drm/intel/issues/1704
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.free

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing mess

[Nautiyal, Ankit K]

On 2/2/2021 2:04 AM, Ville Syrjälä wrote:
> On Mon, Feb 01, 2021 at 08:12:11PM -0000, Patchwork wrote:
>> == Series Details ==
>>
>> Series: drm/i915: Clean up the DDI clock routing mess
>> URL   : https://patchwork.freedesktop.org/series/86544/
>> State : failure
>>
>> == Summary ==
>>
>> CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
>> ====================================================
>>
>> Summary
>> -------
>>
>>    **FAILURE**
>>
>>    Serious unknown changes coming with Patchwork_19556 absolutely need to be
>>    verified manually.
>>    
>>    If you think the reported changes have nothing to do with the changes
>>    introduced in Patchwork_19556, please notify your bug team to allow them
>>    to document this new failure mode, which will reduce false positives in CI.
>>
>>    External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/index.html
>>
>> Possible new issues
>> -------------------
>>
>>    Here are the unknown changes that may have been introduced in Patchwork_19556:
>>
>> ### IGT changes ###
>>
>> #### Possible regressions ####
>>
>>    * igt@kms_chamelium@common-hpd-after-suspend:
>>      - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
>>     [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9713/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
>>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19556/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
> <3> [153.691774] i915 0000:00:02.0: [drm] *ERROR* Failed to read DPCD register 0x92
>
> Seems to be
> https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> except not yet tracked for icl.
>
> That register seems to be related to the HDMI 2.1 PCON stuff.

Yes you are right. I seemed to have missed a check for reading this only 
for DPCD rev>=1.4.

I'll be sending patch to fix this to intel-gfx.

I have already sent a patch to intel-trybot to verify this.

https://patchwork.freedesktop.org/patch/418137/?series=86551&rev=1

Thanks & Regards,

Ankit

>
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