* [Bug 1923197] [NEW] RISC-V priviledged instruction error
@ 2021-04-09 13:02 Teodori Serge
2021-04-09 18:23 ` [Bug 1923197] " Teodori Serge
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Teodori Serge @ 2021-04-09 13:02 UTC (permalink / raw)
To: qemu-devel
Public bug reported:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
** Affects: qemu
Importance: Undecided
Status: New
** Tags: riscv64
** Tags added: riscv64
** Description changed:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
- problem appeared in code after version 5.2.0.
+ problem appeared in code after version 5.2.0. Use following code to
+ test.
- <pre>
- # setup interrupt handling for monitor mode
- la t0, entry_loop
- la t1, entry_trap
- li t2, 0x888
- li t3, 0x1880 # MPP in MSTATUS selects to which mode to return & MPIE selects if to enable interrupts after MRET
- csrw mepc, t0
- csrw mtvec, t1
- csrs mie, t2
- csrs mstatus, t3
- # if supervisor mode not supported, then loop forever
- csrr t0, misa
- li t1, 0x40000
- and t2, t1, t0
- beqz t2, 1f
+ # setup interrupt handling for monitor mode
+ la t0, entry_loop
+ la t1, entry_trap
+ li t2, 0x888
+ li t3, 0x1880 # MPP in MSTATUS selects to which mode to return & MPIE selects if to enable interrupts after MRET
+ csrw mepc, t0
+ csrw mtvec, t1
+ csrs mie, t2
+ csrs mstatus, t3
- # setup interrupt i& exception delegation for supervisor mode
- li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
- li t1, 0x1000
- #li t2, 0x300 # bit 8 & 9 is for ecall from user & supervisor mode
- #li t3, 0x222
- csrw mepc, t0
- csrc mstatus, t1
- #csrs medeleg, t2
- #csrs mideleg, t3
+ # if supervisor mode not supported, then loop forever
+ csrr t0, misa
+ li t1, 0x40000
+ and t2, t1, t0
+ beqz t2, 1f
- # pass mhartid as first parameter to supervisor
- csrr a0, mhartid
+ # setup interrupt i& exception delegation for supervisor mode
+ li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
+ li t1, 0x1000
+ #li t2, 0x300 # bit 8 & 9 is for ecall from user & supervisor mode
+ #li t3, 0x222
+ csrw mepc, t0
+ csrc mstatus, t1
+ #csrs medeleg, t2
+ #csrs mideleg, t3
+
+ # pass mhartid as first parameter to supervisor
+ csrr a0, mhartid
1:
- mret
- </pre>
+ mret
** Description changed:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
-
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
- li t3, 0x1880 # MPP in MSTATUS selects to which mode to return & MPIE selects if to enable interrupts after MRET
+ li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
- #li t2, 0x300 # bit 8 & 9 is for ecall from user & supervisor mode
- #li t3, 0x222
+ li t2, 0x300
+ li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
- #csrs medeleg, t2
- #csrs mideleg, t3
+ csrs medeleg, t2
+ csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
New
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-09 13:02 [Bug 1923197] [NEW] RISC-V priviledged instruction error Teodori Serge
@ 2021-04-09 18:23 ` Teodori Serge
2021-04-15 4:08 ` Alistair Francis
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Teodori Serge @ 2021-04-09 18:23 UTC (permalink / raw)
To: qemu-devel
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Confirmed
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-09 13:02 [Bug 1923197] [NEW] RISC-V priviledged instruction error Teodori Serge
2021-04-09 18:23 ` [Bug 1923197] " Teodori Serge
@ 2021-04-15 4:08 ` Alistair Francis
2021-04-15 6:05 ` Teodori Serge
2021-04-15 4:09 ` Alistair Francis
2021-04-18 3:49 ` Alistair Francis
3 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2021-04-15 4:08 UTC (permalink / raw)
To: qemu-devel
I'm guessing that this is a bug in your guest as it hasn't configured
PMP regions.
>From the RISC-V spec:
"
If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an
S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.
"
Confusingly implemented here means implemented in hardware, not just
configured.
** Changed in: qemu
Status: Confirmed => Invalid
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-09 13:02 [Bug 1923197] [NEW] RISC-V priviledged instruction error Teodori Serge
2021-04-09 18:23 ` [Bug 1923197] " Teodori Serge
2021-04-15 4:08 ` Alistair Francis
@ 2021-04-15 4:09 ` Alistair Francis
2021-04-18 3:49 ` Alistair Francis
3 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2021-04-15 4:09 UTC (permalink / raw)
To: qemu-devel
You can check this by reverting this QEMU commit:
commit d102f19a2085ac931cb998e6153b73248cca49f1
Author: Atish Patra <atish.patra@wdc.com>
Date: Wed Dec 23 11:25:53 2020 -0800
target/riscv/pmp: Raise exception if no PMP entry is configured
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-15 4:08 ` Alistair Francis
@ 2021-04-15 6:05 ` Teodori Serge
0 siblings, 0 replies; 7+ messages in thread
From: Teodori Serge @ 2021-04-15 6:05 UTC (permalink / raw)
To: qemu-devel
Hello Francis,
I'll configure PMP than do the test again. Sorry I hadn't understood what
changed between version 5.2 and 6.0-rc2, since my code worked before.
Best regards,
Teodori Serge
On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923197@bugs.launchpad.net>
wrote:
> I'm guessing that this is a bug in your guest as it hasn't configured
> PMP regions.
>
> >From the RISC-V spec:
>
> "
> If no PMP entry matches an M-mode access, the access succeeds. If no PMP
> entry matches an
> S-mode or U-mode access, but at least one PMP entry is implemented, the
> access fails.
> "
>
> Confusingly implemented here means implemented in hardware, not just
> configured.
>
> ** Changed in: qemu
> Status: Confirmed => Invalid
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1923197
>
> Title:
> RISC-V priviledged instruction error
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
>
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-09 13:02 [Bug 1923197] [NEW] RISC-V priviledged instruction error Teodori Serge
` (2 preceding siblings ...)
2021-04-15 4:09 ` Alistair Francis
@ 2021-04-18 3:49 ` Alistair Francis
2021-04-18 6:37 ` Teodori Serge
3 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2021-04-18 3:49 UTC (permalink / raw)
To: qemu-devel
We fixed a bug to make QEMU act more like hardware, which now means that
PMP must be configured in M-mode.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Bug 1923197] Re: RISC-V priviledged instruction error
2021-04-18 3:49 ` Alistair Francis
@ 2021-04-18 6:37 ` Teodori Serge
0 siblings, 0 replies; 7+ messages in thread
From: Teodori Serge @ 2021-04-18 6:37 UTC (permalink / raw)
To: qemu-devel
Hello Francis,
Yes thank you. I added code to setup a basic PMP and it works now. Thank
you and best regards,
Teodori Serge
On Sun, 18 Apr 2021, 05:55 Alistair Francis, <1923197@bugs.launchpad.net>
wrote:
> We fixed a bug to make QEMU act more like hardware, which now means that
> PMP must be configured in M-mode.
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1923197
>
> Title:
> RISC-V priviledged instruction error
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
>
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-04-18 6:47 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-09 13:02 [Bug 1923197] [NEW] RISC-V priviledged instruction error Teodori Serge
2021-04-09 18:23 ` [Bug 1923197] " Teodori Serge
2021-04-15 4:08 ` Alistair Francis
2021-04-15 6:05 ` Teodori Serge
2021-04-15 4:09 ` Alistair Francis
2021-04-18 3:49 ` Alistair Francis
2021-04-18 6:37 ` Teodori Serge
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