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From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
	<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
	<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
	<stefanc@marvell.com>, <oferh@marvell.com>, <bpeled@marvell.com>
Subject: [”PATCH” 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings
Date: Mon, 12 Apr 2021 18:30:54 +0300	[thread overview]
Message-ID: <1618241456-27200-4-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com>

From: Ben Peled <bpeled@marvell.com>

Adding optional system-controller and mac-reset-bit-mask
needed for linkdown procedure.

Signed-off-by: Ben Peled <bpeled@marvell.com>
---
 Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 7a813d0..2696e79 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -24,6 +24,10 @@ Optional properties:
 - phy-names: names of the PHYs corresponding to the number of lanes.
 	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
 	2 PHYs.
+- marvell,system-controller: address of system controller needed
+	in order to reset MAC used by link-down handle
+- marvell,mac-reset-bit-mask: MAC reset bit of system controller
+	needed in order to reset MAC used by link-down handle
 
 Example:
 
@@ -45,4 +49,6 @@ Example:
 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		num-lanes = <1>;
 		clocks = <&cpm_syscon0 1 13>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(1)>;
 	};
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
	<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
	<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
	<stefanc@marvell.com>, <oferh@marvell.com>, <bpeled@marvell.com>
Subject: [”PATCH” 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings
Date: Mon, 12 Apr 2021 18:30:54 +0300	[thread overview]
Message-ID: <1618241456-27200-4-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com>

From: Ben Peled <bpeled@marvell.com>

Adding optional system-controller and mac-reset-bit-mask
needed for linkdown procedure.

Signed-off-by: Ben Peled <bpeled@marvell.com>
---
 Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 7a813d0..2696e79 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -24,6 +24,10 @@ Optional properties:
 - phy-names: names of the PHYs corresponding to the number of lanes.
 	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
 	2 PHYs.
+- marvell,system-controller: address of system controller needed
+	in order to reset MAC used by link-down handle
+- marvell,mac-reset-bit-mask: MAC reset bit of system controller
+	needed in order to reset MAC used by link-down handle
 
 Example:
 
@@ -45,4 +49,6 @@ Example:
 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		num-lanes = <1>;
 		clocks = <&cpm_syscon0 1 13>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(1)>;
 	};
-- 
2.7.4


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  parent reply	other threads:[~2021-04-12 15:31 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12 15:30 [”PATCH” 0/5] Asynchronous linkdown recovery bpeled
2021-04-12 15:30 ` bpeled
2021-04-12 15:30 ` [”PATCH” 1/5] PCI: armada8k: Disable LTSSM on link down interrupts bpeled
2021-04-12 15:30   ` bpeled
2021-04-12 15:30 ` [”PATCH” 2/5] PCI: armada8k: Add link-down handle bpeled
2021-04-12 15:30   ` bpeled
2021-04-14 12:42   ` Jonathan Cameron
2021-04-14 12:42     ` Jonathan Cameron
2021-04-27  7:07     ` [EXT] " Ben Peled
2021-04-27  7:07       ` Ben Peled
2021-04-12 15:30 ` bpeled [this message]
2021-04-12 15:30   ` [”PATCH” 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings bpeled
2021-04-13 15:10   ` Rob Herring
2021-04-13 15:10     ` Rob Herring
2021-04-26 15:58     ` [EXT] " Ben Peled
2021-04-26 15:58       ` Ben Peled
2021-04-12 15:30 ` [”PATCH” 4/5] arm64: dts: marvell: add pcie mac reset to pcie bpeled
2021-04-12 15:30   ` bpeled
2021-04-12 15:30 ` [”PATCH” 5/5] PCI: armada8k: add device reset to link-down handle bpeled
2021-04-12 15:30   ` bpeled
2021-04-13 10:14 ` [”PATCH” 0/5] Asynchronous linkdown recovery Ben Peled
2021-04-13 10:14   ` Ben Peled

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