* [PATCH v4 0/2] Add DT bindings and DT nodes for USB in SC7280 @ 2021-06-04 11:03 Sandeep Maheswaram 2021-06-04 11:03 ` [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2021-06-04 11:03 ` [PATCH v4 2/2] arm64: dts: qcom: sc7280: Add USB nodes for IDP board Sandeep Maheswaram 0 siblings, 2 replies; 5+ messages in thread From: Sandeep Maheswaram @ 2021-06-04 11:03 UTC (permalink / raw) To: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam, Sandeep Maheswaram This series includes usb controller and phy binding updates for SC7280 SoC and DT chnages for SC7280 SoC and SC7280 IDP board. changes in v4: changed usb3-phy to lanes in qmp phy node as it was causing probe failure. changes in v3: Moved the board specific changes to separate patch. Addressed comments from Matthias in v2. changes in v2: Dropped dt bindings patches as they are already merged in linux-next. Addressed comments from Matthias in v1. Sandeep Maheswaram (2): arm64: dts: qcom: sc7280: Add USB related nodes arm64: dts: qcom: sc7280: Add USB nodes for IDP board arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 ++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-06-04 11:03 [PATCH v4 0/2] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram @ 2021-06-04 11:03 ` Sandeep Maheswaram 2021-06-04 21:40 ` Stephen Boyd 2021-06-06 3:59 ` Bjorn Andersson 2021-06-04 11:03 ` [PATCH v4 2/2] arm64: dts: qcom: sc7280: Add USB nodes for IDP board Sandeep Maheswaram 1 sibling, 2 replies; 5+ messages in thread From: Sandeep Maheswaram @ 2021-06-04 11:03 UTC (permalink / raw) To: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam, Sandeep Maheswaram Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> --- changed usb3-phy to lanes in qmp phy node as it was causing probe failure. arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 +++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0b6f119..d70d5fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -973,6 +973,110 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sm8250-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2: usb@8cf8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x08cf8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface","mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@8c00000 { + compatible = "snps,dwc3"; + reg = <0 0x08c00000 0 0xe000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; @@ -980,6 +1084,51 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0xaaf0000 0 0x10000>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-06-04 11:03 ` [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram @ 2021-06-04 21:40 ` Stephen Boyd 2021-06-06 3:59 ` Bjorn Andersson 1 sibling, 0 replies; 5+ messages in thread From: Stephen Boyd @ 2021-06-04 21:40 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Doug Anderson, Felipe Balbi, Greg Kroah-Hartman, Matthias Kaehlcke, Rob Herring, Sandeep Maheswaram Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam Quoting Sandeep Maheswaram (2021-06-04 04:03:37) > Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- > changed usb3-phy to lanes in qmp phy node as it was causing probe failure. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 +++++++++++++++++++++++++++++++++++ > 1 file changed, 149 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 0b6f119..d70d5fb 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -973,6 +973,110 @@ > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e3000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_2_hsphy: phy@88e4000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e4000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + }; > + > + usb_1_qmpphy: phy-wrapper@88e9000 { > + compatible = "qcom,sm8250-qmp-usb3-phy"; Is this another combo usb/dp phy? > + reg = <0 0x088e9000 0 0x200>, > + <0 0x088e8000 0 0x20>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, This makes me think yes. In which case, can we put the final node in place instead of having to tack on DP phy at a later time? > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lanes@88e9200 { phy@88e9200? > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x400>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + #clock-cells = <1>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-06-04 11:03 ` [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2021-06-04 21:40 ` Stephen Boyd @ 2021-06-06 3:59 ` Bjorn Andersson 1 sibling, 0 replies; 5+ messages in thread From: Bjorn Andersson @ 2021-06-06 3:59 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Rob Herring, Andy Gross, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke, devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam On Fri 04 Jun 06:03 CDT 2021, Sandeep Maheswaram wrote: > Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- > changed usb3-phy to lanes in qmp phy node as it was causing probe failure. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 +++++++++++++++++++++++++++++++++++ > 1 file changed, 149 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 0b6f119..d70d5fb 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -973,6 +973,110 @@ > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e3000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_2_hsphy: phy@88e4000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e4000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + }; > + > + usb_1_qmpphy: phy-wrapper@88e9000 { > + compatible = "qcom,sm8250-qmp-usb3-phy"; No, your sc7280 doesn't have a sm8250 UBS PHY. > + reg = <0 0x088e9000 0 0x200>, > + <0 0x088e8000 0 0x20>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lanes@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x400>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + #clock-cells = <1>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_2: usb@8cf8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x08cf8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface","mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 13 IRQ_TYPE_EDGE_RISING>, > + <&pdc 12 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_SEC_GDSC>; > + > + resets = <&gcc GCC_USB30_SEC_BCR>; > + > + usb_2_dwc3: dwc3@8c00000 { This should be usb@. > + compatible = "snps,dwc3"; > + reg = <0 0x08c00000 0 0xe000>; > + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0xa0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_2_hsphy>; > + phy-names = "usb2-phy"; > + maximum-speed = "high-speed"; > + }; > + }; > + > system-cache-controller@9200000 { > compatible = "qcom,sc7280-llcc"; > reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; > @@ -980,6 +1084,51 @@ > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > > + usb_1: usb@a6f8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > + "dm_hs_phy_irq", "ss_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { Ditto. Regards, Bjorn ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: sc7280: Add USB nodes for IDP board 2021-06-04 11:03 [PATCH v4 0/2] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-06-04 11:03 ` [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram @ 2021-06-04 11:03 ` Sandeep Maheswaram 1 sibling, 0 replies; 5+ messages in thread From: Sandeep Maheswaram @ 2021-06-04 11:03 UTC (permalink / raw) To: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam, Sandeep Maheswaram Add USB nodes for sc7280 IDP board. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 3900cfc..44326d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -276,6 +276,45 @@ status = "okay"; }; +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-06-06 4:00 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-04 11:03 [PATCH v4 0/2] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-06-04 11:03 ` [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2021-06-04 21:40 ` Stephen Boyd 2021-06-06 3:59 ` Bjorn Andersson 2021-06-04 11:03 ` [PATCH v4 2/2] arm64: dts: qcom: sc7280: Add USB nodes for IDP board Sandeep Maheswaram
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