* [PATCH 2/8] drm/amdgpu: allow different boot configs
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-11 7:05 ` [PATCH 3/8] drm/amdgpu: add helper function to query gecc status in boot config Hawking Zhang
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
More boot configs need to be supported via
BOOTCFG_CMD_SET
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..a8856697733e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -535,7 +535,7 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp,
return ret;
}
-static int psp_boot_config_set(struct amdgpu_device *adev)
+static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
{
struct psp_context *psp = &adev->psp;
struct psp_gfx_cmd_resp *cmd = psp->cmd;
@@ -547,8 +547,8 @@ static int psp_boot_config_set(struct amdgpu_device *adev)
cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
- cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;
- cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;
+ cmd->cmd.boot_cfg.boot_config = boot_cfg;
+ cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
}
@@ -1934,7 +1934,7 @@ static int psp_hw_start(struct psp_context *psp)
}
if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
- ret = psp_boot_config_set(adev);
+ ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
if (ret)
dev_warn(adev->dev, "PSP set boot config failed\n");
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/8] drm/amdgpu: add helper function to query gecc status in boot config
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
2021-06-11 7:05 ` [PATCH 2/8] drm/amdgpu: allow different boot configs Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-11 7:05 ` [PATCH 4/8] drm/amdgpu: enable dynamic GECC support (v2) Hawking Zhang
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
Query GECC enablement status in boot config
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a8856697733e..d509d52dd235 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -535,6 +535,29 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp,
return ret;
}
+static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
+{
+ struct psp_context *psp = &adev->psp;
+ struct psp_gfx_cmd_resp *cmd = psp->cmd;
+ int ret;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+ cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
+ cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
+
+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+ if (!ret) {
+ *boot_cfg =
+ (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
+ }
+
+ return ret;
+}
+
static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
{
struct psp_context *psp = &adev->psp;
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/8] drm/amdgpu: enable dynamic GECC support (v2)
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
2021-06-11 7:05 ` [PATCH 2/8] drm/amdgpu: allow different boot configs Hawking Zhang
2021-06-11 7:05 ` [PATCH 3/8] drm/amdgpu: add helper function to query gecc status in boot config Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-11 7:05 ` [PATCH 5/8] drm/amdgpu: add psp runtime db structures Hawking Zhang
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
Dynamic GECC allows user to specify GECC enablement
status, which will take effect in next boot cycle.
v2: initialize boot_cfg to 0xFF
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 57 ++++++++++++++++++++-----
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d509d52dd235..ab4e89186186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1220,19 +1220,62 @@ static int psp_ras_terminate(struct psp_context *psp)
static int psp_ras_initialize(struct psp_context *psp)
{
int ret;
+ uint32_t boot_cfg = 0xFF;
+ struct amdgpu_device *adev = psp->adev;
/*
* TODO: bypass the initialize in sriov for now
*/
- if (amdgpu_sriov_vf(psp->adev))
+ if (amdgpu_sriov_vf(adev))
return 0;
- if (!psp->adev->psp.ta_ras_ucode_size ||
- !psp->adev->psp.ta_ras_start_addr) {
- dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
+ if (!adev->psp.ta_ras_ucode_size ||
+ !adev->psp.ta_ras_start_addr) {
+ dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
return 0;
}
+ if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
+ /* query GECC enablement status from boot config
+ * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
+ */
+ ret = psp_boot_config_get(adev, &boot_cfg);
+ if (ret)
+ dev_warn(adev->dev, "PSP get boot config failed\n");
+
+ if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
+ if (!boot_cfg) {
+ dev_info(adev->dev, "GECC is disabled\n");
+ } else {
+ /* disable GECC in next boot cycle if ras is
+ * disabled by module parameter amdgpu_ras_enable
+ * and/or amdgpu_ras_mask, or boot_config_get call
+ * is failed
+ */
+ ret = psp_boot_config_set(adev, 0);
+ if (ret)
+ dev_warn(adev->dev, "PSP set boot config failed\n");
+ else
+ dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
+ "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
+ }
+ } else {
+ if (1 == boot_cfg) {
+ dev_info(adev->dev, "GECC is enabled\n");
+ } else {
+ /* enable GECC in next boot cycle if it is disabled
+ * in boot config, or force enable GECC if failed to
+ * get boot configuration
+ */
+ ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
+ if (ret)
+ dev_warn(adev->dev, "PSP set boot config failed\n");
+ else
+ dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
+ }
+ }
+ }
+
if (!psp->ras.ras_initialized) {
ret = psp_ras_init_shared_buf(psp);
if (ret)
@@ -1956,12 +1999,6 @@ static int psp_hw_start(struct psp_context *psp)
return ret;
}
- if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
- ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
- if (ret)
- dev_warn(adev->dev, "PSP set boot config failed\n");
- }
-
ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n");
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/8] drm/amdgpu: add psp runtime db structures
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
` (2 preceding siblings ...)
2021-06-11 7:05 ` [PATCH 4/8] drm/amdgpu: enable dynamic GECC support (v2) Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-11 7:05 ` [PATCH 6/8] drm/amdgpu: add helper function to query psp runtime db entry (v2) Hawking Zhang
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
PSP runtime database is used to share various
boot up information with driver.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 54 +++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 46a5328e00e0..4dad9b539f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -226,6 +226,60 @@ struct psp_memory_training_context {
u32 training_cnt;
};
+/** PSP runtime DB **/
+#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
+#define PSP_RUNTIME_DB_OFFSET 0x100000
+#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
+#define PSP_RUNTIME_DB_VER_1 0x0100
+#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
+
+enum psp_runtime_entry_type {
+ PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
+ PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
+ PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
+ PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
+ PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
+ PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
+};
+
+/* PSP runtime DB header */
+struct psp_runtime_data_header {
+ /* determine the existence of runtime db */
+ uint16_t cookie;
+ /* version of runtime db */
+ uint16_t version;
+};
+
+/* PSP runtime DB entry */
+struct psp_runtime_entry {
+ /* type of runtime db entry */
+ uint32_t entry_type;
+ /* offset of entry in bytes */
+ uint16_t offset;
+ /* size of entry in bytes */
+ uint16_t size;
+};
+
+/* PSP runtime DB directory */
+struct psp_runtime_data_directory {
+ /* number of valid entries */
+ uint16_t entry_count;
+ /* db entries*/
+ struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
+};
+
+/* PSP runtime DB boot config feature bitmask */
+enum psp_runtime_boot_cfg_feature {
+ BOOT_CFG_FEATURE_GECC = 0x1,
+ BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
+};
+
+/* PSP runtime DB boot config entry */
+struct psp_runtime_boot_cfg_entry {
+ uint32_t boot_cfg_bitmask;
+ uint32_t reserved;
+};
+
struct psp_context
{
struct amdgpu_device *adev;
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/8] drm/amdgpu: add helper function to query psp runtime db entry (v2)
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
` (3 preceding siblings ...)
2021-06-11 7:05 ` [PATCH 5/8] drm/amdgpu: add psp runtime db structures Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-30 11:08 ` Michel Dänzer
2021-06-11 7:05 ` [PATCH 7/8] drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_int Hawking Zhang
2021-06-11 7:05 ` [PATCH 8/8] drm/amdgpu: disable DRAM memory training when GECC is enabled Hawking Zhang
6 siblings, 1 reply; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
PSP will dump various boot up information into a
portion of local frame buffer, called runtime database.
The helper function is used for driver to query those
shared information.
v2: init ret and check !ret to exit loop as soon as
found the entry
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 68 +++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index ab4e89186186..dc786c91ec9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -164,6 +164,74 @@ static int psp_memory_training_init(struct psp_context *psp)
return ret;
}
+/*
+ * Helper funciton to query psp runtime database entry
+ *
+ * @adev: amdgpu_device pointer
+ * @entry_type: the type of psp runtime database entry
+ * @db_entry: runtime database entry pointer
+ *
+ * Return false if runtime database doesn't exit or entry is invalid
+ * or true if the specific database entry is found, and copy to @db_entry
+ */
+static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
+ enum psp_runtime_entry_type entry_type,
+ void *db_entry)
+{
+ uint64_t db_header_pos, db_dir_pos;
+ struct psp_runtime_data_header db_header = {0};
+ struct psp_runtime_data_directory db_dir = {0};
+ bool ret = false;
+ int i;
+
+ db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
+ db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
+
+ /* read runtime db header from vram */
+ amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
+ sizeof(struct psp_runtime_data_header), false);
+
+ if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
+ /* runtime db doesn't exist, exit */
+ dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
+ return false;
+ }
+
+ /* read runtime database entry from vram */
+ amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
+ sizeof(struct psp_runtime_data_directory), false);
+
+ if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
+ /* invalid db entry count, exit */
+ dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
+ return false;
+ }
+
+ /* look up for requested entry type */
+ for (i = 0; i < db_dir.entry_count && !ret; i++) {
+ if (db_dir.entry_list[i].entry_type == entry_type) {
+ switch (entry_type) {
+ case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
+ if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
+ /* invalid db entry size */
+ dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
+ return false;
+ }
+ /* read runtime database entry */
+ amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
+ (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
+ ret = true;
+ break;
+ default:
+ ret = false;
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
static int psp_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 6/8] drm/amdgpu: add helper function to query psp runtime db entry (v2)
2021-06-11 7:05 ` [PATCH 6/8] drm/amdgpu: add helper function to query psp runtime db entry (v2) Hawking Zhang
@ 2021-06-30 11:08 ` Michel Dänzer
0 siblings, 0 replies; 9+ messages in thread
From: Michel Dänzer @ 2021-06-30 11:08 UTC (permalink / raw)
To: Hawking Zhang; +Cc: amd-gfx
On 2021-06-11 9:05 a.m., Hawking Zhang wrote:
> PSP will dump various boot up information into a
> portion of local frame buffer, called runtime database.
> The helper function is used for driver to query those
> shared information.
>
> v2: init ret and check !ret to exit loop as soon as
> found the entry
>
> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: John Clements <john.clements@amd.com>
> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 68 +++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index ab4e89186186..dc786c91ec9d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -164,6 +164,74 @@ static int psp_memory_training_init(struct psp_context *psp)
> return ret;
> }
>
> +/*
> + * Helper funciton to query psp runtime database entry
> + *
> + * @adev: amdgpu_device pointer
> + * @entry_type: the type of psp runtime database entry
> + * @db_entry: runtime database entry pointer
> + *
> + * Return false if runtime database doesn't exit or entry is invalid
> + * or true if the specific database entry is found, and copy to @db_entry
> + */
> +static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
> + enum psp_runtime_entry_type entry_type,
> + void *db_entry)
> +{
> + uint64_t db_header_pos, db_dir_pos;
> + struct psp_runtime_data_header db_header = {0};
> + struct psp_runtime_data_directory db_dir = {0};
> + bool ret = false;
> + int i;
> +
> + db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
> + db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
> +
> + /* read runtime db header from vram */
> + amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
> + sizeof(struct psp_runtime_data_header), false);
> +
> + if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
> + /* runtime db doesn't exist, exit */
> + dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
> + return false;
> + }
I just noticed this message in the output of
dmesg -l emerg,alert,crit,err,warn
I wonder if these messages really need to be printed by default at all, let alone at warning level. Do they indicate an issue which needs to be addressed?
> + /* read runtime database entry from vram */
> + amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
> + sizeof(struct psp_runtime_data_directory), false);
> +
> + if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
> + /* invalid db entry count, exit */
> + dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
> + return false;
> + }
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast | Mesa and X developer
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 7/8] drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_int
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
` (4 preceding siblings ...)
2021-06-11 7:05 ` [PATCH 6/8] drm/amdgpu: add helper function to query psp runtime db entry (v2) Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
2021-06-11 7:05 ` [PATCH 8/8] drm/amdgpu: disable DRAM memory training when GECC is enabled Hawking Zhang
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
PSP runtime boot_cfg_bitmask carries various psp bl
feature bit mask that can be used by driver. Cache
it in sw_init for further usage.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index dc786c91ec9d..28f95c5cd373 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -237,6 +237,7 @@ static int psp_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
int ret;
+ struct psp_runtime_boot_cfg_entry boot_cfg_entry;
if (!amdgpu_sriov_vf(adev)) {
ret = psp_init_microcode(psp);
@@ -246,6 +247,12 @@ static int psp_sw_init(void *handle)
}
}
+ memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
+ if (psp_get_runtime_db_entry(adev,
+ PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
+ &boot_cfg_entry))
+ psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
+
ret = psp_memory_training_init(psp);
if (ret) {
DRM_ERROR("Failed to initialize memory training!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 4dad9b539f06..2bd85b505f2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -378,6 +378,8 @@ struct psp_context
struct psp_securedisplay_context securedisplay_context;
struct mutex mutex;
struct psp_memory_training_context mem_train_ctx;
+
+ uint32_t boot_cfg_bitmask;
};
struct amdgpu_psp_funcs {
--
2.17.1
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* [PATCH 8/8] drm/amdgpu: disable DRAM memory training when GECC is enabled
2021-06-11 7:05 [PATCH 1/8] drm/amdgpu: update psp gfx i/f to support dynamic GECC Hawking Zhang
` (5 preceding siblings ...)
2021-06-11 7:05 ` [PATCH 7/8] drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_int Hawking Zhang
@ 2021-06-11 7:05 ` Hawking Zhang
6 siblings, 0 replies; 9+ messages in thread
From: Hawking Zhang @ 2021-06-11 7:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang
GECC and G6 mem training are mutually exclusive
functionalities. VBIOS/PSP will set the flag
(BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in
runtime database to indicate whether dram memory
training need to be disabled or not.
For Navi1x families, two stage mem training is always
enabled.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 47 ++++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 28f95c5cd373..7e0e676a9959 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -238,6 +238,7 @@ static int psp_sw_init(void *handle)
struct psp_context *psp = &adev->psp;
int ret;
struct psp_runtime_boot_cfg_entry boot_cfg_entry;
+ struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
if (!amdgpu_sriov_vf(adev)) {
ret = psp_init_microcode(psp);
@@ -250,18 +251,36 @@ static int psp_sw_init(void *handle)
memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
if (psp_get_runtime_db_entry(adev,
PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
- &boot_cfg_entry))
+ &boot_cfg_entry)) {
psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
+ if ((psp->boot_cfg_bitmask) &
+ BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
+ /* If psp runtime database exists, then
+ * only enable two stage memory training
+ * when TWO_STAGE_DRAM_TRAINING bit is set
+ * in runtime database */
+ mem_training_ctx->enable_mem_training = true;
+ }
- ret = psp_memory_training_init(psp);
- if (ret) {
- DRM_ERROR("Failed to initialize memory training!\n");
- return ret;
+ } else {
+ /* If psp runtime database doesn't exist or
+ * is invalid, force enable two stage memory
+ * training */
+ mem_training_ctx->enable_mem_training = true;
}
- ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
- if (ret) {
- DRM_ERROR("Failed to process memory training!\n");
- return ret;
+
+ if (mem_training_ctx->enable_mem_training) {
+ ret = psp_memory_training_init(psp);
+ if (ret) {
+ DRM_ERROR("Failed to initialize memory training!\n");
+ return ret;
+ }
+
+ ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
+ if (ret) {
+ DRM_ERROR("Failed to process memory training!\n");
+ return ret;
+ }
}
if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
@@ -2676,10 +2695,12 @@ static int psp_resume(void *handle)
DRM_INFO("PSP is resuming...\n");
- ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
- if (ret) {
- DRM_ERROR("Failed to process memory training!\n");
- return ret;
+ if (psp->mem_train_ctx.enable_mem_training) {
+ ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
+ if (ret) {
+ DRM_ERROR("Failed to process memory training!\n");
+ return ret;
+ }
}
mutex_lock(&adev->firmware.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 2bd85b505f2c..0b514ba31e42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -224,6 +224,7 @@ struct psp_memory_training_context {
enum psp_memory_training_init_flag init;
u32 training_cnt;
+ bool enable_mem_training;
};
/** PSP runtime DB **/
--
2.17.1
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