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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org
Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com,
	mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com,
	maz@kernel.org, james.morse@arm.com, steven.price@arm.com,
	Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [RFC V2 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field
Date: Mon, 26 Jul 2021 12:07:18 +0530	[thread overview]
Message-ID: <1627281445-12445-4-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1627281445-12445-1-git-send-email-anshuman.khandual@arm.com>

As per ARM ARM (0487G.A) TCR_EL1.DS fields controls whether 52 bit input
and output address get supported on 4K and 16K page size configuration,
when FEAT_LPA2 is known to have been implemented. This adds TCR_DS field
definition which would be used when FEAT_LPA2 gets enabled.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/pgtable-hwdef.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 66671ff..1eb5574 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -275,6 +275,7 @@
 #define TCR_E0PD1		(UL(1) << 56)
 #define TCR_TCMA0		(UL(1) << 57)
 #define TCR_TCMA1		(UL(1) << 58)
+#define TCR_DS			(UL(1) << 59)
 
 /*
  * TTBR.
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org
Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com,
	mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com,
	maz@kernel.org, james.morse@arm.com, steven.price@arm.com,
	Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [RFC V2 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field
Date: Mon, 26 Jul 2021 12:07:18 +0530	[thread overview]
Message-ID: <1627281445-12445-4-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1627281445-12445-1-git-send-email-anshuman.khandual@arm.com>

As per ARM ARM (0487G.A) TCR_EL1.DS fields controls whether 52 bit input
and output address get supported on 4K and 16K page size configuration,
when FEAT_LPA2 is known to have been implemented. This adds TCR_DS field
definition which would be used when FEAT_LPA2 gets enabled.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/pgtable-hwdef.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 66671ff..1eb5574 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -275,6 +275,7 @@
 #define TCR_E0PD1		(UL(1) << 56)
 #define TCR_TCMA0		(UL(1) << 57)
 #define TCR_TCMA1		(UL(1) << 58)
+#define TCR_DS			(UL(1) << 59)
 
 /*
  * TTBR.
-- 
2.7.4


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  parent reply	other threads:[~2021-07-26  6:37 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-26  6:37 [RFC V2 00/10] arm64/mm: Enable FEAT_LPA2 (52 bits PA support on 4K|16K pages) Anshuman Khandual
2021-07-26  6:37 ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 01/10] mm/mmap: Dynamically initialize protection_map[] Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-08-05 17:03   ` Catalin Marinas
2021-08-05 17:03     ` Catalin Marinas
2021-08-12  9:15     ` Anshuman Khandual
2021-08-12  9:15       ` Anshuman Khandual
2021-08-13  7:16       ` Anshuman Khandual
2021-08-13  7:16         ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 02/10] arm64/mm: Consolidate TCR_EL1 fields Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-08-05 17:05   ` Catalin Marinas
2021-08-05 17:05     ` Catalin Marinas
2021-07-26  6:37 ` Anshuman Khandual [this message]
2021-07-26  6:37   ` [RFC V2 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field Anshuman Khandual
2021-08-05 17:06   ` Catalin Marinas
2021-08-05 17:06     ` Catalin Marinas
2021-07-26  6:37 ` [RFC V2 04/10] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-08-05 17:06   ` Catalin Marinas
2021-08-05 17:06     ` Catalin Marinas
2021-07-26  6:37 ` [RFC V2 05/10] arm64/mm: Add CONFIG_ARM64_PA_BITS_52_[LPA|LPA2] Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-08-05 17:25   ` Catalin Marinas
2021-08-05 17:25     ` Catalin Marinas
2021-08-12 10:09     ` Anshuman Khandual
2021-08-12 10:09       ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 07/10] arm64/mm: Detect and enable FEAT_LPA2 Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 08/10] arm64/mm: Add FEAT_LPA2 specific PTE_SHARED and PMD_SECT_S Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-07-26  6:37 ` [RFC V2 10/10] arm64/mm: Enable CONFIG_ARM64_PA_BITS_52 on CONFIG_ARM64_[4K|16K]_PAGES Anshuman Khandual
2021-07-26  6:37   ` Anshuman Khandual
2021-08-05 17:23   ` Catalin Marinas
2021-08-05 17:23     ` Catalin Marinas
2021-08-12  9:13     ` Anshuman Khandual
2021-08-12  9:13       ` Anshuman Khandual

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