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From: Catalin Marinas <catalin.marinas@arm.com>
To: Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Peter Collingbourne <pcc@google.com>,
	Will Deacon <will@kernel.org>,
	Andrey Konovalov <andreyknvl@gmail.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Tejas Belagod <Tejas.Belagod@arm.com>,
	Evgenii Stepanov <eugenis@google.com>
Subject: Re: [PATCH v5] arm64: avoid double ISB on kernel entry
Date: Wed, 28 Jul 2021 18:46:17 +0100	[thread overview]
Message-ID: <162749406642.26134.3898491024786322912.b4-ty@arm.com> (raw)
In-Reply-To: <20210727205439.2557419-1-pcc@google.com>

On Tue, 27 Jul 2021 13:54:39 -0700, Peter Collingbourne wrote:
> Although an ISB is required in order to make the MTE-related system
> register update to GCR_EL1 effective, and the same is true for
> PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two
> ISBs on machines that support both features while we only need to
> issue one. To avoid the unnecessary additional ISB, remove the ISBs
> from the PAC and MTE-specific alternative blocks and add a couple
> of additional blocks that cause us to only execute one ISB if both
> features are supported.

Applied to arm64 (for-next/mte). It still conflicted, so please check
that the result is fine. Thanks!

[1/1] arm64: avoid double ISB on kernel entry
      https://git.kernel.org/arm64/c/d914b80a8f56

-- 
Catalin


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      reply	other threads:[~2021-07-28 17:48 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 20:54 [PATCH v5] arm64: avoid double ISB on kernel entry Peter Collingbourne
2021-07-28 17:46 ` Catalin Marinas [this message]

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