[PATCH v5] arm64: avoid double ISB on kernel entry

[PATCH v5] arm64: avoid double ISB on kernel entry

[Peter Collingbourne]

Although an ISB is required in order to make the MTE-related system
register update to GCR_EL1 effective, and the same is true for
PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two
ISBs on machines that support both features while we only need to
issue one. To avoid the unnecessary additional ISB, remove the ISBs
from the PAC and MTE-specific alternative blocks and add a couple
of additional blocks that cause us to only execute one ISB if both
features are supported.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Link: https://linux-review.googlesource.com/id/Idee7e8114d5ae5a0b171d06220a0eb4bb015a51c
---
v5:
- rebase onto 5.14rc3

v2:
- fix formatting

 arch/arm64/kernel/entry.S | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index eacb9c01add0..102185eeeae0 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -176,7 +176,6 @@ alternative_else_nop_endif
 	ldr_l	\tmp, gcr_kernel_excl
 
 	mte_set_gcr \tmp, \tmp2
-	isb
 1:
 #endif
 	.endm
@@ -250,12 +249,24 @@ alternative_if ARM64_HAS_ADDRESS_AUTH
 	orr	x0, x0, SCTLR_ELx_ENIA
 	msr	sctlr_el1, x0
 2:
-	isb
 alternative_else_nop_endif
 #endif
 
 	mte_set_kernel_gcr x22, x23
 
+	/*
+	 * Any non-self-synchronizing system register updates required for
+	 * kernel entry should be placed before this point.
+	 */
+alternative_if ARM64_MTE
+	isb
+	b	1f
+alternative_else_nop_endif
+alternative_if ARM64_HAS_ADDRESS_AUTH
+	isb
+alternative_else_nop_endif
+1:
+
 	scs_load tsk
 	.else
 	add	x21, sp, #PT_REGS_SIZE
-- 
2.32.0.432.gabb21c7263-goog


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Re: [PATCH v5] arm64: avoid double ISB on kernel entry

[Catalin Marinas]

On Tue, 27 Jul 2021 13:54:39 -0700, Peter Collingbourne wrote:
> Although an ISB is required in order to make the MTE-related system
> register update to GCR_EL1 effective, and the same is true for
> PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two
> ISBs on machines that support both features while we only need to
> issue one. To avoid the unnecessary additional ISB, remove the ISBs
> from the PAC and MTE-specific alternative blocks and add a couple
> of additional blocks that cause us to only execute one ISB if both
> features are supported.

Applied to arm64 (for-next/mte). It still conflicted, so please check
that the result is fine. Thanks!

[1/1] arm64: avoid double ISB on kernel entry
      https://git.kernel.org/arm64/c/d914b80a8f56

-- 
Catalin


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