All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH v2 0/4] drm/i915/fbc: Rework CFB stride/size calculations
@ 2021-09-21 15:25 Ville Syrjala
  2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Rework cfb " Ville Syrjala
                   ` (15 more replies)
  0 siblings, 16 replies; 20+ messages in thread
From: Ville Syrjala @ 2021-09-21 15:25 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The way we calculate the CFB stride/size is kind of a mess, and
I'm not sure if we're even allocating enough stolen memory always.
Let's make it all more straightforward, and add some new related
workarounds as well.

Some of the earlier patches already got merged, and for these
leftovers I respun the min cfb stride calcualtion a bit to be
more explicit. Mainly hoping that I can still figure out what
it's doing after a few years have passed.

Ville Syrjälä (4):
  drm/i915/fbc: Rework cfb stride/size calculations
  drm/i915/fbc: Align FBC segments to 512B on glk+
  drm/i915/fbc: Implement Wa_16011863758 for icl+
  drm/i915/fbc: Allow higher compression limits on FBC1

 drivers/gpu/drm/i915/display/intel_fbc.c | 200 +++++++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h          |   4 +-
 drivers/gpu/drm/i915/i915_reg.h          |   4 +
 3 files changed, 139 insertions(+), 69 deletions(-)

-- 
2.32.0


^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2021-09-23  7:46 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-21 15:25 [Intel-gfx] [PATCH v2 0/4] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Rework cfb " Ville Syrjala
2021-09-22 18:26   ` Shankar, Uma
2021-09-23  4:21   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
2021-09-21 18:12   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/fbc: Allow higher compression limits on FBC1 Ville Syrjala
2021-09-21 17:27 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/fbc: Rework CFB stride/size calculations (rev3) Patchwork
2021-09-21 21:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev4) Patchwork
2021-09-21 21:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-21 22:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev5) Patchwork
2021-09-21 22:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-22  0:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-22 19:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev6) Patchwork
2021-09-22 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-22 21:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-23  4:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev7) Patchwork
2021-09-23  5:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-23  7:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.