* [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work
@ 2021-09-27 18:24 Ville Syrjala
2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala
` (20 more replies)
0 siblings, 21 replies; 36+ messages in thread
From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I had a few hours to burn the other day and so ended up accidentally
implementing per-lane drive settings for DP. This series contains
just the platform agnostic prep parts, and enabling it for LTTPRs.
I'll follow up with the platform specific hw pokey stuff later.
Ville Syrjälä (9):
drm/i915: s/ddi_translations/trans/
drm/i915: Generalize .set_signal_levels()
drm/i915: Nuke usless .set_signal_levels() wrappers
drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels()
drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()
drm/i915: Nuke intel_ddi_hdmi_num_entries()
drm/i915: Pass the lane to intel_ddi_level()
drm/i915: Prepare link training for per-lane drive settings
drm/i915: Allow per-lane drive settings with LTTPRs
drivers/gpu/drm/i915/display/g4x_dp.c | 33 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 310 +++------
drivers/gpu/drm/i915/display/intel_ddi.h | 7 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 640 +++++++++---------
.../drm/i915/display/intel_ddi_buf_trans.h | 4 -
.../drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/intel_dp_link_training.c | 73 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 28 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 5 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 21 +-
drivers/gpu/drm/i915/display/intel_snps_phy.h | 5 +-
11 files changed, 530 insertions(+), 601 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 16:59 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala ` (19 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> "ddi_translations" is a bit too long, let's shorten it to just "trans". Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 92 +-- .../drm/i915/display/intel_ddi_buf_trans.c | 628 +++++++++--------- drivers/gpu/drm/i915/display/intel_snps_phy.c | 12 +- 3 files changed, 366 insertions(+), 366 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a4667741d354..39bacef87ef2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -104,10 +104,10 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; /* If we're boosting the current, set bit 31 of trans1 */ @@ -117,9 +117,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, for (i = 0; i < n_entries; i++) { intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), - ddi_translations->entries[i].hsw.trans1 | iboost_bit); + trans->entries[i].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), - ddi_translations->entries[i].hsw.trans2); + trans->entries[i].hsw.trans2); } } @@ -136,10 +136,10 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; @@ -151,9 +151,9 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, /* Entry 9 is for HDMI: */ intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), - ddi_translations->entries[level].hsw.trans1 | iboost_bit); + trans->entries[level].hsw.trans1 | iboost_bit); intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), - ddi_translations->entries[level].hsw.trans2); + trans->entries[level].hsw.trans2); } void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -971,16 +971,16 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); if (iboost == 0) { - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; int n_entries; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; - iboost = ddi_translations->entries[level].hsw.i_boost; + iboost = trans->entries[level].hsw.i_boost; } /* Make sure that the requested I_boost is valid */ @@ -1000,21 +1000,21 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; enum port port = encoder->port; int n_entries; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; bxt_ddi_phy_set_signal_level(dev_priv, port, - ddi_translations->entries[level].bxt.margin, - ddi_translations->entries[level].bxt.scale, - ddi_translations->entries[level].bxt.enable, - ddi_translations->entries[level].bxt.deemphasis); + trans->entries[level].bxt.margin, + trans->entries[level].bxt.scale, + trans->entries[level].bxt.enable, + trans->entries[level].bxt.deemphasis); } static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, @@ -1051,13 +1051,13 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; u32 val; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; @@ -1066,7 +1066,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; - intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); + intel_dp->hobl_active = is_hobl_buf_trans(trans); intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, intel_dp->hobl_active ? val : 0); } @@ -1084,8 +1084,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel); - val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel); + val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel); + val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel); /* Program Rcomp scalar for every table entry */ val |= RCOMP_SCALAR(0x98); intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); @@ -1096,16 +1096,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1); - val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2); - val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff); + val |= POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1); + val |= POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2); + val |= CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff); intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); } /* Program PORT_TX_DW7 */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); val &= ~N_SCALAR_MASK; - val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar); + val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar); intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); } @@ -1176,15 +1176,15 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; int n_entries, ln; u32 val; if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) return; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; @@ -1205,13 +1205,13 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); + trans->entries[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( - ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); + trans->entries[level].mg.cri_txdeemph_override_17_12); intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); } @@ -1221,9 +1221,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | + trans->entries[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | + trans->entries[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); @@ -1231,9 +1231,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( - ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | + trans->entries[level].mg.cri_txdeemph_override_5_0) | CRI_TXDEEMPH_OVERRIDE_11_6( - ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | + trans->entries[level].mg.cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); @@ -1313,15 +1313,15 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; u32 val, dpcnt_mask, dpcnt_val; int n_entries, ln; if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) return; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; @@ -1329,9 +1329,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK); - dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control); - dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); - dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); + dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.dkl_vswing_control); + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.dkl_de_emphasis_control); + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.dkl_preshoot_control); for (ln = 0; ln < 2; ln++) { intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 796dd04eae01..449daba7afb3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -13,7 +13,7 @@ * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = { { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, @@ -25,12 +25,12 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, }; -static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = { - .entries = _hsw_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp), +static const struct intel_ddi_buf_trans hsw_trans_dp = { + .entries = _hsw_trans_dp, + .num_entries = ARRAY_SIZE(_hsw_trans_dp), }; -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { +static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = { { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, @@ -42,12 +42,12 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, }; -static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = { - .entries = _hsw_ddi_translations_fdi, - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi), +static const struct intel_ddi_buf_trans hsw_trans_fdi = { + .entries = _hsw_trans_fdi, + .num_entries = ARRAY_SIZE(_hsw_trans_fdi), }; -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = { /* Idx NT mV d T mV d db */ { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ @@ -63,13 +63,13 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ }; -static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { - .entries = _hsw_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), +static const struct intel_ddi_buf_trans hsw_trans_hdmi = { + .entries = _hsw_trans_hdmi, + .num_entries = ARRAY_SIZE(_hsw_trans_hdmi), .hdmi_default_entry = 6, }; -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = { { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, @@ -81,12 +81,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, }; -static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = { - .entries = _bdw_ddi_translations_edp, - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp), +static const struct intel_ddi_buf_trans bdw_trans_edp = { + .entries = _bdw_trans_edp, + .num_entries = ARRAY_SIZE(_bdw_trans_edp), }; -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = { { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, @@ -98,12 +98,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, }; -static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = { - .entries = _bdw_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp), +static const struct intel_ddi_buf_trans bdw_trans_dp = { + .entries = _bdw_trans_dp, + .num_entries = ARRAY_SIZE(_bdw_trans_dp), }; -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { +static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = { { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, @@ -115,12 +115,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, }; -static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = { - .entries = _bdw_ddi_translations_fdi, - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi), +static const struct intel_ddi_buf_trans bdw_trans_fdi = { + .entries = _bdw_trans_fdi, + .num_entries = ARRAY_SIZE(_bdw_trans_fdi), }; -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = { /* Idx NT mV d T mV df db */ { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ @@ -134,14 +134,14 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ }; -static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { - .entries = _bdw_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), +static const struct intel_ddi_buf_trans bdw_trans_hdmi = { + .entries = _bdw_trans_hdmi, + .num_entries = ARRAY_SIZE(_bdw_trans_hdmi), .hdmi_default_entry = 7, }; /* Skylake H and S */ -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = { { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -153,13 +153,13 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; -static const struct intel_ddi_buf_trans skl_ddi_translations_dp = { - .entries = _skl_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp), +static const struct intel_ddi_buf_trans skl_trans_dp = { + .entries = _skl_trans_dp, + .num_entries = ARRAY_SIZE(_skl_trans_dp), }; /* Skylake U */ -static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = { { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, @@ -171,13 +171,13 @@ static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; -static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = { - .entries = _skl_u_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp), +static const struct intel_ddi_buf_trans skl_u_trans_dp = { + .entries = _skl_u_trans_dp, + .num_entries = ARRAY_SIZE(_skl_u_trans_dp), }; /* Skylake Y */ -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = { { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -189,13 +189,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; -static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = { - .entries = _skl_y_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp), +static const struct intel_ddi_buf_trans skl_y_trans_dp = { + .entries = _skl_y_trans_dp, + .num_entries = ARRAY_SIZE(_skl_y_trans_dp), }; /* Kabylake H and S */ -static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = { { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -207,13 +207,13 @@ static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, }; -static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = { - .entries = _kbl_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp), +static const struct intel_ddi_buf_trans kbl_trans_dp = { + .entries = _kbl_trans_dp, + .num_entries = ARRAY_SIZE(_kbl_trans_dp), }; /* Kabylake U */ -static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = { { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -225,13 +225,13 @@ static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; -static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = { - .entries = _kbl_u_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp), +static const struct intel_ddi_buf_trans kbl_u_trans_dp = { + .entries = _kbl_u_trans_dp, + .num_entries = ARRAY_SIZE(_kbl_u_trans_dp), }; /* Kabylake Y */ -static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = { { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x00000088, 0x0 } }, { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, @@ -243,16 +243,16 @@ static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, }; -static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = { - .entries = _kbl_y_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp), +static const struct intel_ddi_buf_trans kbl_y_trans_dp = { + .entries = _kbl_y_trans_dp, + .num_entries = ARRAY_SIZE(_kbl_y_trans_dp), }; /* * Skylake/Kabylake H and S * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, @@ -265,16 +265,16 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; -static const struct intel_ddi_buf_trans skl_ddi_translations_edp = { - .entries = _skl_ddi_translations_edp, - .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp), +static const struct intel_ddi_buf_trans skl_trans_edp = { + .entries = _skl_trans_edp, + .num_entries = ARRAY_SIZE(_skl_trans_edp), }; /* * Skylake/Kabylake U * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, @@ -287,16 +287,16 @@ static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, }; -static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = { - .entries = _skl_u_ddi_translations_edp, - .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp), +static const struct intel_ddi_buf_trans skl_u_trans_edp = { + .entries = _skl_u_trans_edp, + .num_entries = ARRAY_SIZE(_skl_u_trans_edp), }; /* * Skylake/Kabylake Y * eDP 1.4 low vswing translation parameters */ -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = { { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, @@ -309,13 +309,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, }; -static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = { - .entries = _skl_y_ddi_translations_edp, - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp), +static const struct intel_ddi_buf_trans skl_y_trans_edp = { + .entries = _skl_y_trans_edp, + .num_entries = ARRAY_SIZE(_skl_y_trans_edp), }; /* Skylake/Kabylake U, H and S */ -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = { { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, { .hsw = { 0x00007011, 0x00000088, 0x0 } }, @@ -329,14 +329,14 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, }; -static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { - .entries = _skl_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), +static const struct intel_ddi_buf_trans skl_trans_hdmi = { + .entries = _skl_trans_hdmi, + .num_entries = ARRAY_SIZE(_skl_trans_hdmi), .hdmi_default_entry = 8, }; /* Skylake/Kabylake Y */ -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = { { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, @@ -350,13 +350,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, }; -static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { - .entries = _skl_y_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), +static const struct intel_ddi_buf_trans skl_y_trans_hdmi = { + .entries = _skl_y_trans_hdmi, + .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi), .hdmi_default_entry = 8, }; -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = { /* Idx NT mV diff db */ { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ @@ -370,12 +370,12 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; -static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = { - .entries = _bxt_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp), +static const struct intel_ddi_buf_trans bxt_trans_dp = { + .entries = _bxt_trans_dp, + .num_entries = ARRAY_SIZE(_bxt_trans_dp), }; -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { +static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = { /* Idx NT mV diff db */ { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ @@ -389,15 +389,15 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ }; -static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = { - .entries = _bxt_ddi_translations_edp, - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp), +static const struct intel_ddi_buf_trans bxt_trans_edp = { + .entries = _bxt_trans_edp, + .num_entries = ARRAY_SIZE(_bxt_trans_edp), }; /* BSpec has 2 recommended values - entries 0 and 8. * Using the entry with higher vswing. */ -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = { /* Idx NT mV diff db */ { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ @@ -411,14 +411,14 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ }; -static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { - .entries = _bxt_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), - .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, +static const struct intel_ddi_buf_trans bxt_trans_hdmi = { + .entries = _bxt_trans_hdmi, + .num_entries = ARRAY_SIZE(_bxt_trans_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1, }; -/* icl_combo_phy_ddi_translations */ -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = { +/* icl_combo_phy_trans */ +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -432,12 +432,12 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = { - .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), +static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = { + .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3, + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3), }; -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ @@ -451,12 +451,12 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = { - .entries = _icl_combo_phy_ddi_translations_edp_hbr2, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), +static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = { + .entries = _icl_combo_phy_trans_edp_hbr2, + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ @@ -467,13 +467,13 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ }; -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { - .entries = _icl_combo_phy_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), - .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, +static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = { + .entries = _icl_combo_phy_trans_hdmi, + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1, }; -static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ @@ -487,12 +487,12 @@ static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { - .entries = _ehl_combo_phy_ddi_translations_dp, - .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), +static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = { + .entries = _ehl_combo_phy_trans_dp, + .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp), }; -static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ @@ -506,12 +506,12 @@ static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = { - .entries = _ehl_combo_phy_ddi_translations_edp_hbr2, - .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2), +static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = { + .entries = _ehl_combo_phy_trans_edp_hbr2, + .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = { /* NT mV Trans mV db */ { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ @@ -525,12 +525,12 @@ static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = { - .entries = _jsl_combo_phy_ddi_translations_edp_hbr, - .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr), +static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = { + .entries = _jsl_combo_phy_trans_edp_hbr, + .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr), }; -static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ @@ -544,12 +544,12 @@ static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ }; -static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = { - .entries = _jsl_combo_phy_ddi_translations_edp_hbr2, - .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2), +static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = { + .entries = _jsl_combo_phy_trans_edp_hbr2, + .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ @@ -563,12 +563,12 @@ static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = { - .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr, - .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr), +static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = { + .entries = _dg1_combo_phy_trans_dp_rbr_hbr, + .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr), }; -static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ @@ -582,12 +582,12 @@ static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = { - .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3), +static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = { + .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3), }; -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = { +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = { /* Voltage swing pre-emphasis */ { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ @@ -601,12 +601,12 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hb { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ }; -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = { - .entries = _icl_mg_phy_ddi_translations_rbr_hbr, - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr), +static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = { + .entries = _icl_mg_phy_trans_rbr_hbr, + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr), }; -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = { /* Voltage swing pre-emphasis */ { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ @@ -620,12 +620,12 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_h { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ }; -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = { - .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3), +static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = { + .entries = _icl_mg_phy_trans_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3), }; -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -639,13 +639,13 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ }; -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { - .entries = _icl_mg_phy_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), - .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, +static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = { + .entries = _icl_mg_phy_trans_hdmi, + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1, }; -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -659,12 +659,12 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hb { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = { - .entries = _tgl_dkl_phy_ddi_translations_dp_hbr, - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr), +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = { + .entries = _tgl_dkl_phy_trans_dp_hbr, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr), }; -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -678,12 +678,12 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hb { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = { - .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2, - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2), +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = { + .entries = _tgl_dkl_phy_trans_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2), }; -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -697,13 +697,13 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[ { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ }; -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { - .entries = _tgl_dkl_phy_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), - .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = { + .entries = _tgl_dkl_phy_trans_hdmi, + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1, }; -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -717,12 +717,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = { - .entries = _tgl_combo_phy_ddi_translations_dp_hbr, - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr), +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = { + .entries = _tgl_combo_phy_trans_dp_hbr, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr), }; -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -736,12 +736,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = { - .entries = _tgl_combo_phy_ddi_translations_dp_hbr2, - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2), +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = { + .entries = _tgl_combo_phy_trans_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2), }; -static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ @@ -755,16 +755,16 @@ static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = { - .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2, - .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2), +static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = { + .entries = _tgl_uy_combo_phy_trans_dp_hbr2, + .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2), }; /* * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries * that DisplayPort specification requires */ -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = { /* VS pre-emp */ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ @@ -777,12 +777,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ }; -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = { - .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl, - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl), +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = { + .entries = _tgl_combo_phy_trans_edp_hbr2_hobl, + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl), }; -static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = { +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -796,12 +796,12 @@ static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = { - .entries = _rkl_combo_phy_ddi_translations_dp_hbr, - .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr), +static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = { + .entries = _rkl_combo_phy_trans_dp_hbr, + .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr), }; -static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ @@ -815,12 +815,12 @@ static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_ { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = { - .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), +static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = { + .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3), }; -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -834,12 +834,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { - .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), +static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = { + .entries = _adls_combo_phy_trans_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3), }; -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = { /* NT mV Trans mV db */ { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */ { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */ @@ -853,12 +853,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_ed { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ }; -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { - .entries = _adls_combo_phy_ddi_translations_edp_hbr2, - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), +static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = { + .entries = _adls_combo_phy_trans_edp_hbr2, + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -872,12 +872,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_ed { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { - .entries = _adls_combo_phy_ddi_translations_edp_hbr3, - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), +static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = { + .entries = _adls_combo_phy_trans_edp_hbr3, + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3), }; -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hdmi[] = { +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_hdmi[] = { /* NT mV Trans mV db */ { .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ { .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ @@ -891,13 +891,13 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hd { .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } }, /* Full Red -3.0 */ }; -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi = { - .entries = _adlp_combo_phy_ddi_translations_hdmi, - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi), - .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) - 1, +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_hdmi = { + .entries = _adlp_combo_phy_trans_hdmi, + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi) - 1, }; -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr[] = { +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -911,12 +911,12 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr = { - .entries = _adlp_combo_phy_ddi_translations_dp_hbr, - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr), +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = { + .entries = _adlp_combo_phy_trans_dp_hbr, + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr), }; -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = { /* NT mV Trans mV db */ { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ @@ -930,22 +930,22 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = { - .entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3), +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = { + .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3), }; -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_hbr3 = { - .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = { + .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3, + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3), }; -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_up_to_hbr2 = { - .entries = _icl_combo_phy_ddi_translations_edp_hbr2, - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = { + .entries = _icl_combo_phy_trans_edp_hbr2, + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2), }; -static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = { +static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */ @@ -959,12 +959,12 @@ static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_h { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ }; -static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr = { - .entries = _adlp_dkl_phy_ddi_translations_dp_hbr, - .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr), +static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = { + .entries = _adlp_dkl_phy_trans_dp_hbr, + .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr), }; -static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */ @@ -978,12 +978,12 @@ static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_h { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ }; -static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3 = { - .entries = _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, - .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), +static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { + .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3, + .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3), }; -static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { +static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ @@ -996,13 +996,13 @@ static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ }; -static const struct intel_ddi_buf_trans dg2_snps_translations = { - .entries = _dg2_snps_translations, - .num_entries = ARRAY_SIZE(_dg2_snps_translations), - .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, +static const struct intel_ddi_buf_trans dg2_snps_trans = { + .entries = _dg2_snps_trans, + .num_entries = ARRAY_SIZE(_dg2_snps_trans), + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1, }; -static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { +static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { { .snps = { 62, 0, 0 } }, /* preset 0 */ { .snps = { 56, 0, 6 } }, /* preset 1 */ { .snps = { 51, 0, 11 } }, /* preset 2 */ @@ -1021,21 +1021,21 @@ static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { { .snps = { 56, 3, 3 } }, /* preset 15 */ }; -static const struct intel_ddi_buf_trans dg2_snps_translations_uhbr = { - .entries = _dg2_snps_translations_uhbr, - .num_entries = ARRAY_SIZE(_dg2_snps_translations_uhbr), +static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = { + .entries = _dg2_snps_trans_uhbr, + .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr), }; bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { - return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; + return table == &tgl_combo_phy_trans_edp_hbr2_hobl; } static const struct intel_ddi_buf_trans * -intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) +intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries) { - *num_entries = ddi_translations->num_entries; - return ddi_translations; + *num_entries = trans->num_entries; + return trans; } static const struct intel_ddi_buf_trans * @@ -1044,11 +1044,11 @@ hsw_get_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); + return intel_get_buf_trans(&hsw_trans_fdi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&hsw_trans_hdmi, n_entries); else - return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); + return intel_get_buf_trans(&hsw_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1059,14 +1059,14 @@ bdw_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); + return intel_get_buf_trans(&bdw_trans_fdi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&bdw_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); + return intel_get_buf_trans(&bdw_trans_edp, n_entries); else - return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); + return intel_get_buf_trans(&bdw_trans_dp, n_entries); } static int skl_buf_trans_num_entries(enum port port, int n_entries) @@ -1080,12 +1080,12 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) static const struct intel_ddi_buf_trans * _skl_get_buf_trans_dp(struct intel_encoder *encoder, - const struct intel_ddi_buf_trans *ddi_translations, + const struct intel_ddi_buf_trans *trans, int *n_entries) { - ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); + trans = intel_get_buf_trans(trans, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); - return ddi_translations; + return trans; } static const struct intel_ddi_buf_trans * @@ -1096,12 +1096,12 @@ skl_y_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1112,12 +1112,12 @@ skl_u_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1128,12 +1128,12 @@ skl_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1144,12 +1144,12 @@ kbl_y_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1160,12 +1160,12 @@ kbl_u_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1176,12 +1176,12 @@ kbl_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); + return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries); else - return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); + return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1192,12 +1192,12 @@ bxt_get_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&bxt_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && i915->vbt.edp.low_vswing) - return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); + return intel_get_buf_trans(&bxt_trans_edp, n_entries); else - return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); + return intel_get_buf_trans(&bxt_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1205,7 +1205,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); } @@ -1217,10 +1217,10 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); } @@ -1233,7 +1233,7 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1246,10 +1246,10 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3, + return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3, n_entries); } else { - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr, + return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr, n_entries); } } @@ -1260,7 +1260,7 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries); else return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); } @@ -1271,9 +1271,9 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries); + return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries); else - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); } static const struct intel_ddi_buf_trans * @@ -1284,12 +1284,12 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && dev_priv->vbt.edp.low_vswing) return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries); + return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries); } static const struct intel_ddi_buf_trans * @@ -1298,9 +1298,9 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries); + return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries); else - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries); + return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries); } static const struct intel_ddi_buf_trans * @@ -1311,12 +1311,12 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && dev_priv->vbt.edp.low_vswing) return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); } static const struct intel_ddi_buf_trans * @@ -1328,14 +1328,14 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, if (crtc_state->port_clock > 270000) { if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { - return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, + return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, n_entries); } else { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2, + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2, n_entries); } } else { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries); } } @@ -1349,13 +1349,13 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); } @@ -1368,7 +1368,7 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1381,10 +1381,10 @@ dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, + return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3, n_entries); else - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, + return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr, n_entries); } @@ -1397,13 +1397,13 @@ dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); else if (dev_priv->vbt.edp.low_vswing) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); else return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); @@ -1415,7 +1415,7 @@ dg1_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1428,9 +1428,9 @@ rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries); else - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); + return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries); } static const struct intel_ddi_buf_trans * @@ -1442,13 +1442,13 @@ rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); } @@ -1461,7 +1461,7 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1474,9 +1474,9 @@ adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries); else - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries); } static const struct intel_ddi_buf_trans * @@ -1488,11 +1488,11 @@ adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); + return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries); else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); else if (i915->vbt.edp.low_vswing) - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); + return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries); else return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } @@ -1503,7 +1503,7 @@ adls_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1516,9 +1516,9 @@ adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries); else - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr, n_entries); + return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries); } static const struct intel_ddi_buf_trans * @@ -1530,13 +1530,13 @@ adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (crtc_state->port_clock > 540000) { - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3, + return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3, n_entries); } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); } else if (dev_priv->vbt.edp.low_vswing) { - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2, + return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2, n_entries); } @@ -1549,7 +1549,7 @@ adlp_get_combo_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&adlp_combo_phy_trans_hdmi, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else @@ -1562,10 +1562,10 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2, + return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2, n_entries); } else { - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr, + return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr, n_entries); } } @@ -1576,7 +1576,7 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries); else return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); } @@ -1587,10 +1587,10 @@ adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, + return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3, n_entries); } else { - return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr, + return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr, n_entries); } } @@ -1601,7 +1601,7 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); + return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries); else return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); } @@ -1612,9 +1612,9 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 1000000) - return intel_get_buf_trans(&dg2_snps_translations_uhbr, n_entries); + return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries); else - return intel_get_buf_trans(&dg2_snps_translations, n_entries); + return intel_get_buf_trans(&dg2_snps_trans, n_entries); } int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, @@ -1622,17 +1622,17 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, int *default_entry) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; int n_entries; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { + if (drm_WARN_ON(&dev_priv->drm, !trans)) { *default_entry = 0; return 0; } - *default_entry = ddi_translations->hdmi_default_entry; + *default_entry = trans->hdmi_default_entry; return n_entries; } diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 2405f70d82de..3734e349f91d 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -56,12 +56,12 @@ void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_ddi_buf_trans *ddi_translations; + const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) level = n_entries - 1; @@ -69,9 +69,9 @@ void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, for (ln = 0; ln < 4; ln++) { u32 val = 0; - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.snps_vswing); + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor); + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor); intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); } -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ 2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala @ 2021-09-29 16:59 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 16:59 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:47PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > "ddi_translations" is a bit too long, let's shorten it to just "trans". > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 92 +-- > .../drm/i915/display/intel_ddi_buf_trans.c | 628 +++++++++--------- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 12 +- > 3 files changed, 366 insertions(+), 366 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index a4667741d354..39bacef87ef2 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -104,10 +104,10 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > u32 iboost_bit = 0; > int i, n_entries; > enum port port = encoder->port; > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > > /* If we're boosting the current, set bit 31 of trans1 */ > @@ -117,9 +117,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > > for (i = 0; i < n_entries; i++) { > intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), > - ddi_translations->entries[i].hsw.trans1 | iboost_bit); > + trans->entries[i].hsw.trans1 | iboost_bit); > intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), > - ddi_translations->entries[i].hsw.trans2); > + trans->entries[i].hsw.trans2); > } > } > > @@ -136,10 +136,10 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > u32 iboost_bit = 0; > int n_entries; > enum port port = encoder->port; > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > @@ -151,9 +151,9 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > /* Entry 9 is for HDMI: */ > intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), > - ddi_translations->entries[level].hsw.trans1 | iboost_bit); > + trans->entries[level].hsw.trans1 | iboost_bit); > intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), > - ddi_translations->entries[level].hsw.trans2); > + trans->entries[level].hsw.trans2); > } > > void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > @@ -971,16 +971,16 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); > > if (iboost == 0) { > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > int n_entries; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > > - iboost = ddi_translations->entries[level].hsw.i_boost; > + iboost = trans->entries[level].hsw.i_boost; > } > > /* Make sure that the requested I_boost is valid */ > @@ -1000,21 +1000,21 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, > int level) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > enum port port = encoder->port; > int n_entries; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > > bxt_ddi_phy_set_signal_level(dev_priv, port, > - ddi_translations->entries[level].bxt.margin, > - ddi_translations->entries[level].bxt.scale, > - ddi_translations->entries[level].bxt.enable, > - ddi_translations->entries[level].bxt.deemphasis); > + trans->entries[level].bxt.margin, > + trans->entries[level].bxt.scale, > + trans->entries[level].bxt.enable, > + trans->entries[level].bxt.deemphasis); > } > > static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, > @@ -1051,13 +1051,13 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > int level) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int n_entries, ln; > u32 val; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > @@ -1066,7 +1066,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; > - intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); > + intel_dp->hobl_active = is_hobl_buf_trans(trans); > intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, > intel_dp->hobl_active ? val : 0); > } > @@ -1084,8 +1084,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > - val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel); > - val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel); > + val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel); > + val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel); > /* Program Rcomp scalar for every table entry */ > val |= RCOMP_SCALAR(0x98); > intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); > @@ -1096,16 +1096,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > - val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1); > - val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2); > - val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff); > + val |= POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1); > + val |= POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2); > + val |= CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff); > intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); > } > > /* Program PORT_TX_DW7 */ > val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); > val &= ~N_SCALAR_MASK; > - val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar); > + val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar); > intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); > } > > @@ -1176,15 +1176,15 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > int n_entries, ln; > u32 val; > > if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) > return; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > @@ -1205,13 +1205,13 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > - ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); > + trans->entries[level].mg.cri_txdeemph_override_17_12); > intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); > > val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > - ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); > + trans->entries[level].mg.cri_txdeemph_override_17_12); > intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); > } > > @@ -1221,9 +1221,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > - ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | > + trans->entries[level].mg.cri_txdeemph_override_5_0) | > CRI_TXDEEMPH_OVERRIDE_11_6( > - ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | > + trans->entries[level].mg.cri_txdeemph_override_11_6) | > CRI_TXDEEMPH_OVERRIDE_EN; > intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); > > @@ -1231,9 +1231,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > - ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | > + trans->entries[level].mg.cri_txdeemph_override_5_0) | > CRI_TXDEEMPH_OVERRIDE_11_6( > - ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | > + trans->entries[level].mg.cri_txdeemph_override_11_6) | > CRI_TXDEEMPH_OVERRIDE_EN; > intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); > > @@ -1313,15 +1313,15 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > u32 val, dpcnt_mask, dpcnt_val; > int n_entries, ln; > > if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) > return; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > level = n_entries - 1; > @@ -1329,9 +1329,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | > DKL_TX_DE_EMPAHSIS_COEFF_MASK | > DKL_TX_VSWING_CONTROL_MASK); > - dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control); > - dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); > - dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); > + dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.dkl_vswing_control); > + dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.dkl_de_emphasis_control); > + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.dkl_preshoot_control); > > for (ln = 0; ln < 2; ln++) { > intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 796dd04eae01..449daba7afb3 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -13,7 +13,7 @@ > * them for both DP and FDI transports, allowing those ports to > * automatically adapt to HDMI connections as well > */ > -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = { > { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, > { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, > { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, > @@ -25,12 +25,12 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { > { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = { > - .entries = _hsw_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp), > +static const struct intel_ddi_buf_trans hsw_trans_dp = { > + .entries = _hsw_trans_dp, > + .num_entries = ARRAY_SIZE(_hsw_trans_dp), > }; > > -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { > +static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = { > { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, > { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, > { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, > @@ -42,12 +42,12 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { > { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = { > - .entries = _hsw_ddi_translations_fdi, > - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi), > +static const struct intel_ddi_buf_trans hsw_trans_fdi = { > + .entries = _hsw_trans_fdi, > + .num_entries = ARRAY_SIZE(_hsw_trans_fdi), > }; > > -static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = { > /* Idx NT mV d T mV d db */ > { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ > { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ > @@ -63,13 +63,13 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { > { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ > }; > > -static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { > - .entries = _hsw_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), > +static const struct intel_ddi_buf_trans hsw_trans_hdmi = { > + .entries = _hsw_trans_hdmi, > + .num_entries = ARRAY_SIZE(_hsw_trans_hdmi), > .hdmi_default_entry = 6, > }; > > -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { > +static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = { > { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, > { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, > { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, > @@ -81,12 +81,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { > { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = { > - .entries = _bdw_ddi_translations_edp, > - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp), > +static const struct intel_ddi_buf_trans bdw_trans_edp = { > + .entries = _bdw_trans_edp, > + .num_entries = ARRAY_SIZE(_bdw_trans_edp), > }; > > -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = { > { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, > { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, > { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, > @@ -98,12 +98,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { > { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = { > - .entries = _bdw_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp), > +static const struct intel_ddi_buf_trans bdw_trans_dp = { > + .entries = _bdw_trans_dp, > + .num_entries = ARRAY_SIZE(_bdw_trans_dp), > }; > > -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { > +static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = { > { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, > { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, > { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, > @@ -115,12 +115,12 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { > { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = { > - .entries = _bdw_ddi_translations_fdi, > - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi), > +static const struct intel_ddi_buf_trans bdw_trans_fdi = { > + .entries = _bdw_trans_fdi, > + .num_entries = ARRAY_SIZE(_bdw_trans_fdi), > }; > > -static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = { > /* Idx NT mV d T mV df db */ > { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ > { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ > @@ -134,14 +134,14 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { > { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ > }; > > -static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { > - .entries = _bdw_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), > +static const struct intel_ddi_buf_trans bdw_trans_hdmi = { > + .entries = _bdw_trans_hdmi, > + .num_entries = ARRAY_SIZE(_bdw_trans_hdmi), > .hdmi_default_entry = 7, > }; > > /* Skylake H and S */ > -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = { > { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, > { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, > { .hsw = { 0x00007011, 0x00000088, 0x0 } }, > @@ -153,13 +153,13 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, > }; > > -static const struct intel_ddi_buf_trans skl_ddi_translations_dp = { > - .entries = _skl_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp), > +static const struct intel_ddi_buf_trans skl_trans_dp = { > + .entries = _skl_trans_dp, > + .num_entries = ARRAY_SIZE(_skl_trans_dp), > }; > > /* Skylake U */ > -static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = { > { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, > { .hsw = { 0x00005012, 0x00000088, 0x0 } }, > { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, > @@ -171,13 +171,13 @@ static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, > }; > > -static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = { > - .entries = _skl_u_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp), > +static const struct intel_ddi_buf_trans skl_u_trans_dp = { > + .entries = _skl_u_trans_dp, > + .num_entries = ARRAY_SIZE(_skl_u_trans_dp), > }; > > /* Skylake Y */ > -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = { > { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, > { .hsw = { 0x00005012, 0x00000088, 0x0 } }, > { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, > @@ -189,13 +189,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, > }; > > -static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = { > - .entries = _skl_y_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp), > +static const struct intel_ddi_buf_trans skl_y_trans_dp = { > + .entries = _skl_y_trans_dp, > + .num_entries = ARRAY_SIZE(_skl_y_trans_dp), > }; > > /* Kabylake H and S */ > -static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = { > { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, > { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, > { .hsw = { 0x00007011, 0x00000088, 0x0 } }, > @@ -207,13 +207,13 @@ static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, > }; > > -static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = { > - .entries = _kbl_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp), > +static const struct intel_ddi_buf_trans kbl_trans_dp = { > + .entries = _kbl_trans_dp, > + .num_entries = ARRAY_SIZE(_kbl_trans_dp), > }; > > /* Kabylake U */ > -static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = { > { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, > { .hsw = { 0x00005012, 0x00000088, 0x0 } }, > { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, > @@ -225,13 +225,13 @@ static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, > }; > > -static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = { > - .entries = _kbl_u_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp), > +static const struct intel_ddi_buf_trans kbl_u_trans_dp = { > + .entries = _kbl_u_trans_dp, > + .num_entries = ARRAY_SIZE(_kbl_u_trans_dp), > }; > > /* Kabylake Y */ > -static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = { > { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, > { .hsw = { 0x00005012, 0x00000088, 0x0 } }, > { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, > @@ -243,16 +243,16 @@ static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { > { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, > }; > > -static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = { > - .entries = _kbl_y_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp), > +static const struct intel_ddi_buf_trans kbl_y_trans_dp = { > + .entries = _kbl_y_trans_dp, > + .num_entries = ARRAY_SIZE(_kbl_y_trans_dp), > }; > > /* > * Skylake/Kabylake H and S > * eDP 1.4 low vswing translation parameters > */ > -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { > +static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = { > { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, > { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, > { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, > @@ -265,16 +265,16 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { > { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans skl_ddi_translations_edp = { > - .entries = _skl_ddi_translations_edp, > - .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp), > +static const struct intel_ddi_buf_trans skl_trans_edp = { > + .entries = _skl_trans_edp, > + .num_entries = ARRAY_SIZE(_skl_trans_edp), > }; > > /* > * Skylake/Kabylake U > * eDP 1.4 low vswing translation parameters > */ > -static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { > +static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = { > { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, > { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, > { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, > @@ -287,16 +287,16 @@ static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { > { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = { > - .entries = _skl_u_ddi_translations_edp, > - .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp), > +static const struct intel_ddi_buf_trans skl_u_trans_edp = { > + .entries = _skl_u_trans_edp, > + .num_entries = ARRAY_SIZE(_skl_u_trans_edp), > }; > > /* > * Skylake/Kabylake Y > * eDP 1.4 low vswing translation parameters > */ > -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { > +static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = { > { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, > { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, > { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, > @@ -309,13 +309,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { > { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, > }; > > -static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = { > - .entries = _skl_y_ddi_translations_edp, > - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp), > +static const struct intel_ddi_buf_trans skl_y_trans_edp = { > + .entries = _skl_y_trans_edp, > + .num_entries = ARRAY_SIZE(_skl_y_trans_edp), > }; > > /* Skylake/Kabylake U, H and S */ > -static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = { > { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, > { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, > { .hsw = { 0x00007011, 0x00000088, 0x0 } }, > @@ -329,14 +329,14 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { > { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, > }; > > -static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { > - .entries = _skl_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), > +static const struct intel_ddi_buf_trans skl_trans_hdmi = { > + .entries = _skl_trans_hdmi, > + .num_entries = ARRAY_SIZE(_skl_trans_hdmi), > .hdmi_default_entry = 8, > }; > > /* Skylake/Kabylake Y */ > -static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = { > { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, > { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, > { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, > @@ -350,13 +350,13 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { > { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, > }; > > -static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { > - .entries = _skl_y_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), > +static const struct intel_ddi_buf_trans skl_y_trans_hdmi = { > + .entries = _skl_y_trans_hdmi, > + .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi), > .hdmi_default_entry = 8, > }; > > -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = { > /* Idx NT mV diff db */ > { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ > { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ > @@ -370,12 +370,12 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { > { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ > }; > > -static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = { > - .entries = _bxt_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp), > +static const struct intel_ddi_buf_trans bxt_trans_dp = { > + .entries = _bxt_trans_dp, > + .num_entries = ARRAY_SIZE(_bxt_trans_dp), > }; > > -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { > +static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = { > /* Idx NT mV diff db */ > { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ > { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ > @@ -389,15 +389,15 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { > { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ > }; > > -static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = { > - .entries = _bxt_ddi_translations_edp, > - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp), > +static const struct intel_ddi_buf_trans bxt_trans_edp = { > + .entries = _bxt_trans_edp, > + .num_entries = ARRAY_SIZE(_bxt_trans_edp), > }; > > /* BSpec has 2 recommended values - entries 0 and 8. > * Using the entry with higher vswing. > */ > -static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = { > /* Idx NT mV diff db */ > { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ > { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ > @@ -411,14 +411,14 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { > { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ > }; > > -static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { > - .entries = _bxt_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), > - .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, > +static const struct intel_ddi_buf_trans bxt_trans_hdmi = { > + .entries = _bxt_trans_hdmi, > + .num_entries = ARRAY_SIZE(_bxt_trans_hdmi), > + .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1, > }; > > -/* icl_combo_phy_ddi_translations */ > -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = { > +/* icl_combo_phy_trans */ > +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -432,12 +432,12 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = { > - .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), > +static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = { > + .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3, > + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ > { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ > @@ -451,12 +451,12 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp > { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > }; > > -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = { > - .entries = _icl_combo_phy_ddi_translations_edp_hbr2, > - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), > +static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = { > + .entries = _icl_combo_phy_trans_edp_hbr2, > + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ > { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ > @@ -467,13 +467,13 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm > { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ > }; > > -static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { > - .entries = _icl_combo_phy_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), > - .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, > +static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = { > + .entries = _icl_combo_phy_trans_hdmi, > + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi), > + .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1, > }; > > -static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { > +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ > @@ -487,12 +487,12 @@ static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { > - .entries = _ehl_combo_phy_ddi_translations_dp, > - .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), > +static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = { > + .entries = _ehl_combo_phy_trans_dp, > + .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp), > }; > > -static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ > { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ > @@ -506,12 +506,12 @@ static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > }; > > -static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = { > - .entries = _ehl_combo_phy_ddi_translations_edp_hbr2, > - .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2), > +static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = { > + .entries = _ehl_combo_phy_trans_edp_hbr2, > + .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = { > /* NT mV Trans mV db */ > { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ > { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ > @@ -525,12 +525,12 @@ static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > }; > > -static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = { > - .entries = _jsl_combo_phy_ddi_translations_edp_hbr, > - .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr), > +static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = { > + .entries = _jsl_combo_phy_trans_edp_hbr, > + .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ > { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ > @@ -544,12 +544,12 @@ static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > }; > > -static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = { > - .entries = _jsl_combo_phy_ddi_translations_edp_hbr2, > - .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2), > +static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = { > + .entries = _jsl_combo_phy_trans_edp_hbr2, > + .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { > +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ > @@ -563,12 +563,12 @@ static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = { > - .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr, > - .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr), > +static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = { > + .entries = _dg1_combo_phy_trans_dp_rbr_hbr, > + .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ > @@ -582,12 +582,12 @@ static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = { > - .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3), > +static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = { > + .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = { > +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = { > /* Voltage swing pre-emphasis */ > { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ > { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ > @@ -601,12 +601,12 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hb > { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ > }; > > -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = { > - .entries = _icl_mg_phy_ddi_translations_rbr_hbr, > - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr), > +static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = { > + .entries = _icl_mg_phy_trans_rbr_hbr, > + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = { > /* Voltage swing pre-emphasis */ > { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ > { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ > @@ -620,12 +620,12 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_h > { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ > }; > > -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = { > - .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3), > +static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = { > + .entries = _icl_mg_phy_trans_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = { > /* HDMI Preset VS Pre-emph */ > { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ > { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ > @@ -639,13 +639,13 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] > { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ > }; > > -static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { > - .entries = _icl_mg_phy_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), > - .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, > +static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = { > + .entries = _icl_mg_phy_trans_hdmi, > + .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi), > + .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1, > }; > > -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = { > /* VS pre-emp Non-trans mV Pre-emph dB */ > { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ > { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ > @@ -659,12 +659,12 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hb > { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ > }; > > -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = { > - .entries = _tgl_dkl_phy_ddi_translations_dp_hbr, > - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr), > +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = { > + .entries = _tgl_dkl_phy_trans_dp_hbr, > + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = { > /* VS pre-emp Non-trans mV Pre-emph dB */ > { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ > { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ > @@ -678,12 +678,12 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hb > { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ > }; > > -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = { > - .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2, > - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2), > +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = { > + .entries = _tgl_dkl_phy_trans_dp_hbr2, > + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = { > /* HDMI Preset VS Pre-emph */ > { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ > { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ > @@ -697,13 +697,13 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[ > { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ > }; > > -static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { > - .entries = _tgl_dkl_phy_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), > - .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, > +static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = { > + .entries = _tgl_dkl_phy_trans_hdmi, > + .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi), > + .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1, > }; > > -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -717,12 +717,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = { > - .entries = _tgl_combo_phy_ddi_translations_dp_hbr, > - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr), > +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = { > + .entries = _tgl_combo_phy_trans_dp_hbr, > + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -736,12 +736,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = { > - .entries = _tgl_combo_phy_ddi_translations_dp_hbr2, > - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2), > +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = { > + .entries = _tgl_combo_phy_trans_dp_hbr2, > + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ > @@ -755,16 +755,16 @@ static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = { > - .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2, > - .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2), > +static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = { > + .entries = _tgl_uy_combo_phy_trans_dp_hbr2, > + .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2), > }; > > /* > * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries > * that DisplayPort specification requires > */ > -static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { > +static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = { > /* VS pre-emp */ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ > @@ -777,12 +777,12 @@ static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ > }; > > -static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = { > - .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > - .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl), > +static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = { > + .entries = _tgl_combo_phy_trans_edp_hbr2_hobl, > + .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl), > }; > > -static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -796,12 +796,12 @@ static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = { > - .entries = _rkl_combo_phy_ddi_translations_dp_hbr, > - .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr), > +static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = { > + .entries = _rkl_combo_phy_trans_dp_hbr, > + .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ > @@ -815,12 +815,12 @@ static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_ > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = { > - .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), > +static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = { > + .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -834,12 +834,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { > - .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), > +static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = { > + .entries = _adls_combo_phy_trans_dp_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { > +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = { > /* NT mV Trans mV db */ > { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */ > { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */ > @@ -853,12 +853,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_ed > { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ > }; > > -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { > - .entries = _adls_combo_phy_ddi_translations_edp_hbr2, > - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), > +static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = { > + .entries = _adls_combo_phy_trans_edp_hbr2, > + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -872,12 +872,12 @@ static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_ed > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { > - .entries = _adls_combo_phy_ddi_translations_edp_hbr3, > - .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), > +static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = { > + .entries = _adls_combo_phy_trans_edp_hbr3, > + .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hdmi[] = { > +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_hdmi[] = { > /* NT mV Trans mV db */ > { .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ > { .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ > @@ -891,13 +891,13 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hd > { .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } }, /* Full Red -3.0 */ > }; > > -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi = { > - .entries = _adlp_combo_phy_ddi_translations_hdmi, > - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi), > - .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) - 1, > +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_hdmi = { > + .entries = _adlp_combo_phy_trans_hdmi, > + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi), > + .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi) - 1, > }; > > -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -911,12 +911,12 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr = { > - .entries = _adlp_combo_phy_ddi_translations_dp_hbr, > - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr), > +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = { > + .entries = _adlp_combo_phy_trans_dp_hbr, > + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = { > /* NT mV Trans mV db */ > { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ > { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ > @@ -930,22 +930,22 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp > { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ > }; > > -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = { > - .entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3), > +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = { > + .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3), > }; > > -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_hbr3 = { > - .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), > +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = { > + .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3, > + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3), > }; > > -static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_up_to_hbr2 = { > - .entries = _icl_combo_phy_ddi_translations_edp_hbr2, > - .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), > +static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = { > + .entries = _icl_combo_phy_trans_edp_hbr2, > + .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2), > }; > > -static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = { > +static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = { > /* VS pre-emp Non-trans mV Pre-emph dB */ > { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */ > { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */ > @@ -959,12 +959,12 @@ static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_h > { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ > }; > > -static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr = { > - .entries = _adlp_dkl_phy_ddi_translations_dp_hbr, > - .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr), > +static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = { > + .entries = _adlp_dkl_phy_trans_dp_hbr, > + .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr), > }; > > -static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = { > +static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = { > /* VS pre-emp Non-trans mV Pre-emph dB */ > { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ > { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */ > @@ -978,12 +978,12 @@ static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_h > { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ > }; > > -static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3 = { > - .entries = _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, > - .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), > +static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { > + .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3, > + .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3), > }; > > -static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { > +static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { > { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ > { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ > { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ > @@ -996,13 +996,13 @@ static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { > { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ > }; > > -static const struct intel_ddi_buf_trans dg2_snps_translations = { > - .entries = _dg2_snps_translations, > - .num_entries = ARRAY_SIZE(_dg2_snps_translations), > - .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, > +static const struct intel_ddi_buf_trans dg2_snps_trans = { > + .entries = _dg2_snps_trans, > + .num_entries = ARRAY_SIZE(_dg2_snps_trans), > + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1, > }; > > -static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { > +static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { > { .snps = { 62, 0, 0 } }, /* preset 0 */ > { .snps = { 56, 0, 6 } }, /* preset 1 */ > { .snps = { 51, 0, 11 } }, /* preset 2 */ > @@ -1021,21 +1021,21 @@ static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { > { .snps = { 56, 3, 3 } }, /* preset 15 */ > }; > > -static const struct intel_ddi_buf_trans dg2_snps_translations_uhbr = { > - .entries = _dg2_snps_translations_uhbr, > - .num_entries = ARRAY_SIZE(_dg2_snps_translations_uhbr), > +static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = { > + .entries = _dg2_snps_trans_uhbr, > + .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr), > }; > > bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) > { > - return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > + return table == &tgl_combo_phy_trans_edp_hbr2_hobl; > } > > static const struct intel_ddi_buf_trans * > -intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) > +intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries) > { > - *num_entries = ddi_translations->num_entries; > - return ddi_translations; > + *num_entries = trans->num_entries; > + return trans; > } > > static const struct intel_ddi_buf_trans * > @@ -1044,11 +1044,11 @@ hsw_get_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > - return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); > + return intel_get_buf_trans(&hsw_trans_fdi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&hsw_trans_hdmi, n_entries); > else > - return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); > + return intel_get_buf_trans(&hsw_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1059,14 +1059,14 @@ bdw_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > - return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); > + return intel_get_buf_trans(&bdw_trans_fdi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&bdw_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); > + return intel_get_buf_trans(&bdw_trans_edp, n_entries); > else > - return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); > + return intel_get_buf_trans(&bdw_trans_dp, n_entries); > } > > static int skl_buf_trans_num_entries(enum port port, int n_entries) > @@ -1080,12 +1080,12 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > > static const struct intel_ddi_buf_trans * > _skl_get_buf_trans_dp(struct intel_encoder *encoder, > - const struct intel_ddi_buf_trans *ddi_translations, > + const struct intel_ddi_buf_trans *trans, > int *n_entries) > { > - ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); > + trans = intel_get_buf_trans(trans, n_entries); > *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); > - return ddi_translations; > + return trans; > } > > static const struct intel_ddi_buf_trans * > @@ -1096,12 +1096,12 @@ skl_y_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1112,12 +1112,12 @@ skl_u_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1128,12 +1128,12 @@ skl_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1144,12 +1144,12 @@ kbl_y_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1160,12 +1160,12 @@ kbl_u_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1176,12 +1176,12 @@ kbl_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&skl_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries); > else > - return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); > + return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1192,12 +1192,12 @@ bxt_get_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&bxt_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > i915->vbt.edp.low_vswing) > - return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); > + return intel_get_buf_trans(&bxt_trans_edp, n_entries); > else > - return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); > + return intel_get_buf_trans(&bxt_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1205,7 +1205,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, > n_entries); > } > > @@ -1217,10 +1217,10 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 540000) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, > n_entries); > } else if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, > n_entries); > } > > @@ -1233,7 +1233,7 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1246,10 +1246,10 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) { > - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3, > + return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3, > n_entries); > } else { > - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr, > + return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr, > n_entries); > } > } > @@ -1260,7 +1260,7 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries); > else > return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); > } > @@ -1271,9 +1271,9 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries); > + return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries); > else > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1284,12 +1284,12 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > dev_priv->vbt.edp.low_vswing) > return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > - return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries); > + return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1298,9 +1298,9 @@ jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries); > + return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries); > else > - return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries); > + return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1311,12 +1311,12 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && > dev_priv->vbt.edp.low_vswing) > return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1328,14 +1328,14 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > if (crtc_state->port_clock > 270000) { > if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > - return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, > + return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, > n_entries); > } else { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2, > + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2, > n_entries); > } > } else { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, > + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, > n_entries); > } > } > @@ -1349,13 +1349,13 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > if (crtc_state->port_clock > 540000) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, > n_entries); > } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, > n_entries); > } else if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, > n_entries); > } > > @@ -1368,7 +1368,7 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1381,10 +1381,10 @@ dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, > + return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3, > n_entries); > else > - return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, > + return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr, > n_entries); > } > > @@ -1397,13 +1397,13 @@ dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > if (crtc_state->port_clock > 540000) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, > n_entries); > else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, > n_entries); > else if (dev_priv->vbt.edp.low_vswing) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, > n_entries); > else > return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > @@ -1415,7 +1415,7 @@ dg1_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1428,9 +1428,9 @@ rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); > + return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries); > else > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); > + return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1442,13 +1442,13 @@ rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > if (crtc_state->port_clock > 540000) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, > + return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, > n_entries); > } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, > n_entries); > } else if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, > n_entries); > } > > @@ -1461,7 +1461,7 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1474,9 +1474,9 @@ adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); > + return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries); > else > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); > + return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1488,11 +1488,11 @@ adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > if (crtc_state->port_clock > 540000) > - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); > + return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries); > else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); > + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries); > else if (i915->vbt.edp.low_vswing) > - return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); > + return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries); > else > return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > @@ -1503,7 +1503,7 @@ adls_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1516,9 +1516,9 @@ adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) > - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); > + return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries); > else > - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr, n_entries); > + return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries); > } > > static const struct intel_ddi_buf_trans * > @@ -1530,13 +1530,13 @@ adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > if (crtc_state->port_clock > 540000) { > - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3, > + return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3, > n_entries); > } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, > n_entries); > } else if (dev_priv->vbt.edp.low_vswing) { > - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2, > + return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2, > n_entries); > } > > @@ -1549,7 +1549,7 @@ adlp_get_combo_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&adlp_combo_phy_trans_hdmi, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > else > @@ -1562,10 +1562,10 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) { > - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2, > + return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2, > n_entries); > } else { > - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr, > + return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr, > n_entries); > } > } > @@ -1576,7 +1576,7 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries); > else > return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); > } > @@ -1587,10 +1587,10 @@ adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 270000) { > - return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, > + return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3, > n_entries); > } else { > - return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr, > + return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr, > n_entries); > } > } > @@ -1601,7 +1601,7 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); > + return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries); > else > return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); > } > @@ -1612,9 +1612,9 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, > int *n_entries) > { > if (crtc_state->port_clock > 1000000) > - return intel_get_buf_trans(&dg2_snps_translations_uhbr, n_entries); > + return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries); > else > - return intel_get_buf_trans(&dg2_snps_translations, n_entries); > + return intel_get_buf_trans(&dg2_snps_trans, n_entries); > } > > int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > @@ -1622,17 +1622,17 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > int *default_entry) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > int n_entries; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > > - if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { > + if (drm_WARN_ON(&dev_priv->drm, !trans)) { > *default_entry = 0; > return 0; > } > > - *default_entry = ddi_translations->hdmi_default_entry; > + *default_entry = trans->hdmi_default_entry; > > return n_entries; > } > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index 2405f70d82de..3734e349f91d 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -56,12 +56,12 @@ void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > int level) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct intel_ddi_buf_trans *ddi_translations; > + const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int n_entries, ln; > > - ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) > level = n_entries - 1; > @@ -69,9 +69,9 @@ void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > for (ln = 0; ln < 4; ln++) { > u32 val = 0; > > - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); > - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); > - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.snps_vswing); > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor); > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor); > > intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); > } > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala 2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 19:17 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala ` (18 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Currently .set_signal_levels() is only used by encoders in DP mode. For most modern platforms there is no essential difference between DP and HDMI, and both codepaths just end up calling the same function under the hood. Let's get remove the need for that extra indirection by moving .set_signal_levels() into the encoder from intel_dp. Since we already plumb the crtc_state/etc. into .set_signal_levels() the code will do the right thing for both DP and HDMI. HSW/BDW/SKL are the only platforms that need a bit of care on account of having to preload the hardware buf_trans register with the full set of values. So we must still remember to call hsw_prepare_{dp,hdmi}_ddi_buffers() to do said preloading, and .set_signal_levels() will just end up selecting the correct entry for DP, and also setting up the iboost magic for both DP and HDMI. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++--- drivers/gpu/drm/i915/display/intel_ddi.c | 108 +++++++++--------- .../drm/i915/display/intel_display_types.h | 5 +- .../drm/i915/display/intel_dp_link_training.c | 5 +- 4 files changed, 75 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 8e0620ae2ed1..e348f075a41d 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -813,10 +813,10 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) return DP_TRAIN_PRE_EMPH_LEVEL_3; } -static void vlv_set_signal_levels(struct intel_dp *intel_dp, +static void vlv_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); unsigned long demph_reg_value, preemph_reg_value, uniqtranscale_reg_value; u8 train_set = intel_dp->train_set[0]; @@ -899,10 +899,10 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp, uniqtranscale_reg_value, 0); } -static void chv_set_signal_levels(struct intel_dp *intel_dp, +static void chv_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 deemph_reg_value, margin_reg_value; bool uniq_trans_scale = false; u8 train_set = intel_dp->train_set[0]; @@ -1020,10 +1020,11 @@ static u32 g4x_signal_levels(u8 train_set) } static void -g4x_set_signal_levels(struct intel_dp *intel_dp, +g4x_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u8 train_set = intel_dp->train_set[0]; u32 signal_levels; @@ -1067,10 +1068,11 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set) } static void -snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, +snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u8 train_set = intel_dp->train_set[0]; u32 signal_levels; @@ -1118,10 +1120,11 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set) } static void -ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, +ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u8 train_set = intel_dp->train_set[0]; u32 signal_levels; @@ -1364,15 +1367,15 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, dig_port->dp.set_link_train = g4x_set_link_train; if (IS_CHERRYVIEW(dev_priv)) - dig_port->dp.set_signal_levels = chv_set_signal_levels; + intel_encoder->set_signal_levels = chv_set_signal_levels; else if (IS_VALLEYVIEW(dev_priv)) - dig_port->dp.set_signal_levels = vlv_set_signal_levels; + intel_encoder->set_signal_levels = vlv_set_signal_levels; else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) - dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; + intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) - dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; + intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; else - dig_port->dp.set_signal_levels = g4x_set_signal_levels; + intel_encoder->set_signal_levels = g4x_set_signal_levels; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 39bacef87ef2..4a22dcde66d9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -129,10 +129,10 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, * HDMI/DVI use cases. */ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int level = intel_ddi_hdmi_level(encoder, crtc_state); u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; @@ -1395,8 +1395,7 @@ static int translate_signal_level(struct intel_dp *intel_dp, return 0; } -static int intel_ddi_dp_level(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static int intel_ddi_dp_level(struct intel_dp *intel_dp) { u8 train_set = intel_dp->train_set[0]; u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | @@ -1405,56 +1404,68 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp, return translate_signal_level(intel_dp, signal_levels); } +static int intel_ddi_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return intel_ddi_hdmi_level(encoder, crtc_state); + else + return intel_ddi_dp_level(enc_to_intel_dp(encoder)); +} + static void -dg2_set_signal_levels(struct intel_dp *intel_dp, +dg2_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp, crtc_state); + int level = intel_ddi_level(encoder, crtc_state); intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); } static void -tgl_set_signal_levels(struct intel_dp *intel_dp, +tgl_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp, crtc_state); + int level = intel_ddi_level(encoder, crtc_state); tgl_ddi_vswing_sequence(encoder, crtc_state, level); } static void -icl_set_signal_levels(struct intel_dp *intel_dp, +icl_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp, crtc_state); + int level = intel_ddi_level(encoder, crtc_state); icl_ddi_vswing_sequence(encoder, crtc_state, level); } static void -bxt_set_signal_levels(struct intel_dp *intel_dp, +bxt_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp, crtc_state); + int level = intel_ddi_level(encoder, crtc_state); bxt_ddi_vswing_sequence(encoder, crtc_state, level); } static void -hsw_set_signal_levels(struct intel_dp *intel_dp, +hsw_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_dp_level(intel_dp, crtc_state); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + int level = intel_ddi_level(encoder, crtc_state); enum port port = encoder->port; u32 signal_levels; + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) + skl_ddi_set_iboost(encoder, crtc_state, level); + + /* HDMI ignores the rest */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return; + signal_levels = DDI_BUF_TRANS_SELECT(level); drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", @@ -1463,9 +1474,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, intel_dp->DP &= ~DDI_BUF_EMP_MASK; intel_dp->DP |= signal_levels; - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - skl_ddi_set_iboost(encoder, crtc_state, level); - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); } @@ -2357,7 +2365,6 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp, crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); @@ -2417,7 +2424,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, */ /* 5.e Configure voltage swing and related IO settings */ - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); + encoder->set_signal_levels(encoder, crtc_state); /* * 5.f Configure and enable DDI_BUF_CTL @@ -2471,7 +2478,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp, crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, @@ -2546,7 +2552,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ /* 7.e Configure voltage swing and related IO settings */ - tgl_ddi_vswing_sequence(encoder, crtc_state, level); + encoder->set_signal_levels(encoder, crtc_state); /* * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up @@ -2614,7 +2620,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp, crtc_state); if (DISPLAY_VER(dev_priv) < 11) drm_WARN_ON(&dev_priv->drm, @@ -2639,13 +2644,12 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, icl_program_mg_dp_mode(dig_port, crtc_state); - if (DISPLAY_VER(dev_priv) >= 11) - icl_ddi_vswing_sequence(encoder, crtc_state, level); - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - bxt_ddi_vswing_sequence(encoder, crtc_state, level); - else + if ((DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) hsw_prepare_dp_ddi_buffers(encoder, crtc_state); + encoder->set_signal_levels(encoder, crtc_state); + intel_ddi_power_up_lanes(encoder, crtc_state); intel_ddi_init_dp_buf_reg(encoder, crtc_state); @@ -3074,7 +3078,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; - int level = intel_ddi_hdmi_level(encoder, crtc_state); enum port port = encoder->port; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, @@ -3084,19 +3087,11 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); - if (IS_DG2(dev_priv)) - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); - else if (DISPLAY_VER(dev_priv) >= 12) - tgl_ddi_vswing_sequence(encoder, crtc_state, level); - else if (DISPLAY_VER(dev_priv) == 11) - icl_ddi_vswing_sequence(encoder, crtc_state, level); - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - bxt_ddi_vswing_sequence(encoder, crtc_state, level); - else - hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level); + if ((DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - skl_ddi_set_iboost(encoder, crtc_state, level); + encoder->set_signal_levels(encoder, crtc_state); /* Display WA #1143: skl,kbl,cfl */ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { @@ -4047,7 +4042,6 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { static struct intel_connector * intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct intel_connector *connector; enum port port = dig_port->base.port; @@ -4060,17 +4054,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) dig_port->dp.set_link_train = intel_ddi_set_link_train; dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; - if (IS_DG2(dev_priv)) - dig_port->dp.set_signal_levels = dg2_set_signal_levels; - else if (DISPLAY_VER(dev_priv) >= 12) - dig_port->dp.set_signal_levels = tgl_set_signal_levels; - else if (DISPLAY_VER(dev_priv) >= 11) - dig_port->dp.set_signal_levels = icl_set_signal_levels; - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - dig_port->dp.set_signal_levels = bxt_set_signal_levels; - else - dig_port->dp.set_signal_levels = hsw_set_signal_levels; - dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; @@ -4642,6 +4625,17 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->get_config = hsw_ddi_get_config; } + if (IS_DG2(dev_priv)) + encoder->set_signal_levels = dg2_set_signal_levels; + else if (DISPLAY_VER(dev_priv) >= 12) + encoder->set_signal_levels = tgl_set_signal_levels; + else if (DISPLAY_VER(dev_priv) >= 11) + encoder->set_signal_levels = icl_set_signal_levels; + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + encoder->set_signal_levels = bxt_set_signal_levels; + else + encoder->set_signal_levels = hsw_set_signal_levels; + intel_ddi_buf_trans_init(encoder); if (DISPLAY_VER(dev_priv) >= 13) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9413ebae15f5..44e4eaa1ed8d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -269,6 +269,9 @@ struct intel_encoder { const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries); + void (*set_signal_levels)(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); + enum hpd_pin hpd_pin; enum intel_display_power_domain power_domain; /* for communication with audio component; protected by av_mutex */ @@ -1601,8 +1604,6 @@ struct intel_dp { u8 dp_train_pat); void (*set_idle_link_train)(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); - void (*set_signal_levels)(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); u8 (*preemph_max)(struct intel_dp *intel_dp); u8 (*voltage_max)(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4f116cd32846..d52929855cd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -398,7 +398,8 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u8 train_set = intel_dp->train_set[0]; char phy_name[10]; @@ -412,7 +413,7 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) - intel_dp->set_signal_levels(intel_dp, crtc_state); + encoder->set_signal_levels(encoder, crtc_state); } static bool -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() 2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala @ 2021-09-29 19:17 ` Imre Deak 2021-09-30 7:33 ` Ville Syrjälä 0 siblings, 1 reply; 36+ messages in thread From: Imre Deak @ 2021-09-29 19:17 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:48PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Currently .set_signal_levels() is only used by encoders in DP mode. > For most modern platforms there is no essential difference between > DP and HDMI, and both codepaths just end up calling the same function > under the hood. Let's get remove the need for that extra indirection > by moving .set_signal_levels() into the encoder from intel_dp. > Since we already plumb the crtc_state/etc. into .set_signal_levels() > the code will do the right thing for both DP and HDMI. I wondered about the rational to add vfuncs to intel_digital_port or intel_encoder, I assume the latter needs less type casting. > HSW/BDW/SKL are the only platforms that need a bit of care on > account of having to preload the hardware buf_trans register > with the full set of values. So we must still remember to call > hsw_prepare_{dp,hdmi}_ddi_buffers() to do said preloading, and > .set_signal_levels() will just end up selecting the correct entry > for DP, and also setting up the iboost magic for both DP and HDMI. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++--- > drivers/gpu/drm/i915/display/intel_ddi.c | 108 +++++++++--------- > .../drm/i915/display/intel_display_types.h | 5 +- > .../drm/i915/display/intel_dp_link_training.c | 5 +- > 4 files changed, 75 insertions(+), 76 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c > index 8e0620ae2ed1..e348f075a41d 100644 > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > @@ -813,10 +813,10 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) > return DP_TRAIN_PRE_EMPH_LEVEL_3; > } > > -static void vlv_set_signal_levels(struct intel_dp *intel_dp, > +static void vlv_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > unsigned long demph_reg_value, preemph_reg_value, > uniqtranscale_reg_value; > u8 train_set = intel_dp->train_set[0]; > @@ -899,10 +899,10 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp, > uniqtranscale_reg_value, 0); > } > > -static void chv_set_signal_levels(struct intel_dp *intel_dp, > +static void chv_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > u32 deemph_reg_value, margin_reg_value; > bool uniq_trans_scale = false; > u8 train_set = intel_dp->train_set[0]; > @@ -1020,10 +1020,11 @@ static u32 g4x_signal_levels(u8 train_set) > } > > static void > -g4x_set_signal_levels(struct intel_dp *intel_dp, > +g4x_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > u8 train_set = intel_dp->train_set[0]; > u32 signal_levels; > > @@ -1067,10 +1068,11 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set) > } > > static void > -snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, > +snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > u8 train_set = intel_dp->train_set[0]; > u32 signal_levels; > > @@ -1118,10 +1120,11 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set) > } > > static void > -ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, > +ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > u8 train_set = intel_dp->train_set[0]; > u32 signal_levels; > > @@ -1364,15 +1367,15 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, > dig_port->dp.set_link_train = g4x_set_link_train; > > if (IS_CHERRYVIEW(dev_priv)) > - dig_port->dp.set_signal_levels = chv_set_signal_levels; > + intel_encoder->set_signal_levels = chv_set_signal_levels; > else if (IS_VALLEYVIEW(dev_priv)) > - dig_port->dp.set_signal_levels = vlv_set_signal_levels; > + intel_encoder->set_signal_levels = vlv_set_signal_levels; I suppose vlv,chv hdmi encoders could also use these, but that'd need deciphering the hard-coded values there. > else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) > - dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; > + intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; > else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) > - dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; > + intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; > else > - dig_port->dp.set_signal_levels = g4x_set_signal_levels; > + intel_encoder->set_signal_levels = g4x_set_signal_levels; > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || > (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 39bacef87ef2..4a22dcde66d9 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -129,10 +129,10 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > * HDMI/DVI use cases. > */ > static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + int level = intel_ddi_hdmi_level(encoder, crtc_state); > u32 iboost_bit = 0; > int n_entries; > enum port port = encoder->port; > @@ -1395,8 +1395,7 @@ static int translate_signal_level(struct intel_dp *intel_dp, > return 0; > } > > -static int intel_ddi_dp_level(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state) > +static int intel_ddi_dp_level(struct intel_dp *intel_dp) > { > u8 train_set = intel_dp->train_set[0]; > u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | > @@ -1405,56 +1404,68 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp, > return translate_signal_level(intel_dp, signal_levels); > } > > +static int intel_ddi_level(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return intel_ddi_hdmi_level(encoder, crtc_state); > + else > + return intel_ddi_dp_level(enc_to_intel_dp(encoder)); > +} > + > static void > -dg2_set_signal_levels(struct intel_dp *intel_dp, > +dg2_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state); > > intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > } > > static void > -tgl_set_signal_levels(struct intel_dp *intel_dp, > +tgl_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state); > > tgl_ddi_vswing_sequence(encoder, crtc_state, level); > } > > static void > -icl_set_signal_levels(struct intel_dp *intel_dp, > +icl_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state); > > icl_ddi_vswing_sequence(encoder, crtc_state, level); > } > > static void > -bxt_set_signal_levels(struct intel_dp *intel_dp, > +bxt_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state); > > bxt_ddi_vswing_sequence(encoder, crtc_state, level); > } > > static void > -hsw_set_signal_levels(struct intel_dp *intel_dp, > +hsw_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + int level = intel_ddi_level(encoder, crtc_state); > enum port port = encoder->port; > u32 signal_levels; > > + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) > + skl_ddi_set_iboost(encoder, crtc_state, level); > + > + /* HDMI ignores the rest */ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return; > + > signal_levels = DDI_BUF_TRANS_SELECT(level); > > drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", > @@ -1463,9 +1474,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, > intel_dp->DP &= ~DDI_BUF_EMP_MASK; > intel_dp->DP |= signal_levels; > > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) > - skl_ddi_set_iboost(encoder, crtc_state, level); > - > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > } > @@ -2357,7 +2365,6 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > > intel_dp_set_link_params(intel_dp, crtc_state->port_clock, > crtc_state->lane_count); > @@ -2417,7 +2424,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, > */ > > /* 5.e Configure voltage swing and related IO settings */ > - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > + encoder->set_signal_levels(encoder, crtc_state); > > /* > * 5.f Configure and enable DDI_BUF_CTL > @@ -2471,7 +2478,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > > intel_dp_set_link_params(intel_dp, > crtc_state->port_clock, > @@ -2546,7 +2552,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > */ > > /* 7.e Configure voltage swing and related IO settings */ > - tgl_ddi_vswing_sequence(encoder, crtc_state, level); > + encoder->set_signal_levels(encoder, crtc_state); > > /* > * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up > @@ -2614,7 +2620,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp, crtc_state); > > if (DISPLAY_VER(dev_priv) < 11) > drm_WARN_ON(&dev_priv->drm, > @@ -2639,13 +2644,12 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > > icl_program_mg_dp_mode(dig_port, crtc_state); > > - if (DISPLAY_VER(dev_priv) >= 11) > - icl_ddi_vswing_sequence(encoder, crtc_state, level); > - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > - bxt_ddi_vswing_sequence(encoder, crtc_state, level); > - else > + if ((DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) || > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) Could be DISPLAY_VER <= 9 && !IS_BXT ? > hsw_prepare_dp_ddi_buffers(encoder, crtc_state); > > + encoder->set_signal_levels(encoder, crtc_state); hsw_set_signal_levels() wasn't called before, but writing DDI_BUF_CTL w/o enabling it is ok I think. Maybe it's worth zeroing intel_dp->train_set already in intel_dp_set_link_params()? > + > intel_ddi_power_up_lanes(encoder, crtc_state); > > intel_ddi_init_dp_buf_reg(encoder, crtc_state); > @@ -3074,7 +3078,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_connector *connector = conn_state->connector; > - int level = intel_ddi_hdmi_level(encoder, crtc_state); > enum port port = encoder->port; > > if (!intel_hdmi_handle_sink_scrambling(encoder, connector, > @@ -3084,19 +3087,11 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, > "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", > connector->base.id, connector->name); > > - if (IS_DG2(dev_priv)) > - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > - else if (DISPLAY_VER(dev_priv) >= 12) > - tgl_ddi_vswing_sequence(encoder, crtc_state, level); > - else if (DISPLAY_VER(dev_priv) == 11) > - icl_ddi_vswing_sequence(encoder, crtc_state, level); > - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > - bxt_ddi_vswing_sequence(encoder, crtc_state, level); > - else > - hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level); > + if ((DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) || > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) Here too could be DISPLAY_VER<=9 && !BXT. Regardless of the above nits, the patch looks ok: Reviewed-by: Imre Deak <imre.deak@intel.com> > + hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); > > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) > - skl_ddi_set_iboost(encoder, crtc_state, level); > + encoder->set_signal_levels(encoder, crtc_state); > > /* Display WA #1143: skl,kbl,cfl */ > if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { > @@ -4047,7 +4042,6 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { > static struct intel_connector * > intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > struct intel_connector *connector; > enum port port = dig_port->base.port; > > @@ -4060,17 +4054,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) > dig_port->dp.set_link_train = intel_ddi_set_link_train; > dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; > > - if (IS_DG2(dev_priv)) > - dig_port->dp.set_signal_levels = dg2_set_signal_levels; > - else if (DISPLAY_VER(dev_priv) >= 12) > - dig_port->dp.set_signal_levels = tgl_set_signal_levels; > - else if (DISPLAY_VER(dev_priv) >= 11) > - dig_port->dp.set_signal_levels = icl_set_signal_levels; > - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > - dig_port->dp.set_signal_levels = bxt_set_signal_levels; > - else > - dig_port->dp.set_signal_levels = hsw_set_signal_levels; > - > dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; > dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; > > @@ -4642,6 +4625,17 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > encoder->get_config = hsw_ddi_get_config; > } > > + if (IS_DG2(dev_priv)) > + encoder->set_signal_levels = dg2_set_signal_levels; > + else if (DISPLAY_VER(dev_priv) >= 12) > + encoder->set_signal_levels = tgl_set_signal_levels; > + else if (DISPLAY_VER(dev_priv) >= 11) > + encoder->set_signal_levels = icl_set_signal_levels; > + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > + encoder->set_signal_levels = bxt_set_signal_levels; > + else > + encoder->set_signal_levels = hsw_set_signal_levels; > + > intel_ddi_buf_trans_init(encoder); > > if (DISPLAY_VER(dev_priv) >= 13) > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 9413ebae15f5..44e4eaa1ed8d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -269,6 +269,9 @@ struct intel_encoder { > const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries); > + void (*set_signal_levels)(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > + > enum hpd_pin hpd_pin; > enum intel_display_power_domain power_domain; > /* for communication with audio component; protected by av_mutex */ > @@ -1601,8 +1604,6 @@ struct intel_dp { > u8 dp_train_pat); > void (*set_idle_link_train)(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state); > - void (*set_signal_levels)(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state); > > u8 (*preemph_max)(struct intel_dp *intel_dp); > u8 (*voltage_max)(struct intel_dp *intel_dp, > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 4f116cd32846..d52929855cd0 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -398,7 +398,8 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state, > enum drm_dp_phy dp_phy) > { > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u8 train_set = intel_dp->train_set[0]; > char phy_name[10]; > > @@ -412,7 +413,7 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, > intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); > > if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) > - intel_dp->set_signal_levels(intel_dp, crtc_state); > + encoder->set_signal_levels(encoder, crtc_state); > } > > static bool > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() 2021-09-29 19:17 ` Imre Deak @ 2021-09-30 7:33 ` Ville Syrjälä 0 siblings, 0 replies; 36+ messages in thread From: Ville Syrjälä @ 2021-09-30 7:33 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Wed, Sep 29, 2021 at 10:17:52PM +0300, Imre Deak wrote: > On Mon, Sep 27, 2021 at 09:24:48PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Currently .set_signal_levels() is only used by encoders in DP mode. > > For most modern platforms there is no essential difference between > > DP and HDMI, and both codepaths just end up calling the same function > > under the hood. Let's get remove the need for that extra indirection > > by moving .set_signal_levels() into the encoder from intel_dp. > > Since we already plumb the crtc_state/etc. into .set_signal_levels() > > the code will do the right thing for both DP and HDMI. > > I wondered about the rational to add vfuncs to intel_digital_port or > intel_encoder, I assume the latter needs less type casting. I guess it's mostly been "do these make sense outside of HDMI/DP?". But considering those are all mostly what's left it's becoming less importnat perhaps. I was actually pondering if we migth split these up in to a few different sets of vfuncs. So and encoder could have pointers to phy_funcs, hpd_funcs, clock_funcs, etc. > > > HSW/BDW/SKL are the only platforms that need a bit of care on > > account of having to preload the hardware buf_trans register > > with the full set of values. So we must still remember to call > > hsw_prepare_{dp,hdmi}_ddi_buffers() to do said preloading, and > > .set_signal_levels() will just end up selecting the correct entry > > for DP, and also setting up the iboost magic for both DP and HDMI. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++--- > > drivers/gpu/drm/i915/display/intel_ddi.c | 108 +++++++++--------- > > .../drm/i915/display/intel_display_types.h | 5 +- > > .../drm/i915/display/intel_dp_link_training.c | 5 +- > > 4 files changed, 75 insertions(+), 76 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c > > index 8e0620ae2ed1..e348f075a41d 100644 > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c <snip> > > @@ -1364,15 +1367,15 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, > > dig_port->dp.set_link_train = g4x_set_link_train; > > > > if (IS_CHERRYVIEW(dev_priv)) > > - dig_port->dp.set_signal_levels = chv_set_signal_levels; > > + intel_encoder->set_signal_levels = chv_set_signal_levels; > > else if (IS_VALLEYVIEW(dev_priv)) > > - dig_port->dp.set_signal_levels = vlv_set_signal_levels; > > + intel_encoder->set_signal_levels = vlv_set_signal_levels; > > I suppose vlv,chv hdmi encoders could also use these, but that'd need deciphering > the hard-coded values there. My current plan is to extrct a buf_trans struct for each, and for now I just populate an array of those and pass the array to the phy code. In the future we might want to unify these with the rest of the buf_trans infrastructure. I was also pondering if we should just move the set_signal_level() funcs from intel_ddi.c to some phy specific files entirely. And could perhaps also move the related buf_trans tables there as well... > > > else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) > > - dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; > > + intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; > > else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) > > - dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; > > + intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; > > else > > - dig_port->dp.set_signal_levels = g4x_set_signal_levels; > > + intel_encoder->set_signal_levels = g4x_set_signal_levels; > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || > > (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 39bacef87ef2..4a22dcde66d9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c <snip> > > @@ -2639,13 +2644,12 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > > > > icl_program_mg_dp_mode(dig_port, crtc_state); > > > > - if (DISPLAY_VER(dev_priv) >= 11) > > - icl_ddi_vswing_sequence(encoder, crtc_state, level); > > - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > > - bxt_ddi_vswing_sequence(encoder, crtc_state, level); > > - else > > + if ((DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) || > > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > > Could be DISPLAY_VER <= 9 && !IS_BXT ? I guess I've become a bit partial to listing things a bit more explicitly. But I must admit that this is a bit ugly in my proposed form. So changing it might be a good idea. > > > hsw_prepare_dp_ddi_buffers(encoder, crtc_state); > > > > + encoder->set_signal_levels(encoder, crtc_state); > > hsw_set_signal_levels() wasn't called before, but writing DDI_BUF_CTL > w/o enabling it is ok I think. Ah right. Hmm. We haven't yet called intel_ddi_init_dp_buf_reg() so this might go a bit wrong actually. So I think I need to reorder the calls a bit and nuke the DDI_BUF_CTL_ENABLE from intel_ddi_init_dp_buf_reg(). intel_ddi_prepare_link_retrain() already sets that bit so it should kick in properly during link training. But I'll have to double check the full flow to make sure I uderstand the order of things. > Maybe it's worth zeroing > intel_dp->train_set already in intel_dp_set_link_params()? I had a patch for that, but for some reason discarded it as "not needed". But now that I think about it again we should in fact do it because currently we only clear these at the start of training a link segment, and what we leave in there at the end will be the DPRX values. So the next modeset might do the initial set_signal_levels() with stale values that don't even make sense for our PHY (eg. if we had a case of LTTPR supporting vswing/preemph 3 and our PHY not supporting those). And considering we'll switch to vswing/preemph 0 anyway at the start of the link training might as well program the PHY accordingly from the start. If we wanted to optimize things and reuse the values from the last succesful link training I think we'd also have to store these separately for LTTPRs, and we'd have to adjust the link training code to not zero the stuff (unless there was a long hpd/etc.). -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala 2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala 2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 19:43 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala ` (17 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Now that .set_signal_levels() is used for HDMI as well, we can remove the extra level of indirection and just plug the correct stuff straight into .set_signal_levels(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 119 +++++------------- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 7 +- drivers/gpu/drm/i915/display/intel_snps_phy.h | 5 +- 4 files changed, 39 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4a22dcde66d9..62ab57c391ef 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -995,11 +995,11 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); } -static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) +static void bxt_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int level = intel_ddi_level(encoder, crtc_state); const struct intel_ddi_buf_trans *trans; enum port port = encoder->port; int n_entries; @@ -1047,10 +1047,10 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) } static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int level = intel_ddi_level(encoder, crtc_state); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; @@ -1109,9 +1109,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); } -static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) +static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); @@ -1162,7 +1161,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(encoder, crtc_state, level); + icl_ddi_combo_vswing_program(encoder, crtc_state); /* 6. Set training enable to trigger update */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); @@ -1170,12 +1169,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); } -static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) +static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); + int level = intel_ddi_level(encoder, crtc_state); const struct intel_ddi_buf_trans *trans; int n_entries, ln; u32 val; @@ -1293,26 +1292,12 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, } } -static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - if (intel_phy_is_combo(dev_priv, phy)) - icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); - else - icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); -} - -static void -tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) +static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); + int level = intel_ddi_level(encoder, crtc_state); const struct intel_ddi_buf_trans *trans; u32 val, dpcnt_mask, dpcnt_val; int n_entries, ln; @@ -1364,19 +1349,6 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, } } -static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - if (intel_phy_is_combo(dev_priv, phy)) - icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); - else - tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); -} - static int translate_signal_level(struct intel_dp *intel_dp, u8 signal_levels) { @@ -1404,8 +1376,8 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) return translate_signal_level(intel_dp, signal_levels); } -static int intel_ddi_level(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +int intel_ddi_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return intel_ddi_hdmi_level(encoder, crtc_state); @@ -1413,42 +1385,6 @@ static int intel_ddi_level(struct intel_encoder *encoder, return intel_ddi_dp_level(enc_to_intel_dp(encoder)); } -static void -dg2_set_signal_levels(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - int level = intel_ddi_level(encoder, crtc_state); - - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); -} - -static void -tgl_set_signal_levels(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - int level = intel_ddi_level(encoder, crtc_state); - - tgl_ddi_vswing_sequence(encoder, crtc_state, level); -} - -static void -icl_set_signal_levels(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - int level = intel_ddi_level(encoder, crtc_state); - - icl_ddi_vswing_sequence(encoder, crtc_state, level); -} - -static void -bxt_set_signal_levels(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - int level = intel_ddi_level(encoder, crtc_state); - - bxt_ddi_vswing_sequence(encoder, crtc_state, level); -} - static void hsw_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) @@ -4625,16 +4561,23 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->get_config = hsw_ddi_get_config; } - if (IS_DG2(dev_priv)) - encoder->set_signal_levels = dg2_set_signal_levels; - else if (DISPLAY_VER(dev_priv) >= 12) - encoder->set_signal_levels = tgl_set_signal_levels; - else if (DISPLAY_VER(dev_priv) >= 11) - encoder->set_signal_levels = icl_set_signal_levels; - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (IS_DG2(dev_priv)) { + encoder->set_signal_levels = intel_snps_phy_set_signal_levels; + } else if (DISPLAY_VER(dev_priv) >= 12) { + if (intel_phy_is_combo(dev_priv, phy)) + encoder->set_signal_levels = icl_combo_phy_set_signal_levels; + else + encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; + } else if (DISPLAY_VER(dev_priv) >= 11) { + if (intel_phy_is_combo(dev_priv, phy)) + encoder->set_signal_levels = icl_combo_phy_set_signal_levels; + else + encoder->set_signal_levels = icl_mg_phy_set_signal_levels; + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { encoder->set_signal_levels = bxt_set_signal_levels; - else + } else { encoder->set_signal_levels = hsw_set_signal_levels; + } intel_ddi_buf_trans_init(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 7d448485d887..d6947c06a455 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -59,13 +59,11 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, bool state); void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, struct intel_crtc_state *crtc_state); -u32 bxt_signal_levels(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); -u32 ddi_signal_levels(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, enum transcoder cpu_transcoder, bool enable, u32 hdcp_mask); void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); +int intel_ddi_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DDI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 3734e349f91d..f59cc320ce9c 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -5,6 +5,7 @@ #include <linux/util_macros.h> +#include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" @@ -51,13 +52,13 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); } -void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level) +void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + int level = intel_ddi_level(encoder, crtc_state); int n_entries, ln; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index a68547a6fee5..11dcd6deb070 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -29,8 +29,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state); int intel_snps_phy_check_hdmi_link_rate(int clock); -void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int level); +void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_SNPS_PHY_H__ */ -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers 2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala @ 2021-09-29 19:43 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 19:43 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:49PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Now that .set_signal_levels() is used for HDMI as well, we can > remove the extra level of indirection and just plug the correct > stuff straight into .set_signal_levels(). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 119 +++++------------- > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 7 +- > drivers/gpu/drm/i915/display/intel_snps_phy.h | 5 +- > 4 files changed, 39 insertions(+), 98 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 4a22dcde66d9..62ab57c391ef 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -995,11 +995,11 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); > } > > -static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > +static void bxt_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + int level = intel_ddi_level(encoder, crtc_state); > const struct intel_ddi_buf_trans *trans; > enum port port = encoder->port; > int n_entries; > @@ -1047,10 +1047,10 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) > } > > static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + int level = intel_ddi_level(encoder, crtc_state); > const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int n_entries, ln; > @@ -1109,9 +1109,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); > } > > -static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > +static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > @@ -1162,7 +1161,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > > /* 5. Program swing and de-emphasis */ > - icl_ddi_combo_vswing_program(encoder, crtc_state, level); > + icl_ddi_combo_vswing_program(encoder, crtc_state); > > /* 6. Set training enable to trigger update */ > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); > @@ -1170,12 +1169,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > } > > -static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > +static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > + int level = intel_ddi_level(encoder, crtc_state); > const struct intel_ddi_buf_trans *trans; > int n_entries, ln; > u32 val; > @@ -1293,26 +1292,12 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > } > } > > -static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > - > - if (intel_phy_is_combo(dev_priv, phy)) > - icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); > - else > - icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > -static void > -tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > +static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > + int level = intel_ddi_level(encoder, crtc_state); > const struct intel_ddi_buf_trans *trans; > u32 val, dpcnt_mask, dpcnt_val; > int n_entries, ln; > @@ -1364,19 +1349,6 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > } > } > > -static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > - > - if (intel_phy_is_combo(dev_priv, phy)) > - icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); > - else > - tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > static int translate_signal_level(struct intel_dp *intel_dp, > u8 signal_levels) > { > @@ -1404,8 +1376,8 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) > return translate_signal_level(intel_dp, signal_levels); > } > > -static int intel_ddi_level(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > +int intel_ddi_level(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > return intel_ddi_hdmi_level(encoder, crtc_state); > @@ -1413,42 +1385,6 @@ static int intel_ddi_level(struct intel_encoder *encoder, > return intel_ddi_dp_level(enc_to_intel_dp(encoder)); > } > > -static void > -dg2_set_signal_levels(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - int level = intel_ddi_level(encoder, crtc_state); > - > - intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > -static void > -tgl_set_signal_levels(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - int level = intel_ddi_level(encoder, crtc_state); > - > - tgl_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > -static void > -icl_set_signal_levels(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - int level = intel_ddi_level(encoder, crtc_state); > - > - icl_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > -static void > -bxt_set_signal_levels(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - int level = intel_ddi_level(encoder, crtc_state); > - > - bxt_ddi_vswing_sequence(encoder, crtc_state, level); > -} > - > static void > hsw_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > @@ -4625,16 +4561,23 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > encoder->get_config = hsw_ddi_get_config; > } > > - if (IS_DG2(dev_priv)) > - encoder->set_signal_levels = dg2_set_signal_levels; > - else if (DISPLAY_VER(dev_priv) >= 12) > - encoder->set_signal_levels = tgl_set_signal_levels; > - else if (DISPLAY_VER(dev_priv) >= 11) > - encoder->set_signal_levels = icl_set_signal_levels; > - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > + if (IS_DG2(dev_priv)) { > + encoder->set_signal_levels = intel_snps_phy_set_signal_levels; > + } else if (DISPLAY_VER(dev_priv) >= 12) { > + if (intel_phy_is_combo(dev_priv, phy)) > + encoder->set_signal_levels = icl_combo_phy_set_signal_levels; > + else > + encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; > + } else if (DISPLAY_VER(dev_priv) >= 11) { > + if (intel_phy_is_combo(dev_priv, phy)) > + encoder->set_signal_levels = icl_combo_phy_set_signal_levels; > + else > + encoder->set_signal_levels = icl_mg_phy_set_signal_levels; > + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > encoder->set_signal_levels = bxt_set_signal_levels; > - else > + } else { > encoder->set_signal_levels = hsw_set_signal_levels; > + } > > intel_ddi_buf_trans_init(encoder); > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h > index 7d448485d887..d6947c06a455 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h > @@ -59,13 +59,11 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, > bool state); > void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, > struct intel_crtc_state *crtc_state); > -u32 bxt_signal_levels(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state); > -u32 ddi_signal_levels(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state); > int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, > enum transcoder cpu_transcoder, > bool enable, u32 hdcp_mask); > void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); > +int intel_ddi_level(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_DDI_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index 3734e349f91d..f59cc320ce9c 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -5,6 +5,7 @@ > > #include <linux/util_macros.h> > > +#include "intel_ddi.h" > #include "intel_ddi_buf_trans.h" > #include "intel_de.h" > #include "intel_display_types.h" > @@ -51,13 +52,13 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, > SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); > } > > -void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level) > +void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > + int level = intel_ddi_level(encoder, crtc_state); > int n_entries, ln; > > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h > index a68547a6fee5..11dcd6deb070 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h > @@ -29,8 +29,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, > const struct intel_mpllb_state *pll_state); > > int intel_snps_phy_check_hdmi_link_rate(int clock); > -void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int level); > +void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_SNPS_PHY_H__ */ > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (2 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 19:48 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala ` (16 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Convert bxt_ddi_phy_set_signal_levels() to act as the full .set_signal_levels() hook instead of going through a pointless wrapper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 24 +-------------- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 30 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dpio_phy.h | 5 ++-- 3 files changed, 24 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 62ab57c391ef..970a796a4f52 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -995,28 +995,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); } -static void bxt_set_signal_levels(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_level(encoder, crtc_state); - const struct intel_ddi_buf_trans *trans; - enum port port = encoder->port; - int n_entries; - - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) - return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; - - bxt_ddi_phy_set_signal_level(dev_priv, port, - trans->entries[level].bxt.margin, - trans->entries[level].bxt.scale, - trans->entries[level].bxt.enable, - trans->entries[level].bxt.deemphasis); -} - static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -4574,7 +4552,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) else encoder->set_signal_levels = icl_mg_phy_set_signal_levels; } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - encoder->set_signal_levels = bxt_set_signal_levels; + encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; } else { encoder->set_signal_levels = hsw_set_signal_levels; } diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 48507ed79950..4d604e4cfa5d 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -23,6 +23,8 @@ #include "display/intel_dp.h" +#include "intel_ddi.h" +#include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dpio_phy.h" @@ -266,15 +268,24 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, *ch = DPIO_CH0; } -void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, - enum port port, u32 margin, u32 scale, - u32 enable, u32 deemphasis) +void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { - u32 val; - enum dpio_phy phy; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int level = intel_ddi_level(encoder, crtc_state); + const struct intel_ddi_buf_trans *trans; enum dpio_channel ch; + enum dpio_phy phy; + int n_entries; + u32 val; - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + return; + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) + level = n_entries - 1; + + bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); /* * While we write to the group register to program all lanes at once we @@ -286,12 +297,13 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); - val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; + val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT | + trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT; intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); val &= ~SCALE_DCOMP_METHOD; - if (enable) + if (trans->entries[level].bxt.enable) val |= SCALE_DCOMP_METHOD; if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) @@ -302,7 +314,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); val &= ~DE_EMPHASIS; - val |= deemphasis << DEEMPH_SHIFT; + val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT; intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h index 6473440e7457..9c3d008e8e1a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h @@ -17,9 +17,8 @@ struct intel_encoder; void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, enum dpio_phy *phy, enum dpio_channel *ch); -void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, - enum port port, u32 margin, u32 scale, - u32 enable, u32 deemphasis); +void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala @ 2021-09-29 19:48 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 19:48 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:50PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Convert bxt_ddi_phy_set_signal_levels() to act as the full > .set_signal_levels() hook instead of going through a pointless wrapper. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 24 +-------------- > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 30 +++++++++++++------ > drivers/gpu/drm/i915/display/intel_dpio_phy.h | 5 ++-- > 3 files changed, 24 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 62ab57c391ef..970a796a4f52 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -995,28 +995,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); > } > > -static void bxt_set_signal_levels(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_level(encoder, crtc_state); > - const struct intel_ddi_buf_trans *trans; > - enum port port = encoder->port; > - int n_entries; > - > - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > - return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > - > - bxt_ddi_phy_set_signal_level(dev_priv, port, > - trans->entries[level].bxt.margin, > - trans->entries[level].bxt.scale, > - trans->entries[level].bxt.enable, > - trans->entries[level].bxt.deemphasis); > -} > - > static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > @@ -4574,7 +4552,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > else > encoder->set_signal_levels = icl_mg_phy_set_signal_levels; > } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > - encoder->set_signal_levels = bxt_set_signal_levels; > + encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; > } else { > encoder->set_signal_levels = hsw_set_signal_levels; > } > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > index 48507ed79950..4d604e4cfa5d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > @@ -23,6 +23,8 @@ > > #include "display/intel_dp.h" > > +#include "intel_ddi.h" > +#include "intel_ddi_buf_trans.h" > #include "intel_de.h" > #include "intel_display_types.h" > #include "intel_dpio_phy.h" > @@ -266,15 +268,24 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, > *ch = DPIO_CH0; > } > > -void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, > - enum port port, u32 margin, u32 scale, > - u32 enable, u32 deemphasis) > +void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > - u32 val; > - enum dpio_phy phy; > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + int level = intel_ddi_level(encoder, crtc_state); > + const struct intel_ddi_buf_trans *trans; > enum dpio_channel ch; > + enum dpio_phy phy; > + int n_entries; > + u32 val; > > - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > + return; > + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > + level = n_entries - 1; > + > + bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); > > /* > * While we write to the group register to program all lanes at once we > @@ -286,12 +297,13 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, > > val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); > val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); > - val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; > + val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT | > + trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT; > intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); > > val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); > val &= ~SCALE_DCOMP_METHOD; > - if (enable) > + if (trans->entries[level].bxt.enable) > val |= SCALE_DCOMP_METHOD; > > if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) > @@ -302,7 +314,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, > > val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); > val &= ~DE_EMPHASIS; > - val |= deemphasis << DEEMPH_SHIFT; > + val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT; > intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); > > val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h > index 6473440e7457..9c3d008e8e1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h > @@ -17,9 +17,8 @@ struct intel_encoder; > > void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, > enum dpio_phy *phy, enum dpio_channel *ch); > -void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, > - enum port port, u32 margin, u32 scale, > - u32 enable, u32 deemphasis); > +void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); > void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); > bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (3 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 20:09 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala ` (15 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> All callers of intel_ddi_level() duplicate the check+WARN to make sure the returned level is actually present in the appropriate buf_trans table. Let's push that stuff into intel_ddi_level() so the callers don't have to worry about it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++--------- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 -- drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 -- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 970a796a4f52..0fd67d2487ad 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -141,8 +141,6 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; /* If we're boosting the current, set bit 31 of trans1 */ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && @@ -977,8 +975,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; iboost = trans->entries[level].hsw.i_boost; } @@ -1037,8 +1033,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -1163,8 +1157,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ for (ln = 0; ln < 2; ln++) { @@ -1286,8 +1278,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | @@ -1357,10 +1347,23 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) int intel_ddi_level(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_ddi_buf_trans *trans; + int level, n_entries; + + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&i915->drm, !trans)) + return 0; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return intel_ddi_hdmi_level(encoder, crtc_state); + level = intel_ddi_hdmi_level(encoder, crtc_state); else - return intel_ddi_dp_level(enc_to_intel_dp(encoder)); + level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); + + if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) + level = n_entries - 1; + + return level; } static void diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 4d604e4cfa5d..96650369164d 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -282,8 +282,6 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index f59cc320ce9c..7a9771dbb63f 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -64,8 +64,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) - level = n_entries - 1; for (ln = 0; ln < 4; ln++) { u32 val = 0; -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala @ 2021-09-29 20:09 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 20:09 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:51PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > All callers of intel_ddi_level() duplicate the check+WARN > to make sure the returned level is actually present in the > appropriate buf_trans table. Let's push that stuff into > intel_ddi_level() so the callers don't have to worry about it. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++--------- > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 -- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 -- > 3 files changed, 15 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 970a796a4f52..0fd67d2487ad 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -141,8 +141,6 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > /* If we're boosting the current, set bit 31 of trans1 */ > if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && > @@ -977,8 +975,6 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > iboost = trans->entries[level].hsw.i_boost; > } > @@ -1037,8 +1033,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > @@ -1163,8 +1157,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ > for (ln = 0; ln < 2; ln++) { > @@ -1286,8 +1278,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | > DKL_TX_DE_EMPAHSIS_COEFF_MASK | > @@ -1357,10 +1347,23 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) > int intel_ddi_level(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + const struct intel_ddi_buf_trans *trans; > + int level, n_entries; > + > + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&i915->drm, !trans)) > + return 0; > + > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - return intel_ddi_hdmi_level(encoder, crtc_state); > + level = intel_ddi_hdmi_level(encoder, crtc_state); > else > - return intel_ddi_dp_level(enc_to_intel_dp(encoder)); > + level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); > + > + if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) > + level = n_entries - 1; > + > + return level; > } > > static void > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > index 4d604e4cfa5d..96650369164d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > @@ -282,8 +282,6 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > > bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); > > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index f59cc320ce9c..7a9771dbb63f 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -64,8 +64,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) > return; > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) > - level = n_entries - 1; > > for (ln = 0; ln < 4; ln++) { > u32 val = 0; > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (4 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 20:11 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala ` (14 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Since intel_ddi_level() now looks that buf_trans table there's no point in having intel_ddi_hdmi_num_entries() around. Just roll the necessary bits of locic into intel_ddi_hdmi_level()/intel_ddi_level(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++----------- .../drm/i915/display/intel_ddi_buf_trans.c | 20 ------------------- .../drm/i915/display/intel_ddi_buf_trans.h | 4 ---- 3 files changed, 5 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 0fd67d2487ad..05124bf4abac 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -74,20 +74,13 @@ static const u8 index_to_dp_signal_levels[] = { }; static int intel_ddi_hdmi_level(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) + const struct intel_ddi_buf_trans *trans) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int n_entries, level, default_entry; + int level; - n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); - if (n_entries == 0) - return 0; level = intel_bios_hdmi_level_shift(encoder); if (level < 0) - level = default_entry; - - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) - level = n_entries - 1; + level = trans->hdmi_default_entry; return level; } @@ -132,7 +125,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_hdmi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state); u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; @@ -1356,7 +1349,7 @@ int intel_ddi_level(struct intel_encoder *encoder, return 0; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - level = intel_ddi_hdmi_level(encoder, crtc_state); + level = intel_ddi_hdmi_level(encoder, trans); else level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 449daba7afb3..a2d39131ea53 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1617,26 +1617,6 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, return intel_get_buf_trans(&dg2_snps_trans, n_entries); } -int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *default_entry) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_ddi_buf_trans *trans; - int n_entries; - - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - - if (drm_WARN_ON(&dev_priv->drm, !trans)) { - *default_entry = 0; - return 0; - } - - *default_entry = trans->hdmi_default_entry; - - return n_entries; -} - void intel_ddi_buf_trans_init(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 94d338287f61..6cdb8e9073c7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -68,10 +68,6 @@ struct intel_ddi_buf_trans { bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table); -int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - int *default_entry); - void intel_ddi_buf_trans_init(struct intel_encoder *encoder); #endif -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() 2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala @ 2021-09-29 20:11 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 20:11 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:52PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Since intel_ddi_level() now looks that buf_trans table there's > no point in having intel_ddi_hdmi_num_entries() around. Just > roll the necessary bits of locic into > intel_ddi_hdmi_level()/intel_ddi_level(). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++----------- > .../drm/i915/display/intel_ddi_buf_trans.c | 20 ------------------- > .../drm/i915/display/intel_ddi_buf_trans.h | 4 ---- > 3 files changed, 5 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 0fd67d2487ad..05124bf4abac 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -74,20 +74,13 @@ static const u8 index_to_dp_signal_levels[] = { > }; > > static int intel_ddi_hdmi_level(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > + const struct intel_ddi_buf_trans *trans) > { > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int n_entries, level, default_entry; > + int level; > > - n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); > - if (n_entries == 0) > - return 0; > level = intel_bios_hdmi_level_shift(encoder); > if (level < 0) > - level = default_entry; > - > - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) > - level = n_entries - 1; > + level = trans->hdmi_default_entry; > > return level; > } > @@ -132,7 +125,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_hdmi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state); > u32 iboost_bit = 0; > int n_entries; > enum port port = encoder->port; > @@ -1356,7 +1349,7 @@ int intel_ddi_level(struct intel_encoder *encoder, > return 0; > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - level = intel_ddi_hdmi_level(encoder, crtc_state); > + level = intel_ddi_hdmi_level(encoder, trans); > else > level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 449daba7afb3..a2d39131ea53 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1617,26 +1617,6 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, > return intel_get_buf_trans(&dg2_snps_trans, n_entries); > } > > -int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *default_entry) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct intel_ddi_buf_trans *trans; > - int n_entries; > - > - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > - > - if (drm_WARN_ON(&dev_priv->drm, !trans)) { > - *default_entry = 0; > - return 0; > - } > - > - *default_entry = trans->hdmi_default_entry; > - > - return n_entries; > -} > - > void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > { > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > index 94d338287f61..6cdb8e9073c7 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > @@ -68,10 +68,6 @@ struct intel_ddi_buf_trans { > > bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table); > > -int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state, > - int *default_entry); > - > void intel_ddi_buf_trans_init(struct intel_encoder *encoder); > > #endif > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (5 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 20:14 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala ` (13 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> In order to have per-lane drive settings we need intel_ddi_level() to accept the lane as a parameter. That is, the eventual goal is to call intel_ddi_level() once for each lane. For now we just pass in a hardcoded 0 and use the same settings for every lane. Ie. no change in behaviour yet. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++--------- drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 05124bf4abac..e6256d4c5af8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -125,7 +125,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; @@ -1017,7 +1017,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; @@ -1139,7 +1139,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); const struct intel_ddi_buf_trans *trans; int n_entries, ln; u32 val; @@ -1260,7 +1260,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); const struct intel_ddi_buf_trans *trans; u32 val, dpcnt_mask, dpcnt_val; int n_entries, ln; @@ -1328,9 +1328,9 @@ static int translate_signal_level(struct intel_dp *intel_dp, return 0; } -static int intel_ddi_dp_level(struct intel_dp *intel_dp) +static int intel_ddi_dp_level(struct intel_dp *intel_dp, int lane) { - u8 train_set = intel_dp->train_set[0]; + u8 train_set = intel_dp->train_set[lane]; u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -1338,7 +1338,8 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) } int intel_ddi_level(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state, + int lane) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_ddi_buf_trans *trans; @@ -1351,7 +1352,7 @@ int intel_ddi_level(struct intel_encoder *encoder, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) level = intel_ddi_hdmi_level(encoder, trans); else - level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); + level = intel_ddi_dp_level(enc_to_intel_dp(encoder), lane); if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) level = n_entries - 1; @@ -1365,7 +1366,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); enum port port = encoder->port; u32 signal_levels; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index d6947c06a455..d6971717ef9c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -64,6 +64,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool enable, u32 hdcp_mask); void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); int intel_ddi_level(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); + const struct intel_crtc_state *crtc_state, + int lane); #endif /* __INTEL_DDI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 96650369164d..5a2eccb12fe4 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -272,7 +272,7 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); const struct intel_ddi_buf_trans *trans; enum dpio_channel ch; enum dpio_phy phy; diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 7a9771dbb63f..b18f08c851dc 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -58,7 +58,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - int level = intel_ddi_level(encoder, crtc_state); + int level = intel_ddi_level(encoder, crtc_state, 0); int n_entries, ln; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() 2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala @ 2021-09-29 20:14 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 20:14 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Sep 27, 2021 at 09:24:53PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > In order to have per-lane drive settings we need intel_ddi_level() > to accept the lane as a parameter. That is, the eventual goal is to > call intel_ddi_level() once for each lane. For now we just pass in > a hardcoded 0 and use the same settings for every lane. Ie. no > change in behaviour yet. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++--------- > drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++- > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +- > 4 files changed, 14 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 05124bf4abac..e6256d4c5af8 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -125,7 +125,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > u32 iboost_bit = 0; > int n_entries; > enum port port = encoder->port; > @@ -1017,7 +1017,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int n_entries, ln; > @@ -1139,7 +1139,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > const struct intel_ddi_buf_trans *trans; > int n_entries, ln; > u32 val; > @@ -1260,7 +1260,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > const struct intel_ddi_buf_trans *trans; > u32 val, dpcnt_mask, dpcnt_val; > int n_entries, ln; > @@ -1328,9 +1328,9 @@ static int translate_signal_level(struct intel_dp *intel_dp, > return 0; > } > > -static int intel_ddi_dp_level(struct intel_dp *intel_dp) > +static int intel_ddi_dp_level(struct intel_dp *intel_dp, int lane) > { > - u8 train_set = intel_dp->train_set[0]; > + u8 train_set = intel_dp->train_set[lane]; > u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | > DP_TRAIN_PRE_EMPHASIS_MASK); > > @@ -1338,7 +1338,8 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp) > } > > int intel_ddi_level(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > + const struct intel_crtc_state *crtc_state, > + int lane) > { > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > const struct intel_ddi_buf_trans *trans; > @@ -1351,7 +1352,7 @@ int intel_ddi_level(struct intel_encoder *encoder, > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > level = intel_ddi_hdmi_level(encoder, trans); > else > - level = intel_ddi_dp_level(enc_to_intel_dp(encoder)); > + level = intel_ddi_dp_level(enc_to_intel_dp(encoder), lane); > > if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) > level = n_entries - 1; > @@ -1365,7 +1366,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > enum port port = encoder->port; > u32 signal_levels; > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h > index d6947c06a455..d6971717ef9c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h > @@ -64,6 +64,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, > bool enable, u32 hdcp_mask); > void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); > int intel_ddi_level(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state); > + const struct intel_crtc_state *crtc_state, > + int lane); > > #endif /* __INTEL_DDI_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > index 96650369164d..5a2eccb12fe4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > @@ -272,7 +272,7 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > const struct intel_ddi_buf_trans *trans; > enum dpio_channel ch; > enum dpio_phy phy; > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index 7a9771dbb63f..b18f08c851dc 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -58,7 +58,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > const struct intel_ddi_buf_trans *trans; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > - int level = intel_ddi_level(encoder, crtc_state); > + int level = intel_ddi_level(encoder, crtc_state, 0); > int n_entries, ln; > > trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (6 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-28 21:22 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-09-29 16:54 ` [Intel-gfx] [PATCH v3 " Ville Syrjala 2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala ` (12 subsequent siblings) 20 siblings, 2 replies; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Adjust the link training code to accommodate per-lane drive settings, if supported by the platform. Actually enabling this will involve some changes to each platform's .set_signal_level() implementation, so for the moment all supported platforms will keep using the current codepath that just uses the same drive settings for all the lanes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_dp_link_training.c | 68 +++++++++++++------ 1 file changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d52929855cd0..4465c83a97d4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,21 +301,33 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; } -void -intel_dp_get_adjust_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state, - enum drm_dp_phy dp_phy, - const u8 link_status[DP_LINK_STATUS_SIZE]) +static bool has_per_lane_signal_levels(struct drm_i915_private *i915, + enum drm_dp_phy dp_phy) +{ + return false; +} + +static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) { u8 v = 0; u8 p = 0; - int lane; u8 voltage_max; u8 preemph_max; - for (lane = 0; lane < crtc_state->lane_count; lane++) { - v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); - p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + if (has_per_lane_signal_levels(dp_to_i915(intel_dp), dp_phy)) { + lane = max(lane, crtc_state->lane_count - 1); + + v = drm_dp_get_adjust_request_voltage(link_status, lane); + p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + } else { + for (lane = 0; lane < crtc_state->lane_count; lane++) { + v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); + p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + } } preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); @@ -328,8 +340,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, if (v >= voltage_max) v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; + return v | p; +} + +void +intel_dp_get_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + for (lane = 0; lane < 4; lane++) - intel_dp->train_set[lane] = v | p; + intel_dp->train_set[lane] = + intel_dp_get_lane_adjust_train(intel_dp, crtc_state, + dp_phy, link_status, lane); } static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, @@ -400,17 +425,22 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u8 train_set = intel_dp->train_set[0]; char phy_name[10]; + int lane; - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); + for (lane = 0; lane < crtc_state->lane_count; lane++) { + u8 train_set = intel_dp->train_set[lane]; + + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s lane %d, vswing level %d%s, pre-emphasis level %d%s\n", + encoder->base.base.id, encoder->base.name, + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + lane, train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); + } if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) encoder->set_signal_levels(encoder, crtc_state); -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 8/9] drm/i915: Prepare link training for per-lane drive settings 2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala @ 2021-09-28 21:22 ` Ville Syrjala 2021-09-29 16:54 ` [Intel-gfx] [PATCH v3 " Ville Syrjala 1 sibling, 0 replies; 36+ messages in thread From: Ville Syrjala @ 2021-09-28 21:22 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Adjust the link training code to accommodate per-lane drive settings, if supported by the platform. Actually enabling this will involve some changes to each platform's .set_signal_level() implementation, so for the moment all supported platforms will keep using the current codepath that just uses the same drive settings for all the lanes. v2: Fix min() vs. max() fumble Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_dp_link_training.c | 68 +++++++++++++------ 1 file changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d52929855cd0..5452f777afac 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,21 +301,33 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; } -void -intel_dp_get_adjust_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state, - enum drm_dp_phy dp_phy, - const u8 link_status[DP_LINK_STATUS_SIZE]) +static bool has_per_lane_signal_levels(struct drm_i915_private *i915, + enum drm_dp_phy dp_phy) +{ + return false; +} + +static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) { u8 v = 0; u8 p = 0; - int lane; u8 voltage_max; u8 preemph_max; - for (lane = 0; lane < crtc_state->lane_count; lane++) { - v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); - p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + if (has_per_lane_signal_levels(dp_to_i915(intel_dp), dp_phy)) { + lane = min(lane, crtc_state->lane_count - 1); + + v = drm_dp_get_adjust_request_voltage(link_status, lane); + p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + } else { + for (lane = 0; lane < crtc_state->lane_count; lane++) { + v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); + p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + } } preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); @@ -328,8 +340,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, if (v >= voltage_max) v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; + return v | p; +} + +void +intel_dp_get_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + for (lane = 0; lane < 4; lane++) - intel_dp->train_set[lane] = v | p; + intel_dp->train_set[lane] = + intel_dp_get_lane_adjust_train(intel_dp, crtc_state, + dp_phy, link_status, lane); } static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, @@ -400,17 +425,22 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u8 train_set = intel_dp->train_set[0]; char phy_name[10]; + int lane; - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); + for (lane = 0; lane < crtc_state->lane_count; lane++) { + u8 train_set = intel_dp->train_set[lane]; + + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s lane %d, vswing level %d%s, pre-emphasis level %d%s\n", + encoder->base.base.id, encoder->base.name, + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + lane, train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); + } if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) encoder->set_signal_levels(encoder, crtc_state); -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v3 8/9] drm/i915: Prepare link training for per-lane drive settings 2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala 2021-09-28 21:22 ` [Intel-gfx] [PATCH v2 " Ville Syrjala @ 2021-09-29 16:54 ` Ville Syrjala 2021-09-29 20:26 ` Imre Deak 1 sibling, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-29 16:54 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Adjust the link training code to accommodate per-lane drive settings, if supported by the platform. Actually enabling this will involve some changes to each platform's .set_signal_level() implementation, so for the moment all supported platforms will keep using the current codepath that just uses the same drive settings for all the lanes. v2: Fix min() vs. max() fumble v3: Compact the debug print to a single line Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_dp_link_training.c | 78 ++++++++++++++----- 1 file changed, 60 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d52929855cd0..f26c44a6b568 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,21 +301,33 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; } -void -intel_dp_get_adjust_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state, - enum drm_dp_phy dp_phy, - const u8 link_status[DP_LINK_STATUS_SIZE]) +static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, + enum drm_dp_phy dp_phy) +{ + return false; +} + +static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) { u8 v = 0; u8 p = 0; - int lane; u8 voltage_max; u8 preemph_max; - for (lane = 0; lane < crtc_state->lane_count; lane++) { - v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); - p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + if (has_per_lane_signal_levels(intel_dp, dp_phy)) { + lane = min(lane, crtc_state->lane_count - 1); + + v = drm_dp_get_adjust_request_voltage(link_status, lane); + p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + } else { + for (lane = 0; lane < crtc_state->lane_count; lane++) { + v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); + p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); + } } preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); @@ -328,8 +340,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, if (v >= voltage_max) v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; + return v | p; +} + +void +intel_dp_get_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + enum drm_dp_phy dp_phy, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + for (lane = 0; lane < 4; lane++) - intel_dp->train_set[lane] = v | p; + intel_dp->train_set[lane] = + intel_dp_get_lane_adjust_train(intel_dp, crtc_state, + dp_phy, link_status, lane); } static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, @@ -394,22 +419,39 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); } +#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" +#define _TRAIN_SET_VSWING_ARGS(train_set) \ + ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ + (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" +#define TRAIN_SET_VSWING_ARGS(train_set) \ + _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[3]) +#define _TRAIN_SET_PREEMPH_ARGS(train_set) \ + ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ + (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" +#define TRAIN_SET_PREEMPH_ARGS(train_set) \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) + void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u8 train_set = intel_dp->train_set[0]; char phy_name[10]; - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] lanes: %d, " + "vswing levels: " TRAIN_SET_FMT ", " + "pre-emphasis levels: " TRAIN_SET_FMT ", at %s\n", + encoder->base.base.id, encoder->base.name, + crtc_state->lane_count, + TRAIN_SET_VSWING_ARGS(intel_dp->train_set), + TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set), intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v3 8/9] drm/i915: Prepare link training for per-lane drive settings 2021-09-29 16:54 ` [Intel-gfx] [PATCH v3 " Ville Syrjala @ 2021-09-29 20:26 ` Imre Deak 2021-09-30 7:07 ` Ville Syrjälä 0 siblings, 1 reply; 36+ messages in thread From: Imre Deak @ 2021-09-29 20:26 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Wed, Sep 29, 2021 at 07:54:52PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Adjust the link training code to accommodate per-lane drive settings, > if supported by the platform. Actually enabling this will involve > some changes to each platform's .set_signal_level() implementation, > so for the moment all supported platforms will keep using the current > codepath that just uses the same drive settings for all the lanes. > > v2: Fix min() vs. max() fumble > v3: Compact the debug print to a single line > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../drm/i915/display/intel_dp_link_training.c | 78 ++++++++++++++----- > 1 file changed, 60 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index d52929855cd0..f26c44a6b568 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -301,21 +301,33 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, > return preemph_max; > } > > -void > -intel_dp_get_adjust_train(struct intel_dp *intel_dp, > - const struct intel_crtc_state *crtc_state, > - enum drm_dp_phy dp_phy, > - const u8 link_status[DP_LINK_STATUS_SIZE]) > +static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, > + enum drm_dp_phy dp_phy) > +{ > + return false; > +} > + > +static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state, > + enum drm_dp_phy dp_phy, > + const u8 link_status[DP_LINK_STATUS_SIZE], > + int lane) > { > u8 v = 0; > u8 p = 0; > - int lane; > u8 voltage_max; > u8 preemph_max; > > - for (lane = 0; lane < crtc_state->lane_count; lane++) { > - v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > - p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > + if (has_per_lane_signal_levels(intel_dp, dp_phy)) { > + lane = min(lane, crtc_state->lane_count - 1); > + > + v = drm_dp_get_adjust_request_voltage(link_status, lane); > + p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); > + } else { > + for (lane = 0; lane < crtc_state->lane_count; lane++) { > + v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > + p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > + } > } > > preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); > @@ -328,8 +340,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, > if (v >= voltage_max) > v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; > > + return v | p; > +} > + > +void > +intel_dp_get_adjust_train(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state, > + enum drm_dp_phy dp_phy, > + const u8 link_status[DP_LINK_STATUS_SIZE]) > +{ > + int lane; > + > for (lane = 0; lane < 4; lane++) > - intel_dp->train_set[lane] = v | p; > + intel_dp->train_set[lane] = > + intel_dp_get_lane_adjust_train(intel_dp, crtc_state, > + dp_phy, link_status, lane); > } > > static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, > @@ -394,22 +419,39 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, > intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); > } > > +#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" > +#define _TRAIN_SET_VSWING_ARGS(train_set) \ > + ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ > + (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" > +#define TRAIN_SET_VSWING_ARGS(train_set) \ > + _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ > + _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ > + _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ > + _TRAIN_SET_VSWING_ARGS((train_set)[3]) > +#define _TRAIN_SET_PREEMPH_ARGS(train_set) \ > + ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ > + (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" > +#define TRAIN_SET_PREEMPH_ARGS(train_set) \ > + _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ > + _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ > + _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ > + _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) > + > void intel_dp_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state, > enum drm_dp_phy dp_phy) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - u8 train_set = intel_dp->train_set[0]; > char phy_name[10]; > > - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", > - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, > - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", > - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> > - DP_TRAIN_PRE_EMPHASIS_SHIFT, > - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? > - " (max)" : "", > + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] lanes: %d, " > + "vswing levels: " TRAIN_SET_FMT ", " > + "pre-emphasis levels: " TRAIN_SET_FMT ", at %s\n", > + encoder->base.base.id, encoder->base.name, > + crtc_state->lane_count, > + TRAIN_SET_VSWING_ARGS(intel_dp->train_set), > + TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set), > intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); Could print the PHY name after [ENCODER:x:y]. Reviewed-by: Imre Deak <imre.deak@intel.com> > > if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v3 8/9] drm/i915: Prepare link training for per-lane drive settings 2021-09-29 20:26 ` Imre Deak @ 2021-09-30 7:07 ` Ville Syrjälä 0 siblings, 0 replies; 36+ messages in thread From: Ville Syrjälä @ 2021-09-30 7:07 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Wed, Sep 29, 2021 at 11:26:02PM +0300, Imre Deak wrote: > On Wed, Sep 29, 2021 at 07:54:52PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Adjust the link training code to accommodate per-lane drive settings, > > if supported by the platform. Actually enabling this will involve > > some changes to each platform's .set_signal_level() implementation, > > so for the moment all supported platforms will keep using the current > > codepath that just uses the same drive settings for all the lanes. > > > > v2: Fix min() vs. max() fumble > > v3: Compact the debug print to a single line > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > .../drm/i915/display/intel_dp_link_training.c | 78 ++++++++++++++----- > > 1 file changed, 60 insertions(+), 18 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > index d52929855cd0..f26c44a6b568 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > @@ -301,21 +301,33 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, > > return preemph_max; > > } > > > > -void > > -intel_dp_get_adjust_train(struct intel_dp *intel_dp, > > - const struct intel_crtc_state *crtc_state, > > - enum drm_dp_phy dp_phy, > > - const u8 link_status[DP_LINK_STATUS_SIZE]) > > +static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, > > + enum drm_dp_phy dp_phy) > > +{ > > + return false; > > +} > > + > > +static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, > > + const struct intel_crtc_state *crtc_state, > > + enum drm_dp_phy dp_phy, > > + const u8 link_status[DP_LINK_STATUS_SIZE], > > + int lane) > > { > > u8 v = 0; > > u8 p = 0; > > - int lane; > > u8 voltage_max; > > u8 preemph_max; > > > > - for (lane = 0; lane < crtc_state->lane_count; lane++) { > > - v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > > - p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > > + if (has_per_lane_signal_levels(intel_dp, dp_phy)) { > > + lane = min(lane, crtc_state->lane_count - 1); > > + > > + v = drm_dp_get_adjust_request_voltage(link_status, lane); > > + p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); > > + } else { > > + for (lane = 0; lane < crtc_state->lane_count; lane++) { > > + v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > > + p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > > + } > > } > > > > preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); > > @@ -328,8 +340,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, > > if (v >= voltage_max) > > v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; > > > > + return v | p; > > +} > > + > > +void > > +intel_dp_get_adjust_train(struct intel_dp *intel_dp, > > + const struct intel_crtc_state *crtc_state, > > + enum drm_dp_phy dp_phy, > > + const u8 link_status[DP_LINK_STATUS_SIZE]) > > +{ > > + int lane; > > + > > for (lane = 0; lane < 4; lane++) > > - intel_dp->train_set[lane] = v | p; > > + intel_dp->train_set[lane] = > > + intel_dp_get_lane_adjust_train(intel_dp, crtc_state, > > + dp_phy, link_status, lane); > > } > > > > static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, > > @@ -394,22 +419,39 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, > > intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); > > } > > > > +#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" > > +#define _TRAIN_SET_VSWING_ARGS(train_set) \ > > + ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ > > + (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" > > +#define TRAIN_SET_VSWING_ARGS(train_set) \ > > + _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ > > + _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ > > + _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ > > + _TRAIN_SET_VSWING_ARGS((train_set)[3]) > > +#define _TRAIN_SET_PREEMPH_ARGS(train_set) \ > > + ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ > > + (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" > > +#define TRAIN_SET_PREEMPH_ARGS(train_set) \ > > + _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ > > + _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ > > + _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ > > + _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) > > + > > void intel_dp_set_signal_levels(struct intel_dp *intel_dp, > > const struct intel_crtc_state *crtc_state, > > enum drm_dp_phy dp_phy) > > { > > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > - u8 train_set = intel_dp->train_set[0]; > > char phy_name[10]; > > > > - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", > > - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, > > - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", > > - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> > > - DP_TRAIN_PRE_EMPHASIS_SHIFT, > > - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? > > - " (max)" : "", > > + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] lanes: %d, " > > + "vswing levels: " TRAIN_SET_FMT ", " > > + "pre-emphasis levels: " TRAIN_SET_FMT ", at %s\n", > > + encoder->base.base.id, encoder->base.name, > > + crtc_state->lane_count, > > + TRAIN_SET_VSWING_ARGS(intel_dp->train_set), > > + TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set), > > intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); > > Could print the PHY name after [ENCODER:x:y]. I think I had that in the mulit-line version, but then I figured it's better to stick to the same format as for the other related debug messages. I suppose we could go through all of them and reorder things a bit... > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > > > if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) > > -- > > 2.32.0 > > -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (7 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala @ 2021-09-27 18:24 ` Ville Syrjala 2021-09-29 16:55 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-09-27 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work Patchwork ` (11 subsequent siblings) 20 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-27 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> LTTPRs should support per-lane drive settings I think, and even if they don't they should implement their own fallback logic to determine suitable common drive settings to use for all the lanes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4465c83a97d4..7051d7a594f3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -304,7 +304,7 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, static bool has_per_lane_signal_levels(struct drm_i915_private *i915, enum drm_dp_phy dp_phy) { - return false; + return dp_phy != DP_PHY_DPRX; } static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 9/9] drm/i915: Allow per-lane drive settings with LTTPRs 2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala @ 2021-09-29 16:55 ` Ville Syrjala 2021-09-29 20:27 ` Imre Deak 0 siblings, 1 reply; 36+ messages in thread From: Ville Syrjala @ 2021-09-29 16:55 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> LTTPRs should support per-lane drive settings I think, and even if they don't they should implement their own fallback logic to determine suitable common drive settings to use for all the lanes. v2: Actually check the correct thing Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index f26c44a6b568..eeea6c73e218 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -304,7 +304,7 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { - return false; + return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy); } static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, -- 2.32.0 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Allow per-lane drive settings with LTTPRs 2021-09-29 16:55 ` [Intel-gfx] [PATCH v2 " Ville Syrjala @ 2021-09-29 20:27 ` Imre Deak 0 siblings, 0 replies; 36+ messages in thread From: Imre Deak @ 2021-09-29 20:27 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Wed, Sep 29, 2021 at 07:55:25PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > LTTPRs should support per-lane drive settings I think, and even if > they don't they should implement their own fallback logic to determine > suitable common drive settings to use for all the lanes. > > v2: Actually check the correct thing > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index f26c44a6b568..eeea6c73e218 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -304,7 +304,7 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, > static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > - return false; > + return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy); > } > > static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, > -- > 2.32.0 > ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (8 preceding siblings ...) 2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala @ 2021-09-27 20:15 ` Patchwork 2021-09-27 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (10 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-27 20:15 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim checkpatch origin/drm-tip d25e0ee15f99 drm/i915: s/ddi_translations/trans/ -:1808: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #1808: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:73: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor); -:1809: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #1809: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:74: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor); total: 0 errors, 2 warnings, 0 checks, 1677 lines checked 158bafff357f drm/i915: Generalize .set_signal_levels() 617cbf9f5683 drm/i915: Nuke usless .set_signal_levels() wrappers d80d9fa4792e drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 34dea577d85c drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 9c635abb2137 drm/i915: Nuke intel_ddi_hdmi_num_entries() 98c92bf385b0 drm/i915: Pass the lane to intel_ddi_level() 386bedb16c5a drm/i915: Prepare link training for per-lane drive settings 14e097e04109 drm/i915: Allow per-lane drive settings with LTTPRs ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DP per-lane drive settings prep work 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (9 preceding siblings ...) 2021-09-27 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work Patchwork @ 2021-09-27 20:16 ` Patchwork 2021-09-27 20:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (9 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-27 20:16 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP per-lane drive settings prep work 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (10 preceding siblings ...) 2021-09-27 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-09-27 20:44 ` Patchwork 2021-09-28 1:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork ` (8 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-27 20:44 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 7803 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work URL : https://patchwork.freedesktop.org/series/95122/ State : success == Summary == CI Bug Log - changes from CI_DRM_10648 -> Patchwork_21170 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/index.html Known issues ------------ Here are the changes found in Patchwork_21170 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +32 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html * igt@core_hotunplug@unbind-rebind: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][2] ([i915#1982] / [i915#4002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html - fi-bxt-dsi: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][6] ([i915#4006] / [i915#4193]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-snb-2600/igt@i915_selftest@live@hangcheck.html * igt@kms_addfb_basic@too-wide: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][9] ([i915#4002]) +87 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_addfb_basic@too-wide.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-bxt-dsi: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-bsw-kefka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bsw-kefka/igt@kms_chamelium@hdmi-edid-read.html - fi-kbl-7500u: [PASS][13] -> [FAIL][14] ([i915#3449]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-dsi: NOTRUN -> [SKIP][16] ([fdo#109271]) +30 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-bxt-dsi: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#1072]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@primary_page_flip: - fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#1072] / [i915#1385]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([i915#3301]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - fi-tgl-1115g4: NOTRUN -> [FAIL][22] ([i915#2722]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/fi-tgl-1115g4/igt@runner@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3449]: https://gitlab.freedesktop.org/drm/intel/issues/3449 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002 [i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4193]: https://gitlab.freedesktop.org/drm/intel/issues/4193 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Participating hosts (38 -> 34) ------------------------------ Additional (2): fi-bsw-kefka fi-tgl-1115g4 Missing (6): bat-adls-5 fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10648 -> Patchwork_21170 CI-20190529: 20190529 CI_DRM_10648: 73d93dcb0d48bb76af25ca3f7149598e4bc68098 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6219: 4b5644c9751b489c73c9bb174644c08b31533cc8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21170: 14e097e04109036a25a0d9ccc26c287cdfa9b3a5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 14e097e04109 drm/i915: Allow per-lane drive settings with LTTPRs 386bedb16c5a drm/i915: Prepare link training for per-lane drive settings 98c92bf385b0 drm/i915: Pass the lane to intel_ddi_level() 9c635abb2137 drm/i915: Nuke intel_ddi_hdmi_num_entries() 34dea577d85c drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() d80d9fa4792e drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 617cbf9f5683 drm/i915: Nuke usless .set_signal_levels() wrappers 158bafff357f drm/i915: Generalize .set_signal_levels() d25e0ee15f99 drm/i915: s/ddi_translations/trans/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/index.html [-- Attachment #2: Type: text/html, Size: 9594 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: DP per-lane drive settings prep work 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (11 preceding siblings ...) 2021-09-27 20:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-09-28 1:25 ` Patchwork 2021-09-28 21:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) Patchwork ` (7 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-28 1:25 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30267 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work URL : https://patchwork.freedesktop.org/series/95122/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10648_full -> Patchwork_21170_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21170_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21170_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21170_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-glk: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-glk8/igt@gem_ctx_isolation@preservation-s3@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@gem_ctx_isolation@preservation-s3@rcs0.html Known issues ------------ Here are the changes found in Patchwork_21170_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html * igt@gem_eio@hibernate: - shard-glk: NOTRUN -> [DMESG-WARN][4] ([i915#1610]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@gem_eio@hibernate.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063] / [i915#3648]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb5/igt@gem_eio@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb7/igt@gem_eio@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb7/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: NOTRUN -> [FAIL][14] ([i915#2842]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][15] -> [SKIP][16] ([i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb8/igt@gem_huc_copy@huc-copy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb7/igt@gem_huc_copy@huc-copy.html - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl7/igt@gem_huc_copy@huc-copy.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#3297]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@vma-merge: - shard-tglb: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@gem_userptr_blits@vma-merge.html * igt@gem_workarounds@suspend-resume: - shard-tglb: [PASS][22] -> [INCOMPLETE][23] ([i915#456]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb8/igt@gem_workarounds@suspend-resume.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb7/igt@gem_workarounds@suspend-resume.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#109289]) +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@gen7_exec_parse@cmd-crossing-page.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][25] ([i915#2856]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@gen9_exec_parse@bb-large.html * igt@i915_pm_lpsp@screens-disabled: - shard-tglb: NOTRUN -> [SKIP][26] ([i915#1902]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@i915_pm_lpsp@screens-disabled.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-tglb: NOTRUN -> [WARN][27] ([i915#2681]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][28] ([fdo#110892]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][29] -> [INCOMPLETE][30] ([i915#3921]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-snb7/igt@i915_selftest@live@hangcheck.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb6/igt@i915_selftest@live@hangcheck.html * igt@kms_big_fb@y-tiled-64bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111614]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb2/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-glk: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +6 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl7/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs: - shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271]) +439 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +6 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [i915#3886]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3689] / [i915#3886]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][42] ([i915#3689]) +4 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs.html * igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271]) +104 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl3/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: - shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271]) +145 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278]) +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-audio: - shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +4 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl3/igt@kms_chamelium@dp-audio.html * igt@kms_chamelium@dp-hpd-with-enabled-mode: - shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl4/igt@kms_chamelium@dp-hpd-with-enabled-mode.html * igt@kms_chamelium@dp-mode-timings: - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109284] / [fdo#111827]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_chamelium@dp-mode-timings.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +19 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb2/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html * igt@kms_color_chamelium@pipe-b-ctm-0-5: - shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109284] / [fdo#111827]) +5 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html * igt@kms_color_chamelium@pipe-c-ctm-blue-to-red: - shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +10 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl2/igt@kms_color_chamelium@pipe-c-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-0-25: - shard-glk: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +2 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_color_chamelium@pipe-d-ctm-0-25.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][53] ([i915#1319]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@legacy: - shard-glk: NOTRUN -> [SKIP][54] ([fdo#109271]) +27 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_content_protection@legacy.html * igt@kms_content_protection@mei_interface: - shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111828]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_content_protection@mei_interface.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen: - shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109278] / [fdo#109279]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-tglb: [PASS][57] -> [INCOMPLETE][58] ([i915#2411] / [i915#2828] / [i915#456]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding: - shard-tglb: NOTRUN -> [SKIP][59] ([fdo#109279] / [i915#3359]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding: - shard-tglb: NOTRUN -> [SKIP][60] ([i915#3359]) +4 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][61] -> [FAIL][62] ([i915#2346] / [i915#533]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@pipe-d-single-bo: - shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#533]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl7/igt@kms_cursor_legacy@pipe-d-single-bo.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][64] -> [FAIL][65] ([i915#79]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][66] -> [FAIL][67] ([i915#2122]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html - shard-tglb: [PASS][68] -> [FAIL][69] ([i915#79]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: NOTRUN -> [DMESG-WARN][70] ([i915#180]) +3 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@plain-flip-fb-recreate@b-dp1: - shard-kbl: [PASS][71] -> [FAIL][72] ([i915#2122]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-kbl4/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl6/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-iclb: [PASS][73] -> [SKIP][74] ([i915#3701]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109280]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt: - shard-tglb: NOTRUN -> [SKIP][76] ([fdo#111825]) +18 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#533]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: - shard-glk: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#533]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-apl: [PASS][79] -> [DMESG-WARN][80] ([i915#180]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][82] ([fdo#108145] / [i915#265]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][83] -> [FAIL][84] ([fdo#108145] / [i915#265]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][85] ([fdo#112054]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_plane_lowres@pipe-a-tiling-yf.html * igt@kms_plane_lowres@pipe-c-tiling-x: - shard-iclb: NOTRUN -> [SKIP][86] ([i915#3536]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_plane_lowres@pipe-c-tiling-x.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +1 similar issue [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html - shard-iclb: NOTRUN -> [SKIP][88] ([i915#658]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3: - shard-glk: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5: - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658]) +3 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4: - shard-tglb: NOTRUN -> [SKIP][91] ([i915#2920]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][92] -> [SKIP][93] ([fdo#109642] / [fdo#111068] / [i915#658]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb3/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][94] -> [SKIP][95] ([fdo#109441]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_psr@psr2_no_drrs: - shard-tglb: NOTRUN -> [FAIL][96] ([i915#132] / [i915#3467]) +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb2/igt@kms_psr@psr2_no_drrs.html * igt@kms_setmode@basic: - shard-snb: NOTRUN -> [FAIL][97] ([i915#31]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-snb7/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-d-query-forked-busy: - shard-skl: NOTRUN -> [SKIP][98] ([fdo#109271]) +12 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl4/igt@kms_vblank@pipe-d-query-forked-busy.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2437]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@kms_writeback@writeback-check-output.html * igt@nouveau_crc@pipe-c-source-outp-inactive: - shard-tglb: NOTRUN -> [SKIP][100] ([i915#2530]) +1 similar issue [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@nouveau_crc@pipe-c-source-outp-inactive.html * igt@perf@polling-small-buf: - shard-skl: [PASS][101] -> [FAIL][102] ([i915#1722]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl1/igt@perf@polling-small-buf.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl6/igt@perf@polling-small-buf.html * igt@perf_pmu@rc6-suspend: - shard-kbl: [PASS][103] -> [DMESG-WARN][104] ([i915#180]) +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-kbl2/igt@perf_pmu@rc6-suspend.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl4/igt@perf_pmu@rc6-suspend.html * igt@prime_nv_api@i915_nv_double_import: - shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109291]) +2 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@prime_nv_api@i915_nv_double_import.html * igt@sysfs_clients@create: - shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +3 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl3/igt@sysfs_clients@create.html * igt@sysfs_clients@sema-10: - shard-tglb: NOTRUN -> [SKIP][107] ([i915#2994]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@sysfs_clients@sema-10.html * igt@sysfs_clients@split-10: - shard-iclb: NOTRUN -> [SKIP][108] ([i915#2994]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb6/igt@sysfs_clients@split-10.html * igt@sysfs_clients@split-50: - shard-kbl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994]) +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: [FAIL][110] ([i915#2842]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-glk4/igt@gem_exec_fair@basic-none-vip@rcs0.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [FAIL][112] ([i915#2842]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_workarounds@suspend-resume: - shard-skl: [INCOMPLETE][114] ([i915#198]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl6/igt@gem_workarounds@suspend-resume.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl1/igt@gem_workarounds@suspend-resume.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][116] ([i915#1436] / [i915#716]) -> [PASS][117] [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl7/igt@gen9_exec_parse@allowed-single.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl4/igt@gen9_exec_parse@allowed-single.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [DMESG-FAIL][118] ([i915#2291] / [i915#541]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl6/igt@i915_selftest@live@gt_heartbeat.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-WARN][120] -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-glk7/igt@kms_big_fb@linear-64bpp-rotate-180.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-glk7/igt@kms_big_fb@linear-64bpp-rotate-180.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [DMESG-WARN][122] ([i915#1982]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl2/igt@kms_color@pipe-a-ctm-0-75.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl9/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-tglb: [INCOMPLETE][124] ([i915#2411] / [i915#456]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [FAIL][126] ([i915#2122]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +5 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-apl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile: - shard-iclb: [SKIP][132] ([i915#3701]) -> [PASS][133] [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-tglb: [INCOMPLETE][134] ([i915#456]) -> [PASS][135] [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10648/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21170/index.html [-- Attachment #2: Type: text/html, Size: 33653 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (12 preceding siblings ...) 2021-09-28 1:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2021-09-28 21:54 ` Patchwork 2021-09-28 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (6 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-28 21:54 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev2) URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim checkpatch origin/drm-tip be9a7b3627c4 drm/i915: s/ddi_translations/trans/ -:1808: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #1808: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:73: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor); -:1809: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #1809: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:74: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor); total: 0 errors, 2 warnings, 0 checks, 1677 lines checked dd4dc5015d60 drm/i915: Generalize .set_signal_levels() f023061edeec drm/i915: Nuke usless .set_signal_levels() wrappers 5d68ca04076a drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() e1c952fcbe3d drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 4e0e5a259061 drm/i915: Nuke intel_ddi_hdmi_num_entries() 21dff7c1cf74 drm/i915: Pass the lane to intel_ddi_level() c2a69b618c76 drm/i915: Prepare link training for per-lane drive settings 9a8086f736c6 drm/i915: Allow per-lane drive settings with LTTPRs ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DP per-lane drive settings prep work (rev2) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (13 preceding siblings ...) 2021-09-28 21:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) Patchwork @ 2021-09-28 21:55 ` Patchwork 2021-09-28 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (5 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-28 21:55 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev2) URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP per-lane drive settings prep work (rev2) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (14 preceding siblings ...) 2021-09-28 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-09-28 22:23 ` Patchwork 2021-09-29 0:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork ` (4 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-28 22:23 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5560 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev2) URL : https://patchwork.freedesktop.org/series/95122/ State : success == Summary == CI Bug Log - changes from CI_DRM_10655 -> Patchwork_21181 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/index.html Known issues ------------ Here are the changes found in Patchwork_21181 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@cs-sdma: - fi-kbl-7500u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-7500u/igt@amdgpu/amd_basic@cs-sdma.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-7500u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-7500u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html #### Possible fixes #### * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick: [DMESG-FAIL][9] ([i915#2927] / [i915#3428]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][11] ([i915#1161]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html #### Warnings #### * igt@kms_chamelium@vga-hpd-fast: - fi-kbl-7500u: [{ABORT}][13] ([i915#1814]) -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Participating hosts (45 -> 37) ------------------------------ Additional (1): fi-kbl-soraka Missing (9): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 bat-jsl-2 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10655 -> Patchwork_21181 CI-20190529: 20190529 CI_DRM_10655: 88d6ecae86a7bb32e8bf2bd233f7f9f9c8bd7abc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6226: 18278534c085c35adcf62f158a8d5356e5496f8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21181: 9a8086f736c623ddda0622f2195b5fbff4bd629e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9a8086f736c6 drm/i915: Allow per-lane drive settings with LTTPRs c2a69b618c76 drm/i915: Prepare link training for per-lane drive settings 21dff7c1cf74 drm/i915: Pass the lane to intel_ddi_level() 4e0e5a259061 drm/i915: Nuke intel_ddi_hdmi_num_entries() e1c952fcbe3d drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 5d68ca04076a drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() f023061edeec drm/i915: Nuke usless .set_signal_levels() wrappers dd4dc5015d60 drm/i915: Generalize .set_signal_levels() be9a7b3627c4 drm/i915: s/ddi_translations/trans/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/index.html [-- Attachment #2: Type: text/html, Size: 7001 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: DP per-lane drive settings prep work (rev2) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (15 preceding siblings ...) 2021-09-28 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-09-29 0:54 ` Patchwork 2021-09-29 17:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4) Patchwork ` (3 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-29 0:54 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30276 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev2) URL : https://patchwork.freedesktop.org/series/95122/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10655_full -> Patchwork_21181_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21181_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21181_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21181_full: ### IGT changes ### #### Possible regressions #### * igt@kms_flip@busy-flip@b-edp1: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl7/igt@kms_flip@busy-flip@b-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl6/igt@kms_flip@busy-flip@b-edp1.html * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-iclb: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html ### Piglit changes ### #### Possible regressions #### * spec@glsl-1.50@execution@built-in-functions@gs-op-selection-bool-mat2x3-mat2x3 (NEW): - pig-snb-2600: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/pig-snb-2600/spec@glsl-1.50@execution@built-in-functions@gs-op-selection-bool-mat2x3-mat2x3.html New tests --------- New tests have been introduced between CI_DRM_10655_full and Patchwork_21181_full: ### New Piglit tests (1) ### * spec@glsl-1.50@execution@built-in-functions@gs-op-selection-bool-mat2x3-mat2x3: - Statuses : 1 fail(s) - Exec time: [0.16] s Known issues ------------ Here are the changes found in Patchwork_21181_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> [SKIP][5] ([fdo#109314]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@gem_ctx_param@set-priority-not-supported.html * igt@gem_eio@in-flight-suspend: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl4/igt@gem_eio@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl1/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_params@no-bsd: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@gem_exec_params@no-bsd.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#112283]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@gem_exec_params@secure-non-root.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl8/igt@gem_pwrite@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-snb2/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@unsync-overlap: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#3297]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@gem_userptr_blits@unsync-overlap.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#198]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl9/igt@gem_workarounds@suspend-resume.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl8/igt@gem_workarounds@suspend-resume.html * igt@gen7_exec_parse@basic-allocation: - shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271]) +33 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@gen7_exec_parse@basic-allocation.html * igt@gen9_exec_parse@unaligned-jump: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#2856]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@gen9_exec_parse@unaligned-jump.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][24] ([fdo#110892]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@kms_big_fb@linear-32bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110725] / [fdo#111614]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_big_fb@linear-32bpp-rotate-90.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][26] ([fdo#111614]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb1/igt@kms_big_fb@linear-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html - shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-0: - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110723]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html * igt@kms_big_joiner@invalid-modeset: - shard-tglb: NOTRUN -> [SKIP][31] ([i915#2705]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb3/igt@kms_big_joiner@invalid-modeset.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +6 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +6 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689] / [i915#3886]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689]) +3 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +8 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html * igt@kms_chamelium@hdmi-hpd-storm: - shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +15 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html * igt@kms_chamelium@hdmi-mode-timings: - shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-snb6/igt@kms_chamelium@hdmi-mode-timings.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +3 similar issues [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_content_protection@atomic-dpms: - shard-kbl: NOTRUN -> [TIMEOUT][42] ([i915#1319]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl6/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@dp-mst-type-0: - shard-tglb: NOTRUN -> [SKIP][43] ([i915#3116]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb1/igt@kms_content_protection@dp-mst-type-0.html * igt@kms_content_protection@mei_interface: - shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111828]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb1/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@uevent: - shard-kbl: NOTRUN -> [FAIL][45] ([i915#2105]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl3/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-32x10-random: - shard-tglb: NOTRUN -> [SKIP][46] ([i915#3359]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x10-random.html * igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen: - shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278]) +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen: - shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271]) +134 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen: - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109279] / [i915#3359]) +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-tglb: [PASS][50] -> [INCOMPLETE][51] ([i915#2411] / [i915#4211]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl3/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_fbcon_fbt@psr-suspend: - shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#2411] / [i915#4173] / [i915#456]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb1/igt@kms_fbcon_fbt@psr-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-flip-vs-rmfb-interruptible: - shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109274]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][57] -> [FAIL][58] ([i915#79]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: NOTRUN -> [DMESG-WARN][59] ([i915#180]) +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite: - shard-snb: NOTRUN -> [SKIP][60] ([fdo#109271]) +177 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109280]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: NOTRUN -> [SKIP][62] ([fdo#111825]) +21 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][63] -> [FAIL][64] ([i915#1188]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_hdr@bpc-switch-suspend: - shard-apl: NOTRUN -> [DMESG-WARN][65] ([i915#180]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl6/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_lowres@pipe-b-tiling-none: - shard-tglb: NOTRUN -> [SKIP][69] ([i915#3536]) +2 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb3/igt@kms_plane_lowres@pipe-b-tiling-none.html * igt@kms_plane_lowres@pipe-d-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][70] ([fdo#112054]) +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_plane_lowres@pipe-d-tiling-yf.html * igt@kms_plane_scaling@2x-scaler-multi-pipe: - shard-glk: [PASS][71] -> [DMESG-WARN][72] ([i915#118] / [i915#95]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk2/igt@kms_plane_scaling@2x-scaler-multi-pipe.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping: - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2733]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html * igt@kms_prime@basic-crc@first-to-second: - shard-tglb: NOTRUN -> [SKIP][74] ([i915#1836]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_prime@basic-crc@first-to-second.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-tglb: NOTRUN -> [SKIP][75] ([i915#2920]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +3 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3: - shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-tglb: NOTRUN -> [FAIL][79] ([i915#132] / [i915#3467]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-tglb: NOTRUN -> [SKIP][82] ([fdo#111615]) +4 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-tglb: [PASS][83] -> [INCOMPLETE][84] ([i915#2828] / [i915#456]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-suspend: - shard-tglb: [PASS][85] -> [INCOMPLETE][86] ([i915#3896]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html * igt@kms_writeback@writeback-fb-id: - shard-tglb: NOTRUN -> [SKIP][87] ([i915#2437]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_writeback@writeback-fb-id.html * igt@kms_writeback@writeback-pixel-formats: - shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@polling: - shard-skl: [PASS][89] -> [FAIL][90] ([i915#1542]) +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@perf@polling.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl5/igt@perf@polling.html * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name: - shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271]) +153 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl3/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html * igt@prime_nv_pcopy@test3_2: - shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109291]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@prime_nv_pcopy@test3_2.html * igt@prime_vgem@basic-userptr: - shard-tglb: NOTRUN -> [SKIP][93] ([i915#3301]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@prime_vgem@basic-userptr.html * igt@prime_vgem@fence-read-hang: - shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109295]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb1/igt@prime_vgem@fence-read-hang.html * igt@sysfs_clients@create: - shard-glk: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-glk7/igt@sysfs_clients@create.html * igt@sysfs_clients@recycle: - shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl3/igt@sysfs_clients@recycle.html * igt@sysfs_clients@sema-10: - shard-kbl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994]) +1 similar issue [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl4/igt@sysfs_clients@sema-10.html * igt@sysfs_clients@sema-25: - shard-tglb: NOTRUN -> [SKIP][98] ([i915#2994]) +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@sysfs_clients@sema-25.html #### Possible fixes #### * igt@gem_exec_fair@basic-none@rcs0: - shard-iclb: [FAIL][99] ([i915#2842]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb8/igt@gem_exec_fair@basic-none@rcs0.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb7/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [FAIL][101] ([i915#2842]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [FAIL][103] ([i915#2842] / [i915#3468]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_parallel@fds@vecs0: - shard-iclb: [INCOMPLETE][105] ([i915#1895]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb7/igt@gem_exec_parallel@fds@vecs0.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb4/igt@gem_exec_parallel@fds@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [SKIP][107] ([i915#2190]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@gem_huc_copy@huc-copy.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb2/igt@gem_huc_copy@huc-copy.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [FAIL][109] ([i915#454]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html * igt@kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][111] ([i915#1982]) -> [PASS][112] +1 similar issue [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_color@pipe-c-ctm-0-25.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl5/igt@kms_color@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114] +3 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-tglb: [INCOMPLETE][115] ([i915#2411] / [i915#4173] / [i915#456]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html - shard-kbl: [INCOMPLETE][117] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1: - shard-skl: [FAIL][119] ([i915#2122]) -> [PASS][120] +2 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile: - shard-iclb: [SKIP][121] ([i915#3701]) -> [PASS][122] +1 similar issue [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html * igt@kms_hdr@bpc-switch: - shard-skl: [FAIL][123] ([i915#1188]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl4/igt@kms_hdr@bpc-switch.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl2/igt@kms_hdr@bpc-switch.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-apl: [DMESG-WARN][125] ([i915#180]) -> [PASS][126] +2 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][127] ([fdo#108145] / [i915#265]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][129] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb1/igt@kms_psr2_su@frontbuffer.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb2/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][131] ([fdo#109441]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_psr@suspend: - shard-tglb: [INCOMPLETE][133] ([i915#456]) -> [PASS][134] +2 similar issues [133]: https://intel-gfx-ci.01.org/tree/drm-tip == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21181/index.html [-- Attachment #2: Type: text/html, Size: 33702 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (16 preceding siblings ...) 2021-09-29 0:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2021-09-29 17:34 ` Patchwork 2021-09-29 17:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-29 17:34 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev4) URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5ca7aed58062 drm/i915: s/ddi_translations/trans/ -:1809: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #1809: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:73: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor); -:1810: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #1810: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:74: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor); total: 0 errors, 2 warnings, 0 checks, 1677 lines checked 12af5655d6e9 drm/i915: Generalize .set_signal_levels() 148ee4908c2b drm/i915: Nuke usless .set_signal_levels() wrappers 96ccc8d77127 drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 40be81462b60 drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 025b7bd7473d drm/i915: Nuke intel_ddi_hdmi_num_entries() 68f42730e749 drm/i915: Pass the lane to intel_ddi_level() 24cdd73489e8 drm/i915: Prepare link training for per-lane drive settings -:95: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects? #95: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:423: +#define _TRAIN_SET_VSWING_ARGS(train_set) \ + ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ + (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" -:98: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #98: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:426: +#define TRAIN_SET_VSWING_ARGS(train_set) \ + _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[3]) -:98: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects? #98: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:426: +#define TRAIN_SET_VSWING_ARGS(train_set) \ + _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ + _TRAIN_SET_VSWING_ARGS((train_set)[3]) -:103: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects? #103: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:431: +#define _TRAIN_SET_PREEMPH_ARGS(train_set) \ + ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ + (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" -:106: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #106: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:434: +#define TRAIN_SET_PREEMPH_ARGS(train_set) \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) -:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects? #106: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:434: +#define TRAIN_SET_PREEMPH_ARGS(train_set) \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ + _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) total: 2 errors, 0 warnings, 4 checks, 111 lines checked def5bc2e3c93 drm/i915: Allow per-lane drive settings with LTTPRs ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DP per-lane drive settings prep work (rev4) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (17 preceding siblings ...) 2021-09-29 17:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4) Patchwork @ 2021-09-29 17:35 ` Patchwork 2021-09-29 18:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-29 21:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-29 17:35 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev4) URL : https://patchwork.freedesktop.org/series/95122/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP per-lane drive settings prep work (rev4) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (18 preceding siblings ...) 2021-09-29 17:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-09-29 18:05 ` Patchwork 2021-09-29 21:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-29 18:05 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 1707 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev4) URL : https://patchwork.freedesktop.org/series/95122/ State : success == Summary == CI Bug Log - changes from CI_DRM_10660 -> Patchwork_21192 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/index.html Changes ------- No changes found Participating hosts (33 -> 28) ------------------------------ Missing (5): bat-dg1-6 fi-tgl-u2 fi-bsw-cyan bat-adlp-4 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10660 -> Patchwork_21192 CI-20190529: 20190529 CI_DRM_10660: 05888a7b7b4aec560d6692e5e9173adc7e76c0df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6227: 6ac2da7fd6b13f04f9aa0ec10f86b831d2756946 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21192: def5bc2e3c93d986e7f69476bb0722ea7cbe0f11 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == def5bc2e3c93 drm/i915: Allow per-lane drive settings with LTTPRs 24cdd73489e8 drm/i915: Prepare link training for per-lane drive settings 68f42730e749 drm/i915: Pass the lane to intel_ddi_level() 025b7bd7473d drm/i915: Nuke intel_ddi_hdmi_num_entries() 40be81462b60 drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() 96ccc8d77127 drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() 148ee4908c2b drm/i915: Nuke usless .set_signal_levels() wrappers 12af5655d6e9 drm/i915: Generalize .set_signal_levels() 5ca7aed58062 drm/i915: s/ddi_translations/trans/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/index.html [-- Attachment #2: Type: text/html, Size: 2329 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: DP per-lane drive settings prep work (rev4) 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala ` (19 preceding siblings ...) 2021-09-29 18:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-09-29 21:12 ` Patchwork 20 siblings, 0 replies; 36+ messages in thread From: Patchwork @ 2021-09-29 21:12 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30276 bytes --] == Series Details == Series: drm/i915: DP per-lane drive settings prep work (rev4) URL : https://patchwork.freedesktop.org/series/95122/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10660_full -> Patchwork_21192_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21192_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21192_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21192_full: ### IGT changes ### #### Possible regressions #### * igt@kms_async_flips@crc: - shard-skl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl9/igt@kms_async_flips@crc.html Known issues ------------ Here are the changes found in Patchwork_21192_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl2/igt@gem_create@create-massive.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][3] ([i915#280]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb7/igt@gem_ctx_sseu@mmap-args.html * igt@gem_eio@unwedge-stress: - shard-skl: NOTRUN -> [TIMEOUT][4] ([i915#2369] / [i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk3/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb1/igt@gem_exec_fair@basic-pace@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb4/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@gem_exec_params@no-blt.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#112283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@gem_exec_params@secure-non-master.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#456]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb3/igt@gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb7/igt@gem_exec_suspend@basic-s0.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk4/igt@gem_exec_whisper@basic-queues-forked-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk8/igt@gem_exec_whisper@basic-queues-forked-all.html * igt@gem_softpin@noreloc-s3: - shard-apl: NOTRUN -> [DMESG-WARN][19] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl8/igt@gem_softpin@noreloc-s3.html * igt@gen3_render_tiledy_blits: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb8/igt@gen3_render_tiledy_blits.html * igt@gen9_exec_parse@bb-start-param: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb3/igt@gen9_exec_parse@bb-start-param.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#1937]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109506] / [i915#2411]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html * igt@i915_selftest@live@gt_lrc: - shard-tglb: NOTRUN -> [DMESG-FAIL][24] ([i915#2373]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - shard-tglb: NOTRUN -> [DMESG-FAIL][25] ([i915#1759] / [i915#2291]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@i915_selftest@live@gt_pm.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][26] -> [FAIL][27] ([i915#2521]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl5/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_big_fb@linear-16bpp-rotate-90: - shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271]) +155 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl7/igt@kms_big_fb@linear-16bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][30] ([i915#3722]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111615]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-iclb: NOTRUN -> [SKIP][34] ([fdo#110723]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109278] / [i915#3886]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689]) +5 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][37] ([i915#3689] / [i915#3886]) +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html - shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +3 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +7 similar issues [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@hdmi-audio-edid: - shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +4 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_chamelium@hdmi-audio-edid.html * igt@kms_chamelium@vga-hpd-after-suspend: - shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +10 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl3/igt@kms_chamelium@vga-hpd-after-suspend.html * igt@kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][43] -> [DMESG-WARN][44] ([i915#1982]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl3/igt@kms_color@pipe-a-ctm-0-5.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl2/igt@kms_color@pipe-a-ctm-0-5.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +3 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl2/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_content_protection@mei_interface: - shard-tglb: NOTRUN -> [SKIP][47] ([fdo#111828]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@srm: - shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl8/igt@kms_content_protection@srm.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-random: - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109279] / [i915#3359]) +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +7 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-512x512-random: - shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271]) +39 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-512x512-random.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][53] ([i915#3359]) +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html * igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen: - shard-tglb: NOTRUN -> [SKIP][54] ([i915#3319]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-256x85-random: - shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109278]) +3 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-tglb: [PASS][56] -> [INCOMPLETE][57] ([i915#4211]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-suspend.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][58] -> [FAIL][59] ([i915#72]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions: - shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271]) +64 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-tglb: [PASS][61] -> [INCOMPLETE][62] ([i915#4173] / [i915#456]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-plain-flip-ts-check: - shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111825]) +19 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb8/igt@kms_flip@2x-plain-flip-ts-check.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [PASS][64] -> [DMESG-WARN][65] ([i915#180]) +3 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@flip-vs-suspend@c-edp1: - shard-skl: [PASS][66] -> [INCOMPLETE][67] ([i915#146] / [i915#198]) +1 similar issue [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl4/igt@kms_flip@flip-vs-suspend@c-edp1.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl10/igt@kms_flip@flip-vs-suspend@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-tglb: NOTRUN -> [SKIP][68] ([i915#2587]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109280]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][70] -> [FAIL][71] ([i915#1188]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: NOTRUN -> [INCOMPLETE][72] ([i915#198] / [i915#2828]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html - shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533]) +2 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][75] ([i915#265]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][76] -> [FAIL][77] ([fdo#108145] / [i915#265]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-b-tiling-x: - shard-tglb: NOTRUN -> [SKIP][78] ([i915#3536]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-x.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html - shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5: - shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658]) +3 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5: - shard-tglb: NOTRUN -> [SKIP][82] ([i915#2920]) +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html * igt@kms_psr@psr2_dpms: - shard-tglb: NOTRUN -> [FAIL][83] ([i915#132] / [i915#3467]) +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_psr@psr2_dpms.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][84] -> [SKIP][85] ([fdo#109441]) +1 similar issue [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html * igt@kms_sysfs_edid_timing: - shard-apl: NOTRUN -> [FAIL][86] ([IGT#2]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl7/igt@kms_sysfs_edid_timing.html - shard-kbl: NOTRUN -> [FAIL][87] ([IGT#2]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@kms_sysfs_edid_timing.html - shard-skl: NOTRUN -> [FAIL][88] ([IGT#2]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@kms_sysfs_edid_timing.html * igt@kms_vrr@flip-suspend: - shard-tglb: NOTRUN -> [SKIP][89] ([fdo#109502]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@kms_vrr@flip-suspend.html * igt@kms_writeback@writeback-check-output: - shard-tglb: NOTRUN -> [SKIP][90] ([i915#2437]) +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_writeback@writeback-check-output.html * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame: - shard-tglb: NOTRUN -> [SKIP][91] ([i915#2530]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html * igt@perf@polling: - shard-skl: [PASS][92] -> [FAIL][93] ([i915#1542]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl2/igt@perf@polling.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl2/igt@perf@polling.html * igt@prime_nv_api@i915_self_import_to_different_fd: - shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109291]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb8/igt@prime_nv_api@i915_self_import_to_different_fd.html * igt@prime_nv_test@i915_import_cpu_mmap: - shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109291]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@prime_nv_test@i915_import_cpu_mmap.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl8/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@split-25: - shard-tglb: NOTRUN -> [SKIP][97] ([i915#2994]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@sysfs_clients@split-25.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglb: [INCOMPLETE][98] ([i915#1373]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@rcs0.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb3/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-iclb: [FAIL][100] ([i915#2842]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [FAIL][102] ([i915#2842]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][104] ([i915#2842]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-iclb: [FAIL][106] ([i915#2849]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_params@dr1-dirt: - shard-skl: [DMESG-WARN][108] ([i915#1982]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl4/igt@gem_exec_params@dr1-dirt.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl10/igt@gem_exec_params@dr1-dirt.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [SKIP][110] ([i915#2190]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb7/igt@gem_huc_copy@huc-copy.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb3/igt@gem_huc_copy@huc-copy.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][112] ([i915#644]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [INCOMPLETE][114] ([i915#198] / [i915#4173]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl2/igt@gem_workarounds@suspend-resume-context.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl7/igt@gem_workarounds@suspend-resume-context.html - shard-kbl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-kbl6/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [FAIL][118] ([i915#454]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html * igt@i915_suspend@forcewake: - shard-tglb: [INCOMPLETE][120] ([i915#456]) -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb7/igt@i915_suspend@forcewake.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb5/igt@i915_suspend@forcewake.html * igt@kms_big_fb@linear-32bpp-rotate-180: - shard-glk: [DMESG-WARN][122] ([i915#118] / [i915#95]) -> [PASS][123] +1 similar issue [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-180.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-180.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [DMESG-WARN][124] ([i915#180]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [FAIL][126] ([i915#2346] / [i915#533]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1: - shard-skl: [FAIL][128] ([i915#2122]) -> [PASS][129] [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-tglb: [INCOMPLETE][130] ([i915#2411] / [i915#456]) -> [PASS][131] +1 similar issue [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][132] ([fdo#108145] / [i915#265]) -> [PASS][133] [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][134] ([fdo#109441]) -> [PASS][135] +2 similar issues [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb6/igt@kms_psr@psr2_no_drrs.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb2/igt@kms_psr@psr2_no_drrs.html * igt@perf@polling-parameterized: - shard-skl: [FAIL][136] ([i915#1542]) -> [PASS][137] [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-skl3/igt@perf@polling-parameterized.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-skl5/igt@perf@polling-parameterized.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][138] ([i915#1804] / [i915#2684]) -> [WARN][139] ([i915#2684]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10660/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: [FAIL][140] ([i915#3722]) -> [F == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21192/index.html [-- Attachment #2: Type: text/html, Size: 33646 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2021-09-30 7:33 UTC | newest] Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala 2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala 2021-09-29 16:59 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala 2021-09-29 19:17 ` Imre Deak 2021-09-30 7:33 ` Ville Syrjälä 2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala 2021-09-29 19:43 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala 2021-09-29 19:48 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala 2021-09-29 20:09 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala 2021-09-29 20:11 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala 2021-09-29 20:14 ` Imre Deak 2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala 2021-09-28 21:22 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-09-29 16:54 ` [Intel-gfx] [PATCH v3 " Ville Syrjala 2021-09-29 20:26 ` Imre Deak 2021-09-30 7:07 ` Ville Syrjälä 2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala 2021-09-29 16:55 ` [Intel-gfx] [PATCH v2 " Ville Syrjala 2021-09-29 20:27 ` Imre Deak 2021-09-27 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work Patchwork 2021-09-27 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-09-27 20:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-28 1:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-28 21:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) Patchwork 2021-09-28 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-09-28 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-29 0:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-29 17:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4) Patchwork 2021-09-29 17:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-09-29 18:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-29 21:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.