[Intel-gfx] [V2 0/4] Enable MIPI DSI video mode on ADLP

[Intel-gfx] [V2 0/4] Enable MIPI DSI video mode on ADLP

[Vandita Kulkarni]

v2: Addressed the review comments on v1.

Vandita Kulkarni (4):
  drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
  drm/i915/dsi/xelpd: Add DSI transcoder support
  drm/i915/dsi/xelpd: Disable DC states in Video mode
  drm/i915/dsi: Ungate clock before enabling the phy

 drivers/gpu/drm/i915/display/icl_dsi.c             | 11 +++++------
 drivers/gpu/drm/i915/display/intel_display_power.c |  1 +
 drivers/gpu/drm/i915/i915_pci.c                    | 11 +++++++++--
 drivers/gpu/drm/i915/i915_reg.h                    |  4 +++-
 4 files changed, 18 insertions(+), 9 deletions(-)

-- 
2.32.0

[Intel-gfx] [V2 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

[Vandita Kulkarni]

v2: Fix the typo, move out the hardcoding from
    macro(Jani, Ville)

Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h        | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 168c84a74d30..63dd75c6448a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1271,7 +1271,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
 	if (DISPLAY_VER(i915) == 13) {
 		for_each_dsi_port(port, intel_dsi->ports)
 			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
-				     TGL_DSI_CHKN_LSHS_GB, 0x4);
+				     TGL_DSI_CHKN_LSHS_GB_MASK,
+				     TGL_DSI_CHKN_LSHS_GB(4));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9f7a729333f..749b043a3ee3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11715,7 +11715,9 @@ enum skl_power_gate {
 #define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\
 						    _TGL_DSI_CHKN_REG_0, \
 						    _TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB			REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK		REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)	REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
+							       (byte_clocks))
 
 /* Display Stream Splitter Control */
 #define DSS_CTL1				_MMIO(0x67400)
-- 
2.32.0

[Intel-gfx] [V2 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support

[Vandita Kulkarni]

Update ADL_P device info to support DSI0, DSI1

v2: Re-define cpu_transcoder_mask only (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..44c3577be748 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
 #define XE_LPD_FEATURES \
 	.abox_mask = GENMASK(1, 0),						\
 	.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },		\
-	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |		\
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),				\
 	.dbuf.size = 4096,							\
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
@@ -955,12 +953,16 @@ static const struct intel_device_info adl_s_info = {
 		[TRANSCODER_B] = PIPE_B_OFFSET,					\
 		[TRANSCODER_C] = PIPE_C_OFFSET,					\
 		[TRANSCODER_D] = PIPE_D_OFFSET,					\
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
 	},									\
 	.trans_offsets = {							\
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
 		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
 	},									\
 	XE_LPD_CURSOR_OFFSETS
 
@@ -969,6 +971,9 @@ static const struct intel_device_info adl_p_info = {
 	XE_LPD_FEATURES,
 	PLATFORM(INTEL_ALDERLAKE_P),
 	.require_force_probe = 1,
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 	.display.has_cdclk_crawl = 1,
 	.display.has_modular_fia = 1,
 	.display.has_psr_hw_tracking = 0,
@@ -1038,6 +1043,8 @@ static const struct intel_device_info dg2_info = {
 		BIT(VECS0) | BIT(VECS1) |
 		BIT(VCS0) | BIT(VCS2),
 	.require_force_probe = 1,
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 };
 
 #undef PLATFORM
-- 
2.32.0

[Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode

[Vandita Kulkarni]

MIPI DSI transcoder cannot be in video mode to support any of the
display C states.

Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode)
Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI enabled)
Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control

v2: Align to the power domain ordering (Jani)
    Add bspec references (Imre)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d88da0d0f05a..b989ddd3d023 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
+	BIT_ULL(POWER_DOMAIN_PORT_DSI) |		\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-- 
2.32.0

[Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Vandita Kulkarni]

For the PHY enable/disable signalling to propagate
between Dispaly and PHY, DDI clocks need to be running when
enabling the PHY.

Bspec: 49188 says gate the clocks after enabling the
       DDI Buffer.
       We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
       clocks after pll mapping") which gates the clocks much before,
       as per the older spec. This commit nullifies its effect and makes
       sure that the clocks are not gated while we enable the DDI
       buffer.
v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 63dd75c6448a..e5ef5c4a32d7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1135,8 +1135,6 @@ static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
 
@@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* step 4c: configure voltage swing and skew */
 	gen11_dsi_voltage_swing_program_seq(encoder);
 
+	gen11_dsi_ungate_clocks(encoder);
+
 	/* enable DDI buffer */
 	gen11_dsi_enable_ddi_buffer(encoder);
 
@@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
 	gen11_dsi_configure_transcoder(encoder, crtc_state);
 
-	/* Step 4l: Gate DDI clocks */
-	if (DISPLAY_VER(dev_priv) == 11)
-		gen11_dsi_gate_clocks(encoder);
+	gen11_dsi_gate_clocks(encoder);
 }
 
 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
-- 
2.32.0

Re: [Intel-gfx] [V2 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

[Jani Nikula]

On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> v2: Fix the typo, move out the hardcoding from
>     macro(Jani, Ville)
>
> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h        | 4 +++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 168c84a74d30..63dd75c6448a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1271,7 +1271,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(i915) == 13) {
>  		for_each_dsi_port(port, intel_dsi->ports)
>  			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> -				     TGL_DSI_CHKN_LSHS_GB, 0x4);
> +				     TGL_DSI_CHKN_LSHS_GB_MASK,
> +				     TGL_DSI_CHKN_LSHS_GB(4));
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9f7a729333f..749b043a3ee3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11715,7 +11715,9 @@ enum skl_power_gate {
>  #define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\
>  						    _TGL_DSI_CHKN_REG_0, \
>  						    _TGL_DSI_CHKN_REG_1)
> -#define TGL_DSI_CHKN_LSHS_GB			REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB_MASK		REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)	REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
> +							       (byte_clocks))
>  
>  /* Display Stream Splitter Control */
>  #define DSS_CTL1				_MMIO(0x67400)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support

[Jani Nikula]

On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Update ADL_P device info to support DSI0, DSI1
>
> v2: Re-define cpu_transcoder_mask only (Jani)
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..44c3577be748 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
>  #define XE_LPD_FEATURES \
>  	.abox_mask = GENMASK(1, 0),						\
>  	.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },		\
> -	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |		\
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),				\
>  	.dbuf.size = 4096,							\
>  	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
>  		BIT(DBUF_S4),							\
> @@ -955,12 +953,16 @@ static const struct intel_device_info adl_s_info = {
>  		[TRANSCODER_B] = PIPE_B_OFFSET,					\
>  		[TRANSCODER_C] = PIPE_C_OFFSET,					\
>  		[TRANSCODER_D] = PIPE_D_OFFSET,					\
> +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
> +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
>  	},									\
>  	.trans_offsets = {							\
>  		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
>  		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
>  		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
>  		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
> +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
> +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
>  	},									\
>  	XE_LPD_CURSOR_OFFSETS
>  
> @@ -969,6 +971,9 @@ static const struct intel_device_info adl_p_info = {
>  	XE_LPD_FEATURES,
>  	PLATFORM(INTEL_ALDERLAKE_P),
>  	.require_force_probe = 1,
> +	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> +			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>  	.display.has_cdclk_crawl = 1,
>  	.display.has_modular_fia = 1,
>  	.display.has_psr_hw_tracking = 0,
> @@ -1038,6 +1043,8 @@ static const struct intel_device_info dg2_info = {
>  		BIT(VECS0) | BIT(VECS1) |
>  		BIT(VCS0) | BIT(VCS2),
>  	.require_force_probe = 1,
> +	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>  };
>  
>  #undef PLATFORM

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP (rev2)

[Patchwork]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev2)
URL   : https://patchwork.freedesktop.org/series/95928/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable MIPI DSI video mode on ADLP (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7121 bytes --]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev2)
URL   : https://patchwork.freedesktop.org/series/95928/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21382
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/index.html

Known issues
------------

  Here are the changes found in Patchwork_21382 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@query-info:
    - fi-ilk-650:         NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-ilk-650/igt@amdgpu/amd_basic@query-info.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][2] ([fdo#109315])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-soraka:      [PASS][4] -> [DMESG-WARN][5] ([i915#1982] / [i915#262])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][7] ([i915#1155])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][8] -> [INCOMPLETE][9] ([i915#3921])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-ilk-650:         NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][15] ([i915#3301])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-bdw-5557u:       NOTRUN -> [FAIL][16] ([i915#1602] / [i915#2029] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [DMESG-WARN][17] ([i915#4269]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-icl-u2:          [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#3363] / [i915#4312])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@runner@aborted.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-icl-u2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312


Participating hosts (36 -> 36)
------------------------------

  Additional (2): fi-tgl-1115g4 fi-ilk-650 
  Missing    (2): fi-bsw-cyan bat-dg1-6 


Build changes
-------------

  * Linux: CI_DRM_10762 -> Patchwork_21382

  CI-20190529: 20190529
  CI_DRM_10762: 448b23374caeafa59d2a057fdc1a7c069b934960 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6255: 9b0881254557edeaf273b2196309fc4e22ea0312 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21382: dda5618485fd640a0559af9e9ebdfe8b463f97a2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

dda5618485fd drm/i915/dsi: Ungate clock before enabling the phy
741c72fc39e7 drm/i915/dsi/xelpd: Disable DC states in Video mode
793e283eb63e drm/i915/dsi/xelpd: Add DSI transcoder support
359b62228634 drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/index.html

[-- Attachment #2: Type: text/html, Size: 8390 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable MIPI DSI video mode on ADLP (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev2)
URL   : https://patchwork.freedesktop.org/series/95928/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21382_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_21382_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@gem_create@create-massive.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][2] ([i915#3002])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb5/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglb:         NOTRUN -> [SKIP][4] ([i915#280]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb2/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@unwedge-stress:
    - shard-skl:          [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@gem_eio@unwedge-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl9/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][9] ([i915#2842]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][12] -> [SKIP][13] ([i915#2190])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb1/igt@gem_huc_copy@huc-copy.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][14] ([i915#2658])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([i915#4270])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-snb:          NOTRUN -> [FAIL][16] ([i915#2724])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@gem_userptr_blits@vma-merge.html
    - shard-apl:          NOTRUN -> [FAIL][17] ([i915#3318])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          NOTRUN -> [DMESG-WARN][18] ([i915#180])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl6/igt@gem_workarounds@suspend-resume-context.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#2856])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglb:         NOTRUN -> [WARN][20] ([i915#2681] / [i915#2684])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#2411] / [i915#456]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb7/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#2521])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@crc:
    - shard-skl:          NOTRUN -> [FAIL][25] ([i915#4272])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl4/igt@kms_async_flips@crc.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][27] ([i915#3743]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([fdo#111615]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-tglb:         NOTRUN -> [FAIL][31] ([i915#1385])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][32] ([i915#4298]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl7/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-snb:          NOTRUN -> [FAIL][33] ([i915#4299])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl3/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +12 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
    - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271]) +388 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3689]) +3 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-skl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +31 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +17 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl3/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-75:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109284] / [fdo#111827])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html

  * igt@kms_content_protection@mei_interface:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([fdo#111828])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_content_protection@mei_interface.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-random:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([fdo#109279] / [i915#3359])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3359]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271]) +46 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109278])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#3319]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][54] -> [FAIL][55] ([i915#2122])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2672])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          NOTRUN -> [SKIP][57] ([fdo#109271]) +317 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][58] ([fdo#111825]) +13 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109280])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][64] ([i915#265])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][66] -> [FAIL][67] ([fdo#108145] / [i915#265])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
    - shard-skl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658]) +6 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@kms_psr2_su@page_flip:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([i915#1911])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_psr2_su@page_flip.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][73] ([fdo#109271]) +144 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl2/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl6/igt@kms_writeback@writeback-fb-id.html

  * igt@nouveau_crc@pipe-a-source-outp-complete:
    - shard-tglb:         NOTRUN -> [SKIP][75] ([i915#2530])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@nouveau_crc@pipe-a-source-outp-complete.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][76] -> [FAIL][77] ([i915#1542]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl9/igt@perf@blocking.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl7/igt@perf@blocking.html

  * igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([fdo#109291])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html

  * igt@prime_nv_api@nv_self_import_to_different_fd:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([fdo#109291]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@prime_nv_api@nv_self_import_to_different_fd.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +4 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@pidname:
    - shard-skl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@recycle:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl2/igt@sysfs_clients@recycle.html

  * igt@sysfs_clients@sema-50:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#2994])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@sysfs_clients@sema-50.html

  * igt@sysfs_clients@split-10:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([i915#2994])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb5/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [TIMEOUT][85] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb7/igt@gem_eio@unwedge-stress.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb8/igt@gem_eio@unwedge-stress.html
    - shard-iclb:         [TIMEOUT][87] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_eio@unwedge-stress.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb4/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][89] ([i915#2842]) -> [PASS][90] +2 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][91] ([i915#2842]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][93] ([i915#2842]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-iclb:         [INCOMPLETE][95] ([i915#1895]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@gem_spin_batch@resubmit-new-all@vecs0:
    - shard-skl:          [DMESG-WARN][97] ([i915#1982]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@gem_spin_batch@resubmit-new-all@vecs0.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl2/igt@gem_spin_batch@resubmit-new-all@vecs0.html

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [INCOMPLETE][99] ([i915#198]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl2/igt@gem_workarounds@suspend-resume.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl4/igt@gem_workarounds@suspend-resume.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][101] ([i915#1436] / [i915#716]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@gen9_exec_parse@allowed-single.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [INCOMPLETE][103] ([i915#3921]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-snb7/igt@i915_selftest@live@hangcheck.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@perf@region:
    - shard-iclb:         [INCOMPLETE][105] -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb4/igt@i915_selftest@perf@region.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb1/igt@i915_selftest@perf@region.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][107] ([i915#118]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-snb:          [SKIP][109] ([fdo#109271]) -> [PASS][110] +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-snb7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][111] ([i915#180]) -> [PASS][112] +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
    - shard-tglb:         [INCOMPLETE][113] ([i915#2411] / [i915#456]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][115] ([i915#2346] / [i915#533]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][117] ([i915#2122]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-skl:          [FAIL][119] ([i915#79]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][121] ([i915#180]) -> [PASS][122] +6 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          [FAIL][123] ([i915#2122]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][125] ([i915#1188]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@kms_hdr@bpc-switch.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl9/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][127] ([fdo#108145] / [i915#265]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [FAIL][129] ([i915#1542]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk8/igt@perf@polling-parameterized.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-glk6/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][131] ([i915#2842]) -> [FAIL][132] ([i915#2852])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][133] ([i915#2842]) -> [FAIL][134] ([i915#2849])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][135] ([i915#1804] / [i915#2684]) -> [WARN][136] ([i915#2684])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][137] ([i915#2684]) -> [WARN][138] ([i915#1804] / [i915#2684])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
   [13

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/index.html

[-- Attachment #2: Type: text/html, Size: 33632 bytes --]

Re: [Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode

[Imre Deak]

On Tue, Oct 19, 2021 at 08:44:34PM +0530, Vandita Kulkarni wrote:
> MIPI DSI transcoder cannot be in video mode to support any of the
> display C states.
> 
> Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode)
> Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI enabled)
> Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control

So none of the DC states (except DC6v which the driver doesn't support)
are supported in DSI video mode and DC3co is supported in command mode.
The selection between video vs. command mode happens using a VBT flag
and I can't see anything that would prevent using command mode on XELPD.
If the support for it is missing, should it be disabled explicitly or at
least a notice printed that DC states are not yet supported?

> v2: Align to the power domain ordering (Jani)
>     Add bspec references (Imre)
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d88da0d0f05a..b989ddd3d023 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
>  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> +	BIT_ULL(POWER_DOMAIN_PORT_DSI) |		\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> -- 
> 2.32.0
> 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP (rev3)

[Patchwork]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev3)
URL   : https://patchwork.freedesktop.org/series/95928/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Jani Nikula]

On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> For the PHY enable/disable signalling to propagate
> between Dispaly and PHY, DDI clocks need to be running when
> enabling the PHY.
>
> Bspec: 49188 says gate the clocks after enabling the
>        DDI Buffer.
>        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
>        clocks after pll mapping") which gates the clocks much before,
>        as per the older spec. This commit nullifies its effect and makes
>        sure that the clocks are not gated while we enable the DDI
>        buffer.
> v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 63dd75c6448a..e5ef5c4a32d7 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1135,8 +1135,6 @@ static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
>  	/* step 4a: power up all lanes of the DDI used by DSI */
>  	gen11_dsi_power_up_lanes(encoder);
>  
> @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  	/* step 4c: configure voltage swing and skew */
>  	gen11_dsi_voltage_swing_program_seq(encoder);
>  
> +	gen11_dsi_ungate_clocks(encoder);
> +

What about the changes to gen11_dsi_map_pll() in commit 991d9557b0c4
("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It starts
off with clocks gated for gen12+, ungated otherwise.

BR,
Jani.


>  	/* enable DDI buffer */
>  	gen11_dsi_enable_ddi_buffer(encoder);
>  
> @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>  	gen11_dsi_configure_transcoder(encoder, crtc_state);
>  
> -	/* Step 4l: Gate DDI clocks */
> -	if (DISPLAY_VER(dev_priv) == 11)
> -		gen11_dsi_gate_clocks(encoder);
> +	gen11_dsi_gate_clocks(encoder);
>  }
>  
>  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable MIPI DSI video mode on ADLP (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2450 bytes --]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev3)
URL   : https://patchwork.freedesktop.org/series/95928/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10806 -> Patchwork_21472
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/index.html

Participating hosts (35 -> 31)
------------------------------

  Missing    (4): fi-icl-u2 bat-adlp-4 bat-dg1-6 bat-dg1-5 

Known issues
------------

  Here are the changes found in Patchwork_21472 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][2] ([i915#3921]) -> [PASS][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921


Build changes
-------------

  * Linux: CI_DRM_10806 -> Patchwork_21472

  CI-20190529: 20190529
  CI_DRM_10806: c5b79188b859e8ba29efe0637a3897f7cccd4f99 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6262: d1c793b26e31cc6ae3f9fa3239805a9bbcc749fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21472: be594d558a3eef5553b8df0f4bef61e626bc9707 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

be594d558a3e drm/i915/dsi: Ungate clock before enabling the phy
5227d715ebc1 drm/i915/dsi/xelpd: Disable DC states in Video mode
e11445c08b71 drm/i915/dsi/xelpd: Add DSI transcoder support
573e6d84f122 drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/index.html

[-- Attachment #2: Type: text/html, Size: 3027 bytes --]

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Kulkarni, Vandita]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, October 28, 2021 5:13 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com; Kulkarni,
> Vandita <vandita.kulkarni@intel.com>
> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> 
> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> > For the PHY enable/disable signalling to propagate between Dispaly and
> > PHY, DDI clocks need to be running when enabling the PHY.
> >
> > Bspec: 49188 says gate the clocks after enabling the
> >        DDI Buffer.
> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
> >        clocks after pll mapping") which gates the clocks much before,
> >        as per the older spec. This commit nullifies its effect and makes
> >        sure that the clocks are not gated while we enable the DDI
> >        buffer.
> > v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)
> >
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 63dd75c6448a..e5ef5c4a32d7 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1135,8 +1135,6 @@ static void
> >  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >  			      const struct intel_crtc_state *crtc_state)  {
> > -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -
> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> >  	gen11_dsi_power_up_lanes(encoder);
> >
> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> >  	/* step 4c: configure voltage swing and skew */
> >  	gen11_dsi_voltage_swing_program_seq(encoder);
> >
> > +	gen11_dsi_ungate_clocks(encoder);
> > +
> 
> What about the changes to gen11_dsi_map_pll() in commit 991d9557b0c4
> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It starts off with
> clocks gated for gen12+, ungated otherwise.

Now the same spec is updated with the gate step after ddi buffer enable.
And the one before is marked with remove tag.
That makes all gen12+ align with gen 11.
You suggested to update the same in the commit message on v1.
Should I still consider just reverting that commit?

Thanks,
Vandita

> 
> BR,
> Jani.
> 
> 
> >  	/* enable DDI buffer */
> >  	gen11_dsi_enable_ddi_buffer(encoder);
> >
> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
> >
> > -	/* Step 4l: Gate DDI clocks */
> > -	if (DISPLAY_VER(dev_priv) == 11)
> > -		gen11_dsi_gate_clocks(encoder);
> > +	gen11_dsi_gate_clocks(encoder);
> >  }
> >
> >  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode

[Kulkarni, Vandita]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Saturday, October 23, 2021 1:53 AM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Roper, Matthew D <matthew.d.roper@intel.com>;
> ville.syrjala@linux.intel.com
> Subject: Re: [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
> 
> On Tue, Oct 19, 2021 at 08:44:34PM +0530, Vandita Kulkarni wrote:
> > MIPI DSI transcoder cannot be in video mode to support any of the
> > display C states.
> >
> > Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode)
> > Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI
> > enabled)
> > Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control
> 
> So none of the DC states (except DC6v which the driver doesn't support) are
> supported in DSI video mode and DC3co is supported in command mode.
> The selection between video vs. command mode happens using a VBT flag
> and I can't see anything that would prevent using command mode on XELPD.
> If the support for it is missing, should it be disabled explicitly or at least a
> notice printed that DC states are not yet supported?

Since we haven't enabled and tried dsi cmd mode on xelpd and in DC3co DMC
Would monitor the idleness of the transcoder, until that is enabled, we can disable
Cmd mode for now.
Will send out a patch to disable cmd mode on xelpd, as it would by default depend on
Vbt like you have mentioned above.

Thanks,
Vandita
 
> 
> > v2: Align to the power domain ordering (Jani)
> >     Add bspec references (Imre)
> >
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_power.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index d88da0d0f05a..b989ddd3d023 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DSI) |		\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >
> >  #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS
> 	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> > --
> > 2.32.0
> >

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Jani Nikula]

On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Thursday, October 28, 2021 5:13 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com; Kulkarni,
>> Vandita <vandita.kulkarni@intel.com>
>> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>> 
>> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> > For the PHY enable/disable signalling to propagate between Dispaly and
>> > PHY, DDI clocks need to be running when enabling the PHY.
>> >
>> > Bspec: 49188 says gate the clocks after enabling the
>> >        DDI Buffer.
>> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
>> >        clocks after pll mapping") which gates the clocks much before,
>> >        as per the older spec. This commit nullifies its effect and makes
>> >        sure that the clocks are not gated while we enable the DDI
>> >        buffer.
>> > v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)
>> >
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
>> >  1 file changed, 3 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 63dd75c6448a..e5ef5c4a32d7 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1135,8 +1135,6 @@ static void
>> >  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> >  			      const struct intel_crtc_state *crtc_state)  {
>> > -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > -
>> >  	/* step 4a: power up all lanes of the DDI used by DSI */
>> >  	gen11_dsi_power_up_lanes(encoder);
>> >
>> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> >  	/* step 4c: configure voltage swing and skew */
>> >  	gen11_dsi_voltage_swing_program_seq(encoder);
>> >
>> > +	gen11_dsi_ungate_clocks(encoder);
>> > +
>> 
>> What about the changes to gen11_dsi_map_pll() in commit 991d9557b0c4
>> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It starts off with
>> clocks gated for gen12+, ungated otherwise.
>
> Now the same spec is updated with the gate step after ddi buffer enable.
> And the one before is marked with remove tag.
> That makes all gen12+ align with gen 11.
> You suggested to update the same in the commit message on v1.
> Should I still consider just reverting that commit?

I'm just royally confused about the sequence myself, so I'm asking
you. ;)

It doesn't help that the code has step references to gen 11 mode set
that are completely different from the steps in gen 12 sequence.

BR,
Jani.



>
> Thanks,
> Vandita
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> >  	/* enable DDI buffer */
>> >  	gen11_dsi_enable_ddi_buffer(encoder);
>> >
>> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
>> >
>> > -	/* Step 4l: Gate DDI clocks */
>> > -	if (DISPLAY_VER(dev_priv) == 11)
>> > -		gen11_dsi_gate_clocks(encoder);
>> > +	gen11_dsi_gate_clocks(encoder);
>> >  }
>> >
>> >  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Kulkarni, Vandita]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, October 28, 2021 8:06 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> 
> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Thursday, October 28, 2021 5:13 PM
> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com; Kulkarni,
> >> Vandita <vandita.kulkarni@intel.com>
> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
> >> phy
> >>
> >> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
> wrote:
> >> > For the PHY enable/disable signalling to propagate between Dispaly
> >> > and PHY, DDI clocks need to be running when enabling the PHY.
> >> >
> >> > Bspec: 49188 says gate the clocks after enabling the
> >> >        DDI Buffer.
> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the
> ddi
> >> >        clocks after pll mapping") which gates the clocks much before,
> >> >        as per the older spec. This commit nullifies its effect and makes
> >> >        sure that the clocks are not gated while we enable the DDI
> >> >        buffer.
> >> > v2: Bspec ref, add a comment wrt earlier clock gating sequence
> >> > (Jani)
> >> >
> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > @@ -1135,8 +1135,6 @@ static void
> >> >  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >> >  			      const struct intel_crtc_state *crtc_state)  {
> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >> > -
> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> >> >  	gen11_dsi_power_up_lanes(encoder);
> >> >
> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> >  	/* step 4c: configure voltage swing and skew */
> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
> >> >
> >> > +	gen11_dsi_ungate_clocks(encoder);
> >> > +
> >>
> >> What about the changes to gen11_dsi_map_pll() in commit 991d9557b0c4
> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It
> >> starts off with clocks gated for gen12+, ungated otherwise.
> >
> > Now the same spec is updated with the gate step after ddi buffer enable.
> > And the one before is marked with remove tag.
> > That makes all gen12+ align with gen 11.
> > You suggested to update the same in the commit message on v1.
> > Should I still consider just reverting that commit?
> 
> I'm just royally confused about the sequence myself, so I'm asking you. ;)
> 
> It doesn't help that the code has step references to gen 11 mode set that are
> completely different from the steps in gen 12 sequence.

Right, they have lot of different steps coming in.
As per gen11 sequence, we were gating pll after enabling ddi buffer.

Initially when there was only gen12 in the bspec, it stated to gate the pll after mapping.
Hence we had that commit  991d9557b0c4.
Then Gen12's mipi dsi sequence was carried fwd for all later platforms as well.
 with the modification saying that
Do not gate the pll until we enable the ddi buffer. 
And this applies to gen 12 as well because they have marked the earlier mentioned step of gating pll
after pll mapping as removed on all gen12 and later platforms.

This patch now is keeping the older step as is, but making sure that clocks are ungated while enabling ddi buffer.

Thanks
Vandita
> 
> BR,
> Jani.
> 
> 
> 
> >
> > Thanks,
> > Vandita
> >
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> >  	/* enable DDI buffer */
> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
> >> >
> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
> >> >
> >> > -	/* Step 4l: Gate DDI clocks */
> >> > -	if (DISPLAY_VER(dev_priv) == 11)
> >> > -		gen11_dsi_gate_clocks(encoder);
> >> > +	gen11_dsi_gate_clocks(encoder);
> >> >  }
> >> >
> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode

[Imre Deak]

On Thu, Oct 28, 2021 at 04:53:22PM +0300, Kulkarni, Vandita wrote:
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Saturday, October 23, 2021 1:53 AM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> > Roper, Matthew D <matthew.d.roper@intel.com>;
> > ville.syrjala@linux.intel.com
> > Subject: Re: [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
> > 
> > On Tue, Oct 19, 2021 at 08:44:34PM +0530, Vandita Kulkarni wrote:
> > > MIPI DSI transcoder cannot be in video mode to support any of the
> > > display C states.
> > >
> > > Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode)
> > > Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI
> > > enabled)
> > > Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control
> > 
> > So none of the DC states (except DC6v which the driver doesn't support) are
> > supported in DSI video mode and DC3co is supported in command mode.
> > The selection between video vs. command mode happens using a VBT flag
> > and I can't see anything that would prevent using command mode on XELPD.
> > If the support for it is missing, should it be disabled explicitly or at least a
> > notice printed that DC states are not yet supported?
> 
> Since we haven't enabled and tried dsi cmd mode on xelpd and in DC3co
> DMC Would monitor the idleness of the transcoder, until that is
> enabled, we can disable Cmd mode for now.  Will send out a patch to
> disable cmd mode on xelpd, as it would by default depend on Vbt like
> you have mentioned above.

Ok. On this patch:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> 
> Thanks,
> Vandita
>  
> > 
> > > v2: Align to the power domain ordering (Jani)
> > >     Add bspec references (Imre)
> > >
> > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_power.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index d88da0d0f05a..b989ddd3d023 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > >  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > > +	BIT_ULL(POWER_DOMAIN_PORT_DSI) |		\
> > >  	BIT_ULL(POWER_DOMAIN_INIT))
> > >
> > >  #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS
> > 	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> > > --
> > > 2.32.0
> > >

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable MIPI DSI video mode on ADLP (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]

== Series Details ==

Series: Enable MIPI DSI video mode on ADLP (rev3)
URL   : https://patchwork.freedesktop.org/series/95928/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10806_full -> Patchwork_21472_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_21472_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-2x:
    - shard-tglb:         NOTRUN -> [SKIP][1] ([i915#1839])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb8/igt@feature_discovery@display-2x.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-tglb:         NOTRUN -> [SKIP][2] ([fdo#109314])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb8/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-apl:          NOTRUN -> [SKIP][3] ([fdo#109271]) +72 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         NOTRUN -> [TIMEOUT][4] ([i915#2369] / [i915#3063] / [i915#3648])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
    - shard-apl:          [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [PASS][11] -> [FAIL][12] ([i915#2842] / [i915#3468])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
    - shard-glk:          NOTRUN -> [SKIP][13] ([fdo#109271]) +38 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-kbl:          NOTRUN -> [FAIL][14] ([i915#3318])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_mixed_blits:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([fdo#109289])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@gen3_mixed_blits.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-tglb:         NOTRUN -> [SKIP][16] ([i915#2856]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-skl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl6/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([i915#454]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][20] -> [INCOMPLETE][21] ([i915#3921])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-snb4/igt@i915_selftest@live@hangcheck.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-snb4/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@forcewake:
    - shard-skl:          [PASS][22] -> [INCOMPLETE][23] ([i915#636])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl7/igt@i915_suspend@forcewake.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl6/igt@i915_suspend@forcewake.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +4 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-apl4/igt@i915_suspend@sysfs-reader.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([fdo#111614])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([i915#118]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-glk3/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][31] ([i915#3743]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#111615]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([i915#3689])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +5 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl3/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-glk:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@hdmi-crc-nonplanar-formats:
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#109284] / [fdo#111827])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-skl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color@pipe-d-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][41] ([fdo#109271]) +223 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl6/igt@kms_color@pipe-d-ctm-max.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@kms_color_chamelium@pipe-c-ctm-max.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-25:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl1/igt@kms_color_chamelium@pipe-d-ctm-0-25.html

  * igt@kms_content_protection@lic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][45] ([i915#1319])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl3/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@mei_interface:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#111828])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_content_protection@mei_interface.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#3319]) +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][48] ([i915#180])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-random:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3359])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x10-random.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][50] -> [FAIL][51] ([i915#72])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#4103])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][53] -> [FAIL][54] ([i915#2346] / [i915#533])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3788])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [PASS][57] -> [INCOMPLETE][58] ([i915#198])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl6/igt@kms_fbcon_fbt@psr-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#111825]) +12 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109274])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
    - shard-glk:          [PASS][61] -> [FAIL][62] ([i915#2122])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][63] -> [FAIL][64] ([i915#79])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2672])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-skl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2672])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#109280])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
    - shard-kbl:          NOTRUN -> [SKIP][68] ([fdo#109271]) +95 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][69] -> [FAIL][70] ([i915#1188]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +5 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([i915#1187])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265]) +4 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][77] ([i915#265])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
    - shard-kbl:          NOTRUN -> [FAIL][78] ([i915#265])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][80] -> [FAIL][81] ([fdo#108145] / [i915#265]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-c-tiling-yf:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([i915#3536])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_plane_lowres@pipe-c-tiling-yf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
    - shard-apl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
    - shard-kbl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2920]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
    - shard-glk:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([i915#658])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         NOTRUN -> [SKIP][88] ([fdo#109441])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_psr@psr2_primary_render.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][89] -> [SKIP][90] ([fdo#109441])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_rmfb@rmfb-ioctl:
    - shard-skl:          [PASS][91] -> [DMESG-WARN][92] ([i915#1982])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl1/igt@kms_rmfb@rmfb-ioctl.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl10/igt@kms_rmfb@rmfb-ioctl.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][93] ([IGT#2])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl4/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#109278])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-d.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-skl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2437]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl6/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-d-source-rg:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#2530]) +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@nouveau_crc@pipe-d-source-rg.html

  * igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][97] ([fdo#109291]) +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb8/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html

  * igt@prime_nv_test@i915_import_gtt_mmap:
    - shard-iclb:         NOTRUN -> [SKIP][98] ([fdo#109291])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb6/igt@prime_nv_test@i915_import_gtt_mmap.html

  * igt@sysfs_clients@create:
    - shard-skl:          NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@sysfs_clients@create.html

  * igt@sysfs_clients@recycle:
    - shard-apl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@sysfs_clients@recycle.html

  * igt@sysfs_clients@recycle-many:
    - shard-glk:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk1/igt@sysfs_clients@recycle-many.html
    - shard-tglb:         NOTRUN -> [SKIP][102] ([i915#2994])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb2/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@split-50:
    - shard-kbl:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2994])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl6/igt@sysfs_clients@split-50.html

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - shard-skl:          [PASS][104] -> [FAIL][105] ([i915#1731]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl2/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  * igt@sysfs_heartbeat_interval@mixed@vcs0:
    - shard-skl:          [PASS][106] -> [WARN][107] ([i915#4055])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vcs0.html

  
#### Possible fixes ####

  * igt@drm_mm@all@insert:
    - shard-skl:          [INCOMPLETE][108] ([i915#2485]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl2/igt@drm_mm@all@insert.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl1/igt@drm_mm@all@insert.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [FAIL][110] ([i915#2410]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglb:         [FAIL][112] ([i915#2842]) -> [PASS][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][114] ([i915#2842]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][116] ([i915#2842]) -> [PASS][117] +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-skl:          [INCOMPLETE][118] ([i915#198]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl1/igt@gem_workarounds@suspend-resume-context.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl8/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-snb:          [SKIP][120] ([fdo#109271]) -> [PASS][121] +3 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-snb6/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-snb6/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_color@pipe-b-ctm-0-75:
    - shard-skl:          [DMESG-WARN][122] ([i915#1982]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl8/igt@kms_color@pipe-b-ctm-0-75.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl8/igt@kms_color@pipe-b-ctm-0-75.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][124] ([i915#180]) -> [PASS][125] +6 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
    - shard-skl:          [FAIL][126] ([i915#2122]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
    - shard-iclb:         [SKIP][128] ([i915#3701]) -> [PASS][129] +2 similar issues
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-tglb:         [INCOMPLETE][130] ([i915#4184] / [i915#456]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-tglb8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][132] ([fdo#108145] / [i915#265]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][134] ([fdo#109441]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][136] ([i915#180]) -> [PASS][137] +1 similar issue
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][138] ([i915#1542]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10806/shard-skl1/igt@perf@polling-parameterized.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Pa

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21472/index.html

[-- Attachment #2: Type: text/html, Size: 33630 bytes --]

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Jani Nikula]

On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Thursday, October 28, 2021 8:06 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
>> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>> 
>> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
>> wrote:
>> >> -----Original Message-----
>> >> From: Nikula, Jani <jani.nikula@intel.com>
>> >> Sent: Thursday, October 28, 2021 5:13 PM
>> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> >> gfx@lists.freedesktop.org
>> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com; Kulkarni,
>> >> Vandita <vandita.kulkarni@intel.com>
>> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
>> >> phy
>> >>
>> >> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
>> wrote:
>> >> > For the PHY enable/disable signalling to propagate between Dispaly
>> >> > and PHY, DDI clocks need to be running when enabling the PHY.
>> >> >
>> >> > Bspec: 49188 says gate the clocks after enabling the
>> >> >        DDI Buffer.
>> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the
>> ddi
>> >> >        clocks after pll mapping") which gates the clocks much before,
>> >> >        as per the older spec. This commit nullifies its effect and makes
>> >> >        sure that the clocks are not gated while we enable the DDI
>> >> >        buffer.
>> >> > v2: Bspec ref, add a comment wrt earlier clock gating sequence
>> >> > (Jani)
>> >> >
>> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
>> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
>> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> > @@ -1135,8 +1135,6 @@ static void
>> >> >  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> >> >  			      const struct intel_crtc_state *crtc_state)  {
>> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> >> > -
>> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
>> >> >  	gen11_dsi_power_up_lanes(encoder);
>> >> >
>> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
>> >> intel_encoder *encoder,
>> >> >  	/* step 4c: configure voltage swing and skew */
>> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
>> >> >
>> >> > +	gen11_dsi_ungate_clocks(encoder);
>> >> > +
>> >>
>> >> What about the changes to gen11_dsi_map_pll() in commit 991d9557b0c4
>> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It
>> >> starts off with clocks gated for gen12+, ungated otherwise.
>> >
>> > Now the same spec is updated with the gate step after ddi buffer enable.
>> > And the one before is marked with remove tag.
>> > That makes all gen12+ align with gen 11.
>> > You suggested to update the same in the commit message on v1.
>> > Should I still consider just reverting that commit?
>> 
>> I'm just royally confused about the sequence myself, so I'm asking you. ;)
>> 
>> It doesn't help that the code has step references to gen 11 mode set that are
>> completely different from the steps in gen 12 sequence.
>
> Right, they have lot of different steps coming in.
> As per gen11 sequence, we were gating pll after enabling ddi buffer.
>
> Initially when there was only gen12 in the bspec, it stated to gate the pll after mapping.
> Hence we had that commit  991d9557b0c4.
> Then Gen12's mipi dsi sequence was carried fwd for all later platforms as well.
>  with the modification saying that
> Do not gate the pll until we enable the ddi buffer. 
> And this applies to gen 12 as well because they have marked the earlier mentioned step of gating pll
> after pll mapping as removed on all gen12 and later platforms.
>
> This patch now is keeping the older step as is, but making sure that clocks are ungated while enabling ddi buffer.

Where does it say for gen12+ that clocks should be ungated at any point?

My reading of the spec:

Gen11, bspec 20845 and 20597:
- start with clocks ungated at mapping
- gate after port/phy enabling (step 4m in gen11 mode set sequence)

Gen12, bspec 49204, 49188 and 55316:
- start with clocks gated at mapping
- gate *if* not already gated (steps 4c and 4i in gen12 mode set sequence)

It may be that your patch is correct, but IMO it does not match bspec.


BR,
Jani.



>
> Thanks
> Vandita
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> >
>> > Thanks,
>> > Vandita
>> >
>> >>
>> >> BR,
>> >> Jani.
>> >>
>> >>
>> >> >  	/* enable DDI buffer */
>> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
>> >> >
>> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
>> >> intel_encoder *encoder,
>> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
>> >> >
>> >> > -	/* Step 4l: Gate DDI clocks */
>> >> > -	if (DISPLAY_VER(dev_priv) == 11)
>> >> > -		gen11_dsi_gate_clocks(encoder);
>> >> > +	gen11_dsi_gate_clocks(encoder);
>> >> >  }
>> >> >
>> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>> >>
>> >> --
>> >> Jani Nikula, Intel Open Source Graphics Center
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Kulkarni, Vandita]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, November 1, 2021 5:37 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> 
> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Thursday, October 28, 2021 8:06 PM
> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
> >> phy
> >>
> >> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> >> wrote:
> >> >> -----Original Message-----
> >> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> >> Sent: Thursday, October 28, 2021 5:13 PM
> >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> >> gfx@lists.freedesktop.org
> >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com;
> >> >> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> >> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling
> >> >> the phy
> >> >>
> >> >> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> wrote:
> >> >> > For the PHY enable/disable signalling to propagate between
> >> >> > Dispaly and PHY, DDI clocks need to be running when enabling the
> PHY.
> >> >> >
> >> >> > Bspec: 49188 says gate the clocks after enabling the
> >> >> >        DDI Buffer.
> >> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi:
> >> >> > Gate the
> >> ddi
> >> >> >        clocks after pll mapping") which gates the clocks much before,
> >> >> >        as per the older spec. This commit nullifies its effect and makes
> >> >> >        sure that the clocks are not gated while we enable the DDI
> >> >> >        buffer.
> >> >> > v2: Bspec ref, add a comment wrt earlier clock gating sequence
> >> >> > (Jani)
> >> >> >
> >> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> >> > ---
> >> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> >> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >> >> >
> >> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> > @@ -1135,8 +1135,6 @@ static void
> >> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >> >> >  			      const struct intel_crtc_state *crtc_state)
> {
> >> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> >> >> > -
> >> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> >> >> >  	gen11_dsi_power_up_lanes(encoder);
> >> >> >
> >> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> >> >> intel_encoder *encoder,
> >> >> >  	/* step 4c: configure voltage swing and skew */
> >> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
> >> >> >
> >> >> > +	gen11_dsi_ungate_clocks(encoder);
> >> >> > +
> >> >>
> >> >> What about the changes to gen11_dsi_map_pll() in commit
> >> >> 991d9557b0c4
> >> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It
> >> >> starts off with clocks gated for gen12+, ungated otherwise.
> >> >
> >> > Now the same spec is updated with the gate step after ddi buffer
> enable.
> >> > And the one before is marked with remove tag.
> >> > That makes all gen12+ align with gen 11.
> >> > You suggested to update the same in the commit message on v1.
> >> > Should I still consider just reverting that commit?
> >>
> >> I'm just royally confused about the sequence myself, so I'm asking
> >> you. ;)
> >>
> >> It doesn't help that the code has step references to gen 11 mode set
> >> that are completely different from the steps in gen 12 sequence.
> >
> > Right, they have lot of different steps coming in.
> > As per gen11 sequence, we were gating pll after enabling ddi buffer.
> >
> > Initially when there was only gen12 in the bspec, it stated to gate the pll
> after mapping.
> > Hence we had that commit  991d9557b0c4.
> > Then Gen12's mipi dsi sequence was carried fwd for all later platforms as
> well.
> >  with the modification saying that
> > Do not gate the pll until we enable the ddi buffer.
> > And this applies to gen 12 as well because they have marked the
> > earlier mentioned step of gating pll after pll mapping as removed on all
> gen12 and later platforms.
> >
> > This patch now is keeping the older step as is, but making sure that clocks
> are ungated while enabling ddi buffer.
> 
> Where does it say for gen12+ that clocks should be ungated at any point?
> 
> My reading of the spec:
> 
> Gen11, bspec 20845 and 20597:
> - start with clocks ungated at mapping
> - gate after port/phy enabling (step 4m in gen11 mode set sequence)
> 
> Gen12, bspec 49204, 49188 and 55316:
> - start with clocks gated at mapping
> - gate *if* not already gated (steps 4c and 4i in gen12 mode set sequence)

Right the ungate step is not mentioned in the bspec.
Instead the step 4.c is marked as Removed.
I had added ungate just to make sure we are addressing the issue mentioned in front of removed tag while
Retaining the old sequence of 4.c

In order to completely adhere to the current bspec, I can
1. submit a patch removing 4.c
or
2.  submit a revert of the patch which was adding 4.c
("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")

Thanks,
Vandita
> 
> It may be that your patch is correct, but IMO it does not match bspec.
> 
> 
> BR,
> Jani.
> 
> 
> 
> >
> > Thanks
> > Vandita
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >> >
> >> > Thanks,
> >> > Vandita
> >> >
> >> >>
> >> >> BR,
> >> >> Jani.
> >> >>
> >> >>
> >> >> >  	/* enable DDI buffer */
> >> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
> >> >> >
> >> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> >> >> intel_encoder *encoder,
> >> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
> >> >> >
> >> >> > -	/* Step 4l: Gate DDI clocks */
> >> >> > -	if (DISPLAY_VER(dev_priv) == 11)
> >> >> > -		gen11_dsi_gate_clocks(encoder);
> >> >> > +	gen11_dsi_gate_clocks(encoder);
> >> >> >  }
> >> >> >
> >> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder
> >> >> > *encoder)
> >> >>
> >> >> --
> >> >> Jani Nikula, Intel Open Source Graphics Center
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Jani Nikula]

On Tue, 02 Nov 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Monday, November 1, 2021 5:37 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
>> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>> 
>> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
>> wrote:
>> >> -----Original Message-----
>> >> From: Nikula, Jani <jani.nikula@intel.com>
>> >> Sent: Thursday, October 28, 2021 8:06 PM
>> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> >> gfx@lists.freedesktop.org
>> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
>> >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
>> >> phy
>> >>
>> >> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
>> >> wrote:
>> >> >> -----Original Message-----
>> >> >> From: Nikula, Jani <jani.nikula@intel.com>
>> >> >> Sent: Thursday, October 28, 2021 5:13 PM
>> >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> >> >> gfx@lists.freedesktop.org
>> >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com;
>> >> >> Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> >> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before enabling
>> >> >> the phy
>> >> >>
>> >> >> On Tue, 19 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com>
>> >> wrote:
>> >> >> > For the PHY enable/disable signalling to propagate between
>> >> >> > Dispaly and PHY, DDI clocks need to be running when enabling the
>> PHY.
>> >> >> >
>> >> >> > Bspec: 49188 says gate the clocks after enabling the
>> >> >> >        DDI Buffer.
>> >> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi:
>> >> >> > Gate the
>> >> ddi
>> >> >> >        clocks after pll mapping") which gates the clocks much before,
>> >> >> >        as per the older spec. This commit nullifies its effect and makes
>> >> >> >        sure that the clocks are not gated while we enable the DDI
>> >> >> >        buffer.
>> >> >> > v2: Bspec ref, add a comment wrt earlier clock gating sequence
>> >> >> > (Jani)
>> >> >> >
>> >> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> >> >> > ---
>> >> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
>> >> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
>> >> >> >
>> >> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
>> >> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> >> >> > @@ -1135,8 +1135,6 @@ static void
>> >> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> >> >> >  			      const struct intel_crtc_state *crtc_state)
>> {
>> >> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder-
>> >base.dev);
>> >> >> > -
>> >> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
>> >> >> >  	gen11_dsi_power_up_lanes(encoder);
>> >> >> >
>> >> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
>> >> >> intel_encoder *encoder,
>> >> >> >  	/* step 4c: configure voltage swing and skew */
>> >> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
>> >> >> >
>> >> >> > +	gen11_dsi_ungate_clocks(encoder);
>> >> >> > +
>> >> >>
>> >> >> What about the changes to gen11_dsi_map_pll() in commit
>> >> >> 991d9557b0c4
>> >> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It
>> >> >> starts off with clocks gated for gen12+, ungated otherwise.
>> >> >
>> >> > Now the same spec is updated with the gate step after ddi buffer
>> enable.
>> >> > And the one before is marked with remove tag.
>> >> > That makes all gen12+ align with gen 11.
>> >> > You suggested to update the same in the commit message on v1.
>> >> > Should I still consider just reverting that commit?
>> >>
>> >> I'm just royally confused about the sequence myself, so I'm asking
>> >> you. ;)
>> >>
>> >> It doesn't help that the code has step references to gen 11 mode set
>> >> that are completely different from the steps in gen 12 sequence.
>> >
>> > Right, they have lot of different steps coming in.
>> > As per gen11 sequence, we were gating pll after enabling ddi buffer.
>> >
>> > Initially when there was only gen12 in the bspec, it stated to gate the pll
>> after mapping.
>> > Hence we had that commit  991d9557b0c4.
>> > Then Gen12's mipi dsi sequence was carried fwd for all later platforms as
>> well.
>> >  with the modification saying that
>> > Do not gate the pll until we enable the ddi buffer.
>> > And this applies to gen 12 as well because they have marked the
>> > earlier mentioned step of gating pll after pll mapping as removed on all
>> gen12 and later platforms.
>> >
>> > This patch now is keeping the older step as is, but making sure that clocks
>> are ungated while enabling ddi buffer.
>> 
>> Where does it say for gen12+ that clocks should be ungated at any point?
>> 
>> My reading of the spec:
>> 
>> Gen11, bspec 20845 and 20597:
>> - start with clocks ungated at mapping
>> - gate after port/phy enabling (step 4m in gen11 mode set sequence)
>> 
>> Gen12, bspec 49204, 49188 and 55316:
>> - start with clocks gated at mapping
>> - gate *if* not already gated (steps 4c and 4i in gen12 mode set sequence)
>
> Right the ungate step is not mentioned in the bspec.
> Instead the step 4.c is marked as Removed.
> I had added ungate just to make sure we are addressing the issue mentioned in front of removed tag while
> Retaining the old sequence of 4.c
>
> In order to completely adhere to the current bspec, I can
> 1. submit a patch removing 4.c
> or
> 2.  submit a revert of the patch which was adding 4.c
> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")

I think if you remove the call to gen11_dsi_ungate_clocks(encoder) from
this patch, the sequence matches bspec.

But this means the sequence is different between display 11 and 12+, and
the clock will be gated for the entire enabling sequence on 12+. That's
my reading of bspec, anyway.

BR,
Jani.



>
> Thanks,
> Vandita
>> 
>> It may be that your patch is correct, but IMO it does not match bspec.
>> 
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> >
>> > Thanks
>> > Vandita
>> >>
>> >> BR,
>> >> Jani.
>> >>
>> >>
>> >>
>> >> >
>> >> > Thanks,
>> >> > Vandita
>> >> >
>> >> >>
>> >> >> BR,
>> >> >> Jani.
>> >> >>
>> >> >>
>> >> >> >  	/* enable DDI buffer */
>> >> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
>> >> >> >
>> >> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
>> >> >> intel_encoder *encoder,
>> >> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> >> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
>> >> >> >
>> >> >> > -	/* Step 4l: Gate DDI clocks */
>> >> >> > -	if (DISPLAY_VER(dev_priv) == 11)
>> >> >> > -		gen11_dsi_gate_clocks(encoder);
>> >> >> > +	gen11_dsi_gate_clocks(encoder);
>> >> >> >  }
>> >> >> >
>> >> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder
>> >> >> > *encoder)
>> >> >>
>> >> >> --
>> >> >> Jani Nikula, Intel Open Source Graphics Center
>> >>
>> >> --
>> >> Jani Nikula, Intel Open Source Graphics Center
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Kulkarni, Vandita]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, November 2, 2021 3:13 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> 
> On Tue, 02 Nov 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Monday, November 1, 2021 5:37 PM
> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
> >> phy
> >>
> >> On Thu, 28 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> >> wrote:
> >> >> -----Original Message-----
> >> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> >> Sent: Thursday, October 28, 2021 8:06 PM
> >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> >> gfx@lists.freedesktop.org
> >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> >> >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling
> >> >> the phy
> >> >>
> >> >> On Thu, 28 Oct 2021, "Kulkarni, Vandita"
> >> >> <vandita.kulkarni@intel.com>
> >> >> wrote:
> >> >> >> -----Original Message-----
> >> >> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> >> >> Sent: Thursday, October 28, 2021 5:13 PM
> >> >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> >> >> >> gfx@lists.freedesktop.org
> >> >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> >> >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com;
> >> >> >> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> >> >> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before
> >> >> >> enabling the phy
> >> >> >>
> >> >> >> On Tue, 19 Oct 2021, Vandita Kulkarni
> >> >> >> <vandita.kulkarni@intel.com>
> >> >> wrote:
> >> >> >> > For the PHY enable/disable signalling to propagate between
> >> >> >> > Dispaly and PHY, DDI clocks need to be running when enabling
> >> >> >> > the
> >> PHY.
> >> >> >> >
> >> >> >> > Bspec: 49188 says gate the clocks after enabling the
> >> >> >> >        DDI Buffer.
> >> >> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi:
> >> >> >> > Gate the
> >> >> ddi
> >> >> >> >        clocks after pll mapping") which gates the clocks much before,
> >> >> >> >        as per the older spec. This commit nullifies its effect and
> makes
> >> >> >> >        sure that the clocks are not gated while we enable the DDI
> >> >> >> >        buffer.
> >> >> >> > v2: Bspec ref, add a comment wrt earlier clock gating
> >> >> >> > sequence
> >> >> >> > (Jani)
> >> >> >> >
> >> >> >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> >> >> > ---
> >> >> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> >> >> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >> >> >> >
> >> >> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
> >> >> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> >> >> > @@ -1135,8 +1135,6 @@ static void
> >> >> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >> >> >> >  			      const struct intel_crtc_state *crtc_state)
> >> {
> >> >> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder-
> >> >base.dev);
> >> >> >> > -
> >> >> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> >> >> >> >  	gen11_dsi_power_up_lanes(encoder);
> >> >> >> >
> >> >> >> > @@ -1146,6 +1144,8 @@
> gen11_dsi_enable_port_and_phy(struct
> >> >> >> intel_encoder *encoder,
> >> >> >> >  	/* step 4c: configure voltage swing and skew */
> >> >> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
> >> >> >> >
> >> >> >> > +	gen11_dsi_ungate_clocks(encoder);
> >> >> >> > +
> >> >> >>
> >> >> >> What about the changes to gen11_dsi_map_pll() in commit
> >> >> >> 991d9557b0c4
> >> >> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")? It
> >> >> >> starts off with clocks gated for gen12+, ungated otherwise.
> >> >> >
> >> >> > Now the same spec is updated with the gate step after ddi buffer
> >> enable.
> >> >> > And the one before is marked with remove tag.
> >> >> > That makes all gen12+ align with gen 11.
> >> >> > You suggested to update the same in the commit message on v1.
> >> >> > Should I still consider just reverting that commit?
> >> >>
> >> >> I'm just royally confused about the sequence myself, so I'm asking
> >> >> you. ;)
> >> >>
> >> >> It doesn't help that the code has step references to gen 11 mode
> >> >> set that are completely different from the steps in gen 12 sequence.
> >> >
> >> > Right, they have lot of different steps coming in.
> >> > As per gen11 sequence, we were gating pll after enabling ddi buffer.
> >> >
> >> > Initially when there was only gen12 in the bspec, it stated to gate
> >> > the pll
> >> after mapping.
> >> > Hence we had that commit  991d9557b0c4.
> >> > Then Gen12's mipi dsi sequence was carried fwd for all later
> >> > platforms as
> >> well.
> >> >  with the modification saying that
> >> > Do not gate the pll until we enable the ddi buffer.
> >> > And this applies to gen 12 as well because they have marked the
> >> > earlier mentioned step of gating pll after pll mapping as removed
> >> > on all
> >> gen12 and later platforms.
> >> >
> >> > This patch now is keeping the older step as is, but making sure
> >> > that clocks
> >> are ungated while enabling ddi buffer.
> >>
> >> Where does it say for gen12+ that clocks should be ungated at any point?
> >>
> >> My reading of the spec:
> >>
> >> Gen11, bspec 20845 and 20597:
> >> - start with clocks ungated at mapping
> >> - gate after port/phy enabling (step 4m in gen11 mode set sequence)
> >>
> >> Gen12, bspec 49204, 49188 and 55316:
> >> - start with clocks gated at mapping
> >> - gate *if* not already gated (steps 4c and 4i in gen12 mode set
> >> sequence)
> >
> > Right the ungate step is not mentioned in the bspec.
> > Instead the step 4.c is marked as Removed.
> > I had added ungate just to make sure we are addressing the issue
> > mentioned in front of removed tag while Retaining the old sequence of
> > 4.c
> >
> > In order to completely adhere to the current bspec, I can 1. submit a
> > patch removing 4.c or 2.  submit a revert of the patch which was
> > adding 4.c
> > ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
> 
> I think if you remove the call to gen11_dsi_ungate_clocks(encoder) from this
> patch, the sequence matches bspec.
> 
> But this means the sequence is different between display 11 and 12+, and the
> clock will be gated for the entire enabling sequence on 12+. That's my
> reading of bspec, anyway.

Right the current bspec doesn't show us where to enable the clocks.
Clock ungating is not mentioned anywhere, and we need to enable clocks before enabling
DDI_BUF_CTL , have requested for sequence update in the bspec.

Thanks,
Vandita
> 
> BR,
> Jani.
> 
> 
> 
> >
> > Thanks,
> > Vandita
> >>
> >> It may be that your patch is correct, but IMO it does not match bspec.
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >> >
> >> > Thanks
> >> > Vandita
> >> >>
> >> >> BR,
> >> >> Jani.
> >> >>
> >> >>
> >> >>
> >> >> >
> >> >> > Thanks,
> >> >> > Vandita
> >> >> >
> >> >> >>
> >> >> >> BR,
> >> >> >> Jani.
> >> >> >>
> >> >> >>
> >> >> >> >  	/* enable DDI buffer */
> >> >> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
> >> >> >> >
> >> >> >> > @@ -1161,9 +1161,7 @@
> gen11_dsi_enable_port_and_phy(struct
> >> >> >> intel_encoder *encoder,
> >> >> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >> >> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
> >> >> >> >
> >> >> >> > -	/* Step 4l: Gate DDI clocks */
> >> >> >> > -	if (DISPLAY_VER(dev_priv) == 11)
> >> >> >> > -		gen11_dsi_gate_clocks(encoder);
> >> >> >> > +	gen11_dsi_gate_clocks(encoder);
> >> >> >> >  }
> >> >> >> >
> >> >> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder
> >> >> >> > *encoder)
> >> >> >>
> >> >> >> --
> >> >> >> Jani Nikula, Intel Open Source Graphics Center
> >> >>
> >> >> --
> >> >> Jani Nikula, Intel Open Source Graphics Center
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy

[Kulkarni, Vandita]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Kulkarni, Vandita
> Sent: Tuesday, November 2, 2021 5:13 PM
> To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
> phy
> 
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Tuesday, November 2, 2021 3:13 PM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> > Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the
> > phy
> >
> > On Tue, 02 Nov 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
> > wrote:
> > >> -----Original Message-----
> > >> From: Nikula, Jani <jani.nikula@intel.com>
> > >> Sent: Monday, November 1, 2021 5:37 PM
> > >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > >> gfx@lists.freedesktop.org
> > >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> > >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> > >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling
> > >> the phy
> > >>
> > >> On Thu, 28 Oct 2021, "Kulkarni, Vandita"
> > >> <vandita.kulkarni@intel.com>
> > >> wrote:
> > >> >> -----Original Message-----
> > >> >> From: Nikula, Jani <jani.nikula@intel.com>
> > >> >> Sent: Thursday, October 28, 2021 8:06 PM
> > >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > >> >> gfx@lists.freedesktop.org
> > >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> > >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com
> > >> >> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling
> > >> >> the phy
> > >> >>
> > >> >> On Thu, 28 Oct 2021, "Kulkarni, Vandita"
> > >> >> <vandita.kulkarni@intel.com>
> > >> >> wrote:
> > >> >> >> -----Original Message-----
> > >> >> >> From: Nikula, Jani <jani.nikula@intel.com>
> > >> >> >> Sent: Thursday, October 28, 2021 5:13 PM
> > >> >> >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > >> >> >> gfx@lists.freedesktop.org
> > >> >> >> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
> > >> >> >> <matthew.d.roper@intel.com>; ville.syrjala@linux.intel.com;
> > >> >> >> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > >> >> >> Subject: Re: [V2 4/4] drm/i915/dsi: Ungate clock before
> > >> >> >> enabling the phy
> > >> >> >>
> > >> >> >> On Tue, 19 Oct 2021, Vandita Kulkarni
> > >> >> >> <vandita.kulkarni@intel.com>
> > >> >> wrote:
> > >> >> >> > For the PHY enable/disable signalling to propagate between
> > >> >> >> > Dispaly and PHY, DDI clocks need to be running when
> > >> >> >> > enabling the
> > >> PHY.
> > >> >> >> >
> > >> >> >> > Bspec: 49188 says gate the clocks after enabling the
> > >> >> >> >        DDI Buffer.
> > >> >> >> >        We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi:
> > >> >> >> > Gate the
> > >> >> ddi
> > >> >> >> >        clocks after pll mapping") which gates the clocks much before,
> > >> >> >> >        as per the older spec. This commit nullifies its
> > >> >> >> > effect and
> > makes
> > >> >> >> >        sure that the clocks are not gated while we enable the DDI
> > >> >> >> >        buffer.
> > >> >> >> > v2: Bspec ref, add a comment wrt earlier clock gating
> > >> >> >> > sequence
> > >> >> >> > (Jani)
> > >> >> >> >
> > >> >> >> > Signed-off-by: Vandita Kulkarni
> > >> >> >> > <vandita.kulkarni@intel.com>
> > >> >> >> > ---
> > >> >> >> >  drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
> > >> >> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
> > >> >> >> >
> > >> >> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> >> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> >> >> > index 63dd75c6448a..e5ef5c4a32d7 100644
> > >> >> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> >> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> >> >> > @@ -1135,8 +1135,6 @@ static void
> > >> >> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> > >> >> >> >  			      const struct intel_crtc_state *crtc_state)
> > >> {
> > >> >> >> > -	struct drm_i915_private *dev_priv = to_i915(encoder-
> > >> >base.dev);
> > >> >> >> > -
> > >> >> >> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> > >> >> >> >  	gen11_dsi_power_up_lanes(encoder);
> > >> >> >> >
> > >> >> >> > @@ -1146,6 +1144,8 @@
> > gen11_dsi_enable_port_and_phy(struct
> > >> >> >> intel_encoder *encoder,
> > >> >> >> >  	/* step 4c: configure voltage swing and skew */
> > >> >> >> >  	gen11_dsi_voltage_swing_program_seq(encoder);
> > >> >> >> >
> > >> >> >> > +	gen11_dsi_ungate_clocks(encoder);
> > >> >> >> > +
> > >> >> >>
> > >> >> >> What about the changes to gen11_dsi_map_pll() in commit
> > >> >> >> 991d9557b0c4
> > >> >> >> ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")?
> > >> >> >> It starts off with clocks gated for gen12+, ungated otherwise.
> > >> >> >
> > >> >> > Now the same spec is updated with the gate step after ddi
> > >> >> > buffer
> > >> enable.
> > >> >> > And the one before is marked with remove tag.
> > >> >> > That makes all gen12+ align with gen 11.
> > >> >> > You suggested to update the same in the commit message on v1.
> > >> >> > Should I still consider just reverting that commit?
> > >> >>
> > >> >> I'm just royally confused about the sequence myself, so I'm
> > >> >> asking you. ;)
> > >> >>
> > >> >> It doesn't help that the code has step references to gen 11 mode
> > >> >> set that are completely different from the steps in gen 12 sequence.
> > >> >
> > >> > Right, they have lot of different steps coming in.
> > >> > As per gen11 sequence, we were gating pll after enabling ddi buffer.
> > >> >
> > >> > Initially when there was only gen12 in the bspec, it stated to
> > >> > gate the pll
> > >> after mapping.
> > >> > Hence we had that commit  991d9557b0c4.
> > >> > Then Gen12's mipi dsi sequence was carried fwd for all later
> > >> > platforms as
> > >> well.
> > >> >  with the modification saying that Do not gate the pll until we
> > >> > enable the ddi buffer.
> > >> > And this applies to gen 12 as well because they have marked the
> > >> > earlier mentioned step of gating pll after pll mapping as removed
> > >> > on all
> > >> gen12 and later platforms.
> > >> >
> > >> > This patch now is keeping the older step as is, but making sure
> > >> > that clocks
> > >> are ungated while enabling ddi buffer.
> > >>
> > >> Where does it say for gen12+ that clocks should be ungated at any point?
> > >>
> > >> My reading of the spec:
> > >>
> > >> Gen11, bspec 20845 and 20597:
> > >> - start with clocks ungated at mapping
> > >> - gate after port/phy enabling (step 4m in gen11 mode set sequence)
> > >>
> > >> Gen12, bspec 49204, 49188 and 55316:
> > >> - start with clocks gated at mapping
> > >> - gate *if* not already gated (steps 4c and 4i in gen12 mode set
> > >> sequence)
> > >
> > > Right the ungate step is not mentioned in the bspec.
> > > Instead the step 4.c is marked as Removed.
> > > I had added ungate just to make sure we are addressing the issue
> > > mentioned in front of removed tag while Retaining the old sequence
> > > of 4.c
> > >
> > > In order to completely adhere to the current bspec, I can 1. submit
> > > a patch removing 4.c or 2.  submit a revert of the patch which was
> > > adding 4.c
> > > ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
> >
> > I think if you remove the call to gen11_dsi_ungate_clocks(encoder)
> > from this patch, the sequence matches bspec.
> >
> > But this means the sequence is different between display 11 and 12+,
> > and the clock will be gated for the entire enabling sequence on 12+.
> > That's my reading of bspec, anyway.
> 
> Right the current bspec doesn't show us where to enable the clocks.
> Clock ungating is not mentioned anywhere, and we need to enable clocks
> before enabling DDI_BUF_CTL , have requested for sequence update in the
> bspec.
As per the lates tbspec update, have floated the revert of 
("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")

This patch can be ignored now.

Thanks,
Vandita
> 
> Thanks,
> Vandita
> >
> > BR,
> > Jani.
> >
> >
> >
> > >
> > > Thanks,
> > > Vandita
> > >>
> > >> It may be that your patch is correct, but IMO it does not match bspec.
> > >>
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >>
> > >> >
> > >> > Thanks
> > >> > Vandita
> > >> >>
> > >> >> BR,
> > >> >> Jani.
> > >> >>
> > >> >>
> > >> >>
> > >> >> >
> > >> >> > Thanks,
> > >> >> > Vandita
> > >> >> >
> > >> >> >>
> > >> >> >> BR,
> > >> >> >> Jani.
> > >> >> >>
> > >> >> >>
> > >> >> >> >  	/* enable DDI buffer */
> > >> >> >> >  	gen11_dsi_enable_ddi_buffer(encoder);
> > >> >> >> >
> > >> >> >> > @@ -1161,9 +1161,7 @@
> > gen11_dsi_enable_port_and_phy(struct
> > >> >> >> intel_encoder *encoder,
> > >> >> >> >  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> > >> >> >> >  	gen11_dsi_configure_transcoder(encoder, crtc_state);
> > >> >> >> >
> > >> >> >> > -	/* Step 4l: Gate DDI clocks */
> > >> >> >> > -	if (DISPLAY_VER(dev_priv) == 11)
> > >> >> >> > -		gen11_dsi_gate_clocks(encoder);
> > >> >> >> > +	gen11_dsi_gate_clocks(encoder);
> > >> >> >> >  }
> > >> >> >> >
> > >> >> >> >  static void gen11_dsi_powerup_panel(struct intel_encoder
> > >> >> >> > *encoder)
> > >> >> >>
> > >> >> >> --
> > >> >> >> Jani Nikula, Intel Open Source Graphics Center
> > >> >>
> > >> >> --
> > >> >> Jani Nikula, Intel Open Source Graphics Center
> > >>
> > >> --
> > >> Jani Nikula, Intel Open Source Graphics Center
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center