From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com>, Jacky Bai <ping.bai@nxp.com> Subject: [PATCH v4 03/12] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Date: Wed, 10 Nov 2021 19:46:46 +0200 [thread overview] Message-ID: <1636566415-22750-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1636566415-22750-1-git-send-email-abel.vesa@nxp.com> From: Jacky Bai <ping.bai@nxp.com> The i.MX8DXL is a device targeting the automotive and industrial market segments. The flexibility of the architecture allows for use in a wide variety of general embedded applications. The chip is designed to achieve both high performance and low power consumption. The chip relies on the power efficient dual (2x) Cortex-A35 cluster. Add the reserved memory node property for dsp reserved memory, the wakeup-irq property for SCU node, the imx ion, the rpmsg and the cm4 rproc support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ 1 file changed, 245 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..f16f88882c39 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8dxl.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 2 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: imx8dxl-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; + }; + + watchdog { + compatible = "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; + + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + /* sorted in register address */ + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com>, Jacky Bai <ping.bai@nxp.com> Subject: [PATCH v4 03/12] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Date: Wed, 10 Nov 2021 19:46:46 +0200 [thread overview] Message-ID: <1636566415-22750-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1636566415-22750-1-git-send-email-abel.vesa@nxp.com> From: Jacky Bai <ping.bai@nxp.com> The i.MX8DXL is a device targeting the automotive and industrial market segments. The flexibility of the architecture allows for use in a wide variety of general embedded applications. The chip is designed to achieve both high performance and low power consumption. The chip relies on the power efficient dual (2x) Cortex-A35 cluster. Add the reserved memory node property for dsp reserved memory, the wakeup-irq property for SCU node, the imx ion, the rpmsg and the cm4 rproc support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ 1 file changed, 245 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..f16f88882c39 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8dxl.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 2 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: imx8dxl-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; + }; + + watchdog { + compatible = "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; + + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + /* sorted in register address */ + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-11-10 17:47 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-10 17:46 [PATCH v4 00/12] arm64: dts: Add i.MX8DXL initial support Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 01/12] dt-bindings: i2c: imx-lpi2c: Fix i.MX 8QM compatible matching Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-19 0:56 ` Rob Herring 2021-11-19 0:56 ` Rob Herring 2021-11-23 8:52 ` Wolfram Sang 2021-11-23 8:52 ` Wolfram Sang 2021-11-23 8:53 ` Wolfram Sang 2021-11-23 8:53 ` Wolfram Sang 2021-11-10 17:46 ` [PATCH v4 02/12] dt-bindings: serial: fsl-lpuart: " Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-19 1:02 ` Rob Herring 2021-11-19 1:02 ` Rob Herring 2021-11-10 17:46 ` Abel Vesa [this message] 2021-11-10 17:46 ` [PATCH v4 03/12] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa 2021-11-10 17:46 ` [PATCH v4 04/12] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 05/12] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 06/12] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 07/12] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 08/12] arm64: dts: freescale: Add lsio " Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 09/12] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 10/12] dt-bindings: fsl: scu: Add i.MX8DXL ocotp binding Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-10 17:46 ` [PATCH v4 11/12] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-19 1:02 ` Rob Herring 2021-11-19 1:02 ` Rob Herring 2021-11-29 8:41 ` Wolfram Sang 2021-11-29 8:41 ` Wolfram Sang 2021-11-10 17:46 ` [PATCH v4 12/12] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa 2021-11-10 17:46 ` Abel Vesa 2021-11-19 1:04 ` Rob Herring 2021-11-19 1:04 ` Rob Herring 2021-11-19 7:17 ` (EXT) " Alexander Stein 2021-11-19 7:17 ` Alexander Stein 2021-11-22 16:45 ` Abel Vesa 2021-11-22 16:45 ` Abel Vesa 2021-11-23 7:30 ` (EXT) " Alexander Stein 2021-11-23 7:30 ` Alexander Stein 2021-11-25 13:19 ` Abel Vesa 2021-11-25 13:19 ` Abel Vesa 2021-11-25 13:23 ` (EXT) " Alexander Stein 2021-11-25 13:23 ` Alexander Stein 2021-11-22 16:29 ` Abel Vesa 2021-11-22 16:29 ` Abel Vesa
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1636566415-22750-4-git-send-email-abel.vesa@nxp.com \ --to=abel.vesa@nxp.com \ --cc=aisheng.dong@nxp.com \ --cc=devicetree@vger.kernel.org \ --cc=festevam@gmail.com \ --cc=gregkh@linuxfoundation.org \ --cc=kernel@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-i2c@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-serial@vger.kernel.org \ --cc=ping.bai@nxp.com \ --cc=robh@kernel.org \ --cc=s.hauer@pengutronix.de \ --cc=shawnguo@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.