From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com> Subject: [RESEND v4 03/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Date: Thu, 16 Dec 2021 20:48:07 +0200 [thread overview] Message-ID: <1639680494-23183-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com> The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and imx8dxl platforms. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ee4e585a9c39..76abdab40c75 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -141,6 +141,13 @@ lsio_mu4: mailbox@5d1f0000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + reg = <0x5d200000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com> Subject: [RESEND v4 03/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Date: Thu, 16 Dec 2021 20:48:07 +0200 [thread overview] Message-ID: <1639680494-23183-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com> The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and imx8dxl platforms. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ee4e585a9c39..76abdab40c75 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -141,6 +141,13 @@ lsio_mu4: mailbox@5d1f0000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + reg = <0x5d200000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-16 18:49 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-16 18:48 [RESEND v4 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 01/10] dt-bindings: serial: fsl-lpuart: Fix i.MX 8QM compatible matching Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 02/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2022-01-26 12:27 ` Shawn Guo 2022-01-26 12:27 ` Shawn Guo 2022-02-10 21:49 ` Abel Vesa 2022-02-10 21:49 ` Abel Vesa 2021-12-16 18:48 ` Abel Vesa [this message] 2021-12-16 18:48 ` [RESEND v4 03/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa 2021-12-16 18:48 ` [RESEND v4 04/10] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2022-01-26 12:36 ` Shawn Guo 2022-01-26 12:36 ` Shawn Guo 2021-12-16 18:48 ` [RESEND v4 05/10] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2022-01-26 12:47 ` Shawn Guo 2022-01-26 12:47 ` Shawn Guo 2022-02-10 21:33 ` Abel Vesa 2022-02-10 21:33 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 06/10] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 07/10] arm64: dts: freescale: Add lsio " Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 08/10] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2022-01-26 12:53 ` Shawn Guo 2022-01-26 12:53 ` Shawn Guo 2022-02-10 21:27 ` Abel Vesa 2022-02-10 21:27 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 09/10] dt-bindings: fsl: scu: Add i.MX8DXL ocotp binding Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-16 18:48 ` [RESEND v4 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa 2021-12-16 18:48 ` Abel Vesa 2021-12-17 16:59 ` Greg Kroah-Hartman 2021-12-17 16:59 ` Greg Kroah-Hartman 2021-12-18 21:58 ` Abel Vesa 2021-12-18 21:58 ` Abel Vesa 2021-12-20 15:35 ` Greg Kroah-Hartman 2021-12-20 15:35 ` Greg Kroah-Hartman
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