[Intel-gfx] [PATCH 0/8] drm/i915: Plane/wm cleanups

[Intel-gfx] [PATCH 0/8] drm/i915: Plane/wm cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move some plane stuff out from intel_display.c, introduce
a scaled_planes bitmask, and using that as an excuse clean
up a bunch of watermark registers.

Ville Syrjälä (8):
  drm/i915: Move intel_plane_atomic_calc_changes() & co. out
  drm/i915: Introduce intel_arm_planes_on_crtc()
  drm/i915: Introduce scaled_planes bitmask
  drm/i915: Use {active,scaled}_planes to compute ilk watermarks
  drm/i915: Remove gen6_check_mch_setup()
  drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
  drm/i915: Clean up SSKPD/MLTR defines
  drm/i915: Polish ilk+ wm register bits

 .../gpu/drm/i915/display/intel_atomic_plane.c | 204 +++++++++++++++++-
 .../gpu/drm/i915/display/intel_atomic_plane.h |  10 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 194 +----------------
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/i915_reg.h               |  68 +++---
 drivers/gpu/drm/i915/i915_reg_defs.h          |  57 +++--
 drivers/gpu/drm/i915/intel_pm.c               | 104 ++++-----
 8 files changed, 322 insertions(+), 318 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 1/8] drm/i915: Move intel_plane_atomic_calc_changes() & co. out

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Exfiltrate intel_plane_atomic_calc_changes() and its friends from
intel_display.c to intel_atomic_plane.c since that is a much better
fit.

While at it also nuke the official looking kernel docs for
intel_wm_need_update() and flag it for eventual destruction so
that people don't get any wrong ideas about using it in new code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 180 +++++++++++++++++
 .../gpu/drm/i915/display/intel_atomic_plane.h |   4 -
 drivers/gpu/drm/i915/display/intel_display.c  | 188 ------------------
 3 files changed, 180 insertions(+), 192 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index bec02333bdeb..3355eb637eac 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -45,6 +45,7 @@
 #include "intel_fb_pin.h"
 #include "intel_pm.h"
 #include "intel_sprite.h"
+#include "skl_scaler.h"
 
 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
 				    struct intel_plane *plane)
@@ -330,6 +331,185 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	plane_state->uapi.visible = false;
 }
 
+/* FIXME nuke when all wm code is atomic */
+static bool intel_wm_need_update(const struct intel_plane_state *cur,
+				 struct intel_plane_state *new)
+{
+	/* Update watermarks on tiling or size changes. */
+	if (new->uapi.visible != cur->uapi.visible)
+		return true;
+
+	if (!cur->hw.fb || !new->hw.fb)
+		return false;
+
+	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
+	    cur->hw.rotation != new->hw.rotation ||
+	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
+	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
+	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
+	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
+		return true;
+
+	return false;
+}
+
+static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
+{
+	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+	int dst_w = drm_rect_width(&plane_state->uapi.dst);
+	int dst_h = drm_rect_height(&plane_state->uapi.dst);
+
+	return src_w != dst_w || src_h != dst_h;
+}
+
+static bool intel_plane_do_async_flip(struct intel_plane *plane,
+				      const struct intel_crtc_state *old_crtc_state,
+				      const struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+	if (!plane->async_flip)
+		return false;
+
+	if (!new_crtc_state->uapi.async_flip)
+		return false;
+
+	/*
+	 * In platforms after DISPLAY13, we might need to override
+	 * first async flip in order to change watermark levels
+	 * as part of optimization.
+	 * So for those, we are checking if this is a first async flip.
+	 * For platforms earlier than DISPLAY13 we always do async flip.
+	 */
+	return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
+}
+
+static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
+					   struct intel_crtc_state *new_crtc_state,
+					   const struct intel_plane_state *old_plane_state,
+					   struct intel_plane_state *new_plane_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
+	bool was_crtc_enabled = old_crtc_state->hw.active;
+	bool is_crtc_enabled = new_crtc_state->hw.active;
+	bool turn_off, turn_on, visible, was_visible;
+	int ret;
+
+	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
+		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
+		if (ret)
+			return ret;
+	}
+
+	was_visible = old_plane_state->uapi.visible;
+	visible = new_plane_state->uapi.visible;
+
+	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
+		was_visible = false;
+
+	/*
+	 * Visibility is calculated as if the crtc was on, but
+	 * after scaler setup everything depends on it being off
+	 * when the crtc isn't active.
+	 *
+	 * FIXME this is wrong for watermarks. Watermarks should also
+	 * be computed as if the pipe would be active. Perhaps move
+	 * per-plane wm computation to the .check_plane() hook, and
+	 * only combine the results from all planes in the current place?
+	 */
+	if (!is_crtc_enabled) {
+		intel_plane_set_invisible(new_crtc_state, new_plane_state);
+		visible = false;
+	}
+
+	if (!was_visible && !visible)
+		return 0;
+
+	turn_off = was_visible && (!visible || mode_changed);
+	turn_on = visible && (!was_visible || mode_changed);
+
+	drm_dbg_atomic(&dev_priv->drm,
+		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
+		       crtc->base.base.id, crtc->base.name,
+		       plane->base.base.id, plane->base.name,
+		       was_visible, visible,
+		       turn_off, turn_on, mode_changed);
+
+	if (turn_on) {
+		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
+			new_crtc_state->update_wm_pre = true;
+
+		/* must disable cxsr around plane enable/disable */
+		if (plane->id != PLANE_CURSOR)
+			new_crtc_state->disable_cxsr = true;
+	} else if (turn_off) {
+		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
+			new_crtc_state->update_wm_post = true;
+
+		/* must disable cxsr around plane enable/disable */
+		if (plane->id != PLANE_CURSOR)
+			new_crtc_state->disable_cxsr = true;
+	} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
+		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+			/* FIXME bollocks */
+			new_crtc_state->update_wm_pre = true;
+			new_crtc_state->update_wm_post = true;
+		}
+	}
+
+	if (visible || was_visible)
+		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
+
+	/*
+	 * ILK/SNB DVSACNTR/Sprite Enable
+	 * IVB SPR_CTL/Sprite Enable
+	 * "When in Self Refresh Big FIFO mode, a write to enable the
+	 *  plane will be internally buffered and delayed while Big FIFO
+	 *  mode is exiting."
+	 *
+	 * Which means that enabling the sprite can take an extra frame
+	 * when we start in big FIFO mode (LP1+). Thus we need to drop
+	 * down to LP0 and wait for vblank in order to make sure the
+	 * sprite gets enabled on the next vblank after the register write.
+	 * Doing otherwise would risk enabling the sprite one frame after
+	 * we've already signalled flip completion. We can resume LP1+
+	 * once the sprite has been enabled.
+	 *
+	 *
+	 * WaCxSRDisabledForSpriteScaling:ivb
+	 * IVB SPR_SCALE/Scaling Enable
+	 * "Low Power watermarks must be disabled for at least one
+	 *  frame before enabling sprite scaling, and kept disabled
+	 *  until sprite scaling is disabled."
+	 *
+	 * ILK/SNB DVSASCALE/Scaling Enable
+	 * "When in Self Refresh Big FIFO mode, scaling enable will be
+	 *  masked off while Big FIFO mode is exiting."
+	 *
+	 * Despite the w/a only being listed for IVB we assume that
+	 * the ILK/SNB note has similar ramifications, hence we apply
+	 * the w/a on all three platforms.
+	 *
+	 * With experimental results seems this is needed also for primary
+	 * plane, not only sprite plane.
+	 */
+	if (plane->id != PLANE_CURSOR &&
+	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
+	     IS_IVYBRIDGE(dev_priv)) &&
+	    (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
+			 intel_plane_is_scaled(new_plane_state))))
+		new_crtc_state->disable_lp_wm = true;
+
+	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
+		new_plane_state->do_async_flip = true;
+
+	return 0;
+}
+
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 					struct intel_crtc_state *new_crtc_state,
 					const struct intel_plane_state *old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index ead789709477..9822b921279c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -56,10 +56,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 					struct intel_plane_state *intel_state);
 int intel_plane_atomic_check(struct intel_atomic_state *state,
 			     struct intel_plane *plane);
-int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
-				    struct intel_crtc_state *crtc_state,
-				    const struct intel_plane_state *old_plane_state,
-				    struct intel_plane_state *plane_state);
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 			       struct intel_plane *plane,
 			       bool *need_cdclk_calc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9712e069e3c1..3f68fb656fb5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4605,194 +4605,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
 	return mode;
 }
 
-/**
- * intel_wm_need_update - Check whether watermarks need updating
- * @cur: current plane state
- * @new: new plane state
- *
- * Check current plane state versus the new one to determine whether
- * watermarks need to be recalculated.
- *
- * Returns true or false.
- */
-static bool intel_wm_need_update(const struct intel_plane_state *cur,
-				 struct intel_plane_state *new)
-{
-	/* Update watermarks on tiling or size changes. */
-	if (new->uapi.visible != cur->uapi.visible)
-		return true;
-
-	if (!cur->hw.fb || !new->hw.fb)
-		return false;
-
-	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
-	    cur->hw.rotation != new->hw.rotation ||
-	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
-	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
-	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
-	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
-		return true;
-
-	return false;
-}
-
-static bool needs_scaling(const struct intel_plane_state *state)
-{
-	int src_w = drm_rect_width(&state->uapi.src) >> 16;
-	int src_h = drm_rect_height(&state->uapi.src) >> 16;
-	int dst_w = drm_rect_width(&state->uapi.dst);
-	int dst_h = drm_rect_height(&state->uapi.dst);
-
-	return (src_w != dst_w || src_h != dst_h);
-}
-
-static bool intel_plane_do_async_flip(struct intel_plane *plane,
-				      const struct intel_crtc_state *old_crtc_state,
-				      const struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *i915 = to_i915(plane->base.dev);
-
-	if (!plane->async_flip)
-		return false;
-
-	if (!new_crtc_state->uapi.async_flip)
-		return false;
-
-	/*
-	 * In platforms after DISPLAY13, we might need to override
-	 * first async flip in order to change watermark levels
-	 * as part of optimization.
-	 * So for those, we are checking if this is a first async flip.
-	 * For platforms earlier than DISPLAY13 we always do async flip.
-	 */
-	return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
-}
-
-int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
-				    struct intel_crtc_state *new_crtc_state,
-				    const struct intel_plane_state *old_plane_state,
-				    struct intel_plane_state *new_plane_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
-	bool was_crtc_enabled = old_crtc_state->hw.active;
-	bool is_crtc_enabled = new_crtc_state->hw.active;
-	bool turn_off, turn_on, visible, was_visible;
-	int ret;
-
-	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
-		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
-		if (ret)
-			return ret;
-	}
-
-	was_visible = old_plane_state->uapi.visible;
-	visible = new_plane_state->uapi.visible;
-
-	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
-		was_visible = false;
-
-	/*
-	 * Visibility is calculated as if the crtc was on, but
-	 * after scaler setup everything depends on it being off
-	 * when the crtc isn't active.
-	 *
-	 * FIXME this is wrong for watermarks. Watermarks should also
-	 * be computed as if the pipe would be active. Perhaps move
-	 * per-plane wm computation to the .check_plane() hook, and
-	 * only combine the results from all planes in the current place?
-	 */
-	if (!is_crtc_enabled) {
-		intel_plane_set_invisible(new_crtc_state, new_plane_state);
-		visible = false;
-	}
-
-	if (!was_visible && !visible)
-		return 0;
-
-	turn_off = was_visible && (!visible || mode_changed);
-	turn_on = visible && (!was_visible || mode_changed);
-
-	drm_dbg_atomic(&dev_priv->drm,
-		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
-		       crtc->base.base.id, crtc->base.name,
-		       plane->base.base.id, plane->base.name,
-		       was_visible, visible,
-		       turn_off, turn_on, mode_changed);
-
-	if (turn_on) {
-		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
-			new_crtc_state->update_wm_pre = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			new_crtc_state->disable_cxsr = true;
-	} else if (turn_off) {
-		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
-			new_crtc_state->update_wm_post = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			new_crtc_state->disable_cxsr = true;
-	} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
-		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
-			/* FIXME bollocks */
-			new_crtc_state->update_wm_pre = true;
-			new_crtc_state->update_wm_post = true;
-		}
-	}
-
-	if (visible || was_visible)
-		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
-
-	/*
-	 * ILK/SNB DVSACNTR/Sprite Enable
-	 * IVB SPR_CTL/Sprite Enable
-	 * "When in Self Refresh Big FIFO mode, a write to enable the
-	 *  plane will be internally buffered and delayed while Big FIFO
-	 *  mode is exiting."
-	 *
-	 * Which means that enabling the sprite can take an extra frame
-	 * when we start in big FIFO mode (LP1+). Thus we need to drop
-	 * down to LP0 and wait for vblank in order to make sure the
-	 * sprite gets enabled on the next vblank after the register write.
-	 * Doing otherwise would risk enabling the sprite one frame after
-	 * we've already signalled flip completion. We can resume LP1+
-	 * once the sprite has been enabled.
-	 *
-	 *
-	 * WaCxSRDisabledForSpriteScaling:ivb
-	 * IVB SPR_SCALE/Scaling Enable
-	 * "Low Power watermarks must be disabled for at least one
-	 *  frame before enabling sprite scaling, and kept disabled
-	 *  until sprite scaling is disabled."
-	 *
-	 * ILK/SNB DVSASCALE/Scaling Enable
-	 * "When in Self Refresh Big FIFO mode, scaling enable will be
-	 *  masked off while Big FIFO mode is exiting."
-	 *
-	 * Despite the w/a only being listed for IVB we assume that
-	 * the ILK/SNB note has similar ramifications, hence we apply
-	 * the w/a on all three platforms.
-	 *
-	 * With experimental results seems this is needed also for primary
-	 * plane, not only sprite plane.
-	 */
-	if (plane->id != PLANE_CURSOR &&
-	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
-	     IS_IVYBRIDGE(dev_priv)) &&
-	    (turn_on || (!needs_scaling(old_plane_state) &&
-			 needs_scaling(new_plane_state))))
-		new_crtc_state->disable_lp_wm = true;
-
-	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
-		new_plane_state->do_async_flip = true;
-
-	return 0;
-}
-
 static bool encoders_cloneable(const struct intel_encoder *a,
 			       const struct intel_encoder *b)
 {
-- 
2.34.1

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Move intel_plane_atomic_calc_changes() & co. out

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Exfiltrate intel_plane_atomic_calc_changes() and its friends from
> intel_display.c to intel_atomic_plane.c since that is a much better
> fit.
>
> While at it also nuke the official looking kernel docs for
> intel_wm_need_update() and flag it for eventual destruction so
> that people don't get any wrong ideas about using it in new code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 180 +++++++++++++++++
>  .../gpu/drm/i915/display/intel_atomic_plane.h |   4 -
>  drivers/gpu/drm/i915/display/intel_display.c  | 188 ------------------
>  3 files changed, 180 insertions(+), 192 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index bec02333bdeb..3355eb637eac 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -45,6 +45,7 @@
>  #include "intel_fb_pin.h"
>  #include "intel_pm.h"
>  #include "intel_sprite.h"
> +#include "skl_scaler.h"
>  
>  static void intel_plane_state_reset(struct intel_plane_state *plane_state,
>  				    struct intel_plane *plane)
> @@ -330,6 +331,185 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
>  	plane_state->uapi.visible = false;
>  }
>  
> +/* FIXME nuke when all wm code is atomic */
> +static bool intel_wm_need_update(const struct intel_plane_state *cur,
> +				 struct intel_plane_state *new)
> +{
> +	/* Update watermarks on tiling or size changes. */
> +	if (new->uapi.visible != cur->uapi.visible)
> +		return true;
> +
> +	if (!cur->hw.fb || !new->hw.fb)
> +		return false;
> +
> +	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
> +	    cur->hw.rotation != new->hw.rotation ||
> +	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
> +	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
> +	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
> +	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
> +		return true;
> +
> +	return false;
> +}
> +
> +static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
> +{
> +	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> +	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> +	int dst_w = drm_rect_width(&plane_state->uapi.dst);
> +	int dst_h = drm_rect_height(&plane_state->uapi.dst);
> +
> +	return src_w != dst_w || src_h != dst_h;
> +}
> +
> +static bool intel_plane_do_async_flip(struct intel_plane *plane,
> +				      const struct intel_crtc_state *old_crtc_state,
> +				      const struct intel_crtc_state *new_crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> +	if (!plane->async_flip)
> +		return false;
> +
> +	if (!new_crtc_state->uapi.async_flip)
> +		return false;
> +
> +	/*
> +	 * In platforms after DISPLAY13, we might need to override
> +	 * first async flip in order to change watermark levels
> +	 * as part of optimization.
> +	 * So for those, we are checking if this is a first async flip.
> +	 * For platforms earlier than DISPLAY13 we always do async flip.
> +	 */
> +	return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
> +}
> +
> +static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
> +					   struct intel_crtc_state *new_crtc_state,
> +					   const struct intel_plane_state *old_plane_state,
> +					   struct intel_plane_state *new_plane_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> +	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
> +	bool was_crtc_enabled = old_crtc_state->hw.active;
> +	bool is_crtc_enabled = new_crtc_state->hw.active;
> +	bool turn_off, turn_on, visible, was_visible;
> +	int ret;
> +
> +	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
> +		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	was_visible = old_plane_state->uapi.visible;
> +	visible = new_plane_state->uapi.visible;
> +
> +	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
> +		was_visible = false;
> +
> +	/*
> +	 * Visibility is calculated as if the crtc was on, but
> +	 * after scaler setup everything depends on it being off
> +	 * when the crtc isn't active.
> +	 *
> +	 * FIXME this is wrong for watermarks. Watermarks should also
> +	 * be computed as if the pipe would be active. Perhaps move
> +	 * per-plane wm computation to the .check_plane() hook, and
> +	 * only combine the results from all planes in the current place?
> +	 */
> +	if (!is_crtc_enabled) {
> +		intel_plane_set_invisible(new_crtc_state, new_plane_state);
> +		visible = false;
> +	}
> +
> +	if (!was_visible && !visible)
> +		return 0;
> +
> +	turn_off = was_visible && (!visible || mode_changed);
> +	turn_on = visible && (!was_visible || mode_changed);
> +
> +	drm_dbg_atomic(&dev_priv->drm,
> +		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
> +		       crtc->base.base.id, crtc->base.name,
> +		       plane->base.base.id, plane->base.name,
> +		       was_visible, visible,
> +		       turn_off, turn_on, mode_changed);
> +
> +	if (turn_on) {
> +		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> +			new_crtc_state->update_wm_pre = true;
> +
> +		/* must disable cxsr around plane enable/disable */
> +		if (plane->id != PLANE_CURSOR)
> +			new_crtc_state->disable_cxsr = true;
> +	} else if (turn_off) {
> +		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> +			new_crtc_state->update_wm_post = true;
> +
> +		/* must disable cxsr around plane enable/disable */
> +		if (plane->id != PLANE_CURSOR)
> +			new_crtc_state->disable_cxsr = true;
> +	} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
> +		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> +			/* FIXME bollocks */
> +			new_crtc_state->update_wm_pre = true;
> +			new_crtc_state->update_wm_post = true;
> +		}
> +	}
> +
> +	if (visible || was_visible)
> +		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
> +
> +	/*
> +	 * ILK/SNB DVSACNTR/Sprite Enable
> +	 * IVB SPR_CTL/Sprite Enable
> +	 * "When in Self Refresh Big FIFO mode, a write to enable the
> +	 *  plane will be internally buffered and delayed while Big FIFO
> +	 *  mode is exiting."
> +	 *
> +	 * Which means that enabling the sprite can take an extra frame
> +	 * when we start in big FIFO mode (LP1+). Thus we need to drop
> +	 * down to LP0 and wait for vblank in order to make sure the
> +	 * sprite gets enabled on the next vblank after the register write.
> +	 * Doing otherwise would risk enabling the sprite one frame after
> +	 * we've already signalled flip completion. We can resume LP1+
> +	 * once the sprite has been enabled.
> +	 *
> +	 *
> +	 * WaCxSRDisabledForSpriteScaling:ivb
> +	 * IVB SPR_SCALE/Scaling Enable
> +	 * "Low Power watermarks must be disabled for at least one
> +	 *  frame before enabling sprite scaling, and kept disabled
> +	 *  until sprite scaling is disabled."
> +	 *
> +	 * ILK/SNB DVSASCALE/Scaling Enable
> +	 * "When in Self Refresh Big FIFO mode, scaling enable will be
> +	 *  masked off while Big FIFO mode is exiting."
> +	 *
> +	 * Despite the w/a only being listed for IVB we assume that
> +	 * the ILK/SNB note has similar ramifications, hence we apply
> +	 * the w/a on all three platforms.
> +	 *
> +	 * With experimental results seems this is needed also for primary
> +	 * plane, not only sprite plane.
> +	 */
> +	if (plane->id != PLANE_CURSOR &&
> +	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
> +	     IS_IVYBRIDGE(dev_priv)) &&
> +	    (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
> +			 intel_plane_is_scaled(new_plane_state))))
> +		new_crtc_state->disable_lp_wm = true;
> +
> +	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
> +		new_plane_state->do_async_flip = true;
> +
> +	return 0;
> +}
> +
>  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
>  					struct intel_crtc_state *new_crtc_state,
>  					const struct intel_plane_state *old_plane_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index ead789709477..9822b921279c 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -56,10 +56,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  					struct intel_plane_state *intel_state);
>  int intel_plane_atomic_check(struct intel_atomic_state *state,
>  			     struct intel_plane *plane);
> -int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
> -				    struct intel_crtc_state *crtc_state,
> -				    const struct intel_plane_state *old_plane_state,
> -				    struct intel_plane_state *plane_state);
>  int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
>  			       struct intel_plane *plane,
>  			       bool *need_cdclk_calc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9712e069e3c1..3f68fb656fb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4605,194 +4605,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
>  	return mode;
>  }
>  
> -/**
> - * intel_wm_need_update - Check whether watermarks need updating
> - * @cur: current plane state
> - * @new: new plane state
> - *
> - * Check current plane state versus the new one to determine whether
> - * watermarks need to be recalculated.
> - *
> - * Returns true or false.
> - */
> -static bool intel_wm_need_update(const struct intel_plane_state *cur,
> -				 struct intel_plane_state *new)
> -{
> -	/* Update watermarks on tiling or size changes. */
> -	if (new->uapi.visible != cur->uapi.visible)
> -		return true;
> -
> -	if (!cur->hw.fb || !new->hw.fb)
> -		return false;
> -
> -	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
> -	    cur->hw.rotation != new->hw.rotation ||
> -	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
> -	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
> -	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
> -	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
> -		return true;
> -
> -	return false;
> -}
> -
> -static bool needs_scaling(const struct intel_plane_state *state)
> -{
> -	int src_w = drm_rect_width(&state->uapi.src) >> 16;
> -	int src_h = drm_rect_height(&state->uapi.src) >> 16;
> -	int dst_w = drm_rect_width(&state->uapi.dst);
> -	int dst_h = drm_rect_height(&state->uapi.dst);
> -
> -	return (src_w != dst_w || src_h != dst_h);
> -}
> -
> -static bool intel_plane_do_async_flip(struct intel_plane *plane,
> -				      const struct intel_crtc_state *old_crtc_state,
> -				      const struct intel_crtc_state *new_crtc_state)
> -{
> -	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> -
> -	if (!plane->async_flip)
> -		return false;
> -
> -	if (!new_crtc_state->uapi.async_flip)
> -		return false;
> -
> -	/*
> -	 * In platforms after DISPLAY13, we might need to override
> -	 * first async flip in order to change watermark levels
> -	 * as part of optimization.
> -	 * So for those, we are checking if this is a first async flip.
> -	 * For platforms earlier than DISPLAY13 we always do async flip.
> -	 */
> -	return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
> -}
> -
> -int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
> -				    struct intel_crtc_state *new_crtc_state,
> -				    const struct intel_plane_state *old_plane_state,
> -				    struct intel_plane_state *new_plane_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> -	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
> -	bool was_crtc_enabled = old_crtc_state->hw.active;
> -	bool is_crtc_enabled = new_crtc_state->hw.active;
> -	bool turn_off, turn_on, visible, was_visible;
> -	int ret;
> -
> -	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
> -		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
> -		if (ret)
> -			return ret;
> -	}
> -
> -	was_visible = old_plane_state->uapi.visible;
> -	visible = new_plane_state->uapi.visible;
> -
> -	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
> -		was_visible = false;
> -
> -	/*
> -	 * Visibility is calculated as if the crtc was on, but
> -	 * after scaler setup everything depends on it being off
> -	 * when the crtc isn't active.
> -	 *
> -	 * FIXME this is wrong for watermarks. Watermarks should also
> -	 * be computed as if the pipe would be active. Perhaps move
> -	 * per-plane wm computation to the .check_plane() hook, and
> -	 * only combine the results from all planes in the current place?
> -	 */
> -	if (!is_crtc_enabled) {
> -		intel_plane_set_invisible(new_crtc_state, new_plane_state);
> -		visible = false;
> -	}
> -
> -	if (!was_visible && !visible)
> -		return 0;
> -
> -	turn_off = was_visible && (!visible || mode_changed);
> -	turn_on = visible && (!was_visible || mode_changed);
> -
> -	drm_dbg_atomic(&dev_priv->drm,
> -		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
> -		       crtc->base.base.id, crtc->base.name,
> -		       plane->base.base.id, plane->base.name,
> -		       was_visible, visible,
> -		       turn_off, turn_on, mode_changed);
> -
> -	if (turn_on) {
> -		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> -			new_crtc_state->update_wm_pre = true;
> -
> -		/* must disable cxsr around plane enable/disable */
> -		if (plane->id != PLANE_CURSOR)
> -			new_crtc_state->disable_cxsr = true;
> -	} else if (turn_off) {
> -		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> -			new_crtc_state->update_wm_post = true;
> -
> -		/* must disable cxsr around plane enable/disable */
> -		if (plane->id != PLANE_CURSOR)
> -			new_crtc_state->disable_cxsr = true;
> -	} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
> -		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> -			/* FIXME bollocks */
> -			new_crtc_state->update_wm_pre = true;
> -			new_crtc_state->update_wm_post = true;
> -		}
> -	}
> -
> -	if (visible || was_visible)
> -		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
> -
> -	/*
> -	 * ILK/SNB DVSACNTR/Sprite Enable
> -	 * IVB SPR_CTL/Sprite Enable
> -	 * "When in Self Refresh Big FIFO mode, a write to enable the
> -	 *  plane will be internally buffered and delayed while Big FIFO
> -	 *  mode is exiting."
> -	 *
> -	 * Which means that enabling the sprite can take an extra frame
> -	 * when we start in big FIFO mode (LP1+). Thus we need to drop
> -	 * down to LP0 and wait for vblank in order to make sure the
> -	 * sprite gets enabled on the next vblank after the register write.
> -	 * Doing otherwise would risk enabling the sprite one frame after
> -	 * we've already signalled flip completion. We can resume LP1+
> -	 * once the sprite has been enabled.
> -	 *
> -	 *
> -	 * WaCxSRDisabledForSpriteScaling:ivb
> -	 * IVB SPR_SCALE/Scaling Enable
> -	 * "Low Power watermarks must be disabled for at least one
> -	 *  frame before enabling sprite scaling, and kept disabled
> -	 *  until sprite scaling is disabled."
> -	 *
> -	 * ILK/SNB DVSASCALE/Scaling Enable
> -	 * "When in Self Refresh Big FIFO mode, scaling enable will be
> -	 *  masked off while Big FIFO mode is exiting."
> -	 *
> -	 * Despite the w/a only being listed for IVB we assume that
> -	 * the ILK/SNB note has similar ramifications, hence we apply
> -	 * the w/a on all three platforms.
> -	 *
> -	 * With experimental results seems this is needed also for primary
> -	 * plane, not only sprite plane.
> -	 */
> -	if (plane->id != PLANE_CURSOR &&
> -	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
> -	     IS_IVYBRIDGE(dev_priv)) &&
> -	    (turn_on || (!needs_scaling(old_plane_state) &&
> -			 needs_scaling(new_plane_state))))
> -		new_crtc_state->disable_lp_wm = true;
> -
> -	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
> -		new_plane_state->do_async_flip = true;
> -
> -	return 0;
> -}
> -
>  static bool encoders_cloneable(const struct intel_encoder *a,
>  			       const struct intel_encoder *b)
>  {

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 2/8] drm/i915: Introduce intel_arm_planes_on_crtc()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason the high level intel_update_crtc() needs to know
that there is something magical about the commit order of
planes between different platforms. So let's hide that
detail even better.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++++++++----
 .../gpu/drm/i915/display/intel_atomic_plane.h |  6 ++----
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-----
 3 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 3355eb637eac..bba2f105b7dd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -716,8 +716,8 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *state,
 	}
 }
 
-void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
-			    struct intel_crtc *crtc)
+static void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
@@ -751,8 +751,8 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
 	}
 }
 
-void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
-			     struct intel_crtc *crtc)
+static void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
@@ -777,6 +777,17 @@ void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
 	}
 }
 
+void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
+			      struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+
+	if (DISPLAY_VER(i915) >= 9)
+		skl_arm_planes_on_crtc(state, crtc);
+	else
+		i9xx_arm_planes_on_crtc(state, crtc);
+}
+
 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
 				      struct intel_crtc_state *crtc_state,
 				      int min_scale, int max_scale,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 9822b921279c..b7973e932e78 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -46,10 +46,8 @@ void intel_plane_destroy_state(struct drm_plane *plane,
 			       struct drm_plane_state *state);
 void intel_update_planes_on_crtc(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc);
-void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
-			    struct intel_crtc *crtc);
-void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
-			     struct intel_crtc *crtc);
+void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
+			      struct intel_crtc *crtc);
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 					struct intel_crtc_state *crtc_state,
 					const struct intel_plane_state *old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3f68fb656fb5..aac1695657df 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7796,7 +7796,6 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 static void intel_update_crtc(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_crtc_state *new_crtc_state =
@@ -7824,10 +7823,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 
 	commit_pipe_pre_planes(state, crtc);
 
-	if (DISPLAY_VER(dev_priv) >= 9)
-		skl_arm_planes_on_crtc(state, crtc);
-	else
-		i9xx_arm_planes_on_crtc(state, crtc);
+	intel_arm_planes_on_crtc(state, crtc);
 
 	commit_pipe_post_planes(state, crtc);
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Introduce intel_arm_planes_on_crtc()

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No reason the high level intel_update_crtc() needs to know
> that there is something magical about the commit order of
> planes between different platforms. So let's hide that
> detail even better.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++++++++----
>  .../gpu/drm/i915/display/intel_atomic_plane.h |  6 ++----
>  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-----
>  3 files changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 3355eb637eac..bba2f105b7dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -716,8 +716,8 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *state,
>  	}
>  }
>  
> -void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> -			    struct intel_crtc *crtc)
> +static void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> +				   struct intel_crtc *crtc)
>  {
>  	struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
> @@ -751,8 +751,8 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
>  	}
>  }
>  
> -void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> -			     struct intel_crtc *crtc)
> +static void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
>  {
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> @@ -777,6 +777,17 @@ void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
>  	}
>  }
>  
> +void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
> +			      struct intel_crtc *crtc)
> +{

I don't much like the intel_arm_ prefix here. I'd go for intel_plane_
something or other.

Can be fixed while applying, or later. *shrug*

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +
> +	if (DISPLAY_VER(i915) >= 9)
> +		skl_arm_planes_on_crtc(state, crtc);
> +	else
> +		i9xx_arm_planes_on_crtc(state, crtc);
> +}
> +
>  int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
>  				      struct intel_crtc_state *crtc_state,
>  				      int min_scale, int max_scale,
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 9822b921279c..b7973e932e78 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -46,10 +46,8 @@ void intel_plane_destroy_state(struct drm_plane *plane,
>  			       struct drm_plane_state *state);
>  void intel_update_planes_on_crtc(struct intel_atomic_state *state,
>  				 struct intel_crtc *crtc);
> -void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> -			    struct intel_crtc *crtc);
> -void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> -			     struct intel_crtc *crtc);
> +void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
> +			      struct intel_crtc *crtc);
>  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
>  					struct intel_crtc_state *crtc_state,
>  					const struct intel_plane_state *old_plane_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3f68fb656fb5..aac1695657df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7796,7 +7796,6 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>  static void intel_update_crtc(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_crtc_state *new_crtc_state =
> @@ -7824,10 +7823,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>  
>  	commit_pipe_pre_planes(state, crtc);
>  
> -	if (DISPLAY_VER(dev_priv) >= 9)
> -		skl_arm_planes_on_crtc(state, crtc);
> -	else
> -		i9xx_arm_planes_on_crtc(state, crtc);
> +	intel_arm_planes_on_crtc(state, crtc);
>  
>  	commit_pipe_post_planes(state, crtc);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Introduce intel_arm_planes_on_crtc()

[Ville Syrjälä]

On Wed, Feb 16, 2022 at 11:38:44AM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > No reason the high level intel_update_crtc() needs to know
> > that there is something magical about the commit order of
> > planes between different platforms. So let's hide that
> > detail even better.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++++++++----
> >  .../gpu/drm/i915/display/intel_atomic_plane.h |  6 ++----
> >  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-----
> >  3 files changed, 18 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 3355eb637eac..bba2f105b7dd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -716,8 +716,8 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *state,
> >  	}
> >  }
> >  
> > -void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> > -			    struct intel_crtc *crtc)
> > +static void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> > +				   struct intel_crtc *crtc)
> >  {
> >  	struct intel_crtc_state *old_crtc_state =
> >  		intel_atomic_get_old_crtc_state(state, crtc);
> > @@ -751,8 +751,8 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> >  	}
> >  }
> >  
> > -void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> > -			     struct intel_crtc *crtc)
> > +static void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> > +				    struct intel_crtc *crtc)
> >  {
> >  	struct intel_crtc_state *new_crtc_state =
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> > @@ -777,6 +777,17 @@ void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> >  	}
> >  }
> >  
> > +void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
> > +			      struct intel_crtc *crtc)
> > +{
> 
> I don't much like the intel_arm_ prefix here. I'd go for intel_plane_
> something or other.

intel_plane_ is rather bad since this operates on multiple planes.
Though I'm not super happy with the _arm_ vs. _update_ thing we have
going on now. The plane hooks I made .update_noarm() and .update_arm()
(which certainly has a few bad puns in it) so should perhaps just
try to follow a similar naming convention for the high level stuff.

I guess I'd prefer intel_crtc_ as the prefix actually since thats
what we pass in anyway.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Introduce intel_arm_planes_on_crtc()

[Jani Nikula]

On Wed, 16 Feb 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 16, 2022 at 11:38:44AM +0200, Jani Nikula wrote:
>> On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > No reason the high level intel_update_crtc() needs to know
>> > that there is something magical about the commit order of
>> > planes between different platforms. So let's hide that
>> > detail even better.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++++++++----
>> >  .../gpu/drm/i915/display/intel_atomic_plane.h |  6 ++----
>> >  drivers/gpu/drm/i915/display/intel_display.c  |  6 +-----
>> >  3 files changed, 18 insertions(+), 13 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> > index 3355eb637eac..bba2f105b7dd 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> > @@ -716,8 +716,8 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *state,
>> >  	}
>> >  }
>> >  
>> > -void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
>> > -			    struct intel_crtc *crtc)
>> > +static void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
>> > +				   struct intel_crtc *crtc)
>> >  {
>> >  	struct intel_crtc_state *old_crtc_state =
>> >  		intel_atomic_get_old_crtc_state(state, crtc);
>> > @@ -751,8 +751,8 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
>> >  	}
>> >  }
>> >  
>> > -void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
>> > -			     struct intel_crtc *crtc)
>> > +static void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
>> > +				    struct intel_crtc *crtc)
>> >  {
>> >  	struct intel_crtc_state *new_crtc_state =
>> >  		intel_atomic_get_new_crtc_state(state, crtc);
>> > @@ -777,6 +777,17 @@ void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
>> >  	}
>> >  }
>> >  
>> > +void intel_arm_planes_on_crtc(struct intel_atomic_state *state,
>> > +			      struct intel_crtc *crtc)
>> > +{
>> 
>> I don't much like the intel_arm_ prefix here. I'd go for intel_plane_
>> something or other.
>
> intel_plane_ is rather bad since this operates on multiple planes.
> Though I'm not super happy with the _arm_ vs. _update_ thing we have
> going on now. The plane hooks I made .update_noarm() and .update_arm()
> (which certainly has a few bad puns in it) so should perhaps just
> try to follow a similar naming convention for the high level stuff.
>
> I guess I'd prefer intel_crtc_ as the prefix actually since thats
> what we pass in anyway.

We can bikeshed this later, I think the patch is net positive as-is.

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 3/8] drm/i915: Introduce scaled_planes bitmask

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add another plane bitmask, this time tracking which planes are
scaled. This is going to be useful in ILK watermark computations,
and skl+ pipe scaler assignments.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c  | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index bba2f105b7dd..79720bd5a485 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -323,6 +323,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 
 	crtc_state->active_planes &= ~BIT(plane->id);
+	crtc_state->scaled_planes &= ~BIT(plane->id);
 	crtc_state->nv12_planes &= ~BIT(plane->id);
 	crtc_state->c8_planes &= ~BIT(plane->id);
 	crtc_state->data_rate[plane->id] = 0;
@@ -536,6 +537,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	if (new_plane_state->uapi.visible)
 		new_crtc_state->active_planes |= BIT(plane->id);
 
+	if (new_plane_state->uapi.visible &&
+	    intel_plane_is_scaled(new_plane_state))
+		new_crtc_state->scaled_planes |= BIT(plane->id);
+
 	if (new_plane_state->uapi.visible &&
 	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 		new_crtc_state->nv12_planes |= BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 60e15226a8cb..7a5c1e334449 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1168,6 +1168,7 @@ struct intel_crtc_state {
 
 	/* bitmask of actually visible planes (enum plane_id) */
 	u8 active_planes;
+	u8 scaled_planes;
 	u8 nv12_planes;
 	u8 c8_planes;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Introduce scaled_planes bitmask

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add another plane bitmask, this time tracking which planes are
> scaled. This is going to be useful in ILK watermark computations,
> and skl+ pipe scaler assignments.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_atomic_plane.c  | 5 +++++
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index bba2f105b7dd..79720bd5a485 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -323,6 +323,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>  
>  	crtc_state->active_planes &= ~BIT(plane->id);
> +	crtc_state->scaled_planes &= ~BIT(plane->id);
>  	crtc_state->nv12_planes &= ~BIT(plane->id);
>  	crtc_state->c8_planes &= ~BIT(plane->id);
>  	crtc_state->data_rate[plane->id] = 0;
> @@ -536,6 +537,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	if (new_plane_state->uapi.visible)
>  		new_crtc_state->active_planes |= BIT(plane->id);
>  
> +	if (new_plane_state->uapi.visible &&
> +	    intel_plane_is_scaled(new_plane_state))
> +		new_crtc_state->scaled_planes |= BIT(plane->id);
> +
>  	if (new_plane_state->uapi.visible &&
>  	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
>  		new_crtc_state->nv12_planes |= BIT(plane->id);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 60e15226a8cb..7a5c1e334449 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1168,6 +1168,7 @@ struct intel_crtc_state {
>  
>  	/* bitmask of actually visible planes (enum plane_id) */
>  	u8 active_planes;
> +	u8 scaled_planes;
>  	u8 nv12_planes;
>  	u8 c8_planes;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 4/8] drm/i915: Use {active, scaled}_planes to compute ilk watermarks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the {active,scaled}_planes bitmasks from the crtc state
rather than poking at the plane state directly. One step
towards eliminating the last use of the somewhat questionble
intel_atomic_crtc_state_for_each_plane_state() macro which
peeks into the plane state without actually holding the plane
mutex.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f2f0e80beef..0fa3dce9bd54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3179,12 +3179,8 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
 	}
 
 	pipe_wm->pipe_enabled = crtc_state->hw.active;
-	if (sprstate) {
-		pipe_wm->sprites_enabled = sprstate->uapi.visible;
-		pipe_wm->sprites_scaled = sprstate->uapi.visible &&
-			(drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
-			 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
-	}
+	pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);
+	pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);
 
 	usable_level = max_level;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Use {active, scaled}_planes to compute ilk watermarks

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the {active,scaled}_planes bitmasks from the crtc state
> rather than poking at the plane state directly. One step
> towards eliminating the last use of the somewhat questionble
> intel_atomic_crtc_state_for_each_plane_state() macro which
> peeks into the plane state without actually holding the plane
> mutex.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4f2f0e80beef..0fa3dce9bd54 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3179,12 +3179,8 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
>  	}
>  
>  	pipe_wm->pipe_enabled = crtc_state->hw.active;
> -	if (sprstate) {
> -		pipe_wm->sprites_enabled = sprstate->uapi.visible;
> -		pipe_wm->sprites_scaled = sprstate->uapi.visible &&
> -			(drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
> -			 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
> -	}
> +	pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);
> +	pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);
>  
>  	usable_level = max_level;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 5/8] drm/i915: Remove gen6_check_mch_setup()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

snb_wm_latency_quirk() already boosts up the latency values
so the extra warning about the SSKPD value being insufficient
is now redundant. Drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0fa3dce9bd54..34e46a9b8300 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7432,17 +7432,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
-{
-	u32 tmp;
-
-	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
-	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
-		drm_dbg_kms(&dev_priv->drm,
-			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
-			    tmp);
-}
-
 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -7500,8 +7489,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 	g4x_disable_trickle_feed(dev_priv);
 
 	cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7853,8 +7840,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	if (!HAS_PCH_NOP(dev_priv))
 		cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.34.1

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Remove gen6_check_mch_setup()

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> snb_wm_latency_quirk() already boosts up the latency values
> so the extra warning about the SSKPD value being insufficient
> is now redundant. Drop it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I just might not understand what's going on...

...but snb_wm_latency_quirk() is only called for display 6, not for ivb
where the check is also removed?

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
>  1 file changed, 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0fa3dce9bd54..34e46a9b8300 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7432,17 +7432,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> -{
> -	u32 tmp;
> -
> -	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
> -	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> -			    tmp);
> -}
> -
>  static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> @@ -7500,8 +7489,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>  	g4x_disable_trickle_feed(dev_priv);
>  
>  	cpt_init_clock_gating(dev_priv);
> -
> -	gen6_check_mch_setup(dev_priv);
>  }
>  
>  static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7853,8 +7840,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	if (!HAS_PCH_NOP(dev_priv))
>  		cpt_init_clock_gating(dev_priv);
> -
> -	gen6_check_mch_setup(dev_priv);
>  }
>  
>  static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Remove gen6_check_mch_setup()

[Ville Syrjälä]

On Wed, Feb 16, 2022 at 11:54:00AM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > snb_wm_latency_quirk() already boosts up the latency values
> > so the extra warning about the SSKPD value being insufficient
> > is now redundant. Drop it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I just might not understand what's going on...
> 
> ...but snb_wm_latency_quirk() is only called for display 6, not for ivb
> where the check is also removed?

Hmm. Not sure this was ever an issue on IVB. I think the BIOSen
might have gotten all fixed by that time. Not sure. I guess we can
keep this for now. And maybe I should just rewrite to look at the
parsed latency values instead...

> 
> BR,
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
> >  1 file changed, 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0fa3dce9bd54..34e46a9b8300 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7432,17 +7432,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > -static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> > -{
> > -	u32 tmp;
> > -
> > -	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
> > -	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
> > -		drm_dbg_kms(&dev_priv->drm,
> > -			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> > -			    tmp);
> > -}
> > -
> >  static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > @@ -7500,8 +7489,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	g4x_disable_trickle_feed(dev_priv);
> >  
> >  	cpt_init_clock_gating(dev_priv);
> > -
> > -	gen6_check_mch_setup(dev_priv);
> >  }
> >  
> >  static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> > @@ -7853,8 +7840,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >  
> >  	if (!HAS_PCH_NOP(dev_priv))
> >  		cpt_init_clock_gating(dev_priv);
> > -
> > -	gen6_check_mch_setup(dev_priv);
> >  }
> >  
> >  static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 6/8] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We treat SSKPD as a 64 bit register. Add the support macros
to define/extract bits in such registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 57 +++++++++++++++++++++-------
 1 file changed, 43 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 34d37bbf08cd..069799aa3768 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -22,20 +22,35 @@
 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
 				 ((__n) < 0 || (__n) > 31))))
 
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low)					\
-	((u32)(GENMASK(__high, __low) +					\
-	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
+#define _REG_GENMASK(__type, __high, __low)				\
+	((__type)(GENMASK(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
 				 __is_constexpr(__low) &&		\
-				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+				 ((__low) < 0 ||			\
+				  (__high) >= BITS_PER_TYPE(__type) ||	\
+				  (__low) > (__high)))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) _REG_GENMASK(u32, __high, __low)
+
+/**
+ * REG_GENMASK64() - Prepare a continuous u64 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
 
 /*
  * Local integer constant expression version of is_power_of_2().
@@ -59,6 +74,8 @@
 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
 
+#define _REG_FIELD_GET(__type, __mask, __val)	((__type)FIELD_GET(__mask, __val))
+
 /**
  * REG_FIELD_GET() - Extract a u32 bitfield value
  * @__mask: shifted mask defining the field's length and position
@@ -69,7 +86,19 @@
  *
  * @return: Masked and shifted value of the field defined by @__mask in @__val.
  */
-#define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
+#define REG_FIELD_GET(__mask, __val)	_REG_FIELD_GET(u32, __mask, __val)
+
+/**
+ * REG_FIELD_GET64() - Extract a u64 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u64 and for consistency with
+ * REG_GENMASK64().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET64(__mask, __val)	_REG_FIELD_GET(u64, __mask, __val)
 
 typedef struct {
 	u32 reg;
-- 
2.34.1

[Intel-gfx] [PATCH v2 6/8] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We treat SSKPD as a 64 bit register. Add the support macros
to define/extract bits in such registers.

v2: Fix 32bit builds

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 34d37bbf08cd..d78d78fce431 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -37,6 +37,21 @@
 				 __is_constexpr(__low) &&		\
 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
 
+/**
+ * REG_GENMASK64() - Prepare a continuous u64 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK64(__high, __low)					\
+	((u64)(GENMASK_ULL(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
+
 /*
  * Local integer constant expression version of is_power_of_2().
  */
@@ -71,6 +86,18 @@
  */
 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
 
+/**
+ * REG_FIELD_GET64() - Extract a u64 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u64 and for consistency with
+ * REG_GENMASK64().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
+
 typedef struct {
 	u32 reg;
 } i915_reg_t;
-- 
2.34.1

Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We treat SSKPD as a 64 bit register. Add the support macros
> to define/extract bits in such registers.
>
> v2: Fix 32bit builds
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index 34d37bbf08cd..d78d78fce431 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -37,6 +37,21 @@
>  				 __is_constexpr(__low) &&		\
>  				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
>  
> +/**
> + * REG_GENMASK64() - Prepare a continuous u64 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK64(__high, __low)					\
> +	((u64)(GENMASK_ULL(__high, __low) +				\
> +	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
> +				 __is_constexpr(__low) &&		\
> +				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
> +
>  /*
>   * Local integer constant expression version of is_power_of_2().
>   */
> @@ -71,6 +86,18 @@
>   */
>  #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
>  
> +/**
> + * REG_FIELD_GET64() - Extract a u64 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u64 and for consistency with
> + * REG_GENMASK64().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
> +
>  typedef struct {
>  	u32 reg;
>  } i915_reg_t;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Give names to the SSKPD/MLTR fields, and use the
REG_GENMASK* and REG_FIELD_GET*.

Also drop the bogus non-mirrored SSKP register define.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 27 ++++++++++++---------------
 drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++------------
 2 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c92314ee26..278c9cbc6f3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1896,10 +1896,17 @@
 #define   MAD_DIMM_A_SIZE_SHIFT		0
 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
 
-/* snb MCH registers for priority tuning */
 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define   MCH_SSKPD_WM0_MASK		0x3f
-#define   MCH_SSKPD_WM0_VAL		0xc
+#define   SSKPD_NEW_WM0_MASK_HSW	REG_GENMASK64(63, 56)
+#define   SSKPD_WM4_MASK_HSW		REG_GENMASK64(40, 32)
+#define   SSKPD_WM3_MASK_HSW		REG_GENMASK64(28, 20)
+#define   SSKPD_WM2_MASK_HSW		REG_GENMASK64(19, 12)
+#define   SSKPD_WM1_MASK_HSW		REG_GENMASK64(11, 4)
+#define   SSKPD_OLD_WM0_MASK_HSW	REG_GENMASK64(3, 0)
+#define   SSKPD_WM3_MASK_SNB		REG_GENMASK(29, 24)
+#define   SSKPD_WM2_MASK_SNB		REG_GENMASK(21, 16)
+#define   SSKPD_WM1_MASK_SNB		REG_GENMASK(13, 8)
+#define   SSKPD_WM0_MASK_SNB		REG_GENMASK(5, 0)
 
 /* Clocking configuration register */
 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
@@ -4321,19 +4328,9 @@
 
 /* Memory latency timer register */
 #define MLTR_ILK		_MMIO(0x11222)
-#define  MLTR_WM1_SHIFT		0
-#define  MLTR_WM2_SHIFT		8
 /* the unit of memory self-refresh latency time is 0.5us */
-#define  ILK_SRLT_MASK		0x3f
-
-
-/* the address where we get all kinds of latency value */
-#define SSKPD			_MMIO(0x5d10)
-#define SSKPD_WM_MASK		0x3f
-#define SSKPD_WM0_SHIFT		0
-#define SSKPD_WM1_SHIFT		8
-#define SSKPD_WM2_SHIFT		16
-#define SSKPD_WM3_SHIFT		24
+#define  MLTR_WM2_MASK		REG_GENMASK(13, 8)
+#define  MLTR_WM1_MASK		REG_GENMASK(5, 0)
 
 /*
  * The two pipe frame counter registers are not synchronized, so
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34e46a9b8300..605944551e1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2946,27 +2946,27 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
 
-		wm[0] = (sskpd >> 56) & 0xFF;
+		wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
 		if (wm[0] == 0)
-			wm[0] = sskpd & 0xF;
-		wm[1] = (sskpd >> 4) & 0xFF;
-		wm[2] = (sskpd >> 12) & 0xFF;
-		wm[3] = (sskpd >> 20) & 0x1FF;
-		wm[4] = (sskpd >> 32) & 0x1FF;
+			wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
+		wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
+		wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
+		wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
+		wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
 	} else if (DISPLAY_VER(dev_priv) >= 6) {
 		u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
 
-		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
-		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
-		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
-		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
+		wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
+		wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
+		wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
+		wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
 	} else if (DISPLAY_VER(dev_priv) >= 5) {
 		u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
 
 		/* ILK primary LP0 latency is 700 ns */
 		wm[0] = 7;
-		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
-		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
+		wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
+		wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
 	} else {
 		MISSING_CASE(INTEL_DEVID(dev_priv));
 	}
-- 
2.34.1

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[kernel test robot]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a011 (https://download.01.org/0day-ci/archive/20220211/202202112244.gwKGUmOj-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project f6685f774697c85d6a352dcea013f46a99f9fe31)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 11 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 11 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 12 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 12 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)


vim +2949 drivers/gpu/drm/i915/intel_pm.c

  2859	
  2860	static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
  2861					  u16 wm[8])
  2862	{
  2863		struct intel_uncore *uncore = &dev_priv->uncore;
  2864	
  2865		if (DISPLAY_VER(dev_priv) >= 9) {
  2866			u32 val;
  2867			int ret, i;
  2868			int level, max_level = ilk_wm_max_level(dev_priv);
  2869			int mult = IS_DG2(dev_priv) ? 2 : 1;
  2870	
  2871			/* read the first set of memory latencies[0:3] */
  2872			val = 0; /* data0 to be programmed to 0 for first set */
  2873			ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
  2874					     &val, NULL);
  2875	
  2876			if (ret) {
  2877				drm_err(&dev_priv->drm,
  2878					"SKL Mailbox read error = %d\n", ret);
  2879				return;
  2880			}
  2881	
  2882			wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2883			wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
  2884					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2885			wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
  2886					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2887			wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
  2888					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2889	
  2890			/* read the second set of memory latencies[4:7] */
  2891			val = 1; /* data0 to be programmed to 1 for second set */
  2892			ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
  2893					     &val, NULL);
  2894			if (ret) {
  2895				drm_err(&dev_priv->drm,
  2896					"SKL Mailbox read error = %d\n", ret);
  2897				return;
  2898			}
  2899	
  2900			wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2901			wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
  2902					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2903			wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
  2904					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2905			wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
  2906					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2907	
  2908			/*
  2909			 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
  2910			 * need to be disabled. We make sure to sanitize the values out
  2911			 * of the punit to satisfy this requirement.
  2912			 */
  2913			for (level = 1; level <= max_level; level++) {
  2914				if (wm[level] == 0) {
  2915					for (i = level + 1; i <= max_level; i++)
  2916						wm[i] = 0;
  2917	
  2918					max_level = level - 1;
  2919	
  2920					break;
  2921				}
  2922			}
  2923	
  2924			/*
  2925			 * WaWmMemoryReadLatency
  2926			 *
  2927			 * punit doesn't take into account the read latency so we need
  2928			 * to add proper adjustement to each valid level we retrieve
  2929			 * from the punit when level 0 response data is 0us.
  2930			 */
  2931			if (wm[0] == 0) {
  2932				u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
  2933	
  2934				for (level = 0; level <= max_level; level++)
  2935					wm[level] += adjust;
  2936			}
  2937	
  2938			/*
  2939			 * WA Level-0 adjustment for 16GB DIMMs: SKL+
  2940			 * If we could not get dimm info enable this WA to prevent from
  2941			 * any underrun. If not able to get Dimm info assume 16GB dimm
  2942			 * to avoid any underrun.
  2943			 */
  2944			if (dev_priv->dram_info.wm_lv_0_adjust_needed)
  2945				wm[0] += 1;
  2946		} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
  2947			u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
  2948	
> 2949			wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
  2950			if (wm[0] == 0)
  2951				wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
  2952			wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
  2953			wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
  2954			wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
  2955			wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
  2956		} else if (DISPLAY_VER(dev_priv) >= 6) {
  2957			u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
  2958	
  2959			wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
  2960			wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
  2961			wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
  2962			wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
  2963		} else if (DISPLAY_VER(dev_priv) >= 5) {
  2964			u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
  2965	
  2966			/* ILK primary LP0 latency is 700 ns */
  2967			wm[0] = 7;
  2968			wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
  2969			wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
  2970		} else {
  2971			MISSING_CASE(INTEL_DEVID(dev_priv));
  2972		}
  2973	}
  2974	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 44589 bytes --]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a011 (https://download.01.org/0day-ci/archive/20220211/202202112244.gwKGUmOj-lkp(a)intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project f6685f774697c85d6a352dcea013f46a99f9fe31)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 9 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 10 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:61: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                               ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 11 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 11 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count >= width of type [-Wshift-count-overflow]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 12 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
   include/linux/compiler_types.h:326:9: note: expanded from macro '__compiletime_assert'
                   if (!(condition))                                       \
                   ~~~~~~^~~~~~~~~~~
   include/linux/compiler.h:56:47: note: expanded from macro 'if'
   #define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) )
                              ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler.h:58:52: note: expanded from macro '__trace_if_var'
   #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
                                                      ^~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: warning: shift count is negative [-Wshift-count-negative]
                   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: expanded from macro 'SSKPD_NEW_WM0_MASK_HSW'
   #define   SSKPD_NEW_WM0_MASK_HSW        REG_GENMASK64(63, 56)
                                           ^
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: expanded from macro 'REG_GENMASK64'
   #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                        ^
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: expanded from macro '_REG_GENMASK'
           ((__type)(GENMASK(__high, __low) +                              \
                     ^
   note: (skipping 12 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)


vim +2949 drivers/gpu/drm/i915/intel_pm.c

  2859	
  2860	static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
  2861					  u16 wm[8])
  2862	{
  2863		struct intel_uncore *uncore = &dev_priv->uncore;
  2864	
  2865		if (DISPLAY_VER(dev_priv) >= 9) {
  2866			u32 val;
  2867			int ret, i;
  2868			int level, max_level = ilk_wm_max_level(dev_priv);
  2869			int mult = IS_DG2(dev_priv) ? 2 : 1;
  2870	
  2871			/* read the first set of memory latencies[0:3] */
  2872			val = 0; /* data0 to be programmed to 0 for first set */
  2873			ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
  2874					     &val, NULL);
  2875	
  2876			if (ret) {
  2877				drm_err(&dev_priv->drm,
  2878					"SKL Mailbox read error = %d\n", ret);
  2879				return;
  2880			}
  2881	
  2882			wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2883			wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
  2884					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2885			wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
  2886					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2887			wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
  2888					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2889	
  2890			/* read the second set of memory latencies[4:7] */
  2891			val = 1; /* data0 to be programmed to 1 for second set */
  2892			ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
  2893					     &val, NULL);
  2894			if (ret) {
  2895				drm_err(&dev_priv->drm,
  2896					"SKL Mailbox read error = %d\n", ret);
  2897				return;
  2898			}
  2899	
  2900			wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2901			wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
  2902					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2903			wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
  2904					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2905			wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
  2906					GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
  2907	
  2908			/*
  2909			 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
  2910			 * need to be disabled. We make sure to sanitize the values out
  2911			 * of the punit to satisfy this requirement.
  2912			 */
  2913			for (level = 1; level <= max_level; level++) {
  2914				if (wm[level] == 0) {
  2915					for (i = level + 1; i <= max_level; i++)
  2916						wm[i] = 0;
  2917	
  2918					max_level = level - 1;
  2919	
  2920					break;
  2921				}
  2922			}
  2923	
  2924			/*
  2925			 * WaWmMemoryReadLatency
  2926			 *
  2927			 * punit doesn't take into account the read latency so we need
  2928			 * to add proper adjustement to each valid level we retrieve
  2929			 * from the punit when level 0 response data is 0us.
  2930			 */
  2931			if (wm[0] == 0) {
  2932				u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
  2933	
  2934				for (level = 0; level <= max_level; level++)
  2935					wm[level] += adjust;
  2936			}
  2937	
  2938			/*
  2939			 * WA Level-0 adjustment for 16GB DIMMs: SKL+
  2940			 * If we could not get dimm info enable this WA to prevent from
  2941			 * any underrun. If not able to get Dimm info assume 16GB dimm
  2942			 * to avoid any underrun.
  2943			 */
  2944			if (dev_priv->dram_info.wm_lv_0_adjust_needed)
  2945				wm[0] += 1;
  2946		} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
  2947			u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
  2948	
> 2949			wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
  2950			if (wm[0] == 0)
  2951				wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
  2952			wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
  2953			wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
  2954			wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
  2955			wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
  2956		} else if (DISPLAY_VER(dev_priv) >= 6) {
  2957			u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
  2958	
  2959			wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
  2960			wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
  2961			wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
  2962			wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
  2963		} else if (DISPLAY_VER(dev_priv) >= 5) {
  2964			u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
  2965	
  2966			/* ILK primary LP0 latency is 700 ns */
  2967			wm[0] = 7;
  2968			wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
  2969			wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
  2970		} else {
  2971			MISSING_CASE(INTEL_DEVID(dev_priv));
  2972		}
  2973	}
  2974	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

Hi Ville,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (https://download.01.org/0day-ci/archive/20220211/202202112353.zFgGmyBW-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:66:16: error: right shift count is negative [-Werror=shift-count-negative]
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
--
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:72:18: error: left shift count is negative [-Werror=shift-count-negative]
      72 |            (1ULL << __bf_shf(_mask))); \
         |                  ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
..


vim +66 include/linux/bitfield.h

bff8c3848e071d3 Peter Zijlstra 2021-11-10  59  
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  60  #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  61  	({								\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  62  		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  63  				 _pfx "mask is not constant");		\
e36488c83b6d871 Arnd Bergmann  2018-08-17  64  		BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero");	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  65  		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @66  				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  67  				 _pfx "value too large for the field"); \
bff8c3848e071d3 Peter Zijlstra 2021-11-10  68  		BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) >	\
bff8c3848e071d3 Peter Zijlstra 2021-11-10  69  				 __bf_cast_unsigned(_reg, ~0ull),	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  70  				 _pfx "type of reg too small for mask"); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  71  		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @72  					      (1ULL << __bf_shf(_mask))); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  73  	})
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  74  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 30135 bytes --]

Hi Ville,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (https://download.01.org/0day-ci/archive/20220211/202202112353.zFgGmyBW-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:66:16: error: right shift count is negative [-Werror=shift-count-negative]
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
--
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:72:18: error: left shift count is negative [-Werror=shift-count-negative]
      72 |            (1ULL << __bf_shf(_mask))); \
         |                  ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
..


vim +66 include/linux/bitfield.h

bff8c3848e071d3 Peter Zijlstra 2021-11-10  59  
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  60  #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  61  	({								\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  62  		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  63  				 _pfx "mask is not constant");		\
e36488c83b6d871 Arnd Bergmann  2018-08-17  64  		BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero");	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  65  		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @66  				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  67  				 _pfx "value too large for the field"); \
bff8c3848e071d3 Peter Zijlstra 2021-11-10  68  		BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) >	\
bff8c3848e071d3 Peter Zijlstra 2021-11-10  69  				 __bf_cast_unsigned(_reg, ~0ull),	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  70  				 _pfx "type of reg too small for mask"); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  71  		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @72  					      (1ULL << __bf_shf(_mask))); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  73  	})
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  74  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[kernel test robot]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-debian-10.3 (https://download.01.org/0day-ci/archive/20220212/202202120007.9ivbCK9s-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:66:16: warning: right shift count is negative [-Wshift-count-negative]
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
--
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:72:18: warning: left shift count is negative [-Wshift-count-negative]
      72 |            (1ULL << __bf_shf(_mask))); \
         |                  ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
..


vim +66 include/linux/bitfield.h

bff8c3848e071d3 Peter Zijlstra 2021-11-10  59  
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  60  #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  61  	({								\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  62  		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  63  				 _pfx "mask is not constant");		\
e36488c83b6d871 Arnd Bergmann  2018-08-17  64  		BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero");	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  65  		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @66  				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  67  				 _pfx "value too large for the field"); \
bff8c3848e071d3 Peter Zijlstra 2021-11-10  68  		BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) >	\
bff8c3848e071d3 Peter Zijlstra 2021-11-10  69  				 __bf_cast_unsigned(_reg, ~0ull),	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  70  				 _pfx "type of reg too small for mask"); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  71  		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @72  					      (1ULL << __bf_shf(_mask))); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  73  	})
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  74  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 30133 bytes --]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20220211]
[cannot apply to v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-debian-10.3 (https://download.01.org/0day-ci/archive/20220212/202202120007.9ivbCK9s-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-wm-cleanups/20220211-170856
        git checkout 24cedeb8c8ca97104e12936a4647665dd0e9b0f8
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:66:19: note: in expansion of macro '__bf_shf'
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                   ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:66:16: warning: right shift count is negative [-Wshift-count-negative]
      66 |      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
         |                ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:65:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      65 |   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |   ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:20: note: in expansion of macro '__bf_cast_unsigned'
      68 |   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
         |                    ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
--
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:72:21: note: in expansion of macro '__bf_shf'
      72 |            (1ULL << __bf_shf(_mask))); \
         |                     ^~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:72:18: warning: left shift count is negative [-Wshift-count-negative]
      72 |            (1ULL << __bf_shf(_mask))); \
         |                  ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
      35 |  (((~UL(0)) - (UL(1) << (l)) + 1) & \
         |                      ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:125:3: note: in expansion of macro '__BF_FIELD_CHECK'
     125 |   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
         |   ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro 'FIELD_GET'
      77 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
         |                                                        ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro '_REG_FIELD_GET'
     101 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
         |                                        ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro 'REG_FIELD_GET64'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |           ^~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
      38 |  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
         |                               ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro 'GENMASK'
      26 |  ((__type)(GENMASK(__high, __low) +    \
         |            ^~~~~~~
   drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro '_REG_GENMASK'
      53 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
         |                                      ^~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro 'REG_GENMASK64'
    1900 | #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
         |                                  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
    2949 |   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
         |                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
      36 |   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
         |           ^~
   include/linux/compiler_types.h:326:9: note: in definition of macro '__compiletime_assert'
     326 |   if (!(condition))     \
         |         ^~~~~~~~~
   include/linux/compiler_types.h:346:2: note: in expansion of macro '_compiletime_assert'
     346 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |  ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
         |  ^~~~~~~~~~~~~~~~
   include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
      21 |  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
         |  ^~~~~~~~~~~~
   include/linux/bitfield.h:71:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
      71 |   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
..


vim +66 include/linux/bitfield.h

bff8c3848e071d3 Peter Zijlstra 2021-11-10  59  
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  60  #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  61  	({								\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  62  		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  63  				 _pfx "mask is not constant");		\
e36488c83b6d871 Arnd Bergmann  2018-08-17  64  		BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero");	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  65  		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @66  				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  67  				 _pfx "value too large for the field"); \
bff8c3848e071d3 Peter Zijlstra 2021-11-10  68  		BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) >	\
bff8c3848e071d3 Peter Zijlstra 2021-11-10  69  				 __bf_cast_unsigned(_reg, ~0ull),	\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  70  				 _pfx "type of reg too small for mask"); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  71  		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
3e9b3112ec74f19 Jakub Kicinski 2016-08-31 @72  					      (1ULL << __bf_shf(_mask))); \
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  73  	})
3e9b3112ec74f19 Jakub Kicinski 2016-08-31  74  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give names to the SSKPD/MLTR fields, and use the
> REG_GENMASK* and REG_FIELD_GET*.
>
> Also drop the bogus non-mirrored SSKP register define.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 27 ++++++++++++---------------
>  drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++------------
>  2 files changed, 24 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 87c92314ee26..278c9cbc6f3c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1896,10 +1896,17 @@
>  #define   MAD_DIMM_A_SIZE_SHIFT		0
>  #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
>  
> -/* snb MCH registers for priority tuning */
>  #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
> -#define   MCH_SSKPD_WM0_MASK		0x3f
> -#define   MCH_SSKPD_WM0_VAL		0xc
> +#define   SSKPD_NEW_WM0_MASK_HSW	REG_GENMASK64(63, 56)
> +#define   SSKPD_WM4_MASK_HSW		REG_GENMASK64(40, 32)
> +#define   SSKPD_WM3_MASK_HSW		REG_GENMASK64(28, 20)
> +#define   SSKPD_WM2_MASK_HSW		REG_GENMASK64(19, 12)
> +#define   SSKPD_WM1_MASK_HSW		REG_GENMASK64(11, 4)
> +#define   SSKPD_OLD_WM0_MASK_HSW	REG_GENMASK64(3, 0)
> +#define   SSKPD_WM3_MASK_SNB		REG_GENMASK(29, 24)
> +#define   SSKPD_WM2_MASK_SNB		REG_GENMASK(21, 16)
> +#define   SSKPD_WM1_MASK_SNB		REG_GENMASK(13, 8)
> +#define   SSKPD_WM0_MASK_SNB		REG_GENMASK(5, 0)
>  
>  /* Clocking configuration register */
>  #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
> @@ -4321,19 +4328,9 @@
>  
>  /* Memory latency timer register */
>  #define MLTR_ILK		_MMIO(0x11222)
> -#define  MLTR_WM1_SHIFT		0
> -#define  MLTR_WM2_SHIFT		8
>  /* the unit of memory self-refresh latency time is 0.5us */
> -#define  ILK_SRLT_MASK		0x3f
> -
> -
> -/* the address where we get all kinds of latency value */
> -#define SSKPD			_MMIO(0x5d10)
> -#define SSKPD_WM_MASK		0x3f
> -#define SSKPD_WM0_SHIFT		0
> -#define SSKPD_WM1_SHIFT		8
> -#define SSKPD_WM2_SHIFT		16
> -#define SSKPD_WM3_SHIFT		24
> +#define  MLTR_WM2_MASK		REG_GENMASK(13, 8)
> +#define  MLTR_WM1_MASK		REG_GENMASK(5, 0)
>  
>  /*
>   * The two pipe frame counter registers are not synchronized, so
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 34e46a9b8300..605944551e1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2946,27 +2946,27 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
>  
> -		wm[0] = (sskpd >> 56) & 0xFF;
> +		wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
>  		if (wm[0] == 0)
> -			wm[0] = sskpd & 0xF;
> -		wm[1] = (sskpd >> 4) & 0xFF;
> -		wm[2] = (sskpd >> 12) & 0xFF;
> -		wm[3] = (sskpd >> 20) & 0x1FF;
> -		wm[4] = (sskpd >> 32) & 0x1FF;
> +			wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
> +		wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
> +		wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
> +		wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
> +		wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
>  	} else if (DISPLAY_VER(dev_priv) >= 6) {
>  		u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
>  
> -		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
> -		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
> -		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
> -		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> +		wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
> +		wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
> +		wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
> +		wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
>  	} else if (DISPLAY_VER(dev_priv) >= 5) {
>  		u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
>  
>  		/* ILK primary LP0 latency is 700 ns */
>  		wm[0] = 7;
> -		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
> -		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
> +		wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
> +		wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
>  	} else {
>  		MISSING_CASE(INTEL_DEVID(dev_priv));
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 8/8] drm/i915: Polish ilk+ wm register bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_GENMASK() & co. for ilk+ watermarm registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 41 +++++++------
 drivers/gpu/drm/i915/intel_pm.c               | 57 +++++++++----------
 3 files changed, 49 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004d470f..b219e162f1d1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -78,7 +78,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	if (DISPLAY_VER(dev_priv) >= 9)
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
+		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
 	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
 		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 278c9cbc6f3c..0dd4d34e7cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4298,33 +4298,32 @@
 #define _WM0_PIPEC_IVB		0x45200
 #define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
 					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
-#define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
-#define  WM0_PIPE_PLANE_SHIFT	16
-#define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
-#define  WM0_PIPE_SPRITE_SHIFT	8
-#define  WM0_PIPE_CURSOR_MASK	(0xff)
+#define  WM0_PIPE_PRIMARY_MASK	REG_GENMASK(23, 16)
+#define  WM0_PIPE_SPRITE_MASK	REG_GENMASK(15, 8)
+#define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(5, 0)
+#define  WM0_PIPE_PRIMARY(x)	REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
+#define  WM0_PIPE_SPRITE(x)	REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
+#define  WM0_PIPE_CURSOR(x)	REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
 #define WM1_LP_ILK		_MMIO(0x45108)
-#define  WM1_LP_SR_EN		(1 << 31)
-#define  WM1_LP_LATENCY_SHIFT	24
-#define  WM1_LP_LATENCY_MASK	(0x7f << 24)
-#define  WM1_LP_FBC_MASK	(0xf << 20)
-#define  WM1_LP_FBC_SHIFT	20
-#define  WM1_LP_FBC_SHIFT_BDW	19
-#define  WM1_LP_SR_MASK		(0x7ff << 8)
-#define  WM1_LP_SR_SHIFT	8
-#define  WM1_LP_CURSOR_MASK	(0xff)
 #define WM2_LP_ILK		_MMIO(0x4510c)
-#define  WM2_LP_EN		(1 << 31)
 #define WM3_LP_ILK		_MMIO(0x45110)
-#define  WM3_LP_EN		(1 << 31)
+#define  WM_LP_ENABLE		REG_BIT(31)
+#define  WM_LP_LATENCY_MASK	REG_GENMASK(30, 24)
+#define  WM_LP_FBC_MASK_BDW	REG_GENMASK(23, 19)
+#define  WM_LP_FBC_MASK_ILK	REG_GENMASK(23, 20)
+#define  WM_LP_PRIMARY_MASK	REG_GENMASK(18, 8)
+#define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
+#define  WM_LP_LATENCY(x)	REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
+#define  WM_LP_FBC_BDW(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
+#define  WM_LP_FBC_ILK(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
+#define  WM_LP_PRIMARY(x)	REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
+#define  WM_LP_CURSOR(x)	REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
 #define WM1S_LP_ILK		_MMIO(0x45120)
 #define WM2S_LP_IVB		_MMIO(0x45124)
 #define WM3S_LP_IVB		_MMIO(0x45128)
-#define  WM1S_LP_EN		(1 << 31)
-
-#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
-	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
-	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
+#define  WM_LP_SPRITE_ENABLE	REG_BIT(31) /* ilk/snb WM1S only */
+#define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
+#define  WM_LP_SPRITE(x)	REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
 
 /* Memory latency timer register */
 #define MLTR_ILK		_MMIO(0x11222)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 605944551e1b..9382284134e6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3409,29 +3409,28 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 		 * disabled. Doing otherwise could cause underruns.
 		 */
 		results->wm_lp[wm_lp - 1] =
-			(ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
-			(r->pri_val << WM1_LP_SR_SHIFT) |
-			r->cur_val;
+			WM_LP_LATENCY(ilk_wm_lp_latency(dev_priv, level)) |
+			WM_LP_PRIMARY(r->pri_val) |
+			WM_LP_CURSOR(r->cur_val);
 
 		if (r->enable)
-			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
+			results->wm_lp[wm_lp - 1] |= WM_LP_ENABLE;
 
 		if (DISPLAY_VER(dev_priv) >= 8)
-			results->wm_lp[wm_lp - 1] |=
-				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
+			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_BDW(r->fbc_val);
 		else
-			results->wm_lp[wm_lp - 1] |=
-				r->fbc_val << WM1_LP_FBC_SHIFT;
+			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_ILK(r->fbc_val);
+
+		results->wm_lp_spr[wm_lp - 1] = WM_LP_SPRITE(r->spr_val);
 
 		/*
-		 * Always set WM1S_LP_EN when spr_val != 0, even if the
+		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
 		 * level is disabled. Doing otherwise could cause underruns.
 		 */
 		if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
 			drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
-			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
-		} else
-			results->wm_lp_spr[wm_lp - 1] = r->spr_val;
+			results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
+		}
 	}
 
 	/* LP0 register values */
@@ -3444,9 +3443,9 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
 			continue;
 
 		results->wm_pipe[pipe] =
-			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
-			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
-			r->cur_val;
+			WM0_PIPE_PRIMARY(r->pri_val) |
+			WM0_PIPE_SPRITE(r->spr_val) |
+			WM0_PIPE_CURSOR(r->cur_val);
 	}
 }
 
@@ -3538,24 +3537,24 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
 	struct ilk_wm_values *previous = &dev_priv->wm.hw;
 	bool changed = false;
 
-	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
-		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
+	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
+		previous->wm_lp[2] &= ~WM_LP_ENABLE;
 		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
 		changed = true;
 	}
-	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
-		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
+	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM_LP_ENABLE) {
+		previous->wm_lp[1] &= ~WM_LP_ENABLE;
 		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
 		changed = true;
 	}
-	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
-		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
+	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM_LP_ENABLE) {
+		previous->wm_lp[0] &= ~WM_LP_ENABLE;
 		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
 		changed = true;
 	}
 
 	/*
-	 * Don't touch WM1S_LP_EN here.
+	 * Don't touch WM_LP_SPRITE_ENABLE here.
 	 * Doing so could cause underruns.
 	 */
 
@@ -6803,9 +6802,9 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 		 * multiple pipes are active.
 		 */
 		active->wm[0].enable = true;
-		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
-		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
-		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
+		active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
+		active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
+		active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
 	} else {
 		int level, max_level = ilk_wm_max_level(dev_priv);
 
@@ -7229,12 +7228,12 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
  */
 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
 {
-	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
-	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
-	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
+	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM_LP_ENABLE);
+	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM_LP_ENABLE);
+	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM_LP_ENABLE);
 
 	/*
-	 * Don't touch WM1S_LP_EN here.
+	 * Don't touch WM_LP_SPRITE_ENABLE here.
 	 * Doing so could cause underruns.
 	 */
 }
-- 
2.34.1

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Polish ilk+ wm register bits

[Jani Nikula]

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_GENMASK() & co. for ilk+ watermarm registers.

*watermark

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 41 +++++++------
>  drivers/gpu/drm/i915/intel_pm.c               | 57 +++++++++----------
>  3 files changed, 49 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f4de004d470f..b219e162f1d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -78,7 +78,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  	if (DISPLAY_VER(dev_priv) >= 9)
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
> +		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
>  		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 278c9cbc6f3c..0dd4d34e7cd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4298,33 +4298,32 @@
>  #define _WM0_PIPEC_IVB		0x45200
>  #define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
>  					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
> -#define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
> -#define  WM0_PIPE_PLANE_SHIFT	16
> -#define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
> -#define  WM0_PIPE_SPRITE_SHIFT	8
> -#define  WM0_PIPE_CURSOR_MASK	(0xff)
> +#define  WM0_PIPE_PRIMARY_MASK	REG_GENMASK(23, 16)

Should be (31,16) to match current WM0_PIPE_PLANE_MASK.

I didn't try to find the bspec, but if this is an intentional fix,
should be split out to a separate patch.

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> +#define  WM0_PIPE_SPRITE_MASK	REG_GENMASK(15, 8)
> +#define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(5, 0)
> +#define  WM0_PIPE_PRIMARY(x)	REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
> +#define  WM0_PIPE_SPRITE(x)	REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
> +#define  WM0_PIPE_CURSOR(x)	REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
>  #define WM1_LP_ILK		_MMIO(0x45108)
> -#define  WM1_LP_SR_EN		(1 << 31)
> -#define  WM1_LP_LATENCY_SHIFT	24
> -#define  WM1_LP_LATENCY_MASK	(0x7f << 24)
> -#define  WM1_LP_FBC_MASK	(0xf << 20)
> -#define  WM1_LP_FBC_SHIFT	20
> -#define  WM1_LP_FBC_SHIFT_BDW	19
> -#define  WM1_LP_SR_MASK		(0x7ff << 8)
> -#define  WM1_LP_SR_SHIFT	8
> -#define  WM1_LP_CURSOR_MASK	(0xff)
>  #define WM2_LP_ILK		_MMIO(0x4510c)
> -#define  WM2_LP_EN		(1 << 31)
>  #define WM3_LP_ILK		_MMIO(0x45110)
> -#define  WM3_LP_EN		(1 << 31)
> +#define  WM_LP_ENABLE		REG_BIT(31)
> +#define  WM_LP_LATENCY_MASK	REG_GENMASK(30, 24)
> +#define  WM_LP_FBC_MASK_BDW	REG_GENMASK(23, 19)
> +#define  WM_LP_FBC_MASK_ILK	REG_GENMASK(23, 20)
> +#define  WM_LP_PRIMARY_MASK	REG_GENMASK(18, 8)
> +#define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
> +#define  WM_LP_LATENCY(x)	REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
> +#define  WM_LP_FBC_BDW(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
> +#define  WM_LP_FBC_ILK(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
> +#define  WM_LP_PRIMARY(x)	REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
> +#define  WM_LP_CURSOR(x)	REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
>  #define WM1S_LP_ILK		_MMIO(0x45120)
>  #define WM2S_LP_IVB		_MMIO(0x45124)
>  #define WM3S_LP_IVB		_MMIO(0x45128)
> -#define  WM1S_LP_EN		(1 << 31)
> -
> -#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
> -	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
> -	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
> +#define  WM_LP_SPRITE_ENABLE	REG_BIT(31) /* ilk/snb WM1S only */
> +#define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
> +#define  WM_LP_SPRITE(x)	REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
>  
>  /* Memory latency timer register */
>  #define MLTR_ILK		_MMIO(0x11222)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 605944551e1b..9382284134e6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3409,29 +3409,28 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
>  		 * disabled. Doing otherwise could cause underruns.
>  		 */
>  		results->wm_lp[wm_lp - 1] =
> -			(ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
> -			(r->pri_val << WM1_LP_SR_SHIFT) |
> -			r->cur_val;
> +			WM_LP_LATENCY(ilk_wm_lp_latency(dev_priv, level)) |
> +			WM_LP_PRIMARY(r->pri_val) |
> +			WM_LP_CURSOR(r->cur_val);
>  
>  		if (r->enable)
> -			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
> +			results->wm_lp[wm_lp - 1] |= WM_LP_ENABLE;
>  
>  		if (DISPLAY_VER(dev_priv) >= 8)
> -			results->wm_lp[wm_lp - 1] |=
> -				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> +			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_BDW(r->fbc_val);
>  		else
> -			results->wm_lp[wm_lp - 1] |=
> -				r->fbc_val << WM1_LP_FBC_SHIFT;
> +			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_ILK(r->fbc_val);
> +
> +		results->wm_lp_spr[wm_lp - 1] = WM_LP_SPRITE(r->spr_val);
>  
>  		/*
> -		 * Always set WM1S_LP_EN when spr_val != 0, even if the
> +		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
>  		 * level is disabled. Doing otherwise could cause underruns.
>  		 */
>  		if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
>  			drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
> -			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
> -		} else
> -			results->wm_lp_spr[wm_lp - 1] = r->spr_val;
> +			results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
> +		}
>  	}
>  
>  	/* LP0 register values */
> @@ -3444,9 +3443,9 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
>  			continue;
>  
>  		results->wm_pipe[pipe] =
> -			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
> -			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
> -			r->cur_val;
> +			WM0_PIPE_PRIMARY(r->pri_val) |
> +			WM0_PIPE_SPRITE(r->spr_val) |
> +			WM0_PIPE_CURSOR(r->cur_val);
>  	}
>  }
>  
> @@ -3538,24 +3537,24 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
>  	struct ilk_wm_values *previous = &dev_priv->wm.hw;
>  	bool changed = false;
>  
> -	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
> -		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
> +	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
> +		previous->wm_lp[2] &= ~WM_LP_ENABLE;
>  		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
>  		changed = true;
>  	}
> -	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
> -		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
> +	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM_LP_ENABLE) {
> +		previous->wm_lp[1] &= ~WM_LP_ENABLE;
>  		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
>  		changed = true;
>  	}
> -	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
> -		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
> +	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM_LP_ENABLE) {
> +		previous->wm_lp[0] &= ~WM_LP_ENABLE;
>  		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
>  		changed = true;
>  	}
>  
>  	/*
> -	 * Don't touch WM1S_LP_EN here.
> +	 * Don't touch WM_LP_SPRITE_ENABLE here.
>  	 * Doing so could cause underruns.
>  	 */
>  
> @@ -6803,9 +6802,9 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
>  		 * multiple pipes are active.
>  		 */
>  		active->wm[0].enable = true;
> -		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
> -		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
> -		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
> +		active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
> +		active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
> +		active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
>  	} else {
>  		int level, max_level = ilk_wm_max_level(dev_priv);
>  
> @@ -7229,12 +7228,12 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
>   */
>  static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
>  {
> -	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
> -	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
> -	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
> +	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM_LP_ENABLE);
> +	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM_LP_ENABLE);
> +	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM_LP_ENABLE);
>  
>  	/*
> -	 * Don't touch WM1S_LP_EN here.
> +	 * Don't touch WM_LP_SPRITE_ENABLE here.
>  	 * Doing so could cause underruns.
>  	 */
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Polish ilk+ wm register bits

[Ville Syrjälä]

On Wed, Feb 16, 2022 at 12:29:52PM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use REG_GENMASK() & co. for ilk+ watermarm registers.
> 
> *watermark
> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  .../drm/i915/display/intel_display_debugfs.c  |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 41 +++++++------
> >  drivers/gpu/drm/i915/intel_pm.c               | 57 +++++++++----------
> >  3 files changed, 49 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index f4de004d470f..b219e162f1d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -78,7 +78,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
> >  	if (DISPLAY_VER(dev_priv) >= 9)
> >  		/* no global SR status; inspect per-plane WM */;
> >  	else if (HAS_PCH_SPLIT(dev_priv))
> > -		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
> > +		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
> >  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
> >  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> >  		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 278c9cbc6f3c..0dd4d34e7cd7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4298,33 +4298,32 @@
> >  #define _WM0_PIPEC_IVB		0x45200
> >  #define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
> >  					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
> > -#define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
> > -#define  WM0_PIPE_PLANE_SHIFT	16
> > -#define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
> > -#define  WM0_PIPE_SPRITE_SHIFT	8
> > -#define  WM0_PIPE_CURSOR_MASK	(0xff)
> > +#define  WM0_PIPE_PRIMARY_MASK	REG_GENMASK(23, 16)
> 
> Should be (31,16) to match current WM0_PIPE_PLANE_MASK.
> 
> I didn't try to find the bspec, but if this is an intentional fix,
> should be split out to a separate patch.

Right. Forgot that I refined the bitfield sizes here. I'll
split that part out.

An easy way to double check these w/o a spec is
ilk_{plane,cursor}_wm_reg_max(). Assuming those are correct
of course :) Hmm, I guess I could also think about rewriting
those to use the *_MASK defines. Though I'd have to define
separate masks for each platform variant...

> 
> Other than that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks.

> 
> > +#define  WM0_PIPE_SPRITE_MASK	REG_GENMASK(15, 8)
> > +#define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(5, 0)
> > +#define  WM0_PIPE_PRIMARY(x)	REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
> > +#define  WM0_PIPE_SPRITE(x)	REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
> > +#define  WM0_PIPE_CURSOR(x)	REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
> >  #define WM1_LP_ILK		_MMIO(0x45108)
> > -#define  WM1_LP_SR_EN		(1 << 31)
> > -#define  WM1_LP_LATENCY_SHIFT	24
> > -#define  WM1_LP_LATENCY_MASK	(0x7f << 24)
> > -#define  WM1_LP_FBC_MASK	(0xf << 20)
> > -#define  WM1_LP_FBC_SHIFT	20
> > -#define  WM1_LP_FBC_SHIFT_BDW	19
> > -#define  WM1_LP_SR_MASK		(0x7ff << 8)
> > -#define  WM1_LP_SR_SHIFT	8
> > -#define  WM1_LP_CURSOR_MASK	(0xff)
> >  #define WM2_LP_ILK		_MMIO(0x4510c)
> > -#define  WM2_LP_EN		(1 << 31)
> >  #define WM3_LP_ILK		_MMIO(0x45110)
> > -#define  WM3_LP_EN		(1 << 31)
> > +#define  WM_LP_ENABLE		REG_BIT(31)
> > +#define  WM_LP_LATENCY_MASK	REG_GENMASK(30, 24)
> > +#define  WM_LP_FBC_MASK_BDW	REG_GENMASK(23, 19)
> > +#define  WM_LP_FBC_MASK_ILK	REG_GENMASK(23, 20)
> > +#define  WM_LP_PRIMARY_MASK	REG_GENMASK(18, 8)
> > +#define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
> > +#define  WM_LP_LATENCY(x)	REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
> > +#define  WM_LP_FBC_BDW(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
> > +#define  WM_LP_FBC_ILK(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
> > +#define  WM_LP_PRIMARY(x)	REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
> > +#define  WM_LP_CURSOR(x)	REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
> >  #define WM1S_LP_ILK		_MMIO(0x45120)
> >  #define WM2S_LP_IVB		_MMIO(0x45124)
> >  #define WM3S_LP_IVB		_MMIO(0x45128)
> > -#define  WM1S_LP_EN		(1 << 31)
> > -
> > -#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
> > -	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
> > -	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
> > +#define  WM_LP_SPRITE_ENABLE	REG_BIT(31) /* ilk/snb WM1S only */
> > +#define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
> > +#define  WM_LP_SPRITE(x)	REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
> >  
> >  /* Memory latency timer register */
> >  #define MLTR_ILK		_MMIO(0x11222)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 605944551e1b..9382284134e6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3409,29 +3409,28 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
> >  		 * disabled. Doing otherwise could cause underruns.
> >  		 */
> >  		results->wm_lp[wm_lp - 1] =
> > -			(ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
> > -			(r->pri_val << WM1_LP_SR_SHIFT) |
> > -			r->cur_val;
> > +			WM_LP_LATENCY(ilk_wm_lp_latency(dev_priv, level)) |
> > +			WM_LP_PRIMARY(r->pri_val) |
> > +			WM_LP_CURSOR(r->cur_val);
> >  
> >  		if (r->enable)
> > -			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
> > +			results->wm_lp[wm_lp - 1] |= WM_LP_ENABLE;
> >  
> >  		if (DISPLAY_VER(dev_priv) >= 8)
> > -			results->wm_lp[wm_lp - 1] |=
> > -				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> > +			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_BDW(r->fbc_val);
> >  		else
> > -			results->wm_lp[wm_lp - 1] |=
> > -				r->fbc_val << WM1_LP_FBC_SHIFT;
> > +			results->wm_lp[wm_lp - 1] |= WM_LP_FBC_ILK(r->fbc_val);
> > +
> > +		results->wm_lp_spr[wm_lp - 1] = WM_LP_SPRITE(r->spr_val);
> >  
> >  		/*
> > -		 * Always set WM1S_LP_EN when spr_val != 0, even if the
> > +		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
> >  		 * level is disabled. Doing otherwise could cause underruns.
> >  		 */
> >  		if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
> >  			drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
> > -			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
> > -		} else
> > -			results->wm_lp_spr[wm_lp - 1] = r->spr_val;
> > +			results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
> > +		}
> >  	}
> >  
> >  	/* LP0 register values */
> > @@ -3444,9 +3443,9 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
> >  			continue;
> >  
> >  		results->wm_pipe[pipe] =
> > -			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
> > -			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
> > -			r->cur_val;
> > +			WM0_PIPE_PRIMARY(r->pri_val) |
> > +			WM0_PIPE_SPRITE(r->spr_val) |
> > +			WM0_PIPE_CURSOR(r->cur_val);
> >  	}
> >  }
> >  
> > @@ -3538,24 +3537,24 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
> >  	struct ilk_wm_values *previous = &dev_priv->wm.hw;
> >  	bool changed = false;
> >  
> > -	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
> > -		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
> > +	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
> > +		previous->wm_lp[2] &= ~WM_LP_ENABLE;
> >  		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
> >  		changed = true;
> >  	}
> > -	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
> > -		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
> > +	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM_LP_ENABLE) {
> > +		previous->wm_lp[1] &= ~WM_LP_ENABLE;
> >  		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
> >  		changed = true;
> >  	}
> > -	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
> > -		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
> > +	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM_LP_ENABLE) {
> > +		previous->wm_lp[0] &= ~WM_LP_ENABLE;
> >  		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
> >  		changed = true;
> >  	}
> >  
> >  	/*
> > -	 * Don't touch WM1S_LP_EN here.
> > +	 * Don't touch WM_LP_SPRITE_ENABLE here.
> >  	 * Doing so could cause underruns.
> >  	 */
> >  
> > @@ -6803,9 +6802,9 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
> >  		 * multiple pipes are active.
> >  		 */
> >  		active->wm[0].enable = true;
> > -		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
> > -		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
> > -		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
> > +		active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
> > +		active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
> > +		active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
> >  	} else {
> >  		int level, max_level = ilk_wm_max_level(dev_priv);
> >  
> > @@ -7229,12 +7228,12 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
> >   */
> >  static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
> >  {
> > -	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
> > -	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
> > -	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
> > +	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM_LP_ENABLE);
> > +	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM_LP_ENABLE);
> > +	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM_LP_ENABLE);
> >  
> >  	/*
> > -	 * Don't touch WM1S_LP_EN here.
> > +	 * Don't touch WM_LP_SPRITE_ENABLE here.
> >  	 * Doing so could cause underruns.
> >  	 */
> >  }
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane/wm cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Plane/wm cleanups
URL   : https://patchwork.freedesktop.org/series/100020/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b7734111702f drm/i915: Move intel_plane_atomic_calc_changes() & co. out
7bcf657c95c4 drm/i915: Introduce intel_arm_planes_on_crtc()
be72ec97a233 drm/i915: Introduce scaled_planes bitmask
58f9b823c9b0 drm/i915: Use {active, scaled}_planes to compute ilk watermarks
1cebc2ca3c27 drm/i915: Remove gen6_check_mch_setup()
24286ee8c4ca drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__type' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:25:
+#define _REG_GENMASK(__type, __high, __low)				\
+	((__type)(GENMASK(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 ||			\
+				  (__high) >= BITS_PER_TYPE(__type) ||	\
+				  (__low) > (__high)))))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:25:
+#define _REG_GENMASK(__type, __high, __low)				\
+	((__type)(GENMASK(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 ||			\
+				  (__high) >= BITS_PER_TYPE(__type) ||	\
+				  (__low) > (__high)))))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:25:
+#define _REG_GENMASK(__type, __high, __low)				\
+	((__type)(GENMASK(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 ||			\
+				  (__high) >= BITS_PER_TYPE(__type) ||	\
+				  (__low) > (__high)))))

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
6c5be20fcbcc drm/i915: Clean up SSKPD/MLTR defines
0798afa629f9 drm/i915: Polish ilk+ wm register bits
-:194: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#194: FILE: drivers/gpu/drm/i915/intel_pm.c:7185:
+	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM_LP_ENABLE);

-:195: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:7186:
+	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM_LP_ENABLE);

-:196: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#196: FILE: drivers/gpu/drm/i915/intel_pm.c:7187:
+	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM_LP_ENABLE);

total: 0 errors, 3 warnings, 0 checks, 172 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Plane/wm cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Plane/wm cleanups
URL   : https://patchwork.freedesktop.org/series/100020/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane/wm cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30695 bytes --]

== Series Details ==

Series: drm/i915: Plane/wm cleanups
URL   : https://patchwork.freedesktop.org/series/100020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11219 -> Patchwork_22254
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/index.html

Participating hosts (48 -> 42)
------------------------------

  Missing    (6): shard-tglu fi-bsw-cyan bat-adlp-4 shard-rkl shard-dg1 bat-jsl-2 

Known issues
------------

  Here are the changes found in Patchwork_22254 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-hsw-4770:        NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-skl-6600u:       NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live:
    - fi-skl-6600u:       NOTRUN -> [FAIL][4] ([i915#4547])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@i915_selftest@live.html

  * igt@i915_selftest@live@hangcheck:
    - fi-bdw-5557u:       NOTRUN -> [INCOMPLETE][5] ([i915#3921])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [PASS][6] -> [DMESG-FAIL][7] ([i915#5026])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][10] ([fdo#109271]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [PASS][11] -> [DMESG-WARN][12] ([i915#4269])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6600u:       NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@cursor_plane_move:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][14] ([fdo#109271]) +13 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html

  * igt@runner@aborted:
    - fi-blb-e6850:       NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-blb-e6850/igt@runner@aborted.html
    - fi-skl-6600u:       NOTRUN -> [FAIL][16] ([i915#1436] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - {bat-rpls-1}:       [INCOMPLETE][17] ([i915#4898]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [INCOMPLETE][19] ([i915#4547]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][21] ([i915#4785]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [DMESG-FAIL][23] ([i915#4494] / [i915#4957]) -> [DMESG-FAIL][24] ([i915#4957])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11219/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/bat-dg1-6/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11219 -> Patchwork_22254

  CI-20190529: 20190529
  CI_DRM_11219: 1129051ad132beede618ec95745886d59c14e266 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22254: 0798afa629f95c4ae0d6c2322c4f6ce7a99ffd48 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_22254/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_pm.o
In file included from <command-line>:
drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_read_wm_latency’:
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:62:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:62:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:64:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:64:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:19: note: in expansion of macro ‘__bf_shf’
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                   ^~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:19: note: in expansion of macro ‘__bf_shf’
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                   ^~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:16: error: right shift count is negative [-Werror=shift-count-negative]
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/index.html

[-- Attachment #2: Type: text/html, Size: 34177 bytes --]

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: Plane/wm cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Plane/wm cleanups
URL   : https://patchwork.freedesktop.org/series/100020/
State : warning

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_pm.o
In file included from <command-line>:
drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_read_wm_latency’:
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:62:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:62:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:64:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:64:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:19: note: in expansion of macro ‘__bf_shf’
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                   ^~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:19: note: in expansion of macro ‘__bf_shf’
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                   ^~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:66:16: error: right shift count is negative [-Werror=shift-count-negative]
      ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
                ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:68:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:68:20: note: in expansion of macro ‘__bf_cast_unsigned’
   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
                    ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
   (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
           ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:68:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
   ^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:68:20: note: in expansion of macro ‘__bf_cast_unsigned’
   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
                    ^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
  (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                               ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:26:12: note: in expansion of macro ‘GENMASK’
  ((__type)(GENMASK(__high, __low) +    \
            ^~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:53:38: note: in expansion of macro ‘_REG_GENMASK’
 #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
                                      ^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:1900:34: note: in expansion of macro ‘REG_GENMASK64’
 #define   SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
                                  ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
                           ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
  (((~UL(0)) - (UL(1) << (l)) + 1) & \
                      ^~
././include/linux/compiler_types.h:326:9: note: in definition of macro ‘__compiletime_assert’
   if (!(condition))     \
         ^~~~~~~~~
././include/linux/compiler_types.h:346:2: note: in expansion of macro ‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
  ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                     ^~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:50:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^~~~~~~~~~~~~~~~
./include/linux/build_bug.h:21:2: note: in expansion of macro ‘BUILD_BUG_ON’
  BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
  ^~~~~~~~~~~~
./include/linux/bitfield.h:71:3: note: in expansion of macro ‘__BUILD_BUG_ON_NOT_POWER_OF_2’
   __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +   \
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:125:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
   __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
   ^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:77:56: note: in expansion of macro ‘FIELD_GET’
 #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
                                                        ^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:101:40: note: in expansion of macro ‘_REG_FIELD_GET’
 #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
                                        ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2949:11: note: in expansion of macro ‘REG_FIELD_GET64’
   wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
           ^~~~~~

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22254/build_32bit.log

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane/wm cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Plane/wm cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/100020/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cfff3831dee5 drm/i915: Move intel_plane_atomic_calc_changes() & co. out
3260cfa17939 drm/i915: Introduce intel_arm_planes_on_crtc()
477c56b8741c drm/i915: Introduce scaled_planes bitmask
69cbcbb18c8c drm/i915: Use {active, scaled}_planes to compute ilk watermarks
a3504cd2f6fa drm/i915: Remove gen6_check_mch_setup()
6d5f50c4f287 drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:49:
+#define REG_GENMASK64(__high, __low)					\
+	((u64)(GENMASK_ULL(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))

-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:49:
+#define REG_GENMASK64(__high, __low)					\
+	((u64)(GENMASK_ULL(__high, __low) +				\
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
+				 __is_constexpr(__low) &&		\
+				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))

total: 0 errors, 0 warnings, 2 checks, 39 lines checked
355d61122f71 drm/i915: Clean up SSKPD/MLTR defines
-:16: WARNING:BAD_SIGN_OFF: Duplicate signature
#16: 
Reported-by: kernel test robot <lkp@intel.com>

-:17: WARNING:BAD_SIGN_OFF: Duplicate signature
#17: 
Reported-by: kernel test robot <lkp@intel.com>

total: 0 errors, 2 warnings, 0 checks, 80 lines checked
c781e8686282 drm/i915: Polish ilk+ wm register bits
-:194: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#194: FILE: drivers/gpu/drm/i915/intel_pm.c:7185:
+	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM_LP_ENABLE);

-:195: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:7186:
+	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM_LP_ENABLE);

-:196: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#196: FILE: drivers/gpu/drm/i915/intel_pm.c:7187:
+	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM_LP_ENABLE);

total: 0 errors, 3 warnings, 0 checks, 172 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Plane/wm cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Plane/wm cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/100020/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane/wm cleanups (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6540 bytes --]

== Series Details ==

Series: drm/i915: Plane/wm cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/100020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11220 -> Patchwork_22257
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/index.html

Participating hosts (46 -> 44)
------------------------------

  Additional (1): bat-jsl-2 
  Missing    (3): fi-bsw-cyan shard-dg1 shard-tglu 

Known issues
------------

  Here are the changes found in Patchwork_22257 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-compute0:
    - fi-blb-e6850:       NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html

  * igt@core_auth@basic-auth:
    - fi-kbl-soraka:      [PASS][2] -> [DMESG-WARN][3] ([i915#1982])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/fi-kbl-soraka/igt@core_auth@basic-auth.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-kbl-soraka/igt@core_auth@basic-auth.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-skl-6600u:       NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-cfl-8700k:       [PASS][6] -> [DMESG-FAIL][7] ([i915#541])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / [i915#4957])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/bat-dg1-6/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][11] ([fdo#109271]) +21 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6600u:       NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-cml-u2:          NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-cml-u2/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-skl-6600u:       [INCOMPLETE][14] ([i915#4547]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [DMESG-FAIL][16] ([i915#5026]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/fi-blb-e6850/igt@i915_selftest@live@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Build changes
-------------

  * Linux: CI_DRM_11220 -> Patchwork_22257

  CI-20190529: 20190529
  CI_DRM_11220: 32e4daa92806f1d9bb97fd9c858c2b1baf9a0ba8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22257: c781e86862828ab4be22f3b8bf80f61090e488fd @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c781e8686282 drm/i915: Polish ilk+ wm register bits
355d61122f71 drm/i915: Clean up SSKPD/MLTR defines
6d5f50c4f287 drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
a3504cd2f6fa drm/i915: Remove gen6_check_mch_setup()
69cbcbb18c8c drm/i915: Use {active, scaled}_planes to compute ilk watermarks
477c56b8741c drm/i915: Introduce scaled_planes bitmask
3260cfa17939 drm/i915: Introduce intel_arm_planes_on_crtc()
cfff3831dee5 drm/i915: Move intel_plane_atomic_calc_changes() & co. out

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/index.html

[-- Attachment #2: Type: text/html, Size: 7484 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane/wm cleanups (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30258 bytes --]

== Series Details ==

Series: drm/i915: Plane/wm cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/100020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11220_full -> Patchwork_22257_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22257_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_cs_tlb@engines@rcs0:
    - {shard-rkl}:        NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/igt@gem_cs_tlb@engines@rcs0.html

  * igt@kms_cursor_legacy@pipe-c-torture-bo:
    - {shard-rkl}:        [SKIP][2] ([i915#4070]) -> [INCOMPLETE][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/igt@kms_cursor_legacy@pipe-c-torture-bo.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-torture-bo.html

  
Known issues
------------

  Here are the changes found in Patchwork_22257_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - {shard-rkl}:        ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-4/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-4/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-6/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-6/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-6/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-1/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-1/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-1/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-1/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-1/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-2/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-2/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-2/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-2/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-4/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-4/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_capture@pi@bcs0:
    - shard-tglb:         [PASS][47] -> [INCOMPLETE][48] ([i915#3371] / [i915#3731])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-tglb6/igt@gem_exec_capture@pi@bcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb6/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          [PASS][49] -> [INCOMPLETE][50] ([i915#4547])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl3/igt@gem_exec_capture@pi@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl9/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-iclb:         [PASS][51] -> [INCOMPLETE][52] ([i915#3371])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-iclb7/igt@gem_exec_capture@pi@vcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-iclb8/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][53] -> [FAIL][54] ([i915#2842]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [PASS][55] -> [FAIL][56] ([i915#2842]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
    - shard-glk:          [PASS][57] -> [DMESG-WARN][58] ([i915#118])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk1/igt@gem_exec_whisper@basic-queues-forked-all.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk8/igt@gem_exec_whisper@basic-queues-forked-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2190])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@random:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl2/igt@gem_lmem_swapping@random.html

  * igt@gem_pread@exhaustion:
    - shard-tglb:         NOTRUN -> [WARN][61] ([i915#2658])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@gem_pread@exhaustion.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][62] -> [FAIL][63] ([i915#454])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#3777]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([fdo#111615])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#3886]) +2 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3886])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-hpd-enable-disable-mode:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@kms_chamelium@dp-hpd-enable-disable-mode.html

  * igt@kms_color@pipe-d-invalid-degamma-lut-sizes:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271]) +44 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl1/igt@kms_color@pipe-d-invalid-degamma-lut-sizes.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-5:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#109274] / [fdo#111825])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][73] -> [FAIL][74] ([i915#2346] / [i915#533])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-glk:          [PASS][75] -> [FAIL][76] ([i915#79])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][77] -> [FAIL][78] ([i915#79])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [PASS][79] -> [DMESG-WARN][80] ([i915#180]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          [PASS][81] -> [FAIL][82] ([i915#2122])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-glk:          [PASS][83] -> [FAIL][84] ([i915#4911])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
    - shard-glk:          [PASS][85] -> [FAIL][86] ([i915#2546])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk9/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][87] -> [DMESG-WARN][88] ([i915#180]) +7 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([fdo#109280] / [fdo#111825]) +2 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][90] -> [FAIL][91] ([i915#1188]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([i915#1187])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          NOTRUN -> [INCOMPLETE][93] ([i915#2828])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][94] ([fdo#108145] / [i915#265])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][95] ([fdo#108145] / [i915#265])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][96] -> [FAIL][97] ([fdo#108145] / [i915#265])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2733])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][99] -> [SKIP][100] ([fdo#109441]) +2 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][101] -> [INCOMPLETE][102] ([i915#4939])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-skl7/igt@kms_psr@suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl6/igt@kms_psr@suspend.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][103] ([IGT#2])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-d-query-forked-busy:
    - shard-skl:          NOTRUN -> [SKIP][104] ([fdo#109271]) +6 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-skl4/igt@kms_vblank@pipe-d-query-forked-busy.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-apl:          NOTRUN -> [SKIP][105] ([fdo#109271]) +86 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-apl:          NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2437])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-a-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][107] ([i915#2530]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@nouveau_crc@pipe-a-source-outp-inactive.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-tglb:         NOTRUN -> [SKIP][108] ([fdo#109289])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb7/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-tglb:         NOTRUN -> [SKIP][109] ([fdo#109291])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb8/igt@prime_nv_api@i915_nv_import_twice.html

  * igt@sysfs_clients@create:
    - shard-apl:          NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2994])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl4/igt@sysfs_clients@create.html

  * igt@sysfs_clients@sema-50:
    - shard-kbl:          NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl1/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@fbdev@unaligned-read:
    - {shard-rkl}:        [SKIP][112] ([i915#2582]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@fbdev@unaligned-read.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-kbl:          [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +3 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-apl:          [TIMEOUT][116] ([i915#3063]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-apl3/igt@gem_eio@in-flight-contexts-10ms.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl3/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][118] ([i915#2842]) -> [PASS][119] +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [FAIL][120] ([i915#2842]) -> [PASS][121] +2 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_gttfill@engines@vecs0:
    - {shard-rkl}:        [INCOMPLETE][122] ([i915#5080]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@gem_exec_gttfill@engines@vecs0.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-1/igt@gem_exec_gttfill@engines@vecs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][124] ([i915#2190]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-tglb1/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - {shard-rkl}:        [SKIP][126] ([fdo#109308]) -> [PASS][127] +1 similar issue
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@i915_pm_rpm@basic-pci-d3-state.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - {shard-rkl}:        [SKIP][128] ([i915#1397]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@i915_pm_rpm@dpms-lpsp.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - {shard-dg1}:        [SKIP][130] ([i915#1397]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-dg1-18/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_atomic@test-only:
    - {shard-rkl}:        [SKIP][132] ([i915#1845]) -> [PASS][133] +20 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_atomic@test-only.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_atomic@test-only.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][134] ([i915#1845] / [i915#4098]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_color@pipe-a-ctm-0-75:
    - {shard-rkl}:        [SKIP][136] ([i915#1149] / [i915#4098]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-4/igt@kms_color@pipe-a-ctm-0-75.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_color@pipe-a-ctm-blue-to-red:
    - {shard-rkl}:        [SKIP][138] ([i915#1149] / [i915#1849]) -> [PASS][139] +2 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_color@pipe-a-ctm-blue-to-red.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_color@pipe-a-ctm-blue-to-red.html

  * igt@kms_color@pipe-b-degamma:
    - {shard-rkl}:        [SKIP][140] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_color@pipe-b-degamma.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_color@pipe-b-degamma.html

  * igt@kms_color@pipe-c-invalid-gamma-lut-sizes:
    - {shard-rkl}:        [SKIP][142] ([i915#4070]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-5/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
    - shard-glk:          [DMESG-WARN][144] ([i915#118]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-glk6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-random:
    - {shard-rkl}:        ([SKIP][146], [SKIP][147]) ([fdo#112022] / [i915#4070]) -> [PASS][148]
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
    - {shard-rkl}:        [SKIP][149] ([fdo#112022]) -> [PASS][150] +2 similar issues
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
    - {shard-rkl}:        [SKIP][151] ([fdo#112022] / [i915#4070]) -> [PASS][152] +2 similar issues
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html

  * igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge:
    - {shard-rkl}:        [SKIP][153] ([i915#1849] / [i915#4070]) -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-iclb:         [FAIL][155] ([i915#2346]) -> [PASS][156]
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - {shard-rkl}:        [SKIP][157] ([fdo#111825]) -> [PASS][158]
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_dp_aux_dev:
    - {shard-rkl}:        [SKIP][159] ([i915#1257]) -> [PASS][160]
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_dp_aux_dev.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
    - {shard-rkl}:        [SKIP][161] ([fdo#111314]) -> [PASS][162] +4 similar issues
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html

  * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled:
    - {shard-rkl}:        ([SKIP][163], [SKIP][164]) ([fdo#111314] / [i915#4098]) -> [PASS][165]
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [INCOMPLETE][166] ([i915#180]) -> [PASS][167]
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr:
    - {shard-rkl}:        [SKIP][168] ([fdo#110189] / [i915#3955]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11220/shard-rkl-2/igt@kms_fbcon_fbt@psr.html

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22257/index.html

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