* [Intel-gfx] [PATCH 1/6] drm/i915: Prepare more multi-GT initialization
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 2/6] drm/i915: Rename and expose common GT early init routine Badal Nilawar
` (9 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
v2:
- Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 54 ++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 ++++++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 70 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..5b4263c708cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -815,20 +815,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
- kfree(gt->uncore);
- kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = &i915->gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -839,14 +835,58 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ if (!HAS_EXTRA_GT_LIST(i915))
+ return 0;
+
+ for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
+ gtdef->setup != NULL;
+ i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev, mmio_bar)))) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 4d56f7d5a3be..3bd36caee321 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -83,6 +83,9 @@ struct gt_defaults {
struct intel_gt {
struct drm_i915_private *i915;
+ const char *name;
+ enum intel_gt_type type;
+
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76aad81c014b..7a9147e7d49e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -918,6 +918,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
+
/*
* Platform has the dedicated compression control state for each lmem surfaces
* stored in lmem to support the 3D and media compression formats.
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6904ad03ca19..b408ce384cd7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -245,6 +245,20 @@ struct intel_runtime_info {
};
};
+enum intel_gt_type {
+ GT_PRIMARY,
+ GT_TILE,
+};
+
+struct intel_gt_definition {
+ enum intel_gt_type type;
+ char *name;
+ int (*setup)(struct intel_gt *gt,
+ phys_addr_t phys_addr);
+ u32 mapping_base;
+ intel_engine_mask_t engine_mask;
+};
+
struct intel_device_info {
struct ip_version media;
@@ -252,6 +266,8 @@ struct intel_device_info {
unsigned int dma_mask_size; /* available DMA address bits */
+ const struct intel_gt_definition *extra_gt_list;
+
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f5904e659ef2..915d58ba383e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
static void mock_gt_probe(struct drm_i915_private *i915)
{
i915->gt[0] = &i915->gt0;
+ i915->gt[0]->name = "Mock GT";
}
struct drm_i915_private *mock_gem_device(void)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH 2/6] drm/i915: Rename and expose common GT early init routine
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 1/6] drm/i915: Prepare more multi-GT initialization Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT Badal Nilawar
` (8 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Radhakrishna Sripada <Radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5b4263c708cc..57a6488c0e14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>->irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = &i915->uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -797,7 +797,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
gt->uncore = uncore;
gt->uncore->debug = mmio_debug;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 1/6] drm/i915: Prepare more multi-GT initialization Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 2/6] drm/i915: Rename and expose common GT early init routine Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register Badal Nilawar
` (7 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++++
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 ++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +++++++++
drivers/gpu/drm/i915/i915_pci.c | 15 +++++++++
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--
drivers/gpu/drm/i915/intel_uncore.h | 20 ++++++++++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57a6488c0e14..bfe77d01f747 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>->i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
@@ -840,7 +845,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -873,7 +878,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..fb2c56777480 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1578,4 +1578,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x380000
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index 000000000000..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+ * Standalone media shares the general MMIO space with the primary
+ * GT. We'll re-use the primary GT's mapping.
+ */
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index 000000000000..3afb310de932
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+#ifndef __INTEL_SA_MEDIA__
+#define __INTEL_SA_MEDIA__
+
+#include <linux/types.h>
+
+struct intel_gt;
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset);
+
+#endif /* __INTEL_SA_MEDIA_H__ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26b25d9434d6..18d3722331e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -26,6 +26,9 @@
#include <drm/drm_drv.h>
#include <drm/i915_pciids.h>
+#include "gt/intel_gt_regs.h"
+#include "gt/intel_sa_media.h"
+
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_pci.h"
@@ -1115,6 +1118,17 @@ static const struct intel_device_info pvc_info = {
.display.has_cdclk_crawl = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
+static const struct intel_gt_definition xelpmp_extra_gt[] = {
+ {
+ .type = GT_MEDIA,
+ .name = "Standalone Media GT",
+ .setup = intel_sa_mediagt_setup,
+ .gsi_offset = MTL_MEDIA_GSI_BASE,
+ .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ },
+ {}
+};
+
__maybe_unused
static const struct intel_device_info mtl_info = {
XE_HP_FEATURES,
@@ -1128,6 +1142,7 @@ static const struct intel_device_info mtl_info = {
.media.ver = 13,
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
+ .extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b408ce384cd7..7b6d5341b34b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -248,14 +248,17 @@ struct intel_runtime_info {
enum intel_gt_type {
GT_PRIMARY,
GT_TILE,
+ GT_MEDIA,
};
struct intel_gt_definition {
enum intel_gt_type type;
char *name;
int (*setup)(struct intel_gt *gt,
- phys_addr_t phys_addr);
+ phys_addr_t phys_addr,
+ u32 gsi_offset);
u32 mapping_base;
+ u32 gsi_offset;
intel_engine_mask_t engine_mask;
};
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9b81b2543ce2..faec6c1aad66 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1771,10 +1771,15 @@ __gen2_read(64)
#undef GEN2_READ_FOOTER
#undef GEN2_READ_HEADER
+#define IS_GSI_REG(reg) ((reg) < 0x40000)
+
#define GEN6_READ_HEADER(x) \
- u32 offset = i915_mmio_reg_offset(reg); \
+ u32 offset; \
unsigned long irqflags; \
u##x val = 0; \
+ if (IS_GSI_REG(reg.reg)) \
+ reg.reg += uncore->gsi_offset; \
+ offset = i915_mmio_reg_offset(reg); \
assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, true, true)
@@ -1876,8 +1881,11 @@ __gen2_write(32)
#undef GEN2_WRITE_HEADER
#define GEN6_WRITE_HEADER \
- u32 offset = i915_mmio_reg_offset(reg); \
+ u32 offset; \
unsigned long irqflags; \
+ if (IS_GSI_REG(reg.reg)) \
+ reg.reg += uncore->gsi_offset; \
+ offset = i915_mmio_reg_offset(reg); \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
@@ -2256,6 +2264,10 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
+ /* The media GT re-uses the primary GT's register mapping */
+ if (uncore->gt->type == GT_MEDIA)
+ return;
+
iounmap(uncore->regs);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b1fa912a65e7..b25efdd9560e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -135,6 +135,16 @@ struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
+ /*
+ * Do we need to apply an additional offset to reach the beginning
+ * of the basic non-engine GT registers (referred to as "GSI" on
+ * newer platforms, or "GT block" on older platforms)? If so, we'll
+ * track that here and apply it transparently to registers in the
+ * appropriate range to maintain compatibility with our existing
+ * register definitions and GT code.
+ */
+ u32 gsi_offset;
+
unsigned int flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
@@ -299,14 +309,20 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
i915_reg_t reg) \
{ \
- return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (offset < 0x40000) \
+ offset += uncore->gsi_offset; \
+ return read##s__(uncore->regs + offset); \
}
#define __raw_write(x__, s__) \
static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
i915_reg_t reg, u##x__ val) \
{ \
- write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (offset < 0x40000) \
+ offset += uncore->gsi_offset; \
+ write##s__(val, uncore->regs + offset); \
}
__raw_read(8, b)
__raw_read(16, w)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (2 preceding siblings ...)
2022-09-09 2:56 ` [Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-10 1:49 ` Dixit, Ashutosh
2022-09-09 2:56 ` [Intel-gfx] [PATCH 5/6] drm/i915/mtl: Modify CAGF functions for MTL Badal Nilawar
` (6 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
From: Don Hiatt <don.hiatt@intel.com>
On GEN12, use the correct GEN12 RPSTAT register mask/shift.
HSD: 1409538411
Cc: Don Hiatt <donhiatt@gmail.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Don Hiatt <don.hiatt@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
drivers/gpu/drm/i915/gt/intel_rps.c | 17 ++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
5 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 108b9e76c32e..96c03a1258e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fb2c56777480..dac59c3e68db 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1510,6 +1510,11 @@
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
+#define GEN12_RPSTAT1 _MMIO(0x1381b4)
+#define GEN12_CAGF_SHIFT 11
+#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
+#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 6fadde4ee7bf..341f96f536e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2040,6 +2040,19 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
}
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 rpstat;
+
+ if (GRAPHICS_VER(i915) >= 12)
+ rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1);
+ else
+ rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
+
+ return rpstat;
+}
+
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
@@ -2047,6 +2060,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
+ else if (GRAPHICS_VER(i915) >= 12)
+ cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -2071,7 +2086,7 @@ static u32 read_cagf(struct intel_rps *rps)
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
} else if (GRAPHICS_VER(i915) >= 6) {
- freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ freq = intel_rps_read_rpstat(rps);
} else {
freq = intel_uncore_read(uncore, MEMSTAT_ILK);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4509dfdc52e0..08bae6d97870 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -47,6 +47,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf1..a24704ec2c18 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_uncore *uncore = gt->uncore;
struct i915_pmu *pmu = &i915->pmu;
struct intel_rps *rps = >->rps;
@@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
* case we assume the system is running at the intended
* frequency. Fortunately, the read should rarely fail!
*/
- val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
+ val = intel_rps_read_rpstat(rps);
if (val)
val = intel_rps_get_cagf(rps, val);
else
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-09 2:56 ` [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register Badal Nilawar
@ 2022-09-10 1:49 ` Dixit, Ashutosh
2022-09-12 11:29 ` Nilawar, Badal
0 siblings, 1 reply; 24+ messages in thread
From: Dixit, Ashutosh @ 2022-09-10 1:49 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
On Thu, 08 Sep 2022 19:56:44 -0700, Badal Nilawar wrote:
>
> From: Don Hiatt <don.hiatt@intel.com>
>
> On GEN12, use the correct GEN12 RPSTAT register mask/shift.
>
> HSD: 1409538411
I think let's remove this.
> Cc: Don Hiatt <donhiatt@gmail.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Don Hiatt <don.hiatt@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> drivers/gpu/drm/i915/gt/intel_rps.c | 17 ++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
> drivers/gpu/drm/i915/i915_pmu.c | 3 +--
> 5 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 108b9e76c32e..96c03a1258e1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
> rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
>
> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + rpstat = intel_rps_read_rpstat(rps);
> rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index fb2c56777480..dac59c3e68db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1510,6 +1510,11 @@
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>
> +#define GEN12_RPSTAT1 _MMIO(0x1381b4)
> +#define GEN12_CAGF_SHIFT 11
> +#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
> +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
Let's remove GEN12_VOLTAGE_MASK, looks like it's not being used.
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN11_GUNIT (28)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 6fadde4ee7bf..341f96f536e8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2040,6 +2040,19 @@ void intel_rps_sanitize(struct intel_rps *rps)
> rps_disable_interrupts(rps);
> }
>
> +u32 intel_rps_read_rpstat(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + u32 rpstat;
> +
> + if (GRAPHICS_VER(i915) >= 12)
> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1);
> + else
> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
Probably nit but how about something like this:
i915_reg_t rpstat;
if (GRAPHICS_VER(i915) >= 12)
rpstat = GEN12_RPSTAT1;
else
rpstat = GEN6_RPSTAT1;
return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
> +
> + return rpstat;
> +}
> +
> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> @@ -2047,6 +2060,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = (rpstat >> 8) & 0xff;
> + else if (GRAPHICS_VER(i915) >= 12)
> + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
> else if (GRAPHICS_VER(i915) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> @@ -2071,7 +2086,7 @@ static u32 read_cagf(struct intel_rps *rps)
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> } else if (GRAPHICS_VER(i915) >= 6) {
> - freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + freq = intel_rps_read_rpstat(rps);
> } else {
> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> index 4509dfdc52e0..08bae6d97870 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -47,6 +47,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
> u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
> u32 intel_rps_read_punit_req(struct intel_rps *rps);
> u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
> +u32 intel_rps_read_rpstat(struct intel_rps *rps);
> void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
> void intel_rps_raise_unslice(struct intel_rps *rps);
> void intel_rps_lower_unslice(struct intel_rps *rps);
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 958b37123bf1..a24704ec2c18 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -371,7 +371,6 @@ static void
> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct intel_uncore *uncore = gt->uncore;
> struct i915_pmu *pmu = &i915->pmu;
> struct intel_rps *rps = >->rps;
>
> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> * case we assume the system is running at the intended
> * frequency. Fortunately, the read should rarely fail!
> */
> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> + val = intel_rps_read_rpstat(rps);
Hmm, we got rid of _fw which the comment above refers to. Maybe we need a
fw flag to intel_rps_read_rpstat?
> if (val)
> val = intel_rps_get_cagf(rps, val);
> else
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-10 1:49 ` Dixit, Ashutosh
@ 2022-09-12 11:29 ` Nilawar, Badal
2022-09-13 0:09 ` Dixit, Ashutosh
0 siblings, 1 reply; 24+ messages in thread
From: Nilawar, Badal @ 2022-09-12 11:29 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: intel-gfx
On 10-09-2022 07:19, Dixit, Ashutosh wrote:
> On Thu, 08 Sep 2022 19:56:44 -0700, Badal Nilawar wrote:
>>
>> From: Don Hiatt <don.hiatt@intel.com>
>>
>> On GEN12, use the correct GEN12 RPSTAT register mask/shift.
>>
>> HSD: 1409538411
>
> I think let's remove this.
Sure.
>
>> Cc: Don Hiatt <donhiatt@gmail.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> Signed-off-by: Don Hiatt <don.hiatt@intel.com>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
>> drivers/gpu/drm/i915/gt/intel_rps.c | 17 ++++++++++++++++-
>> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
>> drivers/gpu/drm/i915/i915_pmu.c | 3 +--
>> 5 files changed, 24 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> index 108b9e76c32e..96c03a1258e1 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> @@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
>> rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
>> rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
>>
>> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
>> + rpstat = intel_rps_read_rpstat(rps);
>> rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
>> rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
>> rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index fb2c56777480..dac59c3e68db 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -1510,6 +1510,11 @@
>> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
>> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>>
>> +#define GEN12_RPSTAT1 _MMIO(0x1381b4)
>> +#define GEN12_CAGF_SHIFT 11
>> +#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
>> +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
>
> Let's remove GEN12_VOLTAGE_MASK, looks like it's not being used.
Yes, not used. I will remove this.
>
>> +
>> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
>> #define GEN11_CSME (31)
>> #define GEN11_GUNIT (28)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index 6fadde4ee7bf..341f96f536e8 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -2040,6 +2040,19 @@ void intel_rps_sanitize(struct intel_rps *rps)
>> rps_disable_interrupts(rps);
>> }
>>
>> +u32 intel_rps_read_rpstat(struct intel_rps *rps)
>> +{
>> + struct drm_i915_private *i915 = rps_to_i915(rps);
>> + u32 rpstat;
>> +
>> + if (GRAPHICS_VER(i915) >= 12)
>> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1);
>> + else
>> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
>
> Probably nit but how about something like this:
>
> i915_reg_t rpstat;
>
> if (GRAPHICS_VER(i915) >= 12)
> rpstat = GEN12_RPSTAT1;
> else
> rpstat = GEN6_RPSTAT1;
>
> return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
Ok
>> +
>> + return rpstat;
>> +}
>> +
>> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>> {
>> struct drm_i915_private *i915 = rps_to_i915(rps);
>> @@ -2047,6 +2060,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>>
>> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> cagf = (rpstat >> 8) & 0xff;
>> + else if (GRAPHICS_VER(i915) >= 12)
>> + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
>> else if (GRAPHICS_VER(i915) >= 9)
>> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> @@ -2071,7 +2086,7 @@ static u32 read_cagf(struct intel_rps *rps)
>> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
>> vlv_punit_put(i915);
>> } else if (GRAPHICS_VER(i915) >= 6) {
>> - freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
>> + freq = intel_rps_read_rpstat(rps);
>> } else {
>> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
>> index 4509dfdc52e0..08bae6d97870 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
>> @@ -47,6 +47,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
>> u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
>> u32 intel_rps_read_punit_req(struct intel_rps *rps);
>> u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
>> +u32 intel_rps_read_rpstat(struct intel_rps *rps);
>> void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
>> void intel_rps_raise_unslice(struct intel_rps *rps);
>> void intel_rps_lower_unslice(struct intel_rps *rps);
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>> index 958b37123bf1..a24704ec2c18 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -371,7 +371,6 @@ static void
>> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> - struct intel_uncore *uncore = gt->uncore;
>> struct i915_pmu *pmu = &i915->pmu;
>> struct intel_rps *rps = >->rps;
>>
>> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>> * case we assume the system is running at the intended
>> * frequency. Fortunately, the read should rarely fail!
>> */
>> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
>> + val = intel_rps_read_rpstat(rps);
>
> Hmm, we got rid of _fw which the comment above refers to. Maybe we need a
> fw flag to intel_rps_read_rpstat?
Above function before reading rpstat it checks if gt is awake. So when
gt is awake shouldn't matter if we read GEN6_RPSTAT1 with forcewake.In
that case we can remove above comment.
Let me know your thoughts on this.
Regards,
Badal Nilawar
>
>> if (val)
>> val = intel_rps_get_cagf(rps, val);
>> else
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-12 11:29 ` Nilawar, Badal
@ 2022-09-13 0:09 ` Dixit, Ashutosh
2022-09-13 7:47 ` Tvrtko Ursulin
0 siblings, 1 reply; 24+ messages in thread
From: Dixit, Ashutosh @ 2022-09-13 0:09 UTC (permalink / raw)
To: Nilawar, Badal; +Cc: intel-gfx
On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
>
> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> >> index 958b37123bf1..a24704ec2c18 100644
> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >> @@ -371,7 +371,6 @@ static void
> >> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >> {
> >> struct drm_i915_private *i915 = gt->i915;
> >> - struct intel_uncore *uncore = gt->uncore;
> >> struct i915_pmu *pmu = &i915->pmu;
> >> struct intel_rps *rps = >->rps;
> >>
> >> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >> * case we assume the system is running at the intended
> >> * frequency. Fortunately, the read should rarely fail!
> >> */
> >> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> >> + val = intel_rps_read_rpstat(rps);
> >
> > Hmm, we got rid of _fw which the comment above refers to. Maybe we need a
> > fw flag to intel_rps_read_rpstat?
>
> Above function before reading rpstat it checks if gt is awake.
Ok, so you are referring to intel_gt_pm_get_if_awake check in frequency_sample.
> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
> forcewake.In that case we can remove above comment. Let me know your
> thoughts on this.
I am not entirely sure about this. For example in c1c82d267ae8
intel_uncore_read_fw was introduced with the same intel_gt_pm_get_if_awake
check. So this would mean even if gt is awake not taking forcewake makes a
difference. The same code pattern was retained in b66ecd0438bf. Maybe it's
because there are no locks?
Under the circumstances I think we could do one of two things:
1. If we want to drop _fw, we should do it as a separate patch with its own
justification so it can be reviewed separately.
2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
intel_rps_read_rpstat.
Thanks.
--
Ashutosh
> >> if (val)
> >> val = intel_rps_get_cagf(rps, val);
> >> else
> >> --
> >> 2.25.1
> >>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-13 0:09 ` Dixit, Ashutosh
@ 2022-09-13 7:47 ` Tvrtko Ursulin
2022-09-14 9:56 ` Nilawar, Badal
0 siblings, 1 reply; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-09-13 7:47 UTC (permalink / raw)
To: Dixit, Ashutosh, Nilawar, Badal; +Cc: intel-gfx
On 13/09/2022 01:09, Dixit, Ashutosh wrote:
> On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>>>> index 958b37123bf1..a24704ec2c18 100644
>>>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>>>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>>>> @@ -371,7 +371,6 @@ static void
>>>> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>>>> {
>>>> struct drm_i915_private *i915 = gt->i915;
>>>> - struct intel_uncore *uncore = gt->uncore;
>>>> struct i915_pmu *pmu = &i915->pmu;
>>>> struct intel_rps *rps = >->rps;
>>>>
>>>> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>>>> * case we assume the system is running at the intended
>>>> * frequency. Fortunately, the read should rarely fail!
>>>> */
>>>> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
>>>> + val = intel_rps_read_rpstat(rps);
>>>
>>> Hmm, we got rid of _fw which the comment above refers to. Maybe we need a
>>> fw flag to intel_rps_read_rpstat?
>>
>> Above function before reading rpstat it checks if gt is awake.
>
> Ok, so you are referring to intel_gt_pm_get_if_awake check in frequency_sample.
>
>> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
>> forcewake.In that case we can remove above comment. Let me know your
>> thoughts on this.
>
> I am not entirely sure about this. For example in c1c82d267ae8
> intel_uncore_read_fw was introduced with the same intel_gt_pm_get_if_awake
> check. So this would mean even if gt is awake not taking forcewake makes a
> difference. The same code pattern was retained in b66ecd0438bf. Maybe it's
> because there are no locks?
Its about power. As c1c82d267ae8 ("drm/i915/pmu: Cheat when reading the
actual frequency to avoid fw") explains the _fw variant is to avoid
preventing RC6, and so increased GPU power draw, just because someone
has PMU open. (Because of the 200Hz sampling timer that is needed for
PMU frequency reporting.)
> Under the circumstances I think we could do one of two things:
> 1. If we want to drop _fw, we should do it as a separate patch with its own
> justification so it can be reviewed separately.
> 2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
> intel_rps_read_rpstat.
Agreed. Or instead of the flag, the usual pattern of having
intel_rps_read_rpstat_fw and make intel_rps_read_rpsstat get the forcewake.
Also, may I ask, this patch is in the MTL enablement series but the
commit message and patch content seem like it is fixing a wider Gen12
issue? What is the extent of incorrect behaviour without it? Should it
be tagged for stable for first Tigerlake supporting kernel?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-13 7:47 ` Tvrtko Ursulin
@ 2022-09-14 9:56 ` Nilawar, Badal
2022-09-14 16:11 ` Dixit, Ashutosh
0 siblings, 1 reply; 24+ messages in thread
From: Nilawar, Badal @ 2022-09-14 9:56 UTC (permalink / raw)
To: Tvrtko Ursulin, Dixit, Ashutosh; +Cc: intel-gfx
On 13-09-2022 13:17, Tvrtko Ursulin wrote:
>
> On 13/09/2022 01:09, Dixit, Ashutosh wrote:
>> On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
>>>>> b/drivers/gpu/drm/i915/i915_pmu.c
>>>>> index 958b37123bf1..a24704ec2c18 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>>>>> @@ -371,7 +371,6 @@ static void
>>>>> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>>>>> {
>>>>> struct drm_i915_private *i915 = gt->i915;
>>>>> - struct intel_uncore *uncore = gt->uncore;
>>>>> struct i915_pmu *pmu = &i915->pmu;
>>>>> struct intel_rps *rps = >->rps;
>>>>>
>>>>> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned
>>>>> int period_ns)
>>>>> * case we assume the system is running at the intended
>>>>> * frequency. Fortunately, the read should rarely fail!
>>>>> */
>>>>> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
>>>>> + val = intel_rps_read_rpstat(rps);
>>>>
>>>> Hmm, we got rid of _fw which the comment above refers to. Maybe we
>>>> need a
>>>> fw flag to intel_rps_read_rpstat?
>>>
>>> Above function before reading rpstat it checks if gt is awake.
>>
>> Ok, so you are referring to intel_gt_pm_get_if_awake check in
>> frequency_sample.
>>
>>> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
>>> forcewake.In that case we can remove above comment. Let me know your
>>> thoughts on this.
>>
>> I am not entirely sure about this. For example in c1c82d267ae8
>> intel_uncore_read_fw was introduced with the same
>> intel_gt_pm_get_if_awake
>> check. So this would mean even if gt is awake not taking forcewake
>> makes a
>> difference. The same code pattern was retained in b66ecd0438bf. Maybe
>> it's
>> because there are no locks?
>
> Its about power. As c1c82d267ae8 ("drm/i915/pmu: Cheat when reading the
> actual frequency to avoid fw") explains the _fw variant is to avoid
> preventing RC6, and so increased GPU power draw, just because someone
> has PMU open. (Because of the 200Hz sampling timer that is needed for
> PMU frequency reporting.)
>
>> Under the circumstances I think we could do one of two things:
>> 1. If we want to drop _fw, we should do it as a separate patch with
>> its own
>> justification so it can be reviewed separately.
>> 2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
>> intel_rps_read_rpstat.
>
> Agreed. Or instead of the flag, the usual pattern of having
> intel_rps_read_rpstat_fw and make intel_rps_read_rpsstat get the forcewake.
>
> Also, may I ask, this patch is in the MTL enablement series but the
> commit message and patch content seem like it is fixing a wider Gen12
> issue? What is the extent of incorrect behaviour without it? Should it
> be tagged for stable for first Tigerlake supporting kernel?
GEN6_RPSTAT1(0xa01c) and GEN12_RPSTAT1(0x1381b4) both are supported by
gen12 and above. The difference between two is GEN6_RPSTAT1 falls under
RENDER forcewake domain and GEN12_RPSTAT1 does not require forcewake to
access. GEN12_RPSTAT1 is punit register and when GT is in RC6 it will
give frequency as 0.
Reason for clubbing this patch with MTL series is due to common function
intel_rps_read_rpstat. I think I should send this patch in separate
series.
Regards,
Badal
>
> Regards,
>
> Tvrtko
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-14 9:56 ` Nilawar, Badal
@ 2022-09-14 16:11 ` Dixit, Ashutosh
2022-09-15 7:33 ` Tvrtko Ursulin
0 siblings, 1 reply; 24+ messages in thread
From: Dixit, Ashutosh @ 2022-09-14 16:11 UTC (permalink / raw)
To: Nilawar, Badal; +Cc: intel-gfx
On Wed, 14 Sep 2022 02:56:26 -0700, Nilawar, Badal wrote:
>
> On 13-09-2022 13:17, Tvrtko Ursulin wrote:
> >
> > On 13/09/2022 01:09, Dixit, Ashutosh wrote:
> >> On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
> >>>
> >>>>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> >>>>> b/drivers/gpu/drm/i915/i915_pmu.c
> >>>>> index 958b37123bf1..a24704ec2c18 100644
> >>>>> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >>>>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >>>>> @@ -371,7 +371,6 @@ static void
> >>>>> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >>>>> {
> >>>>> struct drm_i915_private *i915 = gt->i915;
> >>>>> - struct intel_uncore *uncore = gt->uncore;
> >>>>> struct i915_pmu *pmu = &i915->pmu;
> >>>>> struct intel_rps *rps = >->rps;
> >>>>>
> >>>>> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned
> >>>>> int period_ns)
> >>>>> * case we assume the system is running at the intended
> >>>>> * frequency. Fortunately, the read should rarely fail!
> >>>>> */
> >>>>> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> >>>>> + val = intel_rps_read_rpstat(rps);
> >>>>
> >>>> Hmm, we got rid of _fw which the comment above refers to. Maybe we
> >>>> need a
> >>>> fw flag to intel_rps_read_rpstat?
> >>>
> >>> Above function before reading rpstat it checks if gt is awake.
> >>
> >> Ok, so you are referring to intel_gt_pm_get_if_awake check in
> >> frequency_sample.
> >>
> >>> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
> >>> forcewake.In that case we can remove above comment. Let me know your
> >>> thoughts on this.
> >>
> >> I am not entirely sure about this. For example in c1c82d267ae8
> >> intel_uncore_read_fw was introduced with the same
> >> intel_gt_pm_get_if_awake
> >> check. So this would mean even if gt is awake not taking forcewake makes
> >> a
> >> difference. The same code pattern was retained in b66ecd0438bf. Maybe
> >> it's
> >> because there are no locks?
> >
> > Its about power. As c1c82d267ae8 ("drm/i915/pmu: Cheat when reading the
> > actual frequency to avoid fw") explains the _fw variant is to avoid
> > preventing RC6, and so increased GPU power draw, just because someone has
> > PMU open. (Because of the 200Hz sampling timer that is needed for PMU
> > frequency reporting.)
> >
> >> Under the circumstances I think we could do one of two things:
> >> 1. If we want to drop _fw, we should do it as a separate patch with its
> >> own
> >> justification so it can be reviewed separately.
> >> 2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
> >> intel_rps_read_rpstat.
> >
> > Agreed. Or instead of the flag, the usual pattern of having
> > intel_rps_read_rpstat_fw and make intel_rps_read_rpsstat get the
> > forcewake.
> >
> > Also, may I ask, this patch is in the MTL enablement series but the
> > commit message and patch content seem like it is fixing a wider Gen12
> > issue? What is the extent of incorrect behaviour without it? Should it be
> > tagged for stable for first Tigerlake supporting kernel?
>
> GEN6_RPSTAT1(0xa01c) and GEN12_RPSTAT1(0x1381b4) both are supported by
> gen12 and above. The difference between two is GEN6_RPSTAT1 falls under
> RENDER forcewake domain and GEN12_RPSTAT1 does not require forcewake to
> access. GEN12_RPSTAT1 is punit register and when GT is in RC6 it will give
> frequency as 0.
Correct, so no changes needed for stable kernels. But going forward Badal
is proposing (which I sort of agree with but may need some discussion) that
we change i915 behavior to return 0 freq (instead of cur_freq or RPn) when
GT is idle or in RC6 (so we don't take forcewake to read freq when GT is in
RC6).
> Reason for clubbing this patch with MTL series is due to common function
> intel_rps_read_rpstat. I think I should send this patch in separate series.
Agree!
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
2022-09-14 16:11 ` Dixit, Ashutosh
@ 2022-09-15 7:33 ` Tvrtko Ursulin
0 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-09-15 7:33 UTC (permalink / raw)
To: Dixit, Ashutosh, Nilawar, Badal; +Cc: intel-gfx
On 14/09/2022 17:11, Dixit, Ashutosh wrote:
> On Wed, 14 Sep 2022 02:56:26 -0700, Nilawar, Badal wrote:
>>
>> On 13-09-2022 13:17, Tvrtko Ursulin wrote:
>>>
>>> On 13/09/2022 01:09, Dixit, Ashutosh wrote:
>>>> On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
>>>>>>> b/drivers/gpu/drm/i915/i915_pmu.c
>>>>>>> index 958b37123bf1..a24704ec2c18 100644
>>>>>>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>>>>>>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>>>>>>> @@ -371,7 +371,6 @@ static void
>>>>>>> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
>>>>>>> {
>>>>>>> struct drm_i915_private *i915 = gt->i915;
>>>>>>> - struct intel_uncore *uncore = gt->uncore;
>>>>>>> struct i915_pmu *pmu = &i915->pmu;
>>>>>>> struct intel_rps *rps = >->rps;
>>>>>>>
>>>>>>> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned
>>>>>>> int period_ns)
>>>>>>> * case we assume the system is running at the intended
>>>>>>> * frequency. Fortunately, the read should rarely fail!
>>>>>>> */
>>>>>>> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
>>>>>>> + val = intel_rps_read_rpstat(rps);
>>>>>>
>>>>>> Hmm, we got rid of _fw which the comment above refers to. Maybe we
>>>>>> need a
>>>>>> fw flag to intel_rps_read_rpstat?
>>>>>
>>>>> Above function before reading rpstat it checks if gt is awake.
>>>>
>>>> Ok, so you are referring to intel_gt_pm_get_if_awake check in
>>>> frequency_sample.
>>>>
>>>>> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
>>>>> forcewake.In that case we can remove above comment. Let me know your
>>>>> thoughts on this.
>>>>
>>>> I am not entirely sure about this. For example in c1c82d267ae8
>>>> intel_uncore_read_fw was introduced with the same
>>>> intel_gt_pm_get_if_awake
>>>> check. So this would mean even if gt is awake not taking forcewake makes
>>>> a
>>>> difference. The same code pattern was retained in b66ecd0438bf. Maybe
>>>> it's
>>>> because there are no locks?
>>>
>>> Its about power. As c1c82d267ae8 ("drm/i915/pmu: Cheat when reading the
>>> actual frequency to avoid fw") explains the _fw variant is to avoid
>>> preventing RC6, and so increased GPU power draw, just because someone has
>>> PMU open. (Because of the 200Hz sampling timer that is needed for PMU
>>> frequency reporting.)
>>>
>>>> Under the circumstances I think we could do one of two things:
>>>> 1. If we want to drop _fw, we should do it as a separate patch with its
>>>> own
>>>> justification so it can be reviewed separately.
>>>> 2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
>>>> intel_rps_read_rpstat.
>>>
>>> Agreed. Or instead of the flag, the usual pattern of having
>>> intel_rps_read_rpstat_fw and make intel_rps_read_rpsstat get the
>>> forcewake.
>>>
>>> Also, may I ask, this patch is in the MTL enablement series but the
>>> commit message and patch content seem like it is fixing a wider Gen12
>>> issue? What is the extent of incorrect behaviour without it? Should it be
>>> tagged for stable for first Tigerlake supporting kernel?
>>
>> GEN6_RPSTAT1(0xa01c) and GEN12_RPSTAT1(0x1381b4) both are supported by
>> gen12 and above. The difference between two is GEN6_RPSTAT1 falls under
>> RENDER forcewake domain and GEN12_RPSTAT1 does not require forcewake to
>> access. GEN12_RPSTAT1 is punit register and when GT is in RC6 it will give
>> frequency as 0.
>
> Correct, so no changes needed for stable kernels. But going forward Badal
> is proposing (which I sort of agree with but may need some discussion) that
> we change i915 behavior to return 0 freq (instead of cur_freq or RPn) when
> GT is idle or in RC6 (so we don't take forcewake to read freq when GT is in
> RC6).
We already report zero when GT is idle (as considered by software
tracking) so I guess the only part you'd like to change is drop the else
branch in:
val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
if (val)
val = intel_rps_get_cagf(rps, val);
else
val = rps->cur_freq;
?
What would be pros and cons?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915/mtl: Modify CAGF functions for MTL
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (3 preceding siblings ...)
2022-09-09 2:56 ` [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia Badal Nilawar
` (5 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia
Bspec: 66300
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++++++
drivers/gpu/drm/i915/gt/intel_rps.c | 7 ++++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index dac59c3e68db..ab9a5e66ab34 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1515,6 +1515,14 @@
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+/*
+ * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
+ * 3D - 0x0C60 , SAMedia - 0x380C60
+ * Intel uncore handler redirects transactions for SAMedia to MTL_MEDIA_GSI_BASE
+ */
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
+#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 341f96f536e8..3e4abc25f139 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2045,7 +2045,10 @@ u32 intel_rps_read_rpstat(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 rpstat;
- if (GRAPHICS_VER(i915) >= 12)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ rpstat = intel_uncore_read(rps_to_gt(rps)->uncore,
+ MTL_MIRROR_TARGET_WP1);
+ else if (GRAPHICS_VER(i915) >= 12)
rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1);
else
rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
@@ -2060,6 +2063,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = rpstat & MTL_CAGF_MASK;
else if (GRAPHICS_VER(i915) >= 12)
cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
else if (GRAPHICS_VER(i915) >= 9)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (4 preceding siblings ...)
2022-09-09 2:56 ` [Intel-gfx] [PATCH 5/6] drm/i915/mtl: Modify CAGF functions for MTL Badal Nilawar
@ 2022-09-09 2:56 ` Badal Nilawar
2022-09-10 3:38 ` Dixit, Ashutosh
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev3) Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Badal Nilawar @ 2022-09-09 2:56 UTC (permalink / raw)
To: intel-gfx
For MTL SAMedia updated relevant functions and places in the code to get
Media C6 residency.
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 ++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
drivers/gpu/drm/i915/i915_pmu.c | 8 ++-
6 files changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 96c03a1258e1..6913c0a2ba33 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+ i915_reg_t reg;
+
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+
+ switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) {
+ case MTL_CC0:
+ seq_puts(m, "on\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6;
+ print_rc6_res(m, "RC6 residency since boot:", reg);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
+ else if (MEDIA_VER(i915) >= 13)
+ err = mtl_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index ab9a5e66ab34..2c6cf29888e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1522,6 +1522,16 @@
*/
#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_SHIFT 9
+#define MTL_CC_MASK (0xf << MTL_CC_SHIFT)
+
+/*
+ * MTL: This register contains the total MC6 residency time that SAMedia was
+ * since boot
+ */
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index e066cc33d9f2..fb2cf8ee2eeb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ i915_reg_t reg;
+
+ if (gt->type == GT_MEDIA)
+ reg = MTL_MEDIA_MC6;
+ else
+ reg = GEN6_GT_GFX_RC6;
+
+ return get_residency(gt, reg);
}
static ssize_t rc6p_residency_ms_show(struct device *dev,
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f8d0523f4c18..26f71f7f07c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -745,6 +745,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
unsigned long flags;
unsigned int i;
u32 mul, div;
+ i915_reg_t base;
if (!rc6->supported)
return 0;
@@ -756,8 +757,10 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
* other so we can use the relative address, compared to the smallest
* one as the index into driver storage.
*/
+ base = (rc6_to_gt(rc6)->type == GT_MEDIA) ?
+ MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6_LOCKED;
i = (i915_mmio_reg_offset(reg) -
- i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
+ i915_mmio_reg_offset(base)) / sizeof(u32);
if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
return 0;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 8c70b7e12074..28c6a4b6b8d1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -15,11 +15,18 @@
static u64 rc6_residency(struct intel_rc6 *rc6)
{
+ struct intel_gt *gt = rc6_to_gt(rc6);
+ i915_reg_t reg;
u64 result;
/* XXX VLV_GT_MEDIA_RC6? */
- result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
+ if (gt->type == GT_MEDIA)
+ reg = MTL_MEDIA_MC6;
+ else
+ reg = GEN6_GT_GFX_RC6;
+
+ result = intel_rc6_residency_ns(rc6, reg);
if (HAS_RC6p(rc6_to_i915(rc6)))
result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
if (HAS_RC6pp(rc6_to_i915(rc6)))
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index a24704ec2c18..3653e542cbf8 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -146,9 +146,15 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
static u64 __get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ i915_reg_t reg;
u64 val;
- val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
+ if (gt->type == GT_MEDIA)
+ reg = MTL_MEDIA_MC6;
+ else
+ reg = GEN6_GT_GFX_RC6;
+
+ val = intel_rc6_residency_ns(>->rc6, reg);
if (HAS_RC6p(i915))
val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia
2022-09-09 2:56 ` [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia Badal Nilawar
@ 2022-09-10 3:38 ` Dixit, Ashutosh
0 siblings, 0 replies; 24+ messages in thread
From: Dixit, Ashutosh @ 2022-09-10 3:38 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
On Thu, 08 Sep 2022 19:56:46 -0700, Badal Nilawar wrote:
>
> For MTL SAMedia updated relevant functions and places in the code to get
> Media C6 residency.
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Chris Wilson <chris.p.wilson@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 ++++
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
> drivers/gpu/drm/i915/i915_pmu.c | 8 ++-
> 6 files changed, 93 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 96c03a1258e1..6913c0a2ba33 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m)
> return 0;
> }
>
> +static int mtl_drpc(struct seq_file *m)
> +{
> + struct intel_gt *gt = m->private;
> + struct intel_uncore *uncore = gt->uncore;
> + u32 gt_core_status, rcctl1;
> + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
> + i915_reg_t reg;
> +
Comparing with gen6_drpc do we need to add this here:
mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
And show it later as in gen6_drpc?
> + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> +
> + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
> + mtl_powergate_status = intel_uncore_read(uncore,
> + GEN9_PWRGT_DOMAIN_STATUS);
> +
> + seq_printf(m, "RC6 Enabled: %s\n",
> + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> + if (gt->type == GT_MEDIA) {
> + seq_printf(m, "Media Well Gating Enabled: %s\n",
> + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> + } else {
> + seq_printf(m, "Render Well Gating Enabled: %s\n",
> + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
> + }
> +
> + seq_puts(m, "Current RC state: ");
> +
> + switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) {
> + case MTL_CC0:
> + seq_puts(m, "on\n");
> + break;
> + case MTL_CC6:
> + seq_puts(m, "RC6\n");
> + break;
> + default:
> + seq_puts(m, "Unknown\n");
> + break;
> + }
> +
> + if (gt->type == GT_MEDIA)
> + seq_printf(m, "Media Power Well: %s\n",
> + (mtl_powergate_status &
> + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> + else
> + seq_printf(m, "Render Power Well: %s\n",
> + (mtl_powergate_status &
> + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> +
> + reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6;
> + print_rc6_res(m, "RC6 residency since boot:", reg);
> +
> + return fw_domains_show(m, NULL);
> +}
> +
> static int drpc_show(struct seq_file *m, void *unused)
> {
> struct intel_gt *gt = m->private;
> @@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused)
> with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> err = vlv_drpc(m);
> + else if (MEDIA_VER(i915) >= 13)
Why a MEDIA_VER check here? Should we use 'if (GRAPHICS_VER_FULL(i915) >=
IP_VER(12, 70))' or 'IS_METEORLAKE'?
> + err = mtl_drpc(m);
> else if (GRAPHICS_VER(i915) >= 6)
> err = gen6_drpc(m);
> else
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index ab9a5e66ab34..2c6cf29888e0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1522,6 +1522,16 @@
> */
> #define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
> #define MTL_CAGF_MASK REG_GENMASK(8, 0)
> +#define MTL_CC0 0x0
> +#define MTL_CC6 0x3
> +#define MTL_CC_SHIFT 9
> +#define MTL_CC_MASK (0xf << MTL_CC_SHIFT)
Let's remove MTL_CC_SHIFT and do
#define MTL_CC_MASK REG_GENMASK(12, 9)
Above where we are using these just use REG_FIELD_GET(MTL_CC_MASK,
gt_core_status).
> +
> +/*
> + * MTL: This register contains the total MC6 residency time that SAMedia was
> + * since boot
> + */
> +#define MTL_MEDIA_MC6 _MMIO(0x138048)
>
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index e066cc33d9f2..fb2cf8ee2eeb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
>
> static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
> {
> - return get_residency(gt, GEN6_GT_GFX_RC6p);
> + i915_reg_t reg;
> +
> + if (gt->type == GT_MEDIA)
> + reg = MTL_MEDIA_MC6;
> + else
> + reg = GEN6_GT_GFX_RC6;
> +
> + return get_residency(gt, reg);
This is not right, did you mean to make this change to __rc6_residency_ms_show?
> }
>
> static ssize_t rc6p_residency_ms_show(struct device *dev,
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index f8d0523f4c18..26f71f7f07c6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -745,6 +745,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> unsigned long flags;
> unsigned int i;
> u32 mul, div;
> + i915_reg_t base;
>
> if (!rc6->supported)
> return 0;
> @@ -756,8 +757,10 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> * other so we can use the relative address, compared to the smallest
> * one as the index into driver storage.
> */
> + base = (rc6_to_gt(rc6)->type == GT_MEDIA) ?
> + MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6_LOCKED;
> i = (i915_mmio_reg_offset(reg) -
> - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> + i915_mmio_reg_offset(base)) / sizeof(u32);
> if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 8c70b7e12074..28c6a4b6b8d1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -15,11 +15,18 @@
>
> static u64 rc6_residency(struct intel_rc6 *rc6)
> {
> + struct intel_gt *gt = rc6_to_gt(rc6);
> + i915_reg_t reg;
> u64 result;
>
> /* XXX VLV_GT_MEDIA_RC6? */
>
> - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
> + if (gt->type == GT_MEDIA)
> + reg = MTL_MEDIA_MC6;
> + else
> + reg = GEN6_GT_GFX_RC6;
> +
> + result = intel_rc6_residency_ns(rc6, reg);
> if (HAS_RC6p(rc6_to_i915(rc6)))
> result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
> if (HAS_RC6pp(rc6_to_i915(rc6)))
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index a24704ec2c18..3653e542cbf8 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -146,9 +146,15 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
> static u64 __get_rc6(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + i915_reg_t reg;
> u64 val;
>
> - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
> + if (gt->type == GT_MEDIA)
> + reg = MTL_MEDIA_MC6;
> + else
> + reg = GEN6_GT_GFX_RC6;
> +
> + val = intel_rc6_residency_ns(>->rc6, reg);
>
> if (HAS_RC6p(i915))
> val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev3)
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (5 preceding siblings ...)
2022-09-09 2:56 ` [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia Badal Nilawar
@ 2022-09-09 3:19 ` Patchwork
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-09-09 3:19 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim checkpatch failed
fe6011b91b65 drm/i915: Prepare more multi-GT initialization
-:79: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "gtdef->setup"
#79: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:853:
+ gtdef->setup != NULL;
total: 0 errors, 0 warnings, 1 checks, 148 lines checked
d5f7643cf88d drm/i915: Rename and expose common GT early init routine
ab6b4b22253c drm/i915/xelpmp: Expose media as another GT
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#83:
new file mode 100644
-:119: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!uncore->regs"
#119: FILE: drivers/gpu/drm/i915/gt/intel_sa_media.c:32:
+ if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
total: 0 errors, 1 warnings, 1 checks, 233 lines checked
2343a96e7807 drm/i915: Use GEN12 RPSTAT register
b74e84ff6b00 drm/i915/mtl: Modify CAGF functions for MTL
d993f6987b09 drm/i915/mtl: Add C6 residency support for MTL SAMedia
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev3)
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (6 preceding siblings ...)
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev3) Patchwork
@ 2022-09-09 3:19 ` Patchwork
2022-09-09 3:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-09-09 3:19 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev3)
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (7 preceding siblings ...)
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-09-09 3:30 ` Patchwork
2022-09-09 8:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-12 11:18 ` [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Andi Shyti
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-09-09 3:30 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2433 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12102 -> Patchwork_108156v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_108156v3 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- fi-glk-dsi: [DMESG-WARN][1] -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/fi-glk-dsi/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/fi-glk-dsi/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][3] ([i915#6298]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
Build changes
-------------
* Linux: CI_DRM_12102 -> Patchwork_108156v3
CI-20190529: 20190529
CI_DRM_12102: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6649: 7d91a6952dadaa9001b662ed60c08ccb8364929d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v3: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
cbf664ead393 drm/i915/mtl: Add C6 residency support for MTL SAMedia
a9ae6a14a279 drm/i915/mtl: Modify CAGF functions for MTL
776fb460f689 drm/i915: Use GEN12 RPSTAT register
c3a738c0d899 drm/i915/xelpmp: Expose media as another GT
e13422c54e46 drm/i915: Rename and expose common GT early init routine
ebfdf4bea986 drm/i915: Prepare more multi-GT initialization
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/index.html
[-- Attachment #2: Type: text/html, Size: 3099 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: CAGF and RC6 changes for MTL (rev3)
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (8 preceding siblings ...)
2022-09-09 3:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-09-09 8:23 ` Patchwork
2022-09-12 11:18 ` [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Andi Shyti
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-09-09 8:23 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 21877 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12102_full -> Patchwork_108156v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108156v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108156v3_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
------------------------------
Additional (2): shard-rkl shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108156v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rps@waitboost:
- shard-tglb: [PASS][1] -> [FAIL][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-tglb6/igt@i915_pm_rps@waitboost.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-tglb1/igt@i915_pm_rps@waitboost.html
* igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@pipe-b-vga-1:
- shard-snb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-snb2/igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@pipe-b-vga-1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-snb6/igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@pipe-b-vga-1.html
Known issues
------------
Here are the changes found in Patchwork_108156v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][5] -> [TIMEOUT][6] ([i915#3070])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb2/igt@gem_eio@unwedge-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb1/igt@gem_eio@unwedge-stress.html
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#5784])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-tglb7/igt@gem_eio@unwedge-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][11] ([i915#2846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2846])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#5566] / [i915#716])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-glk7/igt@gen9_exec_parse@allowed-all.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-glk3/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#5566] / [i915#716])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl8/igt@gen9_exec_parse@allowed-single.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271]) +85 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@vga-frame-dump:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][22] ([i915#2105])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#72])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#2346])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#2672] / [i915#3555]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#2672]) +10 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [PASS][29] -> [SKIP][30] ([i915#5176]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#658])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
* igt@perf_pmu@rc6-suspend:
- shard-apl: [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl6/igt@perf_pmu@rc6-suspend.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@perf_pmu@rc6-suspend.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#2994])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][37] ([i915#4525]) -> [PASS][38] +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][39] ([i915#2842]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][41] ([i915#2190]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][43] ([i915#454]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl6/igt@i915_pm_rps@engine-order.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@i915_pm_rps@engine-order.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][49] ([i915#180] / [i915#1982] / [i915#4939] / [i915#6598]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][51] ([i915#5176]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [SKIP][53] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb5/igt@kms_psr2_su@page_flip-xrgb8888.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][57] ([i915#4525]) -> [FAIL][58] ([i915#6117])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][59] ([i915#2920]) -> [SKIP][60] ([i915#658])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb4/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][61] ([i915#658]) -> [SKIP][62] ([i915#2920]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [FAIL][63] ([i915#5939]) -> [SKIP][64] ([fdo#109642] / [fdo#111068] / [i915#658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-iclb1/igt@kms_psr2_su@page_flip-p010.html
* igt@runner@aborted:
- shard-apl: ([FAIL][65], [FAIL][66], [FAIL][67], [FAIL][68]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][69], [FAIL][70], [FAIL][71], [FAIL][72], [FAIL][73]) ([fdo#109271] / [i915#180] / [i915#4312] / [i915#5257] / [i915#6599])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl1/igt@runner@aborted.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl2/igt@runner@aborted.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl8/igt@runner@aborted.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/shard-apl3/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl2/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl6/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl2/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl2/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/shard-apl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
Build changes
-------------
* Linux: CI_DRM_12102 -> Patchwork_108156v3
CI-20190529: 20190529
CI_DRM_12102: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6649: 7d91a6952dadaa9001b662ed60c08ccb8364929d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v3: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/index.html
[-- Attachment #2: Type: text/html, Size: 21880 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
` (9 preceding siblings ...)
2022-09-09 8:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-09-12 11:18 ` Andi Shyti
2022-09-12 12:07 ` Jani Nikula
10 siblings, 1 reply; 24+ messages in thread
From: Andi Shyti @ 2022-09-12 11:18 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
Hi Badal,
you haven't Cc'ed anyone here... Please do CC the people
interested in the patches and dri-devel mailing list.
If you don't mind, could you please resend the series either as a
V2, if you are going to change something, or as a RESEND, if you
will not change anything?
Thanks,
Andi
On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote:
> This series includes the code changes to get CAGF, RC State and
> C6 Residency of MTL. The series depends on:
>
> https://patchwork.freedesktop.org/series/107908/
>
> We have included 3 patches from from the above series as part of this
> series in order for this series to compile. These are the first 3 patches
> authored by Matt Roper. Please do not review these first 3 patches. Only
> patch 4 and 6 needs review.
>
> v2: Included "Use GEN12 RPSTAT register" patch
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Badal Nilawar (2):
> drm/i915/mtl: Modify CAGF functions for MTL
> drm/i915/mtl: Add C6 residency support for MTL SAMedia
>
> Don Hiatt (1):
> drm/i915: Use GEN12 RPSTAT register
>
> Matt Roper (3):
> drm/i915: Prepare more multi-GT initialization
> drm/i915: Rename and expose common GT early init routine
> drm/i915/xelpmp: Expose media as another GT
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 70 +++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 ++++++++
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++-
> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++++++++++
> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_pci.c | 15 ++++
> drivers/gpu/drm/i915/i915_pmu.c | 11 ++-
> drivers/gpu/drm/i915/intel_device_info.h | 19 +++++
> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++-
> drivers/gpu/drm/i915/intel_uncore.h | 20 +++++-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 21 files changed, 325 insertions(+), 26 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
2022-09-12 11:18 ` [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Andi Shyti
@ 2022-09-12 12:07 ` Jani Nikula
2022-09-12 12:12 ` Nilawar, Badal
2022-09-12 17:09 ` Andi Shyti
0 siblings, 2 replies; 24+ messages in thread
From: Jani Nikula @ 2022-09-12 12:07 UTC (permalink / raw)
To: Andi Shyti, Badal Nilawar; +Cc: intel-gfx
On Mon, 12 Sep 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> Hi Badal,
>
> you haven't Cc'ed anyone here... Please do CC the people
> interested in the patches and dri-devel mailing list.
>
> If you don't mind, could you please resend the series either as a
> V2, if you are going to change something, or as a RESEND, if you
> will not change anything?
Anyway some of the patches have been merged already so a rebase is in
order.
BR,
Jani.
>
> Thanks,
> Andi
>
> On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote:
>> This series includes the code changes to get CAGF, RC State and
>> C6 Residency of MTL. The series depends on:
>>
>> https://patchwork.freedesktop.org/series/107908/
>>
>> We have included 3 patches from from the above series as part of this
>> series in order for this series to compile. These are the first 3 patches
>> authored by Matt Roper. Please do not review these first 3 patches. Only
>> patch 4 and 6 needs review.
>>
>> v2: Included "Use GEN12 RPSTAT register" patch
>>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>
>> Badal Nilawar (2):
>> drm/i915/mtl: Modify CAGF functions for MTL
>> drm/i915/mtl: Add C6 residency support for MTL SAMedia
>>
>> Don Hiatt (1):
>> drm/i915: Use GEN12 RPSTAT register
>>
>> Matt Roper (3):
>> drm/i915: Prepare more multi-GT initialization
>> drm/i915: Rename and expose common GT early init routine
>> drm/i915/xelpmp: Expose media as another GT
>>
>> drivers/gpu/drm/i915/Makefile | 1 +
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gt.c | 70 +++++++++++++++----
>> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++-
>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 ++++++++
>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
>> drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++-
>> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++++++++++
>> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
>> drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
>> drivers/gpu/drm/i915/i915_drv.h | 2 +
>> drivers/gpu/drm/i915/i915_pci.c | 15 ++++
>> drivers/gpu/drm/i915/i915_pmu.c | 11 ++-
>> drivers/gpu/drm/i915/intel_device_info.h | 19 +++++
>> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++-
>> drivers/gpu/drm/i915/intel_uncore.h | 20 +++++-
>> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
>> 21 files changed, 325 insertions(+), 26 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>>
>> --
>> 2.25.1
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
2022-09-12 12:07 ` Jani Nikula
@ 2022-09-12 12:12 ` Nilawar, Badal
2022-09-12 17:16 ` Andi Shyti
2022-09-12 17:09 ` Andi Shyti
1 sibling, 1 reply; 24+ messages in thread
From: Nilawar, Badal @ 2022-09-12 12:12 UTC (permalink / raw)
To: Jani Nikula, Andi Shyti; +Cc: intel-gfx
I added Cc: in individual patches. So I thought it will pick
automatically. But anyway I have to fix some of the comments. So I will
fix those and resend the series. I will Cc relevant people.
Regards,
Badal
On 12-09-2022 17:37, Jani Nikula wrote:
> On Mon, 12 Sep 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
>> Hi Badal,
>>
>> you haven't Cc'ed anyone here... Please do CC the people
>> interested in the patches and dri-devel mailing list.
>>
>> If you don't mind, could you please resend the series either as a
>> V2, if you are going to change something, or as a RESEND, if you
>> will not change anything?
>
> Anyway some of the patches have been merged already so a rebase is in
> order.
>
> BR,
> Jani.
>
>>
>> Thanks,
>> Andi
>>
>> On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote:
>>> This series includes the code changes to get CAGF, RC State and
>>> C6 Residency of MTL. The series depends on:
>>>
>>> https://patchwork.freedesktop.org/series/107908/
>>>
>>> We have included 3 patches from from the above series as part of this
>>> series in order for this series to compile. These are the first 3 patches
>>> authored by Matt Roper. Please do not review these first 3 patches. Only
>>> patch 4 and 6 needs review.
>>>
>>> v2: Included "Use GEN12 RPSTAT register" patch
>>>
>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>>
>>> Badal Nilawar (2):
>>> drm/i915/mtl: Modify CAGF functions for MTL
>>> drm/i915/mtl: Add C6 residency support for MTL SAMedia
>>>
>>> Don Hiatt (1):
>>> drm/i915: Use GEN12 RPSTAT register
>>>
>>> Matt Roper (3):
>>> drm/i915: Prepare more multi-GT initialization
>>> drm/i915: Rename and expose common GT early init routine
>>> drm/i915/xelpmp: Expose media as another GT
>>>
>>> drivers/gpu/drm/i915/Makefile | 1 +
>>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 70 +++++++++++++++----
>>> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++-
>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 ++++++++
>>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
>>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>>> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
>>> drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++-
>>> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
>>> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++++++++++
>>> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
>>> drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
>>> drivers/gpu/drm/i915/i915_drv.h | 2 +
>>> drivers/gpu/drm/i915/i915_pci.c | 15 ++++
>>> drivers/gpu/drm/i915/i915_pmu.c | 11 ++-
>>> drivers/gpu/drm/i915/intel_device_info.h | 19 +++++
>>> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++-
>>> drivers/gpu/drm/i915/intel_uncore.h | 20 +++++-
>>> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
>>> 21 files changed, 325 insertions(+), 26 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>>>
>>> --
>>> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
2022-09-12 12:12 ` Nilawar, Badal
@ 2022-09-12 17:16 ` Andi Shyti
0 siblings, 0 replies; 24+ messages in thread
From: Andi Shyti @ 2022-09-12 17:16 UTC (permalink / raw)
To: Nilawar, Badal; +Cc: intel-gfx
Hi Badal,
On Mon, Sep 12, 2022 at 05:42:57PM +0530, Nilawar, Badal wrote:
> I added Cc: in individual patches. So I thought it will pick automatically.
> But anyway I have to fix some of the comments. So I will fix those and
> resend the series. I will Cc relevant people.
yes... it depends on your git-send-email command. I think no one
has received the e-mail other than the mailing list.
If you have the '--suppress-cc=all' flag then you need to
explicitly add the --to/--cc recipients (this is how I do it in
order avoid sending patches to unwanted people).
If you don't have the '--suppress-cc=all' then git-send-email
figures out by itself whom to send the patch by checking the
commit tags.
In both the cases, though, before sending the patches
individually, git-send-email displays the people that have been
added to the 'cc' list.
Please make sure not to forget the dri-devel mailing list
(<dri-devel@lists.freedesktop.org>) and to check if the patches
are actually sent to everyone.
Thanks,
Andi
> Regards,
> Badal
>
> On 12-09-2022 17:37, Jani Nikula wrote:
> > On Mon, 12 Sep 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > > Hi Badal,
> > >
> > > you haven't Cc'ed anyone here... Please do CC the people
> > > interested in the patches and dri-devel mailing list.
> > >
> > > If you don't mind, could you please resend the series either as a
> > > V2, if you are going to change something, or as a RESEND, if you
> > > will not change anything?
> >
> > Anyway some of the patches have been merged already so a rebase is in
> > order.
> >
> > BR,
> > Jani.
> >
> > >
> > > Thanks,
> > > Andi
> > >
> > > On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote:
> > > > This series includes the code changes to get CAGF, RC State and
> > > > C6 Residency of MTL. The series depends on:
> > > >
> > > > https://patchwork.freedesktop.org/series/107908/
> > > >
> > > > We have included 3 patches from from the above series as part of this
> > > > series in order for this series to compile. These are the first 3 patches
> > > > authored by Matt Roper. Please do not review these first 3 patches. Only
> > > > patch 4 and 6 needs review.
> > > >
> > > > v2: Included "Use GEN12 RPSTAT register" patch
> > > >
> > > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > >
> > > > Badal Nilawar (2):
> > > > drm/i915/mtl: Modify CAGF functions for MTL
> > > > drm/i915/mtl: Add C6 residency support for MTL SAMedia
> > > >
> > > > Don Hiatt (1):
> > > > drm/i915: Use GEN12 RPSTAT register
> > > >
> > > > Matt Roper (3):
> > > > drm/i915: Prepare more multi-GT initialization
> > > > drm/i915: Rename and expose common GT early init routine
> > > > drm/i915/xelpmp: Expose media as another GT
> > > >
> > > > drivers/gpu/drm/i915/Makefile | 1 +
> > > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> > > > drivers/gpu/drm/i915/gt/intel_gt.c | 70 +++++++++++++++----
> > > > drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
> > > > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++-
> > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 ++++++++
> > > > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
> > > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
> > > > drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++-
> > > > drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
> > > > drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++++++++++
> > > > drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
> > > > drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
> > > > drivers/gpu/drm/i915/i915_drv.h | 2 +
> > > > drivers/gpu/drm/i915/i915_pci.c | 15 ++++
> > > > drivers/gpu/drm/i915/i915_pmu.c | 11 ++-
> > > > drivers/gpu/drm/i915/intel_device_info.h | 19 +++++
> > > > drivers/gpu/drm/i915/intel_uncore.c | 16 ++++-
> > > > drivers/gpu/drm/i915/intel_uncore.h | 20 +++++-
> > > > .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> > > > 21 files changed, 325 insertions(+), 26 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
> > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
> > > >
> > > > --
> > > > 2.25.1
> >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
2022-09-12 12:07 ` Jani Nikula
2022-09-12 12:12 ` Nilawar, Badal
@ 2022-09-12 17:09 ` Andi Shyti
1 sibling, 0 replies; 24+ messages in thread
From: Andi Shyti @ 2022-09-12 17:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
Hi Jani,
On Mon, Sep 12, 2022 at 03:07:01PM +0300, Jani Nikula wrote:
> On Mon, 12 Sep 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > Hi Badal,
> >
> > you haven't Cc'ed anyone here... Please do CC the people
> > interested in the patches and dri-devel mailing list.
> >
> > If you don't mind, could you please resend the series either as a
> > V2, if you are going to change something, or as a RESEND, if you
> > will not change anything?
>
> Anyway some of the patches have been merged already so a rebase is in
> order.
thanks... I see that some of the patches have been reviewed
previously, I missed that.
Thank you,
Andi
^ permalink raw reply [flat|nested] 24+ messages in thread