* [Intel-gfx] [PATCH 1/4] drm/i915: Always initialize dpll.lock
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
@ 2022-09-21 12:23 ` Ville Syrjala
2022-09-22 15:41 ` Jani Nikula
2022-09-21 12:23 ` [Intel-gfx] [PATCH 2/4] drm/i915: Nuke intel_get_shared_dpll_id() Ville Syrjala
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2022-09-21 12:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Initialize the dll.lock mutex whether or not we manage to
initialize the rest of the dpll mgr.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e5fb66a5dd02..9c60cf69cde1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4193,6 +4193,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
const struct dpll_info *dpll_info;
int i;
+ mutex_init(&dev_priv->display.dpll.lock);
+
if (IS_DG2(dev_priv))
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
dpll_mgr = NULL;
@@ -4237,7 +4239,6 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
dev_priv->display.dpll.mgr = dpll_mgr;
dev_priv->display.dpll.num_shared_dpll = i;
- mutex_init(&dev_priv->display.dpll.lock);
}
/**
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Always initialize dpll.lock
2022-09-21 12:23 ` [Intel-gfx] [PATCH 1/4] drm/i915: Always initialize dpll.lock Ville Syrjala
@ 2022-09-22 15:41 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2022-09-22 15:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Initialize the dll.lock mutex whether or not we manage to
> initialize the rest of the dpll mgr.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e5fb66a5dd02..9c60cf69cde1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4193,6 +4193,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> const struct dpll_info *dpll_info;
> int i;
>
> + mutex_init(&dev_priv->display.dpll.lock);
> +
> if (IS_DG2(dev_priv))
> /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> dpll_mgr = NULL;
> @@ -4237,7 +4239,6 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
>
> dev_priv->display.dpll.mgr = dpll_mgr;
> dev_priv->display.dpll.num_shared_dpll = i;
> - mutex_init(&dev_priv->display.dpll.lock);
> }
>
> /**
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Nuke intel_get_shared_dpll_id()
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
2022-09-21 12:23 ` [Intel-gfx] [PATCH 1/4] drm/i915: Always initialize dpll.lock Ville Syrjala
@ 2022-09-21 12:23 ` Ville Syrjala
2022-09-22 15:42 ` Jani Nikula
2022-09-21 12:23 ` [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID Ville Syrjala
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2022-09-21 12:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Each PLL knows its own ID so intel_get_shared_dpll_id() is
pointless. Get rid of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 -------------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 ---
3 files changed, 2 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 643832d55c28..5057ee3c93fc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3536,7 +3536,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
+ if (pll->info->id == DPLL_ID_ICL_TBTPLL)
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
else
port_dpll_id = ICL_PORT_DPLL_MG_PHY;
@@ -3549,7 +3549,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
+ if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
else
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9c60cf69cde1..f900c4c73cc6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -152,28 +152,6 @@ intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
return &dev_priv->display.dpll.shared_dplls[id];
}
-/**
- * intel_get_shared_dpll_id - get the id of a DPLL
- * @dev_priv: i915 device instance
- * @pll: the DPLL
- *
- * Returns:
- * The id of @pll
- */
-enum intel_dpll_id
-intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
-{
- long pll_idx = pll - dev_priv->display.dpll.shared_dplls;
-
- if (drm_WARN_ON(&dev_priv->drm,
- pll_idx < 0 ||
- pll_idx >= dev_priv->display.dpll.num_shared_dpll))
- return -1;
-
- return pll_idx;
-}
-
/* For ILK+ */
void assert_shared_dpll(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3247dc300ae4..3854f1b4299a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -328,9 +328,6 @@ struct intel_shared_dpll {
struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id);
-enum intel_dpll_id
-intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
bool state);
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Nuke intel_get_shared_dpll_id()
2022-09-21 12:23 ` [Intel-gfx] [PATCH 2/4] drm/i915: Nuke intel_get_shared_dpll_id() Ville Syrjala
@ 2022-09-22 15:42 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2022-09-22 15:42 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Each PLL knows its own ID so intel_get_shared_dpll_id() is
> pointless. Get rid of it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 -------------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 ---
> 3 files changed, 2 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 643832d55c28..5057ee3c93fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3536,7 +3536,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> if (drm_WARN_ON(&i915->drm, !pll))
> return;
>
> - if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
> + if (pll->info->id == DPLL_ID_ICL_TBTPLL)
> port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> else
> port_dpll_id = ICL_PORT_DPLL_MG_PHY;
> @@ -3549,7 +3549,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
> + if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
> else
> crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9c60cf69cde1..f900c4c73cc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -152,28 +152,6 @@ intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
> return &dev_priv->display.dpll.shared_dplls[id];
> }
>
> -/**
> - * intel_get_shared_dpll_id - get the id of a DPLL
> - * @dev_priv: i915 device instance
> - * @pll: the DPLL
> - *
> - * Returns:
> - * The id of @pll
> - */
> -enum intel_dpll_id
> -intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll)
> -{
> - long pll_idx = pll - dev_priv->display.dpll.shared_dplls;
> -
> - if (drm_WARN_ON(&dev_priv->drm,
> - pll_idx < 0 ||
> - pll_idx >= dev_priv->display.dpll.num_shared_dpll))
> - return -1;
> -
> - return pll_idx;
> -}
> -
> /* For ILK+ */
> void assert_shared_dpll(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3247dc300ae4..3854f1b4299a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -328,9 +328,6 @@ struct intel_shared_dpll {
> struct intel_shared_dpll *
> intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
> enum intel_dpll_id id);
> -enum intel_dpll_id
> -intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll);
> void assert_shared_dpll(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> bool state);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
2022-09-21 12:23 ` [Intel-gfx] [PATCH 1/4] drm/i915: Always initialize dpll.lock Ville Syrjala
2022-09-21 12:23 ` [Intel-gfx] [PATCH 2/4] drm/i915: Nuke intel_get_shared_dpll_id() Ville Syrjala
@ 2022-09-21 12:23 ` Ville Syrjala
2022-09-22 15:46 ` Jani Nikula
2022-09-21 12:23 ` [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs Ville Syrjala
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2022-09-21 12:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There's no good reason to keep around this PLL index == PLL ID
footgun. Get rid of it.
Both i915->shared_dplls[] and state->shared_dpll[] are indexed
by the same thing now, which is just the index we get at
initialization from dpll_mgr->dpll_info[]. The rest is all about
PLL IDs now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 64 +++++++++++++------
.../gpu/drm/i915/display/intel_pch_refclk.c | 5 +-
2 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f900c4c73cc6..fb09029cc4aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -110,7 +110,7 @@ static void
intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll_state *shared_dpll)
{
- enum intel_dpll_id i;
+ int i;
/* Copy shared dpll state */
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
@@ -137,6 +137,13 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
return state->shared_dpll;
}
+static int
+intel_shared_dpll_idx(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll)
+{
+ return pll - &i915->display.dpll.shared_dplls[0];
+}
+
/**
* intel_get_shared_dpll_by_id - get a DPLL given its id
* @dev_priv: i915 device instance
@@ -149,7 +156,17 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
{
- return &dev_priv->display.dpll.shared_dplls[id];
+ int i;
+
+ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
+
+ if (pll->info->id == id)
+ return pll;
+ }
+
+ MISSING_CASE(id);
+ return NULL;
}
/* For ILK+ */
@@ -305,16 +322,23 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
unsigned long dpll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_shared_dpll *pll, *unused_pll = NULL;
struct intel_shared_dpll_state *shared_dpll;
- enum intel_dpll_id i;
+ struct intel_shared_dpll *unused_pll = NULL;
+ enum intel_dpll_id id;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
- for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
- pll = &dev_priv->display.dpll.shared_dplls[i];
+ for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
+ struct intel_shared_dpll *pll;
+ int i;
+
+ pll = intel_get_shared_dpll_by_id(dev_priv, id);
+ if (!pll)
+ continue;
+
+ i = intel_shared_dpll_idx(dev_priv, pll);
/* Only want to check enabled timings first */
if (shared_dpll[i].pipe_mask == 0) {
@@ -355,27 +379,29 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll;
- const enum intel_dpll_id id = pll->info->id;
+ int i = intel_shared_dpll_idx(i915, pll);
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- if (shared_dpll[id].pipe_mask == 0)
- shared_dpll[id].hw_state = *pll_state;
+ if (shared_dpll[i].pipe_mask == 0)
+ shared_dpll[i].hw_state = *pll_state;
drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
pipe_name(crtc->pipe));
- shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
+ shared_dpll[i].pipe_mask |= BIT(crtc->pipe);
}
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll;
+ int i = intel_shared_dpll_idx(i915, pll);
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
+ shared_dpll[i].pipe_mask &= ~BIT(crtc->pipe);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -409,14 +435,13 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
- enum intel_dpll_id i;
+ int i;
if (!state->dpll_set)
return;
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
- struct intel_shared_dpll *pll =
- &dev_priv->display.dpll.shared_dplls[i];
+ struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
swap(pll->state, shared_dpll[i]);
}
@@ -510,12 +535,12 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
- enum intel_dpll_id i;
+ enum intel_dpll_id id;
if (HAS_PCH_IBX(dev_priv)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
- i = (enum intel_dpll_id) crtc->pipe;
- pll = &dev_priv->display.dpll.shared_dplls[i];
+ id = (enum intel_dpll_id) crtc->pipe;
+ pll = intel_get_shared_dpll_by_id(dev_priv, id);
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
@@ -4199,10 +4224,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
dpll_mgr = &pch_pll_mgr;
- if (!dpll_mgr) {
- dev_priv->display.dpll.num_shared_dpll = 0;
+ if (!dpll_mgr)
return;
- }
dpll_info = dpll_mgr->dpll_info;
@@ -4211,7 +4234,6 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
break;
- drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index a66097cdc1e0..4db4b8d57e21 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -533,7 +533,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
/* Check if any DPLLs are using the SSC source */
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
- u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
+ struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
+ u32 temp;
+
+ temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
if (!(temp & DPLL_VCO_ENABLE))
continue;
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID
2022-09-21 12:23 ` [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID Ville Syrjala
@ 2022-09-22 15:46 ` Jani Nikula
2022-09-22 19:57 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2022-09-22 15:46 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's no good reason to keep around this PLL index == PLL ID
> footgun. Get rid of it.
>
> Both i915->shared_dplls[] and state->shared_dpll[] are indexed
> by the same thing now, which is just the index we get at
> initialization from dpll_mgr->dpll_info[]. The rest is all about
> PLL IDs now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 64 +++++++++++++------
> .../gpu/drm/i915/display/intel_pch_refclk.c | 5 +-
> 2 files changed, 47 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f900c4c73cc6..fb09029cc4aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -110,7 +110,7 @@ static void
> intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll_state *shared_dpll)
> {
> - enum intel_dpll_id i;
> + int i;
>
> /* Copy shared dpll state */
> for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
> @@ -137,6 +137,13 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> return state->shared_dpll;
> }
>
> +static int
> +intel_shared_dpll_idx(struct drm_i915_private *i915,
> + const struct intel_shared_dpll *pll)
> +{
> + return pll - &i915->display.dpll.shared_dplls[0];
> +}
I liked getting rid of this magic in the previous patch, and would not
like to have it brought back!
I'm thinking
static int
intel_shared_dpll_idx(struct drm_i915_private *i915, enum intel_dpll_id id)
which would loop over shared_dplls[] and return the index, similar to
the function below. Feels more robust.
Otherwise LGTM.
BR,
Jani.
> +
> /**
> * intel_get_shared_dpll_by_id - get a DPLL given its id
> * @dev_priv: i915 device instance
> @@ -149,7 +156,17 @@ struct intel_shared_dpll *
> intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
> enum intel_dpll_id id)
> {
> - return &dev_priv->display.dpll.shared_dplls[id];
> + int i;
> +
> + for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
> + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
> +
> + if (pll->info->id == id)
> + return pll;
> + }
> +
> + MISSING_CASE(id);
> + return NULL;
> }
>
> /* For ILK+ */
> @@ -305,16 +322,23 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> unsigned long dpll_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_shared_dpll *pll, *unused_pll = NULL;
> struct intel_shared_dpll_state *shared_dpll;
> - enum intel_dpll_id i;
> + struct intel_shared_dpll *unused_pll = NULL;
> + enum intel_dpll_id id;
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
>
> drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
>
> - for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
> - pll = &dev_priv->display.dpll.shared_dplls[i];
> + for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
> + struct intel_shared_dpll *pll;
> + int i;
> +
> + pll = intel_get_shared_dpll_by_id(dev_priv, id);
> + if (!pll)
> + continue;
> +
> + i = intel_shared_dpll_idx(dev_priv, pll);
>
> /* Only want to check enabled timings first */
> if (shared_dpll[i].pipe_mask == 0) {
> @@ -355,27 +379,29 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_shared_dpll_state *shared_dpll;
> - const enum intel_dpll_id id = pll->info->id;
> + int i = intel_shared_dpll_idx(i915, pll);
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
>
> - if (shared_dpll[id].pipe_mask == 0)
> - shared_dpll[id].hw_state = *pll_state;
> + if (shared_dpll[i].pipe_mask == 0)
> + shared_dpll[i].hw_state = *pll_state;
>
> drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
> pipe_name(crtc->pipe));
>
> - shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
> + shared_dpll[i].pipe_mask |= BIT(crtc->pipe);
> }
>
> static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll)
> {
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_shared_dpll_state *shared_dpll;
> + int i = intel_shared_dpll_idx(i915, pll);
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> - shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
> + shared_dpll[i].pipe_mask &= ~BIT(crtc->pipe);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state,
> @@ -409,14 +435,13 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
> - enum intel_dpll_id i;
> + int i;
>
> if (!state->dpll_set)
> return;
>
> for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
> - struct intel_shared_dpll *pll =
> - &dev_priv->display.dpll.shared_dplls[i];
> + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
>
> swap(pll->state, shared_dpll[i]);
> }
> @@ -510,12 +535,12 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> - enum intel_dpll_id i;
> + enum intel_dpll_id id;
>
> if (HAS_PCH_IBX(dev_priv)) {
> /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
> - i = (enum intel_dpll_id) crtc->pipe;
> - pll = &dev_priv->display.dpll.shared_dplls[i];
> + id = (enum intel_dpll_id) crtc->pipe;
> + pll = intel_get_shared_dpll_by_id(dev_priv, id);
>
> drm_dbg_kms(&dev_priv->drm,
> "[CRTC:%d:%s] using pre-allocated %s\n",
> @@ -4199,10 +4224,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> dpll_mgr = &pch_pll_mgr;
>
> - if (!dpll_mgr) {
> - dev_priv->display.dpll.num_shared_dpll = 0;
> + if (!dpll_mgr)
> return;
> - }
>
> dpll_info = dpll_mgr->dpll_info;
>
> @@ -4211,7 +4234,6 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
> break;
>
> - drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
> dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index a66097cdc1e0..4db4b8d57e21 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -533,7 +533,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>
> /* Check if any DPLLs are using the SSC source */
> for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
> - u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
> + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
> + u32 temp;
> +
> + temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
>
> if (!(temp & DPLL_VCO_ENABLE))
> continue;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID
2022-09-22 15:46 ` Jani Nikula
@ 2022-09-22 19:57 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2022-09-22 19:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Sep 22, 2022 at 06:46:30PM +0300, Jani Nikula wrote:
> On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > There's no good reason to keep around this PLL index == PLL ID
> > footgun. Get rid of it.
> >
> > Both i915->shared_dplls[] and state->shared_dpll[] are indexed
> > by the same thing now, which is just the index we get at
> > initialization from dpll_mgr->dpll_info[]. The rest is all about
> > PLL IDs now.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 64 +++++++++++++------
> > .../gpu/drm/i915/display/intel_pch_refclk.c | 5 +-
> > 2 files changed, 47 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index f900c4c73cc6..fb09029cc4aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -110,7 +110,7 @@ static void
> > intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
> > struct intel_shared_dpll_state *shared_dpll)
> > {
> > - enum intel_dpll_id i;
> > + int i;
> >
> > /* Copy shared dpll state */
> > for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
> > @@ -137,6 +137,13 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> > return state->shared_dpll;
> > }
> >
> > +static int
> > +intel_shared_dpll_idx(struct drm_i915_private *i915,
> > + const struct intel_shared_dpll *pll)
> > +{
> > + return pll - &i915->display.dpll.shared_dplls[0];
> > +}
>
> I liked getting rid of this magic in the previous patch, and would not
> like to have it brought back!
>
> I'm thinking
>
> static int
> intel_shared_dpll_idx(struct drm_i915_private *i915, enum intel_dpll_id id)
>
> which would loop over shared_dplls[] and return the index, similar to
> the function below. Feels more robust.
Dunno if it's more robust, but I guess it does decouple us
a bit more from the array storage of the actual plls. We
could even do this exactly like eg. drm_crtc, ie. introduce
pll->index for the atomic state indexing but could use a
linked list to keep the actual plls. Though that would
again mean more kmallocs() that can fail, so I don't think
I'll go quite that far, at least not yet. Though I suppose
I could introduce pll->index already...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
` (2 preceding siblings ...)
2022-09-21 12:23 ` [Intel-gfx] [PATCH 3/4] drm/i915: Stop requiring PLL index == PLL ID Ville Syrjala
@ 2022-09-21 12:23 ` Ville Syrjala
2022-09-22 15:55 ` Jani Nikula
2022-09-21 12:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start cleaning up the DPLL ID mess Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2022-09-21 12:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop assuming the size of PLL ID based bitmask is restricted
to I915_NUM_PLLS bits. This is the last thing coupling the
two things together and thus artificially limiting PLL IDs.
We could just pass any arbitrary (large enough) size to
for_each_set_bit() and be done with it, but the WARN
requiring the caller to not pass in a bogus bitmask seems
potentially useful to keep around. So let's just calculate
the full bitmask on the spot.
And while at it let's assert that the PLL IDs will fit
into the bitmask we use for them.
TODO: could also get rid of I915_NUM_PLLS entirely and just
dynamically allocate i915->shared_dplls[] and state->shared_dpll[].
But that would involve error handling in the modeset init path. Uff.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index fb09029cc4aa..ee04b63d2696 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -315,6 +315,21 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
mutex_unlock(&dev_priv->display.dpll.lock);
}
+static unsigned long
+intel_dpll_mask_all(struct drm_i915_private *i915)
+{
+ unsigned long dpll_mask = 0;
+ int i;
+
+ for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &i915->display.dpll.shared_dplls[i];
+
+ dpll_mask |= BIT(pll->info->id);
+ }
+
+ return dpll_mask;
+}
+
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
@@ -322,15 +337,16 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
unsigned long dpll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ unsigned long dpll_mask_all = intel_dpll_mask_all(dev_priv);
struct intel_shared_dpll_state *shared_dpll;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+ drm_WARN_ON(&dev_priv->drm, dpll_mask & ~dpll_mask_all);
- for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
+ for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_shared_dpll *pll;
int i;
@@ -4234,6 +4250,10 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
break;
+ /* must fit into unsigned long bitmask on 32bit */
+ if (drm_WARN_ON(&dev_priv->drm, dpll_info[i].id >= 32))
+ break;
+
dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
}
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs
2022-09-21 12:23 ` [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs Ville Syrjala
@ 2022-09-22 15:55 ` Jani Nikula
2022-09-22 16:06 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2022-09-22 15:55 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop assuming the size of PLL ID based bitmask is restricted
> to I915_NUM_PLLS bits. This is the last thing coupling the
> two things together and thus artificially limiting PLL IDs.
>
> We could just pass any arbitrary (large enough) size to
> for_each_set_bit() and be done with it, but the WARN
> requiring the caller to not pass in a bogus bitmask seems
> potentially useful to keep around. So let's just calculate
> the full bitmask on the spot.
>
> And while at it let's assert that the PLL IDs will fit
> into the bitmask we use for them.
>
> TODO: could also get rid of I915_NUM_PLLS entirely and just
> dynamically allocate i915->shared_dplls[] and state->shared_dpll[].
> But that would involve error handling in the modeset init path. Uff.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index fb09029cc4aa..ee04b63d2696 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -315,6 +315,21 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> mutex_unlock(&dev_priv->display.dpll.lock);
> }
>
> +static unsigned long
> +intel_dpll_mask_all(struct drm_i915_private *i915)
> +{
> + unsigned long dpll_mask = 0;
> + int i;
> +
> + for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) {
> + struct intel_shared_dpll *pll = &i915->display.dpll.shared_dplls[i];
> +
> + dpll_mask |= BIT(pll->info->id);
> + }
> +
> + return dpll_mask;
> +}
> +
> static struct intel_shared_dpll *
> intel_find_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> @@ -322,15 +337,16 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> unsigned long dpll_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + unsigned long dpll_mask_all = intel_dpll_mask_all(dev_priv);
> struct intel_shared_dpll_state *shared_dpll;
> struct intel_shared_dpll *unused_pll = NULL;
> enum intel_dpll_id id;
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
>
> - drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
> + drm_WARN_ON(&dev_priv->drm, dpll_mask & ~dpll_mask_all);
>
> - for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
> + for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> struct intel_shared_dpll *pll;
> int i;
>
> @@ -4234,6 +4250,10 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
> break;
Would be nice to add
unsigned long dpll_mask;
drm_WARN_ON(&dev_priv->drm, dpll_mask & BIT(pll->info->id));
dpll_mask |= BIT(pll->info->id);
to check for collisions.
>
> + /* must fit into unsigned long bitmask on 32bit */
> + if (drm_WARN_ON(&dev_priv->drm, dpll_info[i].id >= 32))
BITS_PER_TYPE(dpll_mask) instead of 32? Of course would only hit this
when actually running a 32-bit build.
Regardless,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + break;
> +
> dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs
2022-09-22 15:55 ` Jani Nikula
@ 2022-09-22 16:06 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2022-09-22 16:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Sep 22, 2022 at 06:55:37PM +0300, Jani Nikula wrote:
> On Wed, 21 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Stop assuming the size of PLL ID based bitmask is restricted
> > to I915_NUM_PLLS bits. This is the last thing coupling the
> > two things together and thus artificially limiting PLL IDs.
> >
> > We could just pass any arbitrary (large enough) size to
> > for_each_set_bit() and be done with it, but the WARN
> > requiring the caller to not pass in a bogus bitmask seems
> > potentially useful to keep around. So let's just calculate
> > the full bitmask on the spot.
> >
> > And while at it let's assert that the PLL IDs will fit
> > into the bitmask we use for them.
> >
> > TODO: could also get rid of I915_NUM_PLLS entirely and just
> > dynamically allocate i915->shared_dplls[] and state->shared_dpll[].
> > But that would involve error handling in the modeset init path. Uff.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++++--
> > 1 file changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index fb09029cc4aa..ee04b63d2696 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -315,6 +315,21 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> > mutex_unlock(&dev_priv->display.dpll.lock);
> > }
> >
> > +static unsigned long
> > +intel_dpll_mask_all(struct drm_i915_private *i915)
> > +{
> > + unsigned long dpll_mask = 0;
> > + int i;
> > +
> > + for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) {
> > + struct intel_shared_dpll *pll = &i915->display.dpll.shared_dplls[i];
> > +
> > + dpll_mask |= BIT(pll->info->id);
> > + }
> > +
> > + return dpll_mask;
> > +}
> > +
> > static struct intel_shared_dpll *
> > intel_find_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > @@ -322,15 +337,16 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> > unsigned long dpll_mask)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + unsigned long dpll_mask_all = intel_dpll_mask_all(dev_priv);
> > struct intel_shared_dpll_state *shared_dpll;
> > struct intel_shared_dpll *unused_pll = NULL;
> > enum intel_dpll_id id;
> >
> > shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> >
> > - drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
> > + drm_WARN_ON(&dev_priv->drm, dpll_mask & ~dpll_mask_all);
> >
> > - for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
> > + for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> > struct intel_shared_dpll *pll;
> > int i;
> >
> > @@ -4234,6 +4250,10 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> > i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
> > break;
>
> Would be nice to add
>
> unsigned long dpll_mask;
>
> drm_WARN_ON(&dev_priv->drm, dpll_mask & BIT(pll->info->id));
>
> dpll_mask |= BIT(pll->info->id);
>
> to check for collisions.
Yeah, I guess we can do that. Doing it only at init time might be
nicer but then I'd have to duplicate some code... What a conundrum.
>
> >
> > + /* must fit into unsigned long bitmask on 32bit */
> > + if (drm_WARN_ON(&dev_priv->drm, dpll_info[i].id >= 32))
>
> BITS_PER_TYPE(dpll_mask) instead of 32? Of course would only hit this
> when actually running a 32-bit build.
I'd prefer to catch it in 64bit builds too. This is the reason
I hate 'long'.
>
> Regardless,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> > + break;
> > +
> > dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start cleaning up the DPLL ID mess
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
` (3 preceding siblings ...)
2022-09-21 12:23 ` [Intel-gfx] [PATCH 4/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs Ville Syrjala
@ 2022-09-21 12:46 ` Patchwork
2022-09-21 13:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-21 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-09-21 12:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start cleaning up the DPLL ID mess
URL : https://patchwork.freedesktop.org/series/108827/
State : warning
== Summary ==
Error: dim checkpatch failed
e566d547b93b drm/i915: Always initialize dpll.lock
081d1cb10d41 drm/i915: Nuke intel_get_shared_dpll_id()
5a44789e2cb2 drm/i915: Stop requiring PLL index == PLL ID
-:156: CHECK:SPACING: No space is necessary after a cast
#156: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:542:
+ id = (enum intel_dpll_id) crtc->pipe;
total: 0 errors, 0 warnings, 1 checks, 160 lines checked
da8ead688b1b drm/i915: Decouple I915_NUM_PLLS from PLL IDs
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Start cleaning up the DPLL ID mess
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
` (4 preceding siblings ...)
2022-09-21 12:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start cleaning up the DPLL ID mess Patchwork
@ 2022-09-21 13:07 ` Patchwork
2022-09-21 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-09-21 13:07 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8973 bytes --]
== Series Details ==
Series: drm/i915: Start cleaning up the DPLL ID mess
URL : https://patchwork.freedesktop.org/series/108827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12164 -> Patchwork_108827v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/index.html
Participating hosts (34 -> 41)
------------------------------
Additional (8): fi-rkl-11600 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adln-1 bat-jsl-3 bat-rpls-1
Missing (1): fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_108827v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#3282])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3012])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][5] ([i915#5982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([fdo#111827]) +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#4103])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#109285] / [i915#4098])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#1072]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#4098])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([fdo#109295] / [i915#3301] / [i915#3708])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
#### Warnings ####
* igt@runner@aborted:
- fi-kbl-guc: [FAIL][13] ([i915#6219] / [i915#6884]) -> [FAIL][14] ([i915#6641] / [i915#6884])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/fi-kbl-guc/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-kbl-guc/igt@runner@aborted.html
- fi-kbl-8809g: [FAIL][15] ([i915#6219] / [i915#6884]) -> [FAIL][16] ([i915#6641] / [i915#6884])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/fi-kbl-8809g/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-kbl-8809g/igt@runner@aborted.html
- fi-apl-guc: [FAIL][17] ([i915#6884]) -> [FAIL][18] ([i915#6641] / [i915#6884])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/fi-apl-guc/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-apl-guc/igt@runner@aborted.html
- fi-skl-guc: [FAIL][19] ([i915#6884]) -> [FAIL][20] ([i915#6641] / [i915#6884])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/fi-skl-guc/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-skl-guc/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][21] ([i915#6219] / [i915#6884]) -> [FAIL][22] ([i915#6641] / [i915#6884] / [i915#6894])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/fi-kbl-soraka/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/fi-kbl-soraka/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6884]: https://gitlab.freedesktop.org/drm/intel/issues/6884
[i915#6894]: https://gitlab.freedesktop.org/drm/intel/issues/6894
Build changes
-------------
* Linux: CI_DRM_12164 -> Patchwork_108827v1
CI-20190529: 20190529
CI_DRM_12164: a1f63e144e545f0ce8f41f41005f2dfc552eb836 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6659: 1becf700a737a7a98555a0cfbe8566355377afb2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108827v1: a1f63e144e545f0ce8f41f41005f2dfc552eb836 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f8ff27079809 drm/i915: Decouple I915_NUM_PLLS from PLL IDs
6fccc1de8618 drm/i915: Stop requiring PLL index == PLL ID
af144a7ff876 drm/i915: Nuke intel_get_shared_dpll_id()
29e3d4c94922 drm/i915: Always initialize dpll.lock
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/index.html
[-- Attachment #2: Type: text/html, Size: 9588 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Start cleaning up the DPLL ID mess
2022-09-21 12:23 [Intel-gfx] [PATCH 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
` (5 preceding siblings ...)
2022-09-21 13:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-09-21 14:05 ` Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-09-21 14:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 31171 bytes --]
== Series Details ==
Series: drm/i915: Start cleaning up the DPLL ID mess
URL : https://patchwork.freedesktop.org/series/108827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12164_full -> Patchwork_108827v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_108827v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) ([i915#4392]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk3/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk9/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk8/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk8/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk7/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk2/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk3/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk7/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk7/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk7/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk9/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk9/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk9/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#1839])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@feature_discovery@display-3x.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#4525]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglb: NOTRUN -> [SKIP][53] ([i915#6344])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][54] -> [FAIL][55] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
- shard-glk: NOTRUN -> [FAIL][56] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][57] -> [FAIL][58] ([i915#2842])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][62] ([i915#2658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-protected-buffer:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#4270])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@gem_pxp@create-protected-buffer.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-glk: NOTRUN -> [SKIP][64] ([fdo#109271]) +79 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][65] -> [DMESG-WARN][66] ([i915#180]) +6 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl3/igt@gem_workarounds@suspend-resume.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl1/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#2527] / [i915#2856])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@gen9_exec_parse@allowed-single.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#5286])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#111615])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#3689] / [i915#3886]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][71] ([i915#3689] / [i915#6095]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][73] ([fdo#111615] / [i915#3689])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-tglb: NOTRUN -> [SKIP][74] ([fdo#109284] / [fdo#111827]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@ctm-max:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [fdo#111827]) +4 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@kms_color_chamelium@ctm-max.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109274] / [fdo#111825] / [i915#3637]) +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#2587] / [i915#2672]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#2672]) +4 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#109280] / [fdo#111825]) +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#6497]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@tiling-4:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#112054] / [i915#5288])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#5235]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#2920])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][86] -> [SKIP][87] ([fdo#109441]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#109291])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@prime_nv_pcopy@test1_macro.html
* igt@sysfs_clients@fair-0:
- shard-tglb: NOTRUN -> [SKIP][89] ([i915#2994])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@sema-25:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk8/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-tglb: [FAIL][91] ([i915#5784]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-tglb1/igt@gem_eio@reset-stress.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb7/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][93] ([i915#4525]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_userptr_blits@huge-split:
- shard-apl: [FAIL][99] ([i915#3376]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl3/igt@gem_userptr_blits@huge-split.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl2/igt@gem_userptr_blits@huge-split.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][101] ([i915#4281]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][103] ([i915#6537]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl7/igt@i915_pm_rps@engine-order.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl6/igt@i915_pm_rps@engine-order.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][105] ([i915#5591]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglb: [FAIL][107] ([i915#3743]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-tglb6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-dp-1:
- shard-apl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-b-dp-1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl6/igt@kms_cursor_crc@cursor-suspend@pipe-b-dp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [SKIP][111] ([i915#5176]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][113] ([fdo#109441]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb3/igt@kms_psr@psr2_primary_blt.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-tglb: [INCOMPLETE][115] -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-tglb8/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-tglb8/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][117] ([i915#658]) -> [SKIP][118] ([i915#2920])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][119] ([fdo#111068] / [i915#658]) -> [SKIP][120] ([i915#2920])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][121], [FAIL][122], [FAIL][123]) ([i915#3002] / [i915#4312] / [i915#6884]) -> ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#6884])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl6/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl7/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-apl2/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl6/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl8/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl8/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl3/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-apl7/igt@runner@aborted.html
- shard-skl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#6884]) -> ([FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173]) ([i915#6641] / [i915#6884])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl10/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl10/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl3/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl10/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl10/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl6/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl5/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl9/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl9/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl6/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl9/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl4/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl6/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12164/shard-skl4/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl1/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl10/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl4/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl7/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl6/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl9/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl3/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl4/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl10/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl6/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl5/igt@runner@aborted.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl6/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl3/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl7/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl10/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl4/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl9/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl1/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl5/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl1/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/shard-skl9/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
[i915#6884]: https://gitlab.freedesktop.org/drm/intel/issues/6884
Build changes
-------------
* Linux: CI_DRM_12164 -> Patchwork_108827v1
CI-20190529: 20190529
CI_DRM_12164: a1f63e144e545f0ce8f41f41005f2dfc552eb836 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6659: 1becf700a737a7a98555a0cfbe8566355377afb2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108827v1: a1f63e144e545f0ce8f41f41005f2dfc552eb836 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108827v1/index.html
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