From: Jing Zhang <renyu.zj@linux.alibaba.com> To: John Garry <john.g.garry@oracle.com>, Ian Rogers <irogers@google.com>, Xing Zhengjun <zhengjun.xing@linux.intel.com>, Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, Andrew Kilroy <andrew.kilroy@arm.com>, Shuai Xue <xueshuai@linux.alibaba.com>, Zhuo Song <zhuo.song@linux.alibaba.com>, Jing Zhang <renyu.zj@linux.alibaba.com> Subject: [PATCH v3 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2 Date: Fri, 25 Nov 2022 01:14:43 +0800 [thread overview] Message-ID: <1669310088-13482-2-git-send-email-renyu.zj@linux.alibaba.com> (raw) In-Reply-To: <1669310088-13482-1-git-send-email-renyu.zj@linux.alibaba.com> In-Reply-To: <1668411720-3581-1-git-send-email-renyu.zj@linux.alibaba.com> The formula of topdown L1 on neoverse-n2 is from ARM sbsa7.0 platform design document [0], D37-38. However, due to the wrong count of stall_slot and stall_slot_frontend on neoverse-n2, the real stall_slot and real stall_slot_frontend need to subtract cpu_cycles, so correct the expression of topdown metrics. Reference from ARM neoverse-n2 errata notice [1], D117. Since neoverse-n2 does not yet support topdown L2, metricgroups such as Cache, TLB, Branch, InstructionsMix, and PEutilization will be added to further analysis of performance bottlenecks in the following patches. Reference from ARM PMU guide [2][3]. [0] https://documentation-service.arm.com/static/60250c7395978b529036da86?token= [1] https://documentation-service.arm.com/static/636a66a64e6cf12278ad89cb?token= [2] https://documentation-service.arm.com/static/628f8fa3dfaf015c2b76eae8?token= [3] https://documentation-service.arm.com/static/62cfe21e31ea212bb6627393?token= Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com> --- .../arch/arm64/arm/neoverse-n2/metrics.json | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json new file mode 100644 index 0000000..8628140 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json @@ -0,0 +1,34 @@ +[ + { + "MetricExpr": "(stall_slot_frontend - cpu_cycles) / (5 * cpu_cycles)", + "PublicDescription": "Frontend bound L1 topdown metric", + "BriefDescription": "Frontend bound L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "frontend_bound", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "(1 - op_retired / op_spec) * (1 - (stall_slot - cpu_cycles) / (5 * cpu_cycles))", + "PublicDescription": "Bad speculation L1 topdown metric", + "BriefDescription": "Bad speculation L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "bad_speculation", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "(op_retired / op_spec) * (1 - (stall_slot - cpu_cycles) / (5 * cpu_cycles))", + "PublicDescription": "Retiring L1 topdown metric", + "BriefDescription": "Retiring L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "retiring", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "stall_slot_backend / (5 * cpu_cycles)", + "PublicDescription": "Backend Bound L1 topdown metric", + "BriefDescription": "Backend Bound L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "backend_bound", + "ScaleUnit": "100%" + } +] -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: Jing Zhang <renyu.zj@linux.alibaba.com> To: John Garry <john.g.garry@oracle.com>, Ian Rogers <irogers@google.com>, Xing Zhengjun <zhengjun.xing@linux.intel.com>, Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, Andrew Kilroy <andrew.kilroy@arm.com>, Shuai Xue <xueshuai@linux.alibaba.com>, Zhuo Song <zhuo.song@linux.alibaba.com>, Jing Zhang <renyu.zj@linux.alibaba.com> Subject: [PATCH v3 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2 Date: Fri, 25 Nov 2022 01:14:43 +0800 [thread overview] Message-ID: <1669310088-13482-2-git-send-email-renyu.zj@linux.alibaba.com> (raw) In-Reply-To: <1669310088-13482-1-git-send-email-renyu.zj@linux.alibaba.com> In-Reply-To: <1668411720-3581-1-git-send-email-renyu.zj@linux.alibaba.com> The formula of topdown L1 on neoverse-n2 is from ARM sbsa7.0 platform design document [0], D37-38. However, due to the wrong count of stall_slot and stall_slot_frontend on neoverse-n2, the real stall_slot and real stall_slot_frontend need to subtract cpu_cycles, so correct the expression of topdown metrics. Reference from ARM neoverse-n2 errata notice [1], D117. Since neoverse-n2 does not yet support topdown L2, metricgroups such as Cache, TLB, Branch, InstructionsMix, and PEutilization will be added to further analysis of performance bottlenecks in the following patches. Reference from ARM PMU guide [2][3]. [0] https://documentation-service.arm.com/static/60250c7395978b529036da86?token= [1] https://documentation-service.arm.com/static/636a66a64e6cf12278ad89cb?token= [2] https://documentation-service.arm.com/static/628f8fa3dfaf015c2b76eae8?token= [3] https://documentation-service.arm.com/static/62cfe21e31ea212bb6627393?token= Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com> --- .../arch/arm64/arm/neoverse-n2/metrics.json | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json new file mode 100644 index 0000000..8628140 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json @@ -0,0 +1,34 @@ +[ + { + "MetricExpr": "(stall_slot_frontend - cpu_cycles) / (5 * cpu_cycles)", + "PublicDescription": "Frontend bound L1 topdown metric", + "BriefDescription": "Frontend bound L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "frontend_bound", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "(1 - op_retired / op_spec) * (1 - (stall_slot - cpu_cycles) / (5 * cpu_cycles))", + "PublicDescription": "Bad speculation L1 topdown metric", + "BriefDescription": "Bad speculation L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "bad_speculation", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "(op_retired / op_spec) * (1 - (stall_slot - cpu_cycles) / (5 * cpu_cycles))", + "PublicDescription": "Retiring L1 topdown metric", + "BriefDescription": "Retiring L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "retiring", + "ScaleUnit": "100%" + }, + { + "MetricExpr": "stall_slot_backend / (5 * cpu_cycles)", + "PublicDescription": "Backend Bound L1 topdown metric", + "BriefDescription": "Backend Bound L1 topdown metric", + "MetricGroup": "TopdownL1", + "MetricName": "backend_bound", + "ScaleUnit": "100%" + } +] -- 1.8.3.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-24 17:15 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-31 11:11 [PATCH RFC 0/6] Add metrics for neoverse-n2 Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 2/6] perf vendor events arm64: Add TLB " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 3/6] perf vendor events arm64: Add cache " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 4/6] perf vendor events arm64: Add branch " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-10-31 11:11 ` [PATCH RFC 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang 2022-10-31 11:11 ` Jing Zhang 2022-11-14 7:41 ` [RFC PATCH v2 0/6] Add " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-24 17:14 ` [PATCH v3 " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-24 17:14 ` Jing Zhang [this message] 2022-11-24 17:14 ` [PATCH v3 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang 2022-11-24 17:14 ` [PATCH v3 2/6] perf vendor events arm64: Add TLB " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-24 17:14 ` [PATCH v3 3/6] perf vendor events arm64: Add cache " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-24 17:14 ` [PATCH v3 4/6] perf vendor events arm64: Add branch " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-24 17:14 ` [PATCH v3 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-30 18:58 ` Ian Rogers 2022-11-30 18:58 ` Ian Rogers 2022-12-01 11:08 ` Jing Zhang 2022-12-01 11:08 ` Jing Zhang 2022-12-02 20:05 ` Ian Rogers 2022-12-02 20:05 ` Ian Rogers 2022-12-04 7:10 ` Jing Zhang 2022-12-04 7:10 ` Jing Zhang 2022-11-24 17:14 ` [PATCH v3 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang 2022-11-24 17:14 ` Jing Zhang 2022-11-14 7:41 ` [RFC PATCH v2 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-14 12:59 ` [External] : " John Garry 2022-11-14 12:59 ` John Garry 2022-11-15 8:43 ` Jing Zhang 2022-11-15 8:43 ` Jing Zhang 2022-11-15 11:19 ` John Garry 2022-11-15 11:19 ` John Garry 2022-11-21 9:53 ` Jing Zhang 2022-11-21 9:53 ` Jing Zhang 2022-11-21 10:22 ` John Garry 2022-11-21 10:22 ` John Garry 2022-11-21 15:17 ` Jing Zhang 2022-11-21 15:17 ` Jing Zhang 2022-11-21 17:55 ` John Garry 2022-11-21 17:55 ` John Garry 2022-11-22 9:24 ` Jing Zhang 2022-11-22 9:24 ` Jing Zhang 2022-11-22 14:00 ` James Clark 2022-11-22 14:00 ` James Clark 2022-11-22 15:41 ` Jing Zhang 2022-11-22 15:41 ` Jing Zhang 2022-11-23 14:26 ` James Clark 2022-11-23 14:26 ` James Clark 2022-11-24 16:32 ` Jing Zhang 2022-11-24 16:32 ` Jing Zhang 2022-11-24 16:51 ` James Clark 2022-11-24 16:51 ` James Clark 2022-11-14 7:41 ` [RFC PATCH v2 2/6] perf vendor events arm64: Add TLB " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-14 7:41 ` [RFC PATCH v2 3/6] perf vendor events arm64: Add cache " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-14 8:35 ` Xing Zhengjun 2022-11-14 8:35 ` Xing Zhengjun 2022-11-15 6:28 ` Jing Zhang 2022-11-15 6:28 ` Jing Zhang 2022-11-14 7:41 ` [RFC PATCH v2 4/6] perf vendor events arm64: Add branch " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-14 7:41 ` [RFC PATCH v2 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang 2022-11-14 7:41 ` Jing Zhang 2022-11-14 7:42 ` [RFC PATCH v2 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang 2022-11-14 7:42 ` Jing Zhang 2022-11-16 11:19 ` [PATCH RFC 0/6] Add " James Clark 2022-11-16 11:19 ` James Clark 2022-11-16 15:26 ` Jing Zhang 2022-11-16 15:26 ` Jing Zhang 2022-11-21 11:51 ` James Clark 2022-11-21 11:51 ` James Clark 2022-11-22 7:11 ` Jing Zhang 2022-11-22 7:11 ` Jing Zhang 2022-11-22 11:53 ` James Clark 2022-11-22 11:53 ` James Clark 2022-11-19 3:30 ` Jing Zhang 2022-11-19 3:30 ` Jing Zhang [not found] ` <CAP-5=fW+Z_Tc3BfK1bRKUeKWfxtPfoZXL9D2BhcU1SzNOruSsg@mail.gmail.com> 2022-11-20 3:49 ` Jing Zhang 2022-11-20 3:49 ` Jing Zhang 2022-11-21 11:55 ` James Clark 2022-11-21 11:55 ` James Clark
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