From: Kuogee Hsieh <quic_khsieh@quicinc.com> To: <dri-devel@lists.freedesktop.org>, <robdclark@gmail.com>, <sean@poorly.run>, <swboyd@chromium.org>, <dianders@chromium.org>, <vkoul@kernel.org>, <daniel@ffwll.ch>, <airlied@linux.ie>, <agross@kernel.org>, <dmitry.baryshkov@linaro.org>, <andersson@kernel.org>, <konrad.dybcio@somainline.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <devicetree@vger.kernel.org>, <airlied@gmail.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com>, <quic_abhinavk@quicinc.com>, <quic_sbillaka@quicinc.com>, <freedreno@lists.freedesktop.org>, <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v9 5/5] drm/msm/dp: add support of max dp link rate Date: Mon, 5 Dec 2022 15:08:14 -0800 [thread overview] Message-ID: <1670281694-13281-6-git-send-email-quic_khsieh@quicinc.com> (raw) In-Reply-To: <1670281694-13281-1-git-send-email-quic_khsieh@quicinc.com> By default, HBR2 (5.4G) is the max link link be supported. This patch uses the actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that. Changes in v2: -- add max link rate from dtsi Changes in v3: -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint Changes in v4: -- delete unnecessary pr_err Changes in v5: -- split parser function into different patch Changes in v9: -- revised commit test Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bfd0aef..edee550 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) struct edid *edid; dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; + dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; + + drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", + dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..933fa9c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; + /* Limit data lanes from data-lanes of endpoint properity of dtsi */ if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); + /* Limit link rate from link-frequencies of endpoint properity of dtsi */ + if (link_info->rate > dp_panel->max_dp_link_rate) + link_info->rate = dp_panel->max_dp_link_rate; drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index d861197a..f04d021 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct dp_panel { u32 vic; u32 max_dp_lanes; + u32 max_dp_link_rate; u32 max_bw_code; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Kuogee Hsieh <quic_khsieh@quicinc.com> To: <dri-devel@lists.freedesktop.org>, <robdclark@gmail.com>, <sean@poorly.run>, <swboyd@chromium.org>, <dianders@chromium.org>, <vkoul@kernel.org>, <daniel@ffwll.ch>, <airlied@linux.ie>, <agross@kernel.org>, <dmitry.baryshkov@linaro.org>, <andersson@kernel.org>, <konrad.dybcio@somainline.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <devicetree@vger.kernel.org>, <airlied@gmail.com> Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, Kuogee Hsieh <quic_khsieh@quicinc.com>, freedreno@lists.freedesktop.org Subject: [PATCH v9 5/5] drm/msm/dp: add support of max dp link rate Date: Mon, 5 Dec 2022 15:08:14 -0800 [thread overview] Message-ID: <1670281694-13281-6-git-send-email-quic_khsieh@quicinc.com> (raw) In-Reply-To: <1670281694-13281-1-git-send-email-quic_khsieh@quicinc.com> By default, HBR2 (5.4G) is the max link link be supported. This patch uses the actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that. Changes in v2: -- add max link rate from dtsi Changes in v3: -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint Changes in v4: -- delete unnecessary pr_err Changes in v5: -- split parser function into different patch Changes in v9: -- revised commit test Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bfd0aef..edee550 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) struct edid *edid; dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; + dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; + + drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", + dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..933fa9c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; + /* Limit data lanes from data-lanes of endpoint properity of dtsi */ if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); + /* Limit link rate from link-frequencies of endpoint properity of dtsi */ + if (link_info->rate > dp_panel->max_dp_link_rate) + link_info->rate = dp_panel->max_dp_link_rate; drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index d861197a..f04d021 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct dp_panel { u32 vic; u32 max_dp_lanes; + u32 max_dp_link_rate; u32 max_bw_code; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2022-12-05 23:09 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-05 23:08 [PATCH v9 0/5] Add data-lanes and link-frequencies to dp_out endpoint Kuogee Hsieh 2022-12-05 23:08 ` Kuogee Hsieh 2022-12-05 23:08 ` [PATCH v9 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into " Kuogee Hsieh 2022-12-05 23:08 ` Kuogee Hsieh 2022-12-05 23:08 ` [PATCH v9 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property Kuogee Hsieh 2022-12-05 23:08 ` Kuogee Hsieh 2022-12-06 12:47 ` Rob Herring 2022-12-06 12:47 ` Rob Herring 2022-12-05 23:08 ` [PATCH v9 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint Kuogee Hsieh 2022-12-05 23:08 ` Kuogee Hsieh 2022-12-05 23:08 ` [PATCH v9 4/5] drm/msm/dp: parser link-frequencies " Kuogee Hsieh 2022-12-05 23:08 ` Kuogee Hsieh 2022-12-05 23:41 ` Dmitry Baryshkov 2022-12-05 23:41 ` Dmitry Baryshkov 2022-12-05 23:08 ` Kuogee Hsieh [this message] 2022-12-05 23:08 ` [PATCH v9 5/5] drm/msm/dp: add support of max dp link rate Kuogee Hsieh
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