From: Mohamed Mediouni <mohamed.mediouni@caramail.com> To: Alexander Graf <graf@amazon.com> Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Marc Zyngier <maz@kernel.org>, Hector Martin <marcan@marcan.st>, linux-kernel@vger.kernel.org, Stan Skowronek <stan@corellium.com> Subject: Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors Date: Wed, 20 Jan 2021 19:06:48 +0100 [thread overview] Message-ID: <17579DC5-13AF-48E1-9B72-91B14AB485FA@caramail.com> (raw) In-Reply-To: <ce5692a9-e716-514a-f196-b0645bb03eb8@amazon.com> > On 20 Jan 2021, at 17:47, Alexander Graf <graf@amazon.com> wrote: > > On 20.01.21 14:27, Mohamed Mediouni wrote: >> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware quirk. >> On Apple processors, writes using the nGnRE device memory type get dropped in flight, >> getting to nowhere. >> Signed-off-by: Stan Skowronek <stan@corellium.com> >> Signed-off-by: Mohamed Mediouni <mohamed.mediouni@caramail.com> >> --- >> arch/arm64/mm/proc.S | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S >> index 1f7ee8c8b7b8..06436916f137 100644 >> --- a/arch/arm64/mm/proc.S >> +++ b/arch/arm64/mm/proc.S >> @@ -51,6 +51,25 @@ >> #define TCR_KASAN_HW_FLAGS 0 >> #endif >> +#ifdef CONFIG_ARCH_APPLE > > Is there any particular reason for this #ifdef? > > > Alex > Not a particular reason, as we explicitly check for the implementer ID. However, without CONFIG_ARCH_APPLE, other parts of the support for Apple CPUs will not be available anyway. >> + >> +/* >> + * Apple cores appear to black-hole writes done with nGnRE. >> + * We settled on a work-around that uses MAIR vs changing every single user of >> + * nGnRE across the arm64 code. >> + */ >> + >> +#define MAIR_EL1_SET_APPLE \ >> + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) >> + >> +#endif >> + >> /* >> * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and >> * changed during __cpu_setup to Normal Tagged if the system supports MTE. >> @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup) >> * Memory region attributes >> */ >> mov_q x5, MAIR_EL1_SET >> +#ifdef CONFIG_ARCH_APPLE >> + mrs x0, MIDR_EL1 >> + lsr w0, w0, #24 >> + mov_q x1, MAIR_EL1_SET_APPLE >> + cmp x0, #0x61 // 0x61 = Implementer: Apple >> + csel x5, x1, x5, eq >> +#endif >> #ifdef CONFIG_ARM64_MTE >> mte_tcr .req x20 >> -- >> 2.29.2 > > > > > Amazon Development Center Germany GmbH > Krausenstr. 38 > 10117 Berlin > Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss > Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B > Sitz: Berlin > Ust-ID: DE 289 237 879
WARNING: multiple messages have this Message-ID (diff)
From: Mohamed Mediouni <mohamed.mediouni@caramail.com> To: Alexander Graf <graf@amazon.com> Cc: Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Hector Martin <marcan@marcan.st>, linux-kernel@vger.kernel.org, Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>, linux-arm-kernel@lists.infradead.org, Stan Skowronek <stan@corellium.com> Subject: Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors Date: Wed, 20 Jan 2021 19:06:48 +0100 [thread overview] Message-ID: <17579DC5-13AF-48E1-9B72-91B14AB485FA@caramail.com> (raw) In-Reply-To: <ce5692a9-e716-514a-f196-b0645bb03eb8@amazon.com> > On 20 Jan 2021, at 17:47, Alexander Graf <graf@amazon.com> wrote: > > On 20.01.21 14:27, Mohamed Mediouni wrote: >> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware quirk. >> On Apple processors, writes using the nGnRE device memory type get dropped in flight, >> getting to nowhere. >> Signed-off-by: Stan Skowronek <stan@corellium.com> >> Signed-off-by: Mohamed Mediouni <mohamed.mediouni@caramail.com> >> --- >> arch/arm64/mm/proc.S | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S >> index 1f7ee8c8b7b8..06436916f137 100644 >> --- a/arch/arm64/mm/proc.S >> +++ b/arch/arm64/mm/proc.S >> @@ -51,6 +51,25 @@ >> #define TCR_KASAN_HW_FLAGS 0 >> #endif >> +#ifdef CONFIG_ARCH_APPLE > > Is there any particular reason for this #ifdef? > > > Alex > Not a particular reason, as we explicitly check for the implementer ID. However, without CONFIG_ARCH_APPLE, other parts of the support for Apple CPUs will not be available anyway. >> + >> +/* >> + * Apple cores appear to black-hole writes done with nGnRE. >> + * We settled on a work-around that uses MAIR vs changing every single user of >> + * nGnRE across the arm64 code. >> + */ >> + >> +#define MAIR_EL1_SET_APPLE \ >> + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ >> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) >> + >> +#endif >> + >> /* >> * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and >> * changed during __cpu_setup to Normal Tagged if the system supports MTE. >> @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup) >> * Memory region attributes >> */ >> mov_q x5, MAIR_EL1_SET >> +#ifdef CONFIG_ARCH_APPLE >> + mrs x0, MIDR_EL1 >> + lsr w0, w0, #24 >> + mov_q x1, MAIR_EL1_SET_APPLE >> + cmp x0, #0x61 // 0x61 = Implementer: Apple >> + csel x5, x1, x5, eq >> +#endif >> #ifdef CONFIG_ARM64_MTE >> mte_tcr .req x20 >> -- >> 2.29.2 > > > > > Amazon Development Center Germany GmbH > Krausenstr. 38 > 10117 Berlin > Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss > Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B > Sitz: Berlin > Ust-ID: DE 289 237 879 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-20 18:17 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-20 13:27 [RFC PATCH 0/7] Linux on Apple Silicon Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 13:27 ` [RFC PATCH 1/7] arm64: kernel: FIQ support Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 13:27 ` [RFC PATCH 2/7] arm64: kernel: Add a WFI hook Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 16:46 ` Alexander Graf 2021-01-20 16:46 ` Alexander Graf [not found] ` <94C20F55-D3B8-4349-B26F-9EA8AAEBF639@caramail.com> 2021-01-21 12:33 ` Hector Martin 'marcan' 2021-01-21 12:33 ` Hector Martin 'marcan' 2021-01-21 10:52 ` Arnd Bergmann 2021-01-21 10:52 ` Arnd Bergmann 2021-01-21 11:01 ` Mohamed Mediouni 2021-01-21 11:01 ` Mohamed Mediouni 2021-01-21 11:36 ` Arnd Bergmann 2021-01-21 11:36 ` Arnd Bergmann 2021-01-20 13:27 ` [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 16:47 ` Alexander Graf 2021-01-20 16:47 ` Alexander Graf 2021-01-20 18:06 ` Mohamed Mediouni [this message] 2021-01-20 18:06 ` Mohamed Mediouni 2021-01-20 18:10 ` Alexander Graf 2021-01-20 18:10 ` Alexander Graf 2021-01-21 11:27 ` Will Deacon 2021-01-21 11:27 ` Will Deacon 2021-01-21 11:38 ` Arnd Bergmann 2021-01-21 11:38 ` Arnd Bergmann 2021-01-21 11:44 ` Marc Zyngier 2021-01-21 11:44 ` Marc Zyngier 2021-01-21 12:47 ` Will Deacon 2021-01-21 12:47 ` Will Deacon 2021-01-21 15:12 ` Mohamed Mediouni 2021-01-21 15:12 ` Mohamed Mediouni 2021-01-21 16:25 ` Marc Zyngier 2021-01-21 16:25 ` Marc Zyngier 2021-01-21 17:55 ` Will Deacon 2021-01-21 17:55 ` Will Deacon 2021-01-21 18:15 ` Marc Zyngier 2021-01-21 18:15 ` Marc Zyngier 2021-01-21 18:22 ` Mohamed Mediouni 2021-01-21 18:22 ` Mohamed Mediouni 2021-01-21 18:22 ` Will Deacon 2021-01-21 18:22 ` Will Deacon 2021-01-20 13:27 ` [RFC PATCH 4/7] irqchip/apple-aic: Add support for Apple AIC Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 17:11 ` Alexander Graf 2021-01-20 17:11 ` Alexander Graf 2021-01-20 18:04 ` Mohamed Mediouni 2021-01-20 18:04 ` Mohamed Mediouni 2021-01-20 20:16 ` Andrew Lunn 2021-01-20 20:16 ` Andrew Lunn 2021-01-20 21:18 ` Stan Skowronek 2021-01-20 21:18 ` Stan Skowronek 2021-01-21 9:48 ` Linus Walleij 2021-01-21 9:48 ` Linus Walleij 2021-01-21 10:37 ` Arnd Bergmann 2021-01-21 10:37 ` Arnd Bergmann 2021-01-21 15:29 ` Hector Martin 'marcan' 2021-01-21 15:29 ` Hector Martin 'marcan' 2021-01-21 17:09 ` Rob Herring 2021-01-21 17:09 ` Rob Herring 2021-01-21 17:45 ` Rob Herring 2021-01-21 17:45 ` Rob Herring 2021-01-21 16:44 ` Rob Herring 2021-01-21 16:44 ` Rob Herring 2021-01-21 16:53 ` Hector Martin 'marcan' 2021-01-21 16:53 ` Hector Martin 'marcan' 2021-01-20 13:27 ` [RFC PATCH 5/7] arm64/Kconfig: Add Apple Silicon SoC platform Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-20 13:27 ` [RFC PATCH 6/7] arm64: kernel: Apple CPU start driver Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-21 11:14 ` Arnd Bergmann 2021-01-21 11:14 ` Arnd Bergmann 2021-01-20 13:27 ` [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver Mohamed Mediouni 2021-01-20 13:27 ` Mohamed Mediouni 2021-01-21 12:44 ` Arnd Bergmann 2021-01-21 12:44 ` Arnd Bergmann 2021-01-21 12:50 ` Mohamed Mediouni 2021-01-21 12:50 ` Mohamed Mediouni 2021-01-21 13:00 ` Arnd Bergmann 2021-01-21 13:00 ` Arnd Bergmann 2021-01-21 13:01 ` Hector Martin 'marcan' 2021-01-21 13:01 ` Hector Martin 'marcan' 2021-01-21 13:22 ` Marc Zyngier 2021-01-21 13:22 ` Marc Zyngier 2021-01-21 13:32 ` Mark Rutland 2021-01-21 13:32 ` Mark Rutland 2021-01-21 14:05 ` Marc Zyngier 2021-01-21 14:05 ` Marc Zyngier 2021-01-21 13:34 ` Mohamed Mediouni 2021-01-21 13:34 ` Mohamed Mediouni 2021-01-21 14:10 ` Marc Zyngier 2021-01-21 14:10 ` Marc Zyngier 2021-01-21 15:09 ` Arnd Bergmann 2021-01-21 15:09 ` Arnd Bergmann 2021-01-21 15:18 ` Mohamed Mediouni 2021-01-21 15:18 ` Mohamed Mediouni 2021-01-21 16:40 ` Rob Herring 2021-01-21 16:40 ` Rob Herring 2021-01-21 16:43 ` Mohamed Mediouni 2021-01-21 16:43 ` Mohamed Mediouni 2021-01-21 17:37 ` Rob Herring 2021-01-21 17:37 ` Rob Herring 2021-01-21 18:08 ` Mohamed Mediouni 2021-01-21 18:08 ` Mohamed Mediouni 2021-01-21 18:57 ` Rob Herring 2021-01-21 18:57 ` Rob Herring 2021-02-02 19:15 ` Linus Walleij 2021-02-02 19:15 ` Linus Walleij
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