From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers
Date: Wed, 18 Aug 2021 15:16:34 -1000 [thread overview]
Message-ID: <17aa85ef-b5b9-0bf8-dc81-c65b88440c5b@linaro.org> (raw)
In-Reply-To: <CAEUhbmXT-Hbrm6YJMuyBtuQrB3D0wt3pkQHNpPCqB8m0Ek3PFg@mail.gmail.com>
On 8/18/21 12:58 AM, Bin Meng wrote:
>> +static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
>> +{
>> + if (reg_num != 0) {
>> + if (ctx->w) {
>> + tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
>
> What about zero extension?
All of the RV64 word instructions sign-extend the result.
>> void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
>> {
>> - DisasContext ctx;
>> + DisasContext ctx = { };
>
> Why is this change? I believe we should explicitly initialize the ctx
> in riscv_tr_init_disas_context()
I considered it easier to zero-init the whole thing here.
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers
Date: Wed, 18 Aug 2021 15:16:34 -1000 [thread overview]
Message-ID: <17aa85ef-b5b9-0bf8-dc81-c65b88440c5b@linaro.org> (raw)
In-Reply-To: <CAEUhbmXT-Hbrm6YJMuyBtuQrB3D0wt3pkQHNpPCqB8m0Ek3PFg@mail.gmail.com>
On 8/18/21 12:58 AM, Bin Meng wrote:
>> +static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
>> +{
>> + if (reg_num != 0) {
>> + if (ctx->w) {
>> + tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
>
> What about zero extension?
All of the RV64 word instructions sign-extend the result.
>> void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
>> {
>> - DisasContext ctx;
>> + DisasContext ctx = { };
>
> Why is this change? I believe we should explicitly initialize the ctx
> in riscv_tr_init_disas_context()
I considered it easier to zero-init the whole thing here.
r~
next prev parent reply other threads:[~2021-08-19 1:18 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-17 21:17 [PATCH v2 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 01/21] " Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 7:23 ` Bin Meng
2021-08-18 7:23 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 9:20 ` Bin Meng
2021-08-18 9:20 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-18 9:27 ` Bin Meng
2021-08-18 9:27 ` Bin Meng
2021-08-19 6:20 ` Alistair Francis
2021-08-19 6:20 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 10:58 ` Bin Meng
2021-08-18 10:58 ` Bin Meng
2021-08-19 1:16 ` Richard Henderson [this message]
2021-08-19 1:16 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 6:25 ` Alistair Francis
2021-08-19 6:25 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 2:42 ` Bin Meng
2021-08-19 2:42 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 2:43 ` Bin Meng
2021-08-19 2:43 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-19 6:29 ` Alistair Francis
2021-08-19 6:29 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:19 ` Philippe Mathieu-Daudé
2021-08-17 22:19 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:13 ` Bin Meng
2021-08-19 6:13 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:19 ` Bin Meng
2021-08-19 6:19 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:22 ` Bin Meng
2021-08-19 6:22 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 7:08 ` Bin Meng
2021-08-19 7:08 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:18 ` [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 21:18 ` [PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-17 21:18 ` Richard Henderson
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