From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v2 06/21] target/riscv: Remove gen_arith_div*
Date: Thu, 19 Aug 2021 16:28:47 +1000 [thread overview]
Message-ID: <CAKmqyKPMcXJ5KxPG4xu+sJD8hHW3_oKtgh8N40+1eoWSOFeygQ@mail.gmail.com> (raw)
In-Reply-To: <20210817211803.283639-7-richard.henderson@linaro.org>
On Wed, Aug 18, 2021 at 7:21 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use ctx->w and the enhanced gen_arith function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 42 -------------------------
> target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++-----
> 2 files changed, 8 insertions(+), 50 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4819682bf1..e337dca01b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -491,48 +491,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
> return true;
> }
>
> -static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
> - void(*func)(TCGv, TCGv, TCGv))
> -{
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> -
> - gen_get_gpr(ctx, source1, a->rs1);
> - gen_get_gpr(ctx, source2, a->rs2);
> - tcg_gen_ext32s_tl(source1, source1);
> - tcg_gen_ext32s_tl(source2, source2);
> -
> - (*func)(source1, source1, source2);
> -
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(ctx, a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> -}
> -
> -static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
> - void(*func)(TCGv, TCGv, TCGv))
> -{
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> -
> - gen_get_gpr(ctx, source1, a->rs1);
> - gen_get_gpr(ctx, source2, a->rs2);
> - tcg_gen_ext32u_tl(source1, source1);
> - tcg_gen_ext32u_tl(source2, source2);
> -
> - (*func)(source1, source1, source2);
> -
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(ctx, a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> -}
> -
> static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> {
> tcg_gen_deposit_tl(ret, arg1, arg2,
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index 013b3f7009..3d93b24c25 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_w(ctx, a, &gen_div);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_SIGN, gen_div);
> }
>
> static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_uw(ctx, a, &gen_divu);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_ZERO, gen_divu);
> }
>
> static bool trans_remw(DisasContext *ctx, arg_remw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_w(ctx, a, &gen_rem);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_SIGN, gen_rem);
> }
>
> static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_uw(ctx, a, &gen_remu);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_ZERO, gen_remu);
> }
> --
> 2.25.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v2 06/21] target/riscv: Remove gen_arith_div*
Date: Thu, 19 Aug 2021 16:28:47 +1000 [thread overview]
Message-ID: <CAKmqyKPMcXJ5KxPG4xu+sJD8hHW3_oKtgh8N40+1eoWSOFeygQ@mail.gmail.com> (raw)
In-Reply-To: <20210817211803.283639-7-richard.henderson@linaro.org>
On Wed, Aug 18, 2021 at 7:21 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use ctx->w and the enhanced gen_arith function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 42 -------------------------
> target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++-----
> 2 files changed, 8 insertions(+), 50 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4819682bf1..e337dca01b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -491,48 +491,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
> return true;
> }
>
> -static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
> - void(*func)(TCGv, TCGv, TCGv))
> -{
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> -
> - gen_get_gpr(ctx, source1, a->rs1);
> - gen_get_gpr(ctx, source2, a->rs2);
> - tcg_gen_ext32s_tl(source1, source1);
> - tcg_gen_ext32s_tl(source2, source2);
> -
> - (*func)(source1, source1, source2);
> -
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(ctx, a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> -}
> -
> -static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
> - void(*func)(TCGv, TCGv, TCGv))
> -{
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> -
> - gen_get_gpr(ctx, source1, a->rs1);
> - gen_get_gpr(ctx, source2, a->rs2);
> - tcg_gen_ext32u_tl(source1, source1);
> - tcg_gen_ext32u_tl(source2, source2);
> -
> - (*func)(source1, source1, source2);
> -
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(ctx, a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> -}
> -
> static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> {
> tcg_gen_deposit_tl(ret, arg1, arg2,
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index 013b3f7009..3d93b24c25 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_w(ctx, a, &gen_div);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_SIGN, gen_div);
> }
>
> static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_uw(ctx, a, &gen_divu);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_ZERO, gen_divu);
> }
>
> static bool trans_remw(DisasContext *ctx, arg_remw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_w(ctx, a, &gen_rem);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_SIGN, gen_rem);
> }
>
> static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> -
> - return gen_arith_div_uw(ctx, a, &gen_remu);
> + ctx->w = true;
> + return gen_arith(ctx, a, EXT_ZERO, gen_remu);
> }
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-08-19 6:30 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-17 21:17 [PATCH v2 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 01/21] " Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 7:23 ` Bin Meng
2021-08-18 7:23 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 9:20 ` Bin Meng
2021-08-18 9:20 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-18 9:27 ` Bin Meng
2021-08-18 9:27 ` Bin Meng
2021-08-19 6:20 ` Alistair Francis
2021-08-19 6:20 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-18 10:58 ` Bin Meng
2021-08-18 10:58 ` Bin Meng
2021-08-19 1:16 ` Richard Henderson
2021-08-19 1:16 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 6:25 ` Alistair Francis
2021-08-19 6:25 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 2:42 ` Bin Meng
2021-08-19 2:42 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 2:43 ` Bin Meng
2021-08-19 2:43 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis [this message]
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-19 6:29 ` Alistair Francis
2021-08-19 6:29 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:19 ` Philippe Mathieu-Daudé
2021-08-17 22:19 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:13 ` Bin Meng
2021-08-19 6:13 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:17 ` [PATCH v2 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:19 ` Bin Meng
2021-08-19 6:19 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 6:22 ` Bin Meng
2021-08-19 6:22 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 7:08 ` Bin Meng
2021-08-19 7:08 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-17 21:17 ` Richard Henderson
2021-08-17 21:18 ` [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-17 21:18 ` Richard Henderson
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 21:18 ` [PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-17 21:18 ` Richard Henderson
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