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From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
Date: Fri, 09 Sep 2016 12:12:26 +0000	[thread overview]
Message-ID: <1868022.yBeGKSLdet@avalon> (raw)
In-Reply-To: <1473421394-9745-7-git-send-email-bd-phuc@jinso.co.jp>

Hi Bui Duc,

Thank you for the patch.

On Friday 09 Sep 2016 20:43:12 bd-phuc@jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> 
> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings.
> 
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
>  drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
> index 103c493..1542aef 100644
> --- a/drivers/clocksource/sh_cmt.c
> +++ b/drivers/clocksource/sh_cmt.c
> @@ -69,6 +69,7 @@ enum sh_cmt_model {
>  	SH_CMT_32BIT_FAST,
>  	SH_CMT_48BIT,
>  	SH_CMT_48BIT_GEN2,
> +	SH_CMT_48BIT_GEN3,
>  };
> 
>  struct sh_cmt_info {
> @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = {
>  		.read_count = sh_cmt_read32,
>  		.write_count = sh_cmt_write32,
>  	},
> +	[SH_CMT_48BIT_GEN3] = {
> +		.model = SH_CMT_48BIT_GEN3,
> +		.width = 32,
> +		.overflow_bit = SH_CMT32_CMCSR_CMF,
> +		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
> +		.read_control = sh_cmt_read32,
> +		.write_control = sh_cmt_write32,
> +		.read_count = sh_cmt_read32,
> +		.write_count = sh_cmt_write32,
> +	},
>  };
> 
>  #define CMCSR 0 /* channel register */
> @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->cmt = cmt;
>  	ch->index = index;
>  	ch->hwidx = hwidx;
> +	ch->timer_bit = hwidx;
> 
>  	/*
>  	 * Compute the address of the channel control register block. For the
> @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, case SH_CMT_48BIT_GEN2:
>  		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
>  		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
> +		break;
> +	case SH_CMT_48BIT_GEN3:
> +		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
> +		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
>  		break;
>  	}
> 
> @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->match_value = ch->max_match_value;
>  	raw_spin_lock_init(&ch->lock);
> 
> -	ch->timer_bit = cmt->info->model = SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
> -
>  	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
>  			      clockevent, clocksource);
>  	if (ret) {
> @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[]
> __maybe_unused = {
>  	{ .compatible = "renesas,cmt-32-fast", .data > &sh_cmt_info[SH_CMT_32BIT_FAST] },
>  	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT]
> },
>  	{ .compatible = "renesas,cmt-48-gen2", .data > &sh_cmt_info[SH_CMT_48BIT_GEN2] },
> +	{ .compatible = "renesas,cmt-48-gen3", .data > &sh_cmt_info[SH_CMT_48BIT_GEN3] },

Given that the Gen2 and Gen3 CMT seem identical based on the above code, how 
about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above 
changes.

>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sh_cmt_of_table);

-- 
Regards,

Laurent Pinchart


WARNING: multiple messages have this Message-ID
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: bd-phuc@jinso.co.jp
Cc: daniel.lezcano@linaro.org, tglx@linutronix.de,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-sh@vger.kernel.org, geert+renesas@glider.be,
	linux-renesas-soc@vger.kernel.org,
	linux-arm-kernel@vger.kernel.org,
	laurent.pinchart+renesas@ideasonboard.com, magnus.damm@gmail.com,
	horms@verge.net.au, kuninori.morimoto.gx@renesas.com,
	yoshihiro.shimoda.uh@renesas.com, ryusuke.sakato.bx@renesas.com,
	h-inayoshi@jinso.co.jp, cm-hiep@jinso.co.jp, nv-dung@jinso.co.jp
Subject: Re: [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
Date: Fri, 09 Sep 2016 15:12:26 +0300	[thread overview]
Message-ID: <1868022.yBeGKSLdet@avalon> (raw)
In-Reply-To: <1473421394-9745-7-git-send-email-bd-phuc@jinso.co.jp>

Hi Bui Duc,

Thank you for the patch.

On Friday 09 Sep 2016 20:43:12 bd-phuc@jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> 
> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings.
> 
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
>  drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
> index 103c493..1542aef 100644
> --- a/drivers/clocksource/sh_cmt.c
> +++ b/drivers/clocksource/sh_cmt.c
> @@ -69,6 +69,7 @@ enum sh_cmt_model {
>  	SH_CMT_32BIT_FAST,
>  	SH_CMT_48BIT,
>  	SH_CMT_48BIT_GEN2,
> +	SH_CMT_48BIT_GEN3,
>  };
> 
>  struct sh_cmt_info {
> @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = {
>  		.read_count = sh_cmt_read32,
>  		.write_count = sh_cmt_write32,
>  	},
> +	[SH_CMT_48BIT_GEN3] = {
> +		.model = SH_CMT_48BIT_GEN3,
> +		.width = 32,
> +		.overflow_bit = SH_CMT32_CMCSR_CMF,
> +		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
> +		.read_control = sh_cmt_read32,
> +		.write_control = sh_cmt_write32,
> +		.read_count = sh_cmt_read32,
> +		.write_count = sh_cmt_write32,
> +	},
>  };
> 
>  #define CMCSR 0 /* channel register */
> @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->cmt = cmt;
>  	ch->index = index;
>  	ch->hwidx = hwidx;
> +	ch->timer_bit = hwidx;
> 
>  	/*
>  	 * Compute the address of the channel control register block. For the
> @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, case SH_CMT_48BIT_GEN2:
>  		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
>  		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
> +		break;
> +	case SH_CMT_48BIT_GEN3:
> +		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
> +		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
>  		break;
>  	}
> 
> @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->match_value = ch->max_match_value;
>  	raw_spin_lock_init(&ch->lock);
> 
> -	ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
> -
>  	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
>  			      clockevent, clocksource);
>  	if (ret) {
> @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[]
> __maybe_unused = {
>  	{ .compatible = "renesas,cmt-32-fast", .data =
> &sh_cmt_info[SH_CMT_32BIT_FAST] },
>  	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT]
> },
>  	{ .compatible = "renesas,cmt-48-gen2", .data =
> &sh_cmt_info[SH_CMT_48BIT_GEN2] },
> +	{ .compatible = "renesas,cmt-48-gen3", .data =
> &sh_cmt_info[SH_CMT_48BIT_GEN3] },

Given that the Gen2 and Gen3 CMT seem identical based on the above code, how 
about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above 
changes.

>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sh_cmt_of_table);

-- 
Regards,

Laurent Pinchart

WARNING: multiple messages have this Message-ID
From: laurent.pinchart@ideasonboard.com (Laurent Pinchart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
Date: Fri, 09 Sep 2016 15:12:26 +0300	[thread overview]
Message-ID: <1868022.yBeGKSLdet@avalon> (raw)
In-Reply-To: <1473421394-9745-7-git-send-email-bd-phuc@jinso.co.jp>

Hi Bui Duc,

Thank you for the patch.

On Friday 09 Sep 2016 20:43:12 bd-phuc at jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> 
> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings.
> 
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
>  drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
> index 103c493..1542aef 100644
> --- a/drivers/clocksource/sh_cmt.c
> +++ b/drivers/clocksource/sh_cmt.c
> @@ -69,6 +69,7 @@ enum sh_cmt_model {
>  	SH_CMT_32BIT_FAST,
>  	SH_CMT_48BIT,
>  	SH_CMT_48BIT_GEN2,
> +	SH_CMT_48BIT_GEN3,
>  };
> 
>  struct sh_cmt_info {
> @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = {
>  		.read_count = sh_cmt_read32,
>  		.write_count = sh_cmt_write32,
>  	},
> +	[SH_CMT_48BIT_GEN3] = {
> +		.model = SH_CMT_48BIT_GEN3,
> +		.width = 32,
> +		.overflow_bit = SH_CMT32_CMCSR_CMF,
> +		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
> +		.read_control = sh_cmt_read32,
> +		.write_control = sh_cmt_write32,
> +		.read_count = sh_cmt_read32,
> +		.write_count = sh_cmt_write32,
> +	},
>  };
> 
>  #define CMCSR 0 /* channel register */
> @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->cmt = cmt;
>  	ch->index = index;
>  	ch->hwidx = hwidx;
> +	ch->timer_bit = hwidx;
> 
>  	/*
>  	 * Compute the address of the channel control register block. For the
> @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, case SH_CMT_48BIT_GEN2:
>  		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
>  		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
> +		break;
> +	case SH_CMT_48BIT_GEN3:
> +		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
> +		ch->ioctrl = ch->iostart + 0x10;
> +		ch->timer_bit = 0;
>  		break;
>  	}
> 
> @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel
> *ch, unsigned int index, ch->match_value = ch->max_match_value;
>  	raw_spin_lock_init(&ch->lock);
> 
> -	ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
> -
>  	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
>  			      clockevent, clocksource);
>  	if (ret) {
> @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[]
> __maybe_unused = {
>  	{ .compatible = "renesas,cmt-32-fast", .data =
> &sh_cmt_info[SH_CMT_32BIT_FAST] },
>  	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT]
> },
>  	{ .compatible = "renesas,cmt-48-gen2", .data =
> &sh_cmt_info[SH_CMT_48BIT_GEN2] },
> +	{ .compatible = "renesas,cmt-48-gen3", .data =
> &sh_cmt_info[SH_CMT_48BIT_GEN3] },

Given that the Gen2 and Gen3 CMT seem identical based on the above code, how 
about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above 
changes.

>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sh_cmt_of_table);

-- 
Regards,

Laurent Pinchart

  reply	other threads:[~2016-09-09 12:12 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-09 11:43 [PATCH 0/8] clocksource: sh_cmt: Add R-car Gen3 CMT0/1 support bd-phuc
2016-09-09 11:43 ` bd-phuc at jinso.co.jp
2016-09-09 11:43 ` bd-phuc
2016-09-09 11:43 ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 11:43 ` [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 12:07   ` Geert Uytterhoeven
2016-09-09 12:07     ` Geert Uytterhoeven
2016-09-09 12:07     ` Geert Uytterhoeven
2016-09-09 12:07     ` Geert Uytterhoeven
2016-09-12 15:12     ` Bui Duc Phuc
2016-09-12 15:12       ` Bui Duc Phuc
2016-09-12 15:12       ` Bui Duc Phuc
2016-09-12 15:12       ` Bui Duc Phuc
2016-09-09 11:43 ` [PATCH 2/8] ARM64: dts: r8a7795: Add CMT device to DT bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 11:43 ` [PATCH 3/8] ARM64: dts: r8a7796: " bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 11:43 ` [PATCH 4/8] clk: renesas: r8a7795: Add CMT clocks bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-12  8:31   ` Geert Uytterhoeven
2016-09-12  8:31     ` Geert Uytterhoeven
2016-09-12  8:31     ` Geert Uytterhoeven
2016-09-12  8:31     ` Geert Uytterhoeven
2016-09-12 14:57     ` Bui Duc Phuc
2016-09-12 14:57       ` Bui Duc Phuc
2016-09-12 14:57       ` Bui Duc Phuc
2016-09-12 14:57       ` Bui Duc Phuc
2016-09-09 11:43 ` [PATCH 5/8] clk: renesas: r8a7796: " bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-12  8:35   ` Geert Uytterhoeven
2016-09-12  8:35     ` Geert Uytterhoeven
2016-09-12  8:35     ` Geert Uytterhoeven
2016-09-12  8:35     ` Geert Uytterhoeven
2016-09-12 15:00     ` Bui Duc Phuc
2016-09-12 15:00       ` Bui Duc Phuc
2016-09-12 15:00       ` Bui Duc Phuc
2016-09-12 15:00       ` Bui Duc Phuc
2016-09-09 11:43 ` [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 12:12   ` Laurent Pinchart [this message]
2016-09-09 12:12     ` Laurent Pinchart
2016-09-09 12:12     ` Laurent Pinchart
2016-09-09 11:43 ` [PATCH 7/8] clocksource: Kconfig: Modify CMT config support 64bit bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q
2016-09-09 11:47   ` Sergei Shtylyov
2016-09-09 11:47     ` Sergei Shtylyov
2016-09-09 11:47     ` Sergei Shtylyov
2016-09-09 11:47     ` Sergei Shtylyov
2016-09-09  3:06     ` Bui Duc Phuc
2016-09-09  3:06       ` Bui Duc Phuc
2016-09-09  3:06       ` Bui Duc Phuc
2016-09-09 12:08   ` Laurent Pinchart
2016-09-09 12:08     ` Laurent Pinchart
2016-09-09 12:08     ` Laurent Pinchart
2016-09-12  0:25     ` Bui Duc Phuc
2016-09-12  0:25       ` Bui Duc Phuc
2016-09-12  0:25       ` Bui Duc Phuc
2016-09-09 11:43 ` [PATCH 8/8] ARM64: defconfig: Enable SH_TIMER_CMT config option bd-phuc
2016-09-09 11:43   ` bd-phuc at jinso.co.jp
2016-09-09 11:43   ` bd-phuc
2016-09-09 11:43   ` bd-phuc-HEF513clHfp3+QwDJ9on6Q

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