* [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 9:06 ` Kieran Bingham
2021-06-23 3:46 ` [RFC PATCH 02/15] drm: rcar-du: Add R-Car DSI driver Laurent Pinchart
` (15 subsequent siblings)
16 siblings, 1 reply; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It
can operate in either DSI or CSI-2 mode, with up to four data lanes.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
.../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
new file mode 100644
index 000000000000..7e1b606a65ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car MIPI DSI/CSI-2 Encoder
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
+ R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
+ to four data lanes.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a779a0-dsi-csi2-tx # for V3U
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Functional clock
+ - description: DSI (and CSI-2) functional clock
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: fck
+ - const: dsi
+ - const: pll
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Parallel input port
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: DSI/CSI-2 output port
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+ #include <dt-bindings/power/r8a779a0-sysc.h>
+
+ dsi0: dsi-encoder@fed80000 {
+ compatible = "renesas,r8a779a0-dsi-csi2-tx";
+ reg = <0xfed80000 0x10000>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ clocks = <&cpg CPG_MOD 415>,
+ <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "fck", "dsi", "pll";
+ resets = <&cpg 415>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&du_out_dsi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <&sn65dsi86_in>;
+ };
+ };
+ };
+ };
+...
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
2021-06-23 3:46 ` [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX Laurent Pinchart
@ 2021-06-23 9:06 ` Kieran Bingham
2021-06-23 13:06 ` Laurent Pinchart
2021-06-23 13:12 ` Geert Uytterhoeven
0 siblings, 2 replies; 23+ messages in thread
From: Kieran Bingham @ 2021-06-23 9:06 UTC (permalink / raw)
To: Laurent Pinchart, linux-renesas-soc; +Cc: LUU HOAI
Hi Laurent,
On 23/06/2021 04:46, Laurent Pinchart wrote:
> The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It
> can operate in either DSI or CSI-2 mode, with up to four data lanes.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++
> 1 file changed, 118 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> new file mode 100644
> index 000000000000..7e1b606a65ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> @@ -0,0 +1,118 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car MIPI DSI/CSI-2 Encoder
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
> + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
> + to four data lanes.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r8a779a0-dsi-csi2-tx # for V3U
Only a potential nit ...
Is it worth moving the "# for V3U" over a bit to allow for extended
compatibles in the future without re-aligning the table?
Looks like 37 chars before it currently, it could at least move to
position 40.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Functional clock
> + - description: DSI (and CSI-2) functional clock
> + - description: PLL reference clock
> +
> + clock-names:
> + items:
> + - const: fck
> + - const: dsi
> + - const: pll
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Parallel input port
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: DSI/CSI-2 output port
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> + - resets
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
> + #include <dt-bindings/power/r8a779a0-sysc.h>
> +
> + dsi0: dsi-encoder@fed80000 {
> + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> + reg = <0xfed80000 0x10000>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 415>,
> + <&cpg CPG_CORE R8A779A0_CLK_DSI>,
> + <&cpg CPG_CORE R8A779A0_CLK_CP>;
> + clock-names = "fck", "dsi", "pll";
is the CP/PLL clock actually needed?
I don't see any other gen3 peripheral referencing it.
Is it expected to be required for calculations in the DSI encoder?
Otherwise,
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> + resets = <&cpg 415>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&du_out_dsi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + data-lanes = <1 2>;
> + remote-endpoint = <&sn65dsi86_in>;
> + };
> + };
> + };
> + };
> +...
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
2021-06-23 9:06 ` Kieran Bingham
@ 2021-06-23 13:06 ` Laurent Pinchart
2021-06-23 13:12 ` Geert Uytterhoeven
1 sibling, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 13:06 UTC (permalink / raw)
To: Kieran Bingham; +Cc: linux-renesas-soc, LUU HOAI
On Wed, Jun 23, 2021 at 10:06:37AM +0100, Kieran Bingham wrote:
> Hi Laurent,
>
> On 23/06/2021 04:46, Laurent Pinchart wrote:
> > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It
> > can operate in either DSI or CSI-2 mode, with up to four data lanes.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++
> > 1 file changed, 118 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> > new file mode 100644
> > index 000000000000..7e1b606a65ea
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> > @@ -0,0 +1,118 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder
> > +
> > +maintainers:
> > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > +
> > +description: |
> > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
> > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
> > + to four data lanes.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,r8a779a0-dsi-csi2-tx # for V3U
>
> Only a potential nit ...
>
> Is it worth moving the "# for V3U" over a bit to allow for extended
> compatibles in the future without re-aligning the table?
>
> Looks like 37 chars before it currently, it could at least move to
> position 40.
If that's all it requires to make you happy, no problem :-)
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Functional clock
> > + - description: DSI (and CSI-2) functional clock
> > + - description: PLL reference clock
> > +
> > + clock-names:
> > + items:
> > + - const: fck
> > + - const: dsi
> > + - const: pll
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: Parallel input port
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: DSI/CSI-2 output port
> > +
> > + properties:
> > + endpoint:
> > + $ref: /schemas/media/video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + required:
> > + - data-lanes
> > +
> > + required:
> > + - port@0
> > + - port@1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - power-domains
> > + - resets
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
> > + #include <dt-bindings/power/r8a779a0-sysc.h>
> > +
> > + dsi0: dsi-encoder@fed80000 {
> > + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> > + reg = <0xfed80000 0x10000>;
> > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> > + clocks = <&cpg CPG_MOD 415>,
> > + <&cpg CPG_CORE R8A779A0_CLK_DSI>,
> > + <&cpg CPG_CORE R8A779A0_CLK_CP>;
> > + clock-names = "fck", "dsi", "pll";
>
> is the CP/PLL clock actually needed?
>
> I don't see any other gen3 peripheral referencing it.
>
> Is it expected to be required for calculations in the DSI encoder?
It's listed in the datasheet as the DSI PLL input clock. The driver
still uses the old "extal" name though, which I'll fix.
> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> > + resets = <&cpg 415>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dsi0_in: endpoint {
> > + remote-endpoint = <&du_out_dsi0>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + dsi0_out: endpoint {
> > + data-lanes = <1 2>;
> > + remote-endpoint = <&sn65dsi86_in>;
> > + };
> > + };
> > + };
> > + };
> > +...
> >
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
2021-06-23 9:06 ` Kieran Bingham
2021-06-23 13:06 ` Laurent Pinchart
@ 2021-06-23 13:12 ` Geert Uytterhoeven
2021-06-23 14:36 ` Kieran Bingham
1 sibling, 1 reply; 23+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 13:12 UTC (permalink / raw)
To: Kieran Bingham; +Cc: Laurent Pinchart, Linux-Renesas, LUU HOAI
Hi Kieran,
On Wed, Jun 23, 2021 at 11:06 AM Kieran Bingham
<kieran.bingham@ideasonboard.com> wrote:
> On 23/06/2021 04:46, Laurent Pinchart wrote:
> > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It
> > can operate in either DSI or CSI-2 mode, with up to four data lanes.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++
> > 1 file changed, 118 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> > new file mode 100644
> > index 000000000000..7e1b606a65ea
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> > @@ -0,0 +1,118 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder
> > +
> > +maintainers:
> > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > +
> > +description: |
> > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
> > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
> > + to four data lanes.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,r8a779a0-dsi-csi2-tx # for V3U
>
> Only a potential nit ...
>
> Is it worth moving the "# for V3U" over a bit to allow for extended
> compatibles in the future without re-aligning the table?
>
> Looks like 37 chars before it currently, it could at least move to
> position 40.
Happy predicting the future ;-)
Did you take into account adding items and/or oneOf, which will
impact alignment, too?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
2021-06-23 13:12 ` Geert Uytterhoeven
@ 2021-06-23 14:36 ` Kieran Bingham
0 siblings, 0 replies; 23+ messages in thread
From: Kieran Bingham @ 2021-06-23 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Laurent Pinchart, Linux-Renesas, LUU HOAI
On 23/06/2021 14:12, Geert Uytterhoeven wrote:
> Hi Kieran,
>
> On Wed, Jun 23, 2021 at 11:06 AM Kieran Bingham
> <kieran.bingham@ideasonboard.com> wrote:
>> On 23/06/2021 04:46, Laurent Pinchart wrote:
>>> The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It
>>> can operate in either DSI or CSI-2 mode, with up to four data lanes.
>>>
>>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>>> ---
>>> .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++
>>> 1 file changed, 118 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
>>> new file mode 100644
>>> index 000000000000..7e1b606a65ea
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
>>> @@ -0,0 +1,118 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas R-Car MIPI DSI/CSI-2 Encoder
>>> +
>>> +maintainers:
>>> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>>> +
>>> +description: |
>>> + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
>>> + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
>>> + to four data lanes.
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - renesas,r8a779a0-dsi-csi2-tx # for V3U
>>
>> Only a potential nit ...
>>
>> Is it worth moving the "# for V3U" over a bit to allow for extended
>> compatibles in the future without re-aligning the table?
>>
>> Looks like 37 chars before it currently, it could at least move to
>> position 40.
>
> Happy predicting the future ;-)
>
> Did you take into account adding items and/or oneOf, which will
> impact alignment, too?
Maybe it should be way over at 60 chars then ;-)
Not a big issue, I don't mind either way, I'd just indent a little to
try to save when someone adds small updates that then requires a big
table change.
Ps. .. the lottery numbers this week are ...
> Gr{oetje,eeting}s,
>
> Geert
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RFC PATCH 02/15] drm: rcar-du: Add R-Car DSI driver
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 03/15] drm: rcar-du: dsi: Use the correct compatible Laurent Pinchart
` (14 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
From: LUU HOAI <hoai.luu.ub@renesas.com>
The driver supports the MIPI DSI/CSI-2 TX encoder found in the R-Car V3U
SoC. It currently supports DSI mode only.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/Kconfig | 6 +
drivers/gpu/drm/rcar-du/Makefile | 1 +
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 896 +++++++++++++++++++
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h | 26 +
drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h | 172 ++++
5 files changed, 1101 insertions(+)
create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index b47e74421e34..8cb94fe90639 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -38,6 +38,12 @@ config DRM_RCAR_LVDS
help
Enable support for the R-Car Display Unit embedded LVDS encoders.
+config DRM_RCAR_MIPI_DSI
+ tristate "R-Car DU MIPI DSI Encoder Support"
+ depends on DRM && DRM_BRIDGE && OF
+ help
+ Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
+
config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 4d1187ccc3e5..adc1b49d02cf 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
obj-$(CONFIG_DRM_RCAR_LVDS) += rcar_lvds.o
+obj-$(CONFIG_DRM_RCAR_MIPI_DSI) += rcar_mipi_dsi.o
# 'remote-endpoint' is fixed up at run-time
DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
new file mode 100644
index 000000000000..ef2a9b283b4e
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -0,0 +1,896 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rcar_mipi_dsi.c -- R-Car MIPI DSI Encoder
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+#include "rcar_mipi_dsi_regs.h"
+
+struct rcar_mipi_dsi {
+ struct device *dev;
+ const struct rcar_mipi_dsi_device_info *info;
+ struct reset_control *rstc;
+
+ struct mipi_dsi_host host;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_connector connector;
+
+ void __iomem *mmio;
+ struct {
+ struct clk *mod;
+ struct clk *extal;
+ struct clk *dsi;
+ } clocks;
+
+ struct drm_display_mode display_mode;
+ enum mipi_dsi_pixel_format format;
+ unsigned int num_data_lanes;
+ unsigned int lanes;
+};
+
+#define bridge_to_rcar_mipi_dsi(b) \
+ container_of(b, struct rcar_mipi_dsi, bridge)
+
+#define connector_to_rcar_mipi_dsi(c) \
+ container_of(c, struct rcar_mipi_dsi, connector)
+
+#define host_to_rcar_mipi_dsi(c) \
+ container_of(c, struct rcar_mipi_dsi, host)
+
+static const u32 phtw[] = {
+ 0x01020114, 0x01600115, /* General testing */
+ 0x01030116, 0x0102011d, /* General testing */
+ 0x011101a4, 0x018601a4, /* 1Gbps testing */
+ 0x014201a0, 0x010001a3, /* 1Gbps testing */
+ 0x0101011f, /* 1Gbps testing */
+};
+
+static const u32 phtw2[] = {
+ 0x010c0130, 0x010c0140, /* General testing */
+ 0x010c0150, 0x010c0180, /* General testing */
+ 0x010c0190,
+ 0x010a0160, 0x010a0170,
+ 0x01800164, 0x01800174, /* 1Gbps testing */
+};
+
+static const u32 hsfreqrange_table[][2] = {
+ {80000000, 0x00}, {90000000, 0x10}, {100000000, 0x20},
+ {110000000, 0x30}, {120000000, 0x01}, {130000000, 0x11},
+ {140000000, 0x21}, {150000000, 0x31}, {160000000, 0x02},
+ {170000000, 0x12}, {180000000, 0x22}, {190000000, 0x32},
+ {205000000, 0x03}, {220000000, 0x13}, {235000000, 0x23},
+ {250000000, 0x33}, {275000000, 0x04}, {300000000, 0x14},
+ {325000000, 0x25}, {350000000, 0x35}, {400000000, 0x05},
+ {450000000, 0x16}, {500000000, 0x26}, {550000000, 0x37},
+ {600000000, 0x07}, {650000000, 0x18}, {700000000, 0x28},
+ {750000000, 0x39}, {800000000, 0x09}, {850000000, 0x19},
+ {900000000, 0x29}, {950000000, 0x3a}, {1000000000, 0x0a},
+ {1050000000, 0x1a}, {1100000000, 0x2a}, {1150000000, 0x3b},
+ {1200000000, 0x0b}, {1250000000, 0x1b}, {1300000000, 0x2b},
+ {1350000000, 0x3c}, {1400000000, 0x0c}, {1450000000, 0x1c},
+ {1500000000, 0x2c}, {1550000000, 0x3d}, {1600000000, 0x0d},
+ {1650000000, 0x1d}, {1700000000, 0x2e}, {1750000000, 0x3e},
+ {1800000000, 0x0e}, {1850000000, 0x1e}, {1900000000, 0x2f},
+ {1950000000, 0x3f}, {2000000000, 0x0f}, {2050000000, 0x40},
+ {2100000000, 0x41}, {2150000000, 0x42}, {2200000000, 0x43},
+ {2250000000, 0x44}, {2300000000, 0x45}, {2350000000, 0x46},
+ {2400000000, 0x47}, {2450000000, 0x48}, {2500000000, 0x49},
+ { /* sentinel */ },
+};
+
+struct vco_cntrl_value {
+ u32 min_freq;
+ u32 max_freq;
+ u16 value;
+};
+
+static const struct vco_cntrl_value vco_cntrl_table[] = {
+ { .min_freq = 40000000, .max_freq = 55000000, .value = 0x3f},
+ { .min_freq = 52500000, .max_freq = 80000000, .value = 0x39},
+ { .min_freq = 80000000, .max_freq = 110000000, .value = 0x2f},
+ { .min_freq = 105000000, .max_freq = 160000000, .value = 0x29},
+ { .min_freq = 160000000, .max_freq = 220000000, .value = 0x1f},
+ { .min_freq = 210000000, .max_freq = 320000000, .value = 0x19},
+ { .min_freq = 320000000, .max_freq = 440000000, .value = 0x0f},
+ { .min_freq = 420000000, .max_freq = 660000000, .value = 0x09},
+ { .min_freq = 630000000, .max_freq = 1149000000, .value = 0x03},
+ { .min_freq = 1100000000, .max_freq = 1152000000, .value = 0x01},
+ { .min_freq = 1150000000, .max_freq = 1250000000, .value = 0x01},
+ { /* sentinel */ },
+};
+
+static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *mipi_dsi,
+ u32 reg, u32 data)
+{
+ iowrite32(data, mipi_dsi->mmio + reg);
+}
+
+static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *mipi_dsi, u32 reg)
+{
+ return ioread32(mipi_dsi->mmio + reg);
+}
+
+static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *mipi_dsi,
+ u32 reg, u32 clr)
+{
+ rcar_mipi_dsi_write(mipi_dsi, reg,
+ rcar_mipi_dsi_read(mipi_dsi, reg) & ~clr);
+}
+
+static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *mipi_dsi,
+ u32 reg, u32 set)
+{
+ rcar_mipi_dsi_write(mipi_dsi, reg,
+ rcar_mipi_dsi_read(mipi_dsi, reg) | set);
+}
+
+static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *mipi_dsi, u32 phtw)
+{
+ unsigned int timeout;
+ u32 status;
+
+ rcar_mipi_dsi_write(mipi_dsi, PHTW, phtw);
+
+ for (timeout = 10; timeout > 0; --timeout) {
+ status = rcar_mipi_dsi_read(mipi_dsi, PHTW);
+ if (!(status & PHTW_DWEN) &&
+ !(status & PHTW_CWEN))
+ break;
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev,
+ "failed to test phtw with data %x\n", phtw);
+ return -ETIMEDOUT;
+ }
+
+ return timeout;
+}
+
+/* -----------------------------------------------------------------------------
+ * Hardware Setup
+ */
+
+struct dsi_setup_info {
+ unsigned int err;
+ u16 vco_cntrl;
+ u16 prop_cntrl;
+ u16 hsfreqrange;
+ u16 div;
+ unsigned int m;
+ unsigned int n;
+};
+
+static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *mipi_dsi,
+ struct clk *clk, unsigned long target,
+ struct dsi_setup_info *setup_info)
+{
+
+ const struct vco_cntrl_value *vco_cntrl;
+ unsigned long fout_target;
+ unsigned long fin, fout;
+ unsigned long hsfreq;
+ unsigned int divider;
+ unsigned int n;
+ unsigned int i;
+ unsigned int err;
+
+ /*
+ * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
+ * The range out Fout is [40 - 1250] Mhz
+ */
+ fout_target = target *
+ mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) /
+ (2 * mipi_dsi->lanes);
+ if (fout_target < 40000000 || fout_target > 1250000000)
+ return;
+
+ /* Find vco_cntrl */
+ for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
+ if (fout_target > vco_cntrl->min_freq &&
+ fout_target <= vco_cntrl->max_freq) {
+ setup_info->vco_cntrl = vco_cntrl->value;
+ if (fout_target >= 1150000000)
+ setup_info->prop_cntrl = 0x0c;
+ else
+ setup_info->prop_cntrl = 0x0b;
+ break;
+ }
+ }
+
+ /* Add divider */
+ setup_info->div = (setup_info->vco_cntrl & 0x30) >> 4;
+
+ /* Find hsfreqrange */
+ hsfreq = fout_target * 2;
+ for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
+ if (hsfreq > hsfreqrange_table[i][0] &&
+ hsfreq <= hsfreqrange_table[i+1][0]) {
+ setup_info->hsfreqrange = hsfreqrange_table[i+1][1];
+ break;
+ }
+ }
+
+ /*
+ * Calculate n and m for PLL clock
+ * Following the HW manual the ranges of n and m are
+ * n = [3-8] and m = [64-625]
+ */
+ fin = clk_get_rate(clk);
+ divider = 1 << setup_info->div;
+ for (n = 3; n < 9; n++) {
+ unsigned long fpfd;
+ unsigned int m;
+
+ fpfd = fin / n;
+
+ for (m = 64; m < 626; m++) {
+ fout = fpfd * m / divider;
+ err = abs((long)(fout - fout_target) * 10000 /
+ (long)fout_target);
+ if (err < setup_info->err) {
+ setup_info->m = m - 2;
+ setup_info->n = n - 1;
+ setup_info->err = err;
+ if (err == 0)
+ goto done;
+ }
+ }
+ }
+
+done:
+ dev_dbg(mipi_dsi->dev,
+ "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
+ clk, fin, fout, fout_target, setup_info->err / 100,
+ setup_info->err % 100, setup_info->m,
+ setup_info->n, setup_info->div);
+ dev_dbg(mipi_dsi->dev,
+ "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
+ setup_info->vco_cntrl,
+ setup_info->prop_cntrl,
+ setup_info->hsfreqrange);
+}
+
+static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *mipi_dsi)
+{
+ struct drm_display_mode *mode = &mipi_dsi->display_mode;
+ u32 setr;
+ u32 vprmset0r;
+ u32 vprmset1r;
+ u32 vprmset2r;
+ u32 vprmset3r;
+ u32 vprmset4r;
+
+ /* Configuration for Pixel Stream and Packet Header */
+ if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 24)
+ rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ TXVMPSPHSETR_DT_RGB24);
+ else if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 18)
+ rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ TXVMPSPHSETR_DT_RGB18);
+ else if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 16)
+ rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ TXVMPSPHSETR_DT_RGB16);
+ else {
+ dev_warn(mipi_dsi->dev, "unsupported format");
+ return;
+ }
+
+ /* Configuration for Blanking sequence and Input Pixel */
+ setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN |
+ TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES |
+ TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
+ rcar_mipi_dsi_write(mipi_dsi, TXVMSETR, setr);
+
+ /* Configuration for Video Parameters */
+ vprmset0r = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ?
+ TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW) |
+ ((mode->flags & DRM_MODE_FLAG_PHSYNC) ?
+ TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW) |
+ TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
+
+ vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay) |
+ TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
+
+ vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay) |
+ TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
+
+ vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay) |
+ TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
+
+ vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay) |
+ TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
+
+ rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET0R, vprmset0r);
+ rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET1R, vprmset1r);
+ rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET2R, vprmset2r);
+ rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET3R, vprmset3r);
+ rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET4R, vprmset4r);
+}
+
+static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *mipi_dsi)
+{
+ struct drm_display_mode *mode = &mipi_dsi->display_mode;
+ struct dsi_setup_info setup_info = {.err = -1 };
+ unsigned int timeout;
+ int ret, i;
+ int dsi_format;
+ u32 phy_setup;
+ u32 clockset2, clockset3;
+ u32 ppisetr;
+ u32 vclkset;
+
+ /* Checking valid format */
+ dsi_format = mipi_dsi_pixel_format_to_bpp(mipi_dsi->format);
+ if (dsi_format < 0) {
+ dev_warn(mipi_dsi->dev, "invalid format");
+ return -EINVAL;
+ }
+
+ /* Parametters Calulation */
+ rcar_mipi_dsi_parametters_calc(mipi_dsi, mipi_dsi->clocks.extal,
+ mode->clock * 1000, &setup_info);
+
+ /* LPCLK enable */
+ rcar_mipi_dsi_set(mipi_dsi, LPCLKSET, LPCLKSET_CKEN);
+
+ /* CFGCLK enabled */
+ rcar_mipi_dsi_set(mipi_dsi, CFGCLKSET, CFGCLKSET_CKEN);
+
+ rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
+ rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+
+ rcar_mipi_dsi_set(mipi_dsi, PHTC, PHTC_TESTCLR);
+ rcar_mipi_dsi_clr(mipi_dsi, PHTC, PHTC_TESTCLR);
+
+ /* PHY setting */
+ phy_setup = rcar_mipi_dsi_read(mipi_dsi, PHYSETUP);
+ phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
+ phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
+ rcar_mipi_dsi_write(mipi_dsi, PHYSETUP, phy_setup);
+
+ for (i = 0; i < ARRAY_SIZE(phtw); i++) {
+ ret = rcar_mipi_dsi_phtw_test(mipi_dsi, phtw[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* PLL Clock Setting */
+ rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+ rcar_mipi_dsi_set(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+ rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+
+ clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n) |
+ CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
+ clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl) |
+ CLOCKSET3_INT_CNTRL(0) |
+ CLOCKSET3_CPBIAS_CNTRL(0x10) |
+ CLOCKSET3_GMP_CNTRL(1);
+ rcar_mipi_dsi_write(mipi_dsi, CLOCKSET2, clockset2);
+ rcar_mipi_dsi_write(mipi_dsi, CLOCKSET3, clockset3);
+
+ rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+ rcar_mipi_dsi_set(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+ udelay(10);
+ rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+
+ ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
+ rcar_mipi_dsi_write(mipi_dsi, PPISETR, ppisetr);
+
+ rcar_mipi_dsi_set(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+ rcar_mipi_dsi_set(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
+ usleep_range(400, 500);
+
+ /* Checking PPI clock status register */
+ for (timeout = 10; timeout > 0; --timeout) {
+ if ((rcar_mipi_dsi_read(mipi_dsi, PPICLSR) & PPICLSR_STPST) &&
+ (rcar_mipi_dsi_read(mipi_dsi, PPIDLSR) & PPIDLSR_STPST) &&
+ (rcar_mipi_dsi_read(mipi_dsi, CLOCKSET1) & CLOCKSET1_LOCK))
+ break;
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev, "failed to enable PPI clock\n");
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
+ ret = rcar_mipi_dsi_phtw_test(mipi_dsi, phtw2[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Enable DOT clock */
+ vclkset = VCLKSET_CKEN;
+ rcar_mipi_dsi_set(mipi_dsi, VCLKSET, vclkset);
+
+ if (dsi_format == 24)
+ vclkset |= VCLKSET_BPP_24;
+ else if (dsi_format == 18)
+ vclkset |= VCLKSET_BPP_18;
+ else if (dsi_format == 16)
+ vclkset |= VCLKSET_BPP_16;
+ else {
+ dev_warn(mipi_dsi->dev, "unsupported format");
+ return -EINVAL;
+ }
+ vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div) |
+ VCLKSET_LANE(mipi_dsi->lanes - 1);
+
+ rcar_mipi_dsi_set(mipi_dsi, VCLKSET, vclkset);
+
+ /* After setting VCLKSET register, enable VCLKEN */
+ rcar_mipi_dsi_set(mipi_dsi, VCLKEN, VCLKEN_CKEN);
+
+ dev_dbg(mipi_dsi->dev, "DSI device is started\n");
+
+ return 0;
+}
+
+static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *mipi_dsi)
+{
+ rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
+ rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+
+ dev_dbg(mipi_dsi->dev, "DSI device is shutdown\n");
+}
+
+static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *mipi_dsi)
+{
+ /*
+ * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
+ * write how to check. So we skip this check in this patch
+ */
+ unsigned int timeout;
+ u32 status;
+
+ /* Start HS clock */
+ rcar_mipi_dsi_set(mipi_dsi, PPICLCR, PPICLCR_TXREQHS);
+
+ for (timeout = 10; timeout > 0; --timeout) {
+ status = rcar_mipi_dsi_read(mipi_dsi, PPICLSR);
+
+ if (status & PPICLSR_TOHS) {
+ rcar_mipi_dsi_set(mipi_dsi, PPICLSCR, PPICLSCR_TOHS);
+ break;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev, "failed to enable HS clock\n");
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(mipi_dsi->dev, "Start High Speed Clock");
+
+ return 0;
+}
+
+static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
+{
+ unsigned int timeout;
+ u32 status;
+
+ /* Check status of Tranmission */
+ for (timeout = 10; timeout > 0; --timeout) {
+ status = rcar_mipi_dsi_read(mipi_dsi, LINKSR);
+ if (!(status & LINKSR_LPBUSY) &&
+ !(status & LINKSR_HSBUSY)) {
+ rcar_mipi_dsi_clr(mipi_dsi, TXVMCR, TXVMCR_VFCLR);
+ break;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Check Clear Video mode FIFO */
+ for (timeout = 10; timeout > 0; --timeout) {
+ status = rcar_mipi_dsi_read(mipi_dsi, TXVMSR);
+ if (status & TXVMSR_VFRDY) {
+ rcar_mipi_dsi_set(mipi_dsi, TXVMCR, TXVMCR_EN_VIDEO);
+ break;
+ }
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Check Video transmission */
+ for (timeout = 10; timeout > 0; --timeout) {
+ status = rcar_mipi_dsi_read(mipi_dsi, TXVMSR);
+ if (status & TXVMSR_RDY)
+ break;
+
+ usleep_range(1000, 2000);
+ }
+
+ if (!timeout) {
+ dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(mipi_dsi->dev, "Start video transferring");
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Bridge
+ */
+
+static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+
+ return drm_bridge_attach(bridge->encoder, mipi_dsi->next_bridge, bridge,
+ flags);
+}
+
+static void rcar_mipi_dsi_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+
+ mipi_dsi->display_mode = *adjusted_mode;
+}
+
+static void rcar_mipi_dsi_enable(struct drm_bridge *bridge)
+{
+ struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ int ret;
+
+ rcar_mipi_dsi_set_display_timing(mipi_dsi);
+
+ ret = rcar_mipi_dsi_start_hs_clock(mipi_dsi);
+ if (ret < 0)
+ return;
+
+ ret = rcar_mipi_dsi_start_video(mipi_dsi);
+ if (ret < 0)
+ return;
+
+}
+
+static enum drm_mode_status
+rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock > 297000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
+ .attach = rcar_mipi_dsi_attach,
+ .mode_set = rcar_mipi_dsi_mode_set,
+ .enable = rcar_mipi_dsi_enable,
+ .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
+};
+
+/* -----------------------------------------------------------------------------
+ * Clock Setting
+ */
+
+int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
+{
+ struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ int ret;
+
+ reset_control_deassert(mipi_dsi->rstc);
+
+ ret = clk_prepare_enable(mipi_dsi->clocks.mod);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(mipi_dsi->clocks.dsi);
+ if (ret < 0)
+ return ret;
+
+ ret = rcar_mipi_dsi_startup(mipi_dsi);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_enable);
+
+void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge)
+{
+ struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+
+ rcar_mipi_dsi_shutdown(mipi_dsi);
+
+ /* Disable DSI clock and reset HW */
+ clk_disable_unprepare(mipi_dsi->clocks.dsi);
+
+ clk_disable_unprepare(mipi_dsi->clocks.mod);
+
+ reset_control_assert(mipi_dsi->rstc);
+}
+EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_disable);
+
+/* -----------------------------------------------------------------------------
+ * Host setting
+ */
+
+static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *device)
+{
+ struct rcar_mipi_dsi *mipi_dsi = host_to_rcar_mipi_dsi(host);
+
+ if (device->lanes > mipi_dsi->num_data_lanes)
+ return -EINVAL;
+
+ mipi_dsi->lanes = device->lanes;
+ mipi_dsi->format = device->format;
+
+ return 0;
+}
+
+static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *device)
+{
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
+ .attach = rcar_mipi_dsi_host_attach,
+ .detach = rcar_mipi_dsi_host_detach,
+};
+
+/* -----------------------------------------------------------------------------
+ * Probe & Remove
+ */
+
+static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
+{
+ struct device_node *local_output = NULL;
+ struct device_node *remote_input = NULL;
+ struct device_node *remote = NULL;
+ struct device_node *node;
+ struct property *prop;
+ bool is_bridge = false;
+ int ret = 0;
+ int len, num_lanes;
+
+ local_output = of_graph_get_endpoint_by_regs(mipi_dsi->dev->of_node,
+ 1, 0);
+ if (!local_output) {
+ dev_dbg(mipi_dsi->dev, "unconnected port@1\n");
+ ret = -ENODEV;
+ goto done;
+ }
+
+ /*
+ * Locate the connected entity and
+ * infer its type from the number of endpoints.
+ */
+ remote = of_graph_get_remote_port_parent(local_output);
+ if (!remote) {
+ dev_dbg(mipi_dsi->dev, "unconnected endpoint %pOF\n",
+ local_output);
+ ret = -ENODEV;
+ goto done;
+ }
+
+ if (!of_device_is_available(remote)) {
+ dev_dbg(mipi_dsi->dev, "connected entity %pOF is disabled\n",
+ remote);
+ ret = -ENODEV;
+ goto done;
+ }
+
+ remote_input = of_graph_get_remote_endpoint(local_output);
+
+ for_each_endpoint_of_node(remote, node) {
+ if (node != remote_input) {
+ /*
+ * The endpoint which is not input node must be bridge
+ */
+ is_bridge = true;
+ of_node_put(node);
+ break;
+ }
+ }
+
+ if (!is_bridge) {
+ ret = -ENODEV;
+ goto done;
+ }
+
+ mipi_dsi->next_bridge = of_drm_find_bridge(remote);
+ if (!mipi_dsi->next_bridge) {
+ ret = -EPROBE_DEFER;
+ goto done;
+ }
+
+ /* Get lanes information */
+ prop = of_find_property(local_output, "data-lanes", &len);
+ if (!prop) {
+ mipi_dsi->num_data_lanes = 4;
+ dev_dbg(mipi_dsi->dev,
+ "failed to find data lane information, using default\n");
+ goto done;
+ }
+
+ num_lanes = len / sizeof(u32);
+
+ if (num_lanes < 1 || num_lanes > 4) {
+ dev_err(mipi_dsi->dev, "data lanes definition is not correct\n");
+ return -EINVAL;
+ }
+
+ mipi_dsi->num_data_lanes = num_lanes;
+done:
+ of_node_put(local_output);
+ of_node_put(remote_input);
+ of_node_put(remote);
+
+ return ret;
+}
+
+static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *mipi_dsi,
+ const char *name,
+ bool optional)
+{
+ struct clk *clk;
+
+ clk = devm_clk_get(mipi_dsi->dev, name);
+ if (!IS_ERR(clk))
+ return clk;
+
+ if (PTR_ERR(clk) == -ENOENT && optional)
+ return NULL;
+
+ if (PTR_ERR(clk) != -EPROBE_DEFER)
+ dev_err(mipi_dsi->dev, "failed to get %s clock\n",
+ name ? name : "module");
+
+ return clk;
+}
+
+static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *mipi_dsi)
+{
+ mipi_dsi->clocks.mod = rcar_mipi_dsi_get_clock(mipi_dsi, NULL, false);
+ if (IS_ERR(mipi_dsi->clocks.mod))
+ return PTR_ERR(mipi_dsi->clocks.mod);
+
+ mipi_dsi->clocks.extal = rcar_mipi_dsi_get_clock(mipi_dsi, "extal",
+ true);
+ if (IS_ERR(mipi_dsi->clocks.extal))
+ return PTR_ERR(mipi_dsi->clocks.extal);
+
+ mipi_dsi->clocks.dsi = rcar_mipi_dsi_get_clock(mipi_dsi, "dsi", true);
+ if (IS_ERR(mipi_dsi->clocks.dsi))
+ return PTR_ERR(mipi_dsi->clocks.dsi);
+
+ if (!mipi_dsi->clocks.extal && !mipi_dsi->clocks.dsi) {
+ dev_err(mipi_dsi->dev,
+ "no input clock (extal, dclkin.0)\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rcar_mipi_dsi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_mipi_dsi *mipi_dsi;
+ struct resource *mem;
+ int ret;
+
+ mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
+ if (mipi_dsi == NULL)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, mipi_dsi);
+
+ mipi_dsi->dev = dev;
+ mipi_dsi->info = of_device_get_match_data(&pdev->dev);
+
+ ret = rcar_mipi_dsi_parse_dt(mipi_dsi);
+ if (ret < 0)
+ return ret;
+
+ /* Initialize the DRM bridge. */
+ mipi_dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
+ mipi_dsi->bridge.of_node = pdev->dev.of_node;
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mipi_dsi->mmio = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(mipi_dsi->mmio))
+ return PTR_ERR(mipi_dsi->mmio);
+
+ ret = rcar_mipi_dsi_get_clocks(mipi_dsi);
+ if (ret < 0)
+ return ret;
+
+ mipi_dsi->rstc = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(mipi_dsi->rstc)) {
+ dev_err(&pdev->dev, "failed to get cpg reset\n");
+ return PTR_ERR(mipi_dsi->rstc);
+ }
+
+ /* Initialize the DST host. */
+ mipi_dsi->host.dev = dev;
+ mipi_dsi->host.ops = &rcar_mipi_dsi_host_ops;
+ ret = mipi_dsi_host_register(&mipi_dsi->host);
+ if (ret < 0)
+ return ret;
+
+ drm_bridge_add(&mipi_dsi->bridge);
+
+ return 0;
+}
+
+static int rcar_mipi_dsi_remove(struct platform_device *pdev)
+{
+ struct rcar_mipi_dsi *mipi_dsi = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&mipi_dsi->bridge);
+
+ mipi_dsi_host_unregister(&mipi_dsi->host);
+
+ return 0;
+}
+
+static const struct of_device_id rcar_mipi_dsi_of_table[] = {
+ { .compatible = "renesas,r8a779a0-mipi-dsi" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
+
+static struct platform_driver rcar_mipi_dsi_platform_driver = {
+ .probe = rcar_mipi_dsi_probe,
+ .remove = rcar_mipi_dsi_remove,
+ .driver = {
+ .name = "rcar-mipi-dsi",
+ .of_match_table = rcar_mipi_dsi_of_table,
+ },
+};
+
+module_platform_driver(rcar_mipi_dsi_platform_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
new file mode 100644
index 000000000000..a937ab7ddcd4
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rcar_mipi_dsi.h -- R-Car MIPI_DSI Encoder
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_MIPI_DSI_H__
+#define __RCAR_MIPI_DSI_H__
+
+struct drm_bridge;
+
+#if IS_ENABLED(CONFIG_DRM_RCAR_MIPI_DSI)
+int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge);
+void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge);
+
+#else
+static inline int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
+{
+ return -ENOSYS;
+}
+static inline void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge) { }
+
+#endif /* CONFIG_DRM_RCAR_MIPI_DSI */
+
+#endif /* __RCAR_MIPI_DSI_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h
new file mode 100644
index 000000000000..0e7a9274749f
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rcar_mipi_dsi_regs.h -- R-Car MIPI DSI Interface Registers Definitions
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_MIPI_DSI_REGS_H__
+#define __RCAR_MIPI_DSI_REGS_H__
+
+#define LINKSR 0x010
+#define LINKSR_LPBUSY (1 << 1)
+#define LINKSR_HSBUSY (1 << 0)
+
+/*
+ * Video Mode Register
+ */
+#define TXVMSETR 0x180
+#define TXVMSETR_SYNSEQ_PULSES (0 << 16)
+#define TXVMSETR_SYNSEQ_EVENTS (1 << 16)
+#define TXVMSETR_VSTPM (1 << 15)
+#define TXVMSETR_PIXWDTH (1 << 8)
+#define TXVMSETR_VSEN_EN (1 << 4)
+#define TXVMSETR_VSEN_DIS (0 << 4)
+#define TXVMSETR_HFPBPEN_EN (1 << 2)
+#define TXVMSETR_HFPBPEN_DIS (0 << 2)
+#define TXVMSETR_HBPBPEN_EN (1 << 1)
+#define TXVMSETR_HBPBPEN_DIS (0 << 1)
+#define TXVMSETR_HSABPEN_EN (1 << 0)
+#define TXVMSETR_HSABPEN_DIS (0 << 0)
+
+#define TXVMCR 0x190
+#define TXVMCR_VFCLR (1 << 12)
+#define TXVMCR_EN_VIDEO (1 << 0)
+
+#define TXVMSR 0x1a0
+#define TXVMSR_STR (1 << 16)
+#define TXVMSR_VFRDY (1 << 12)
+#define TXVMSR_ACT (1 << 8)
+#define TXVMSR_RDY (1 << 0)
+
+#define TXVMSCR 0x1a4
+#define TXVMSCR_STR (1 << 16)
+
+#define TXVMPSPHSETR 0x1c0
+#define TXVMPSPHSETR_DT_RGB16 (0x0e << 16)
+#define TXVMPSPHSETR_DT_RGB18 (0x1e << 16)
+#define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16)
+#define TXVMPSPHSETR_DT_RGB24 (0x3e << 16)
+#define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16)
+
+#define TXVMVPRMSET0R 0x1d0
+#define TXVMVPRMSET0R_HSPOL_HIG (0 << 17)
+#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17)
+#define TXVMVPRMSET0R_VSPOL_HIG (0 << 16)
+#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16)
+#define TXVMVPRMSET0R_CSPC_RGB (0 << 4)
+#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4)
+#define TXVMVPRMSET0R_BPP_16 (0 << 0)
+#define TXVMVPRMSET0R_BPP_18 (1 << 0)
+#define TXVMVPRMSET0R_BPP_24 (2 << 0)
+
+#define TXVMVPRMSET1R 0x1d4
+#define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)
+#define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0)
+
+#define TXVMVPRMSET2R 0x1d8
+#define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16)
+#define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0)
+
+#define TXVMVPRMSET3R 0x1dc
+#define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16)
+#define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0)
+
+#define TXVMVPRMSET4R 0x1e0
+#define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16)
+#define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0)
+
+/*
+ * PHY-Protocol Interface (PPI) Registers
+ */
+#define PPISETR 0x700
+#define PPISETR_DLEN_0 (0x1 << 0)
+#define PPISETR_DLEN_1 (0x3 << 0)
+#define PPISETR_DLEN_2 (0x7 << 0)
+#define PPISETR_DLEN_3 (0xf << 0)
+#define PPISETR_CLEN (1 << 8)
+
+#define PPICLCR 0x710
+#define PPICLCR_TXREQHS (1 << 8)
+#define PPICLCR_TXULPSEXT (1 << 1)
+#define PPICLCR_TXULPSCLK (1 << 0)
+
+#define PPICLSR 0x720
+#define PPICLSR_HSTOLP (1 << 27)
+#define PPICLSR_TOHS (1 << 26)
+#define PPICLSR_STPST (1 << 0)
+
+#define PPICLSCR 0x724
+#define PPICLSCR_HSTOLP (1 << 27)
+#define PPICLSCR_TOHS (1 << 26)
+
+#define PPIDLSR 0x760
+#define PPIDLSR_STPST (0xf << 0)
+
+/*
+ * Clocks registers
+ */
+#define LPCLKSET 0x1000
+#define LPCLKSET_CKEN (1 << 8)
+#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
+
+#define CFGCLKSET 0x1004
+#define CFGCLKSET_CKEN (1 << 8)
+#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
+
+#define DOTCLKDIV 0x1008
+#define DOTCLKDIV_CKEN (1 << 8)
+#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
+
+#define VCLKSET 0x100c
+#define VCLKSET_CKEN (1 << 16)
+#define VCLKSET_COLOR_RGB (0 << 8)
+#define VCLKSET_COLOR_YCC (1 << 8)
+#define VCLKSET_DIV(x) (((x) & 0x3) << 4)
+#define VCLKSET_BPP_16 (0 << 2)
+#define VCLKSET_BPP_18 (1 << 2)
+#define VCLKSET_BPP_18L (2 << 2)
+#define VCLKSET_BPP_24 (3 << 2)
+#define VCLKSET_LANE(x) (((x) & 0x3) << 0)
+
+#define VCLKEN 0x1010
+#define VCLKEN_CKEN (1 << 0)
+
+#define PHYSETUP 0x1014
+#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
+#define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16)
+#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
+#define PHYSETUP_SHUTDOWNZ (1 << 1)
+#define PHYSETUP_RSTZ (1 << 0)
+
+#define CLOCKSET1 0x101c
+#define CLOCKSET1_LOCK_PHY (1 << 17)
+#define CLOCKSET1_LOCK (1 << 16)
+#define CLOCKSET1_CLKSEL (1 << 8)
+#define CLOCKSET1_CLKINSEL_EXTAL (0 << 2)
+#define CLOCKSET1_CLKINSEL_DIG (1 << 2)
+#define CLOCKSET1_CLKINSEL_DU (1 << 3)
+#define CLOCKSET1_SHADOW_CLEAR (1 << 1)
+#define CLOCKSET1_UPDATEPLL (1 << 0)
+
+#define CLOCKSET2 0x1020
+#define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
+#define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8)
+#define CLOCKSET2_N(x) (((x) & 0xf) << 0)
+
+#define CLOCKSET3 0x1024
+#define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24)
+#define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16)
+#define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8)
+#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
+
+#define PHTW 0x1034
+#define PHTW_DWEN (1 << 24)
+#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
+#define PHTW_CWEN (1 << 8)
+#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
+
+#define PHTC 0x103c
+#define PHTC_TESTCLR (1 << 0)
+
+#endif /* __RCAR_MIPI_DSI_REGS_H__ */
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 03/15] drm: rcar-du: dsi: Use the correct compatible
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 01/15] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 02/15] drm: rcar-du: Add R-Car DSI driver Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 04/15] drm: rcar-du: dsi: Reorganize probe function Laurent Pinchart
` (13 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
From: Kieran Bingham <kieran.bingham@ideasonboard.com>
The compatible imported by the driver does not match the bindings
created.
Update accordingly.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index ef2a9b283b4e..0c9887557761 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -875,7 +875,7 @@ static int rcar_mipi_dsi_remove(struct platform_device *pdev)
}
static const struct of_device_id rcar_mipi_dsi_of_table[] = {
- { .compatible = "renesas,r8a779a0-mipi-dsi" },
+ { .compatible = "renesas,r8a779a0-dsi-csi2-tx" },
{ }
};
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 04/15] drm: rcar-du: dsi: Reorganize probe function
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (2 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 03/15] drm: rcar-du: dsi: Use the correct compatible Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 05/15] drm: rcar-du: dsi: Use dev_err_probe() Laurent Pinchart
` (12 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 0c9887557761..92cd431631bf 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -832,10 +832,7 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- /* Initialize the DRM bridge. */
- mipi_dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
- mipi_dsi->bridge.of_node = pdev->dev.of_node;
-
+ /* Acquire resources. */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mipi_dsi->mmio = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(mipi_dsi->mmio))
@@ -851,13 +848,16 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
return PTR_ERR(mipi_dsi->rstc);
}
- /* Initialize the DST host. */
+ /* Initialize the DSI host. */
mipi_dsi->host.dev = dev;
mipi_dsi->host.ops = &rcar_mipi_dsi_host_ops;
ret = mipi_dsi_host_register(&mipi_dsi->host);
if (ret < 0)
return ret;
+ /* Initialize the DRM bridge. */
+ mipi_dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
+ mipi_dsi->bridge.of_node = pdev->dev.of_node;
drm_bridge_add(&mipi_dsi->bridge);
return 0;
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 05/15] drm: rcar-du: dsi: Use dev_err_probe()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (3 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 04/15] drm: rcar-du: dsi: Reorganize probe function Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 06/15] drm: rcar-du: dsi: Shorten mipi_dsi variable name to dsi Laurent Pinchart
` (11 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 92cd431631bf..17cff0305c6c 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -781,9 +781,8 @@ static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *mipi_dsi,
if (PTR_ERR(clk) == -ENOENT && optional)
return NULL;
- if (PTR_ERR(clk) != -EPROBE_DEFER)
- dev_err(mipi_dsi->dev, "failed to get %s clock\n",
- name ? name : "module");
+ dev_err_probe(mipi_dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
+ name ? name : "module");
return clk;
}
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 06/15] drm: rcar-du: dsi: Shorten mipi_dsi variable name to dsi
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (4 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 05/15] drm: rcar-du: dsi: Use dev_err_probe() Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 07/15] drm: rcar-du: dsi: Use dsi->dev consistently in probe() Laurent Pinchart
` (10 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 331 ++++++++++++------------
1 file changed, 161 insertions(+), 170 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 17cff0305c6c..fbc8ba154e28 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -119,40 +119,35 @@ static const struct vco_cntrl_value vco_cntrl_table[] = {
{ /* sentinel */ },
};
-static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *mipi_dsi,
- u32 reg, u32 data)
+static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
{
- iowrite32(data, mipi_dsi->mmio + reg);
+ iowrite32(data, dsi->mmio + reg);
}
-static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *mipi_dsi, u32 reg)
+static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
{
- return ioread32(mipi_dsi->mmio + reg);
+ return ioread32(dsi->mmio + reg);
}
-static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *mipi_dsi,
- u32 reg, u32 clr)
+static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
{
- rcar_mipi_dsi_write(mipi_dsi, reg,
- rcar_mipi_dsi_read(mipi_dsi, reg) & ~clr);
+ rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
}
-static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *mipi_dsi,
- u32 reg, u32 set)
+static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
{
- rcar_mipi_dsi_write(mipi_dsi, reg,
- rcar_mipi_dsi_read(mipi_dsi, reg) | set);
+ rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
}
-static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *mipi_dsi, u32 phtw)
+static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
{
unsigned int timeout;
u32 status;
- rcar_mipi_dsi_write(mipi_dsi, PHTW, phtw);
+ rcar_mipi_dsi_write(dsi, PHTW, phtw);
for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(mipi_dsi, PHTW);
+ status = rcar_mipi_dsi_read(dsi, PHTW);
if (!(status & PHTW_DWEN) &&
!(status & PHTW_CWEN))
break;
@@ -161,8 +156,7 @@ static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *mipi_dsi, u32 phtw)
}
if (!timeout) {
- dev_err(mipi_dsi->dev,
- "failed to test phtw with data %x\n", phtw);
+ dev_err(dsi->dev, "failed to test phtw with data %x\n", phtw);
return -ETIMEDOUT;
}
@@ -183,7 +177,7 @@ struct dsi_setup_info {
unsigned int n;
};
-static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *mipi_dsi,
+static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *dsi,
struct clk *clk, unsigned long target,
struct dsi_setup_info *setup_info)
{
@@ -202,8 +196,8 @@ static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *mipi_dsi,
* The range out Fout is [40 - 1250] Mhz
*/
fout_target = target *
- mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) /
- (2 * mipi_dsi->lanes);
+ mipi_dsi_pixel_format_to_bpp(dsi->format) /
+ (2 * dsi->lanes);
if (fout_target < 40000000 || fout_target > 1250000000)
return;
@@ -261,21 +255,21 @@ static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *mipi_dsi,
}
done:
- dev_dbg(mipi_dsi->dev,
+ dev_dbg(dsi->dev,
"%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
clk, fin, fout, fout_target, setup_info->err / 100,
setup_info->err % 100, setup_info->m,
setup_info->n, setup_info->div);
- dev_dbg(mipi_dsi->dev,
+ dev_dbg(dsi->dev,
"vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
setup_info->vco_cntrl,
setup_info->prop_cntrl,
setup_info->hsfreqrange);
}
-static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *mipi_dsi)
+static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi)
{
- struct drm_display_mode *mode = &mipi_dsi->display_mode;
+ struct drm_display_mode *mode = &dsi->display_mode;
u32 setr;
u32 vprmset0r;
u32 vprmset1r;
@@ -284,17 +278,17 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *mipi_dsi)
u32 vprmset4r;
/* Configuration for Pixel Stream and Packet Header */
- if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 24)
- rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
TXVMPSPHSETR_DT_RGB24);
- else if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 18)
- rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
TXVMPSPHSETR_DT_RGB18);
- else if (mipi_dsi_pixel_format_to_bpp(mipi_dsi->format) == 16)
- rcar_mipi_dsi_write(mipi_dsi, TXVMPSPHSETR,
+ else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
TXVMPSPHSETR_DT_RGB16);
else {
- dev_warn(mipi_dsi->dev, "unsupported format");
+ dev_warn(dsi->dev, "unsupported format");
return;
}
@@ -302,7 +296,7 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *mipi_dsi)
setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN |
TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES |
TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
- rcar_mipi_dsi_write(mipi_dsi, TXVMSETR, setr);
+ rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
/* Configuration for Video Parameters */
vprmset0r = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ?
@@ -323,16 +317,16 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *mipi_dsi)
vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay) |
TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
- rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET0R, vprmset0r);
- rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET1R, vprmset1r);
- rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET2R, vprmset2r);
- rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET3R, vprmset3r);
- rcar_mipi_dsi_write(mipi_dsi, TXVMVPRMSET4R, vprmset4r);
+ rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
+ rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
+ rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
+ rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
+ rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
}
-static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *mipi_dsi)
+static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi)
{
- struct drm_display_mode *mode = &mipi_dsi->display_mode;
+ struct drm_display_mode *mode = &dsi->display_mode;
struct dsi_setup_info setup_info = {.err = -1 };
unsigned int timeout;
int ret, i;
@@ -343,44 +337,44 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *mipi_dsi)
u32 vclkset;
/* Checking valid format */
- dsi_format = mipi_dsi_pixel_format_to_bpp(mipi_dsi->format);
+ dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
if (dsi_format < 0) {
- dev_warn(mipi_dsi->dev, "invalid format");
+ dev_warn(dsi->dev, "invalid format");
return -EINVAL;
}
/* Parametters Calulation */
- rcar_mipi_dsi_parametters_calc(mipi_dsi, mipi_dsi->clocks.extal,
- mode->clock * 1000, &setup_info);
+ rcar_mipi_dsi_parametters_calc(dsi, dsi->clocks.extal,
+ mode->clock * 1000, &setup_info);
/* LPCLK enable */
- rcar_mipi_dsi_set(mipi_dsi, LPCLKSET, LPCLKSET_CKEN);
+ rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
/* CFGCLK enabled */
- rcar_mipi_dsi_set(mipi_dsi, CFGCLKSET, CFGCLKSET_CKEN);
+ rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
- rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
- rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+ rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
+ rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
- rcar_mipi_dsi_set(mipi_dsi, PHTC, PHTC_TESTCLR);
- rcar_mipi_dsi_clr(mipi_dsi, PHTC, PHTC_TESTCLR);
+ rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
+ rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
/* PHY setting */
- phy_setup = rcar_mipi_dsi_read(mipi_dsi, PHYSETUP);
+ phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
- rcar_mipi_dsi_write(mipi_dsi, PHYSETUP, phy_setup);
+ rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
for (i = 0; i < ARRAY_SIZE(phtw); i++) {
- ret = rcar_mipi_dsi_phtw_test(mipi_dsi, phtw[i]);
+ ret = rcar_mipi_dsi_phtw_test(dsi, phtw[i]);
if (ret < 0)
return ret;
}
/* PLL Clock Setting */
- rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
- rcar_mipi_dsi_set(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
- rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+ rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+ rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
+ rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n) |
CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
@@ -388,45 +382,45 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *mipi_dsi)
CLOCKSET3_INT_CNTRL(0) |
CLOCKSET3_CPBIAS_CNTRL(0x10) |
CLOCKSET3_GMP_CNTRL(1);
- rcar_mipi_dsi_write(mipi_dsi, CLOCKSET2, clockset2);
- rcar_mipi_dsi_write(mipi_dsi, CLOCKSET3, clockset3);
+ rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
+ rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
- rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
- rcar_mipi_dsi_set(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+ rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+ rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
udelay(10);
- rcar_mipi_dsi_clr(mipi_dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
+ rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
- rcar_mipi_dsi_write(mipi_dsi, PPISETR, ppisetr);
+ rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
- rcar_mipi_dsi_set(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
- rcar_mipi_dsi_set(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
+ rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+ rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
usleep_range(400, 500);
/* Checking PPI clock status register */
for (timeout = 10; timeout > 0; --timeout) {
- if ((rcar_mipi_dsi_read(mipi_dsi, PPICLSR) & PPICLSR_STPST) &&
- (rcar_mipi_dsi_read(mipi_dsi, PPIDLSR) & PPIDLSR_STPST) &&
- (rcar_mipi_dsi_read(mipi_dsi, CLOCKSET1) & CLOCKSET1_LOCK))
+ if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
+ (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
+ (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
break;
usleep_range(1000, 2000);
}
if (!timeout) {
- dev_err(mipi_dsi->dev, "failed to enable PPI clock\n");
+ dev_err(dsi->dev, "failed to enable PPI clock\n");
return -ETIMEDOUT;
}
for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
- ret = rcar_mipi_dsi_phtw_test(mipi_dsi, phtw2[i]);
+ ret = rcar_mipi_dsi_phtw_test(dsi, phtw2[i]);
if (ret < 0)
return ret;
}
/* Enable DOT clock */
vclkset = VCLKSET_CKEN;
- rcar_mipi_dsi_set(mipi_dsi, VCLKSET, vclkset);
+ rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
if (dsi_format == 24)
vclkset |= VCLKSET_BPP_24;
@@ -435,31 +429,31 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *mipi_dsi)
else if (dsi_format == 16)
vclkset |= VCLKSET_BPP_16;
else {
- dev_warn(mipi_dsi->dev, "unsupported format");
+ dev_warn(dsi->dev, "unsupported format");
return -EINVAL;
}
vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div) |
- VCLKSET_LANE(mipi_dsi->lanes - 1);
+ VCLKSET_LANE(dsi->lanes - 1);
- rcar_mipi_dsi_set(mipi_dsi, VCLKSET, vclkset);
+ rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
/* After setting VCLKSET register, enable VCLKEN */
- rcar_mipi_dsi_set(mipi_dsi, VCLKEN, VCLKEN_CKEN);
+ rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
- dev_dbg(mipi_dsi->dev, "DSI device is started\n");
+ dev_dbg(dsi->dev, "DSI device is started\n");
return 0;
}
-static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *mipi_dsi)
+static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
{
- rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_RSTZ);
- rcar_mipi_dsi_clr(mipi_dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
+ rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
+ rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
- dev_dbg(mipi_dsi->dev, "DSI device is shutdown\n");
+ dev_dbg(dsi->dev, "DSI device is shutdown\n");
}
-static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *mipi_dsi)
+static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
{
/*
* In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
@@ -469,13 +463,13 @@ static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *mipi_dsi)
u32 status;
/* Start HS clock */
- rcar_mipi_dsi_set(mipi_dsi, PPICLCR, PPICLCR_TXREQHS);
+ rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(mipi_dsi, PPICLSR);
+ status = rcar_mipi_dsi_read(dsi, PPICLSR);
if (status & PPICLSR_TOHS) {
- rcar_mipi_dsi_set(mipi_dsi, PPICLSCR, PPICLSCR_TOHS);
+ rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
break;
}
@@ -483,26 +477,26 @@ static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *mipi_dsi)
}
if (!timeout) {
- dev_err(mipi_dsi->dev, "failed to enable HS clock\n");
+ dev_err(dsi->dev, "failed to enable HS clock\n");
return -ETIMEDOUT;
}
- dev_dbg(mipi_dsi->dev, "Start High Speed Clock");
+ dev_dbg(dsi->dev, "Start High Speed Clock");
return 0;
}
-static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
+static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
{
unsigned int timeout;
u32 status;
/* Check status of Tranmission */
for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(mipi_dsi, LINKSR);
+ status = rcar_mipi_dsi_read(dsi, LINKSR);
if (!(status & LINKSR_LPBUSY) &&
!(status & LINKSR_HSBUSY)) {
- rcar_mipi_dsi_clr(mipi_dsi, TXVMCR, TXVMCR_VFCLR);
+ rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
break;
}
@@ -510,15 +504,15 @@ static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
}
if (!timeout) {
- dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ dev_err(dsi->dev, "Failed to enable Video clock\n");
return -ETIMEDOUT;
}
/* Check Clear Video mode FIFO */
for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(mipi_dsi, TXVMSR);
+ status = rcar_mipi_dsi_read(dsi, TXVMSR);
if (status & TXVMSR_VFRDY) {
- rcar_mipi_dsi_set(mipi_dsi, TXVMCR, TXVMCR_EN_VIDEO);
+ rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
break;
}
@@ -526,13 +520,13 @@ static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
}
if (!timeout) {
- dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ dev_err(dsi->dev, "Failed to enable Video clock\n");
return -ETIMEDOUT;
}
/* Check Video transmission */
for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(mipi_dsi, TXVMSR);
+ status = rcar_mipi_dsi_read(dsi, TXVMSR);
if (status & TXVMSR_RDY)
break;
@@ -540,11 +534,11 @@ static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
}
if (!timeout) {
- dev_err(mipi_dsi->dev, "Failed to enable Video clock\n");
+ dev_err(dsi->dev, "Failed to enable Video clock\n");
return -ETIMEDOUT;
}
- dev_dbg(mipi_dsi->dev, "Start video transferring");
+ dev_dbg(dsi->dev, "Start video transferring");
return 0;
}
@@ -556,9 +550,9 @@ static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *mipi_dsi)
static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
- struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
- return drm_bridge_attach(bridge->encoder, mipi_dsi->next_bridge, bridge,
+ return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
flags);
}
@@ -566,23 +560,23 @@ static void rcar_mipi_dsi_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
- struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
- mipi_dsi->display_mode = *adjusted_mode;
+ dsi->display_mode = *adjusted_mode;
}
static void rcar_mipi_dsi_enable(struct drm_bridge *bridge)
{
- struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
int ret;
- rcar_mipi_dsi_set_display_timing(mipi_dsi);
+ rcar_mipi_dsi_set_display_timing(dsi);
- ret = rcar_mipi_dsi_start_hs_clock(mipi_dsi);
+ ret = rcar_mipi_dsi_start_hs_clock(dsi);
if (ret < 0)
return;
- ret = rcar_mipi_dsi_start_video(mipi_dsi);
+ ret = rcar_mipi_dsi_start_video(dsi);
if (ret < 0)
return;
@@ -612,20 +606,20 @@ static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
{
- struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
int ret;
- reset_control_deassert(mipi_dsi->rstc);
+ reset_control_deassert(dsi->rstc);
- ret = clk_prepare_enable(mipi_dsi->clocks.mod);
+ ret = clk_prepare_enable(dsi->clocks.mod);
if (ret < 0)
return ret;
- ret = clk_prepare_enable(mipi_dsi->clocks.dsi);
+ ret = clk_prepare_enable(dsi->clocks.dsi);
if (ret < 0)
return ret;
- ret = rcar_mipi_dsi_startup(mipi_dsi);
+ ret = rcar_mipi_dsi_startup(dsi);
if (ret < 0)
return ret;
@@ -635,16 +629,16 @@ EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_enable);
void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge)
{
- struct rcar_mipi_dsi *mipi_dsi = bridge_to_rcar_mipi_dsi(bridge);
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
- rcar_mipi_dsi_shutdown(mipi_dsi);
+ rcar_mipi_dsi_shutdown(dsi);
/* Disable DSI clock and reset HW */
- clk_disable_unprepare(mipi_dsi->clocks.dsi);
+ clk_disable_unprepare(dsi->clocks.dsi);
- clk_disable_unprepare(mipi_dsi->clocks.mod);
+ clk_disable_unprepare(dsi->clocks.mod);
- reset_control_assert(mipi_dsi->rstc);
+ reset_control_assert(dsi->rstc);
}
EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_disable);
@@ -655,13 +649,13 @@ EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_disable);
static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
- struct rcar_mipi_dsi *mipi_dsi = host_to_rcar_mipi_dsi(host);
+ struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
- if (device->lanes > mipi_dsi->num_data_lanes)
+ if (device->lanes > dsi->num_data_lanes)
return -EINVAL;
- mipi_dsi->lanes = device->lanes;
- mipi_dsi->format = device->format;
+ dsi->lanes = device->lanes;
+ dsi->format = device->format;
return 0;
}
@@ -681,7 +675,7 @@ static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
* Probe & Remove
*/
-static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
+static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
{
struct device_node *local_output = NULL;
struct device_node *remote_input = NULL;
@@ -692,10 +686,10 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
int ret = 0;
int len, num_lanes;
- local_output = of_graph_get_endpoint_by_regs(mipi_dsi->dev->of_node,
+ local_output = of_graph_get_endpoint_by_regs(dsi->dev->of_node,
1, 0);
if (!local_output) {
- dev_dbg(mipi_dsi->dev, "unconnected port@1\n");
+ dev_dbg(dsi->dev, "unconnected port@1\n");
ret = -ENODEV;
goto done;
}
@@ -706,15 +700,14 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
*/
remote = of_graph_get_remote_port_parent(local_output);
if (!remote) {
- dev_dbg(mipi_dsi->dev, "unconnected endpoint %pOF\n",
- local_output);
+ dev_dbg(dsi->dev, "unconnected endpoint %pOF\n", local_output);
ret = -ENODEV;
goto done;
}
if (!of_device_is_available(remote)) {
- dev_dbg(mipi_dsi->dev, "connected entity %pOF is disabled\n",
- remote);
+ dev_dbg(dsi->dev, "connected entity %pOF is disabled\n",
+ remote);
ret = -ENODEV;
goto done;
}
@@ -737,8 +730,8 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
goto done;
}
- mipi_dsi->next_bridge = of_drm_find_bridge(remote);
- if (!mipi_dsi->next_bridge) {
+ dsi->next_bridge = of_drm_find_bridge(remote);
+ if (!dsi->next_bridge) {
ret = -EPROBE_DEFER;
goto done;
}
@@ -746,8 +739,8 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
/* Get lanes information */
prop = of_find_property(local_output, "data-lanes", &len);
if (!prop) {
- mipi_dsi->num_data_lanes = 4;
- dev_dbg(mipi_dsi->dev,
+ dsi->num_data_lanes = 4;
+ dev_dbg(dsi->dev,
"failed to find data lane information, using default\n");
goto done;
}
@@ -755,11 +748,11 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
num_lanes = len / sizeof(u32);
if (num_lanes < 1 || num_lanes > 4) {
- dev_err(mipi_dsi->dev, "data lanes definition is not correct\n");
+ dev_err(dsi->dev, "data lanes definition is not correct\n");
return -EINVAL;
}
- mipi_dsi->num_data_lanes = num_lanes;
+ dsi->num_data_lanes = num_lanes;
done:
of_node_put(local_output);
of_node_put(remote_input);
@@ -768,43 +761,41 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *mipi_dsi)
return ret;
}
-static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *mipi_dsi,
+static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
const char *name,
bool optional)
{
struct clk *clk;
- clk = devm_clk_get(mipi_dsi->dev, name);
+ clk = devm_clk_get(dsi->dev, name);
if (!IS_ERR(clk))
return clk;
if (PTR_ERR(clk) == -ENOENT && optional)
return NULL;
- dev_err_probe(mipi_dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
+ dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
name ? name : "module");
return clk;
}
-static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *mipi_dsi)
+static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
{
- mipi_dsi->clocks.mod = rcar_mipi_dsi_get_clock(mipi_dsi, NULL, false);
- if (IS_ERR(mipi_dsi->clocks.mod))
- return PTR_ERR(mipi_dsi->clocks.mod);
+ dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
+ if (IS_ERR(dsi->clocks.mod))
+ return PTR_ERR(dsi->clocks.mod);
- mipi_dsi->clocks.extal = rcar_mipi_dsi_get_clock(mipi_dsi, "extal",
- true);
- if (IS_ERR(mipi_dsi->clocks.extal))
- return PTR_ERR(mipi_dsi->clocks.extal);
+ dsi->clocks.extal = rcar_mipi_dsi_get_clock(dsi, "extal", true);
+ if (IS_ERR(dsi->clocks.extal))
+ return PTR_ERR(dsi->clocks.extal);
- mipi_dsi->clocks.dsi = rcar_mipi_dsi_get_clock(mipi_dsi, "dsi", true);
- if (IS_ERR(mipi_dsi->clocks.dsi))
- return PTR_ERR(mipi_dsi->clocks.dsi);
+ dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
+ if (IS_ERR(dsi->clocks.dsi))
+ return PTR_ERR(dsi->clocks.dsi);
- if (!mipi_dsi->clocks.extal && !mipi_dsi->clocks.dsi) {
- dev_err(mipi_dsi->dev,
- "no input clock (extal, dclkin.0)\n");
+ if (!dsi->clocks.extal && !dsi->clocks.dsi) {
+ dev_err(dsi->dev, "no input clock (extal, dclkin.0)\n");
return -EINVAL;
}
@@ -814,61 +805,61 @@ static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *mipi_dsi)
static int rcar_mipi_dsi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct rcar_mipi_dsi *mipi_dsi;
+ struct rcar_mipi_dsi *dsi;
struct resource *mem;
int ret;
- mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
- if (mipi_dsi == NULL)
+ dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
+ if (dsi == NULL)
return -ENOMEM;
- platform_set_drvdata(pdev, mipi_dsi);
+ platform_set_drvdata(pdev, dsi);
- mipi_dsi->dev = dev;
- mipi_dsi->info = of_device_get_match_data(&pdev->dev);
+ dsi->dev = dev;
+ dsi->info = of_device_get_match_data(&pdev->dev);
- ret = rcar_mipi_dsi_parse_dt(mipi_dsi);
+ ret = rcar_mipi_dsi_parse_dt(dsi);
if (ret < 0)
return ret;
/* Acquire resources. */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- mipi_dsi->mmio = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(mipi_dsi->mmio))
- return PTR_ERR(mipi_dsi->mmio);
+ dsi->mmio = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(dsi->mmio))
+ return PTR_ERR(dsi->mmio);
- ret = rcar_mipi_dsi_get_clocks(mipi_dsi);
+ ret = rcar_mipi_dsi_get_clocks(dsi);
if (ret < 0)
return ret;
- mipi_dsi->rstc = devm_reset_control_get(&pdev->dev, NULL);
- if (IS_ERR(mipi_dsi->rstc)) {
+ dsi->rstc = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(dsi->rstc)) {
dev_err(&pdev->dev, "failed to get cpg reset\n");
- return PTR_ERR(mipi_dsi->rstc);
+ return PTR_ERR(dsi->rstc);
}
/* Initialize the DSI host. */
- mipi_dsi->host.dev = dev;
- mipi_dsi->host.ops = &rcar_mipi_dsi_host_ops;
- ret = mipi_dsi_host_register(&mipi_dsi->host);
+ dsi->host.dev = dev;
+ dsi->host.ops = &rcar_mipi_dsi_host_ops;
+ ret = mipi_dsi_host_register(&dsi->host);
if (ret < 0)
return ret;
/* Initialize the DRM bridge. */
- mipi_dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
- mipi_dsi->bridge.of_node = pdev->dev.of_node;
- drm_bridge_add(&mipi_dsi->bridge);
+ dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
+ dsi->bridge.of_node = pdev->dev.of_node;
+ drm_bridge_add(&dsi->bridge);
return 0;
}
static int rcar_mipi_dsi_remove(struct platform_device *pdev)
{
- struct rcar_mipi_dsi *mipi_dsi = platform_get_drvdata(pdev);
+ struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
- drm_bridge_remove(&mipi_dsi->bridge);
+ drm_bridge_remove(&dsi->bridge);
- mipi_dsi_host_unregister(&mipi_dsi->host);
+ mipi_dsi_host_unregister(&dsi->host);
return 0;
}
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 07/15] drm: rcar-du: dsi: Use dsi->dev consistently in probe()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (5 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 06/15] drm: rcar-du: dsi: Shorten mipi_dsi variable name to dsi Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 08/15] drm: rcar-du: dsi: Get next bridge " Laurent Pinchart
` (9 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index fbc8ba154e28..454c25591a14 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -804,7 +804,6 @@ static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
static int rcar_mipi_dsi_probe(struct platform_device *pdev)
{
- struct device *dev = &pdev->dev;
struct rcar_mipi_dsi *dsi;
struct resource *mem;
int ret;
@@ -815,7 +814,7 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, dsi);
- dsi->dev = dev;
+ dsi->dev = &pdev->dev;
dsi->info = of_device_get_match_data(&pdev->dev);
ret = rcar_mipi_dsi_parse_dt(dsi);
@@ -824,7 +823,7 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
/* Acquire resources. */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- dsi->mmio = devm_ioremap_resource(&pdev->dev, mem);
+ dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
if (IS_ERR(dsi->mmio))
return PTR_ERR(dsi->mmio);
@@ -832,14 +831,14 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- dsi->rstc = devm_reset_control_get(&pdev->dev, NULL);
+ dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
if (IS_ERR(dsi->rstc)) {
- dev_err(&pdev->dev, "failed to get cpg reset\n");
+ dev_err(dsi->dev, "failed to get cpg reset\n");
return PTR_ERR(dsi->rstc);
}
/* Initialize the DSI host. */
- dsi->host.dev = dev;
+ dsi->host.dev = dsi->dev;
dsi->host.ops = &rcar_mipi_dsi_host_ops;
ret = mipi_dsi_host_register(&dsi->host);
if (ret < 0)
@@ -847,7 +846,7 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
/* Initialize the DRM bridge. */
dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
- dsi->bridge.of_node = pdev->dev.of_node;
+ dsi->bridge.of_node = dsi->dev->of_node;
drm_bridge_add(&dsi->bridge);
return 0;
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 08/15] drm: rcar-du: dsi: Get next bridge in probe()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (6 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 07/15] drm: rcar-du: dsi: Use dsi->dev consistently in probe() Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 09/15] drm: rcar-du: dsi: Simplify DT parsing Laurent Pinchart
` (8 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 65 +++++++------------------
1 file changed, 17 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 454c25591a14..a6bb7f25164b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -20,6 +20,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>
@@ -678,11 +679,7 @@ static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
{
struct device_node *local_output = NULL;
- struct device_node *remote_input = NULL;
- struct device_node *remote = NULL;
- struct device_node *node;
struct property *prop;
- bool is_bridge = false;
int ret = 0;
int len, num_lanes;
@@ -694,48 +691,6 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
goto done;
}
- /*
- * Locate the connected entity and
- * infer its type from the number of endpoints.
- */
- remote = of_graph_get_remote_port_parent(local_output);
- if (!remote) {
- dev_dbg(dsi->dev, "unconnected endpoint %pOF\n", local_output);
- ret = -ENODEV;
- goto done;
- }
-
- if (!of_device_is_available(remote)) {
- dev_dbg(dsi->dev, "connected entity %pOF is disabled\n",
- remote);
- ret = -ENODEV;
- goto done;
- }
-
- remote_input = of_graph_get_remote_endpoint(local_output);
-
- for_each_endpoint_of_node(remote, node) {
- if (node != remote_input) {
- /*
- * The endpoint which is not input node must be bridge
- */
- is_bridge = true;
- of_node_put(node);
- break;
- }
- }
-
- if (!is_bridge) {
- ret = -ENODEV;
- goto done;
- }
-
- dsi->next_bridge = of_drm_find_bridge(remote);
- if (!dsi->next_bridge) {
- ret = -EPROBE_DEFER;
- goto done;
- }
-
/* Get lanes information */
prop = of_find_property(local_output, "data-lanes", &len);
if (!prop) {
@@ -755,8 +710,6 @@ static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
dsi->num_data_lanes = num_lanes;
done:
of_node_put(local_output);
- of_node_put(remote_input);
- of_node_put(remote);
return ret;
}
@@ -805,6 +758,7 @@ static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
static int rcar_mipi_dsi_probe(struct platform_device *pdev)
{
struct rcar_mipi_dsi *dsi;
+ struct drm_panel *panel;
struct resource *mem;
int ret;
@@ -837,6 +791,21 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
return PTR_ERR(dsi->rstc);
}
+ ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
+ &dsi->next_bridge);
+ if (ret) {
+ dev_err_probe(dsi->dev, ret, "could not find next bridge\n");
+ return ret;
+ }
+
+ if (!dsi->next_bridge) {
+ dsi->next_bridge = devm_drm_panel_bridge_add(dsi->dev, panel);
+ if (IS_ERR(dsi->next_bridge)) {
+ dev_err(dsi->dev, "failed to create panel bridge\n");
+ return PTR_ERR(dsi->next_bridge);
+ }
+ }
+
/* Initialize the DSI host. */
dsi->host.dev = dsi->dev;
dsi->host.ops = &rcar_mipi_dsi_host_ops;
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 09/15] drm: rcar-du: dsi: Simplify DT parsing
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (7 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 08/15] drm: rcar-du: dsi: Get next bridge " Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 10/15] drm: rcar-du: dsi: Add error handling in rcar_mipi_dsi_clk_enable() Laurent Pinchart
` (7 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 41 +++++++++----------------
1 file changed, 14 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index a6bb7f25164b..d16bf50e8acb 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -678,40 +678,27 @@ static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
{
- struct device_node *local_output = NULL;
- struct property *prop;
- int ret = 0;
- int len, num_lanes;
+ struct device_node *ep;
+ u32 data_lanes[4];
+ int ret;
- local_output = of_graph_get_endpoint_by_regs(dsi->dev->of_node,
- 1, 0);
- if (!local_output) {
+ ep = of_graph_get_endpoint_by_regs(dsi->dev->of_node, 1, 0);
+ if (!ep) {
dev_dbg(dsi->dev, "unconnected port@1\n");
- ret = -ENODEV;
- goto done;
+ return -ENODEV;
}
- /* Get lanes information */
- prop = of_find_property(local_output, "data-lanes", &len);
- if (!prop) {
- dsi->num_data_lanes = 4;
- dev_dbg(dsi->dev,
- "failed to find data lane information, using default\n");
- goto done;
- }
-
- num_lanes = len / sizeof(u32);
+ ret = of_property_read_variable_u32_array(ep, "data-lanes", data_lanes,
+ 1, 4);
+ of_node_put(ep);
- if (num_lanes < 1 || num_lanes > 4) {
- dev_err(dsi->dev, "data lanes definition is not correct\n");
- return -EINVAL;
+ if (ret < 0) {
+ dev_err(dsi->dev, "missing or invalid data-lanes property\n");
+ return -ENODEV;
}
- dsi->num_data_lanes = num_lanes;
-done:
- of_node_put(local_output);
-
- return ret;
+ dsi->num_data_lanes = ret;
+ return 0;
}
static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 10/15] drm: rcar-du: dsi: Add error handling in rcar_mipi_dsi_clk_enable()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (8 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 09/15] drm: rcar-du: dsi: Simplify DT parsing Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 11/15] drm: rcar-du: dsi: Simplify error handling in rcar_mipi_dsi_enable() Laurent Pinchart
` (6 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index d16bf50e8acb..2ef82ef0edc5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -618,13 +618,19 @@ int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
ret = clk_prepare_enable(dsi->clocks.dsi);
if (ret < 0)
- return ret;
+ goto err_clock_mod;
ret = rcar_mipi_dsi_startup(dsi);
if (ret < 0)
- return ret;
+ goto err_clock_dsi;
return 0;
+
+err_clock_dsi:
+ clk_disable_unprepare(dsi->clocks.dsi);
+err_clock_mod:
+ clk_disable_unprepare(dsi->clocks.mod);
+ return ret;
}
EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_enable);
@@ -634,9 +640,7 @@ void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge)
rcar_mipi_dsi_shutdown(dsi);
- /* Disable DSI clock and reset HW */
clk_disable_unprepare(dsi->clocks.dsi);
-
clk_disable_unprepare(dsi->clocks.mod);
reset_control_assert(dsi->rstc);
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 11/15] drm: rcar-du: dsi: Simplify error handling in rcar_mipi_dsi_enable()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (9 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 10/15] drm: rcar-du: dsi: Add error handling in rcar_mipi_dsi_clk_enable() Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 12/15] drm: rcar-du: dsi: Turn container_of() wrappers to inline functions Laurent Pinchart
` (5 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 2ef82ef0edc5..e8db56cc98f4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -577,10 +577,7 @@ static void rcar_mipi_dsi_enable(struct drm_bridge *bridge)
if (ret < 0)
return;
- ret = rcar_mipi_dsi_start_video(dsi);
- if (ret < 0)
- return;
-
+ rcar_mipi_dsi_start_video(dsi);
}
static enum drm_mode_status
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 12/15] drm: rcar-du: dsi: Turn container_of() wrappers to inline functions
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (10 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 11/15] drm: rcar-du: dsi: Simplify error handling in rcar_mipi_dsi_enable() Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 13/15] drm: rcar-du: dsi: Various style and typo fixes Laurent Pinchart
` (4 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index e8db56cc98f4..db31baecde7d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -49,14 +49,17 @@ struct rcar_mipi_dsi {
unsigned int lanes;
};
-#define bridge_to_rcar_mipi_dsi(b) \
- container_of(b, struct rcar_mipi_dsi, bridge)
+static inline struct rcar_mipi_dsi *
+bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct rcar_mipi_dsi, bridge);
+}
-#define connector_to_rcar_mipi_dsi(c) \
- container_of(c, struct rcar_mipi_dsi, connector)
-
-#define host_to_rcar_mipi_dsi(c) \
- container_of(c, struct rcar_mipi_dsi, host)
+static inline struct rcar_mipi_dsi *
+host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
+{
+ return container_of(host, struct rcar_mipi_dsi, host);
+}
static const u32 phtw[] = {
0x01020114, 0x01600115, /* General testing */
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 13/15] drm: rcar-du: dsi: Various style and typo fixes
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (11 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 12/15] drm: rcar-du: dsi: Turn container_of() wrappers to inline functions Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 14/15] drm: rcar-du: dsi: Use read_poll_timeout() Laurent Pinchart
` (3 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 148 ++++++++++++------------
1 file changed, 71 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index db31baecde7d..2ac4171e6c6a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -78,27 +78,27 @@ static const u32 phtw2[] = {
};
static const u32 hsfreqrange_table[][2] = {
- {80000000, 0x00}, {90000000, 0x10}, {100000000, 0x20},
- {110000000, 0x30}, {120000000, 0x01}, {130000000, 0x11},
- {140000000, 0x21}, {150000000, 0x31}, {160000000, 0x02},
- {170000000, 0x12}, {180000000, 0x22}, {190000000, 0x32},
- {205000000, 0x03}, {220000000, 0x13}, {235000000, 0x23},
- {250000000, 0x33}, {275000000, 0x04}, {300000000, 0x14},
- {325000000, 0x25}, {350000000, 0x35}, {400000000, 0x05},
- {450000000, 0x16}, {500000000, 0x26}, {550000000, 0x37},
- {600000000, 0x07}, {650000000, 0x18}, {700000000, 0x28},
- {750000000, 0x39}, {800000000, 0x09}, {850000000, 0x19},
- {900000000, 0x29}, {950000000, 0x3a}, {1000000000, 0x0a},
- {1050000000, 0x1a}, {1100000000, 0x2a}, {1150000000, 0x3b},
- {1200000000, 0x0b}, {1250000000, 0x1b}, {1300000000, 0x2b},
- {1350000000, 0x3c}, {1400000000, 0x0c}, {1450000000, 0x1c},
- {1500000000, 0x2c}, {1550000000, 0x3d}, {1600000000, 0x0d},
- {1650000000, 0x1d}, {1700000000, 0x2e}, {1750000000, 0x3e},
- {1800000000, 0x0e}, {1850000000, 0x1e}, {1900000000, 0x2f},
- {1950000000, 0x3f}, {2000000000, 0x0f}, {2050000000, 0x40},
- {2100000000, 0x41}, {2150000000, 0x42}, {2200000000, 0x43},
- {2250000000, 0x44}, {2300000000, 0x45}, {2350000000, 0x46},
- {2400000000, 0x47}, {2450000000, 0x48}, {2500000000, 0x49},
+ { 80000000, 0x00 }, { 90000000, 0x10 }, { 100000000, 0x20 },
+ { 110000000, 0x30 }, { 120000000, 0x01 }, { 130000000, 0x11 },
+ { 140000000, 0x21 }, { 150000000, 0x31 }, { 160000000, 0x02 },
+ { 170000000, 0x12 }, { 180000000, 0x22 }, { 190000000, 0x32 },
+ { 205000000, 0x03 }, { 220000000, 0x13 }, { 235000000, 0x23 },
+ { 250000000, 0x33 }, { 275000000, 0x04 }, { 300000000, 0x14 },
+ { 325000000, 0x25 }, { 350000000, 0x35 }, { 400000000, 0x05 },
+ { 450000000, 0x16 }, { 500000000, 0x26 }, { 550000000, 0x37 },
+ { 600000000, 0x07 }, { 650000000, 0x18 }, { 700000000, 0x28 },
+ { 750000000, 0x39 }, { 800000000, 0x09 }, { 850000000, 0x19 },
+ { 900000000, 0x29 }, { 950000000, 0x3a }, { 1000000000, 0x0a },
+ { 1050000000, 0x1a }, { 1100000000, 0x2a }, { 1150000000, 0x3b },
+ { 1200000000, 0x0b }, { 1250000000, 0x1b }, { 1300000000, 0x2b },
+ { 1350000000, 0x3c }, { 1400000000, 0x0c }, { 1450000000, 0x1c },
+ { 1500000000, 0x2c }, { 1550000000, 0x3d }, { 1600000000, 0x0d },
+ { 1650000000, 0x1d }, { 1700000000, 0x2e }, { 1750000000, 0x3e },
+ { 1800000000, 0x0e }, { 1850000000, 0x1e }, { 1900000000, 0x2f },
+ { 1950000000, 0x3f }, { 2000000000, 0x0f }, { 2050000000, 0x40 },
+ { 2100000000, 0x41 }, { 2150000000, 0x42 }, { 2200000000, 0x43 },
+ { 2250000000, 0x44 }, { 2300000000, 0x45 }, { 2350000000, 0x46 },
+ { 2400000000, 0x47 }, { 2450000000, 0x48 }, { 2500000000, 0x49 },
{ /* sentinel */ },
};
@@ -109,17 +109,17 @@ struct vco_cntrl_value {
};
static const struct vco_cntrl_value vco_cntrl_table[] = {
- { .min_freq = 40000000, .max_freq = 55000000, .value = 0x3f},
- { .min_freq = 52500000, .max_freq = 80000000, .value = 0x39},
- { .min_freq = 80000000, .max_freq = 110000000, .value = 0x2f},
- { .min_freq = 105000000, .max_freq = 160000000, .value = 0x29},
- { .min_freq = 160000000, .max_freq = 220000000, .value = 0x1f},
- { .min_freq = 210000000, .max_freq = 320000000, .value = 0x19},
- { .min_freq = 320000000, .max_freq = 440000000, .value = 0x0f},
- { .min_freq = 420000000, .max_freq = 660000000, .value = 0x09},
- { .min_freq = 630000000, .max_freq = 1149000000, .value = 0x03},
- { .min_freq = 1100000000, .max_freq = 1152000000, .value = 0x01},
- { .min_freq = 1150000000, .max_freq = 1250000000, .value = 0x01},
+ { .min_freq = 40000000, .max_freq = 55000000, .value = 0x3f },
+ { .min_freq = 52500000, .max_freq = 80000000, .value = 0x39 },
+ { .min_freq = 80000000, .max_freq = 110000000, .value = 0x2f },
+ { .min_freq = 105000000, .max_freq = 160000000, .value = 0x29 },
+ { .min_freq = 160000000, .max_freq = 220000000, .value = 0x1f },
+ { .min_freq = 210000000, .max_freq = 320000000, .value = 0x19 },
+ { .min_freq = 320000000, .max_freq = 440000000, .value = 0x0f },
+ { .min_freq = 420000000, .max_freq = 660000000, .value = 0x09 },
+ { .min_freq = 630000000, .max_freq = 1149000000, .value = 0x03 },
+ { .min_freq = 1100000000, .max_freq = 1152000000, .value = 0x01 },
+ { .min_freq = 1150000000, .max_freq = 1250000000, .value = 0x01 },
{ /* sentinel */ },
};
@@ -152,8 +152,7 @@ static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
for (timeout = 10; timeout > 0; --timeout) {
status = rcar_mipi_dsi_read(dsi, PHTW);
- if (!(status & PHTW_DWEN) &&
- !(status & PHTW_CWEN))
+ if (!(status & PHTW_DWEN) && !(status & PHTW_CWEN))
break;
usleep_range(1000, 2000);
@@ -181,9 +180,9 @@ struct dsi_setup_info {
unsigned int n;
};
-static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *dsi,
- struct clk *clk, unsigned long target,
- struct dsi_setup_info *setup_info)
+static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
+ struct clk *clk, unsigned long target,
+ struct dsi_setup_info *setup_info)
{
const struct vco_cntrl_value *vco_cntrl;
@@ -199,16 +198,15 @@ static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *dsi,
* Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
* The range out Fout is [40 - 1250] Mhz
*/
- fout_target = target *
- mipi_dsi_pixel_format_to_bpp(dsi->format) /
- (2 * dsi->lanes);
+ fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
+ / (2 * dsi->lanes);
if (fout_target < 40000000 || fout_target > 1250000000)
return;
/* Find vco_cntrl */
for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
if (fout_target > vco_cntrl->min_freq &&
- fout_target <= vco_cntrl->max_freq) {
+ fout_target <= vco_cntrl->max_freq) {
setup_info->vco_cntrl = vco_cntrl->value;
if (fout_target >= 1150000000)
setup_info->prop_cntrl = 0x0c;
@@ -247,7 +245,7 @@ static void rcar_mipi_dsi_parametters_calc(struct rcar_mipi_dsi *dsi,
for (m = 64; m < 626; m++) {
fout = fpfd * m / divider;
err = abs((long)(fout - fout_target) * 10000 /
- (long)fout_target);
+ (long)fout_target);
if (err < setup_info->err) {
setup_info->m = m - 2;
setup_info->n = n - 1;
@@ -283,43 +281,40 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi)
/* Configuration for Pixel Stream and Packet Header */
if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
- rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
- TXVMPSPHSETR_DT_RGB24);
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
- rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
- TXVMPSPHSETR_DT_RGB18);
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
- rcar_mipi_dsi_write(dsi, TXVMPSPHSETR,
- TXVMPSPHSETR_DT_RGB16);
+ rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
else {
dev_warn(dsi->dev, "unsupported format");
return;
}
/* Configuration for Blanking sequence and Input Pixel */
- setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN |
- TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES |
- TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
+ setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
+ | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
+ | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
/* Configuration for Video Parameters */
- vprmset0r = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ?
- TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW) |
- ((mode->flags & DRM_MODE_FLAG_PHSYNC) ?
- TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW) |
- TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
+ vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
+ TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
+ | (mode->flags & DRM_MODE_FLAG_PHSYNC ?
+ TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
+ | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
- vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay) |
- TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
+ vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
+ | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
- vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay) |
- TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
+ vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
+ | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
- vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay) |
- TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
+ vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
+ | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
- vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay) |
- TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
+ vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
+ | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
@@ -347,9 +342,9 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi)
return -EINVAL;
}
- /* Parametters Calulation */
- rcar_mipi_dsi_parametters_calc(dsi, dsi->clocks.extal,
- mode->clock * 1000, &setup_info);
+ /* Parameters Calculation */
+ rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.extal,
+ mode->clock * 1000, &setup_info);
/* LPCLK enable */
rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
@@ -380,12 +375,12 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi)
rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
- clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n) |
- CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
- clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl) |
- CLOCKSET3_INT_CNTRL(0) |
- CLOCKSET3_CPBIAS_CNTRL(0x10) |
- CLOCKSET3_GMP_CNTRL(1);
+ clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n)
+ | CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
+ clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl)
+ | CLOCKSET3_INT_CNTRL(0)
+ | CLOCKSET3_CPBIAS_CNTRL(0x10)
+ | CLOCKSET3_GMP_CNTRL(1);
rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
@@ -436,8 +431,8 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi)
dev_warn(dsi->dev, "unsupported format");
return -EINVAL;
}
- vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div) |
- VCLKSET_LANE(dsi->lanes - 1);
+ vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div)
+ | VCLKSET_LANE(dsi->lanes - 1);
rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
@@ -498,8 +493,7 @@ static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
/* Check status of Tranmission */
for (timeout = 10; timeout > 0; --timeout) {
status = rcar_mipi_dsi_read(dsi, LINKSR);
- if (!(status & LINKSR_LPBUSY) &&
- !(status & LINKSR_HSBUSY)) {
+ if (!(status & LINKSR_LPBUSY) && !(status & LINKSR_HSBUSY)) {
rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
break;
}
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 14/15] drm: rcar-du: dsi: Use read_poll_timeout()
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (12 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 13/15] drm: rcar-du: dsi: Various style and typo fixes Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 3:46 ` [RFC PATCH 15/15] drm: rcar-du: dsi: Include the DSI header Laurent Pinchart
` (2 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 114 +++++++++---------------
1 file changed, 43 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 2ac4171e6c6a..381b5bc9bce1 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -8,6 +8,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -145,25 +146,21 @@ static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
{
- unsigned int timeout;
u32 status;
+ int ret;
rcar_mipi_dsi_write(dsi, PHTW, phtw);
- for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(dsi, PHTW);
- if (!(status & PHTW_DWEN) && !(status & PHTW_CWEN))
- break;
-
- usleep_range(1000, 2000);
- }
-
- if (!timeout) {
- dev_err(dsi->dev, "failed to test phtw with data %x\n", phtw);
- return -ETIMEDOUT;
+ ret = read_poll_timeout(rcar_mipi_dsi_read, status,
+ !(status & (PHTW_DWEN | PHTW_CWEN)),
+ 2000, 10000, false, dsi, PHTW);
+ if (ret < 0) {
+ dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
+ phtw);
+ return ret;
}
- return timeout;
+ return ret;
}
/* -----------------------------------------------------------------------------
@@ -458,86 +455,61 @@ static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
* In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
* write how to check. So we skip this check in this patch
*/
- unsigned int timeout;
u32 status;
+ int ret;
- /* Start HS clock */
+ /* Start HS clock. */
rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
- for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(dsi, PPICLSR);
-
- if (status & PPICLSR_TOHS) {
- rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
- break;
- }
-
- usleep_range(1000, 2000);
- }
-
- if (!timeout) {
+ ret = read_poll_timeout(rcar_mipi_dsi_read, status,
+ status & PPICLSR_TOHS,
+ 2000, 10000, false, dsi, PPICLSR);
+ if (ret < 0) {
dev_err(dsi->dev, "failed to enable HS clock\n");
- return -ETIMEDOUT;
+ return ret;
}
- dev_dbg(dsi->dev, "Start High Speed Clock");
+ rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
return 0;
}
static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
{
- unsigned int timeout;
u32 status;
-
- /* Check status of Tranmission */
- for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(dsi, LINKSR);
- if (!(status & LINKSR_LPBUSY) && !(status & LINKSR_HSBUSY)) {
- rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
- break;
- }
-
- usleep_range(1000, 2000);
+ int ret;
+
+ /* Wait for the link to be ready. */
+ ret = read_poll_timeout(rcar_mipi_dsi_read, status,
+ !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
+ 2000, 10000, false, dsi, LINKSR);
+ if (ret < 0) {
+ dev_err(dsi->dev, "Link failed to become ready\n");
+ return ret;
}
- if (!timeout) {
- dev_err(dsi->dev, "Failed to enable Video clock\n");
- return -ETIMEDOUT;
- }
+ /* De-assert video FIFO clear. */
+ rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
- /* Check Clear Video mode FIFO */
- for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(dsi, TXVMSR);
- if (status & TXVMSR_VFRDY) {
- rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
- break;
- }
-
- usleep_range(1000, 2000);
+ ret = read_poll_timeout(rcar_mipi_dsi_read, status,
+ status & TXVMSR_VFRDY,
+ 2000, 10000, false, dsi, TXVMSR);
+ if (ret < 0) {
+ dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
+ return ret;
}
- if (!timeout) {
- dev_err(dsi->dev, "Failed to enable Video clock\n");
- return -ETIMEDOUT;
- }
+ /* Enable transmission in video mode. */
+ rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
- /* Check Video transmission */
- for (timeout = 10; timeout > 0; --timeout) {
- status = rcar_mipi_dsi_read(dsi, TXVMSR);
- if (status & TXVMSR_RDY)
- break;
-
- usleep_range(1000, 2000);
- }
-
- if (!timeout) {
- dev_err(dsi->dev, "Failed to enable Video clock\n");
- return -ETIMEDOUT;
+ ret = read_poll_timeout(rcar_mipi_dsi_read, status,
+ status & TXVMSR_RDY,
+ 2000, 10000, false, dsi, TXVMSR);
+ if (ret < 0) {
+ dev_err(dsi->dev, "Failed to enable video transmission\n");
+ return ret;
}
- dev_dbg(dsi->dev, "Start video transferring");
-
return 0;
}
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 15/15] drm: rcar-du: dsi: Include the DSI header
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (13 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 14/15] drm: rcar-du: dsi: Use read_poll_timeout() Laurent Pinchart
@ 2021-06-23 3:46 ` Laurent Pinchart
2021-06-23 11:00 ` [RFC PATCH 16/15] rcar-du: dsi: Unexport clock functions Kieran Bingham
2021-06-23 11:23 ` [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Kieran Bingham
16 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 3:46 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Kieran Bingham, LUU HOAI
From: Kieran Bingham <kieran.bingham@ideasonboard.com>
The rcar_mipi_dsi.h header declares the interface for the CRTC component
to use.
The lack of inclusion of the header causes a compiler warning.
Include the header correctly at the beginning of the component to ensure
consistency.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
---
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 381b5bc9bce1..f708bcf5984c 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Renesas Electronics Corporation
*/
+#include "rcar_mipi_dsi.h"
+
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 23+ messages in thread* [RFC PATCH 16/15] rcar-du: dsi: Unexport clock functions
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (14 preceding siblings ...)
2021-06-23 3:46 ` [RFC PATCH 15/15] drm: rcar-du: dsi: Include the DSI header Laurent Pinchart
@ 2021-06-23 11:00 ` Kieran Bingham
2021-06-23 13:11 ` Laurent Pinchart
2021-06-23 11:23 ` [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Kieran Bingham
16 siblings, 1 reply; 23+ messages in thread
From: Kieran Bingham @ 2021-06-23 11:00 UTC (permalink / raw)
To: linux-renesas-soc, Laurent Pinchart; +Cc: LUU HOAI, Kieran Bingham
The rcar_mipi_dsi_clk_enable and rcar_mipi_dsi_clk_disable functions
are exported so that they can be operated directly from the DU CRTC.
This is not required, and can be handled directly through the bridge.
The functionality is split while moving, as the rcar_mipi_dsi_startup()
and rcar_mipi_dsi_shutdown() are not handling the clocks and so
shouldn't be left in the clock specific functions.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
---
This patch extends Laurent's series, and would ultimately be squashed
into the DSI driver.
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 98 ++++++++++++++-----------
drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h | 26 -------
2 files changed, 54 insertions(+), 70 deletions(-)
delete mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
index 026026bbb367..4c5ef4de0ea7 100644
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
@@ -5,8 +5,6 @@
* Copyright (C) 2020 Renesas Electronics Corporation
*/
-#include "rcar_mipi_dsi.h"
-
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -451,6 +449,33 @@ static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
dev_dbg(dsi->dev, "DSI device is shutdown\n");
}
+static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
+{
+ int ret;
+
+ reset_control_deassert(dsi->rstc);
+
+ ret = clk_prepare_enable(dsi->clocks.mod);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(dsi->clocks.dsi);
+ if (ret < 0) {
+ clk_disable_unprepare(dsi->clocks.mod);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
+{
+ clk_disable_unprepare(dsi->clocks.dsi);
+ clk_disable_unprepare(dsi->clocks.mod);
+
+ reset_control_assert(dsi->rstc);
+}
+
static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
{
/*
@@ -542,13 +567,38 @@ static void rcar_mipi_dsi_enable(struct drm_bridge *bridge)
struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
int ret;
+ ret = rcar_mipi_dsi_clk_enable(dsi);
+ if (ret < 0) {
+ dev_err(dsi->dev, "failed to enable DSI clocks\n");
+ return;
+ }
+
+ ret = rcar_mipi_dsi_startup(dsi);
+ if (ret < 0)
+ goto err_dsi_startup;
+
rcar_mipi_dsi_set_display_timing(dsi);
ret = rcar_mipi_dsi_start_hs_clock(dsi);
if (ret < 0)
- return;
+ goto err_dsi_start_hs;
rcar_mipi_dsi_start_video(dsi);
+
+ return;
+
+err_dsi_start_hs:
+ rcar_mipi_dsi_shutdown(dsi);
+err_dsi_startup:
+ rcar_mipi_dsi_clk_disable(dsi);
+}
+
+static void rcar_mipi_dsi_disable(struct drm_bridge *bridge)
+{
+ struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
+
+ rcar_mipi_dsi_shutdown(dsi);
+ rcar_mipi_dsi_clk_disable(dsi);
}
static enum drm_mode_status
@@ -566,6 +616,7 @@ static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
.attach = rcar_mipi_dsi_attach,
.mode_set = rcar_mipi_dsi_mode_set,
.enable = rcar_mipi_dsi_enable,
+ .disable = rcar_mipi_dsi_disable,
.mode_valid = rcar_mipi_dsi_bridge_mode_valid,
};
@@ -573,47 +624,6 @@ static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
* Clock Setting
*/
-int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
-{
- struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
- int ret;
-
- reset_control_deassert(dsi->rstc);
-
- ret = clk_prepare_enable(dsi->clocks.mod);
- if (ret < 0)
- return ret;
-
- ret = clk_prepare_enable(dsi->clocks.dsi);
- if (ret < 0)
- goto err_clock_mod;
-
- ret = rcar_mipi_dsi_startup(dsi);
- if (ret < 0)
- goto err_clock_dsi;
-
- return 0;
-
-err_clock_dsi:
- clk_disable_unprepare(dsi->clocks.dsi);
-err_clock_mod:
- clk_disable_unprepare(dsi->clocks.mod);
- return ret;
-}
-EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_enable);
-
-void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge)
-{
- struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
-
- rcar_mipi_dsi_shutdown(dsi);
-
- clk_disable_unprepare(dsi->clocks.dsi);
- clk_disable_unprepare(dsi->clocks.mod);
-
- reset_control_assert(dsi->rstc);
-}
-EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_disable);
/* -----------------------------------------------------------------------------
* Host setting
diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
deleted file mode 100644
index a937ab7ddcd4..000000000000
--- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * rcar_mipi_dsi.h -- R-Car MIPI_DSI Encoder
- *
- * Copyright (C) 2020 Renesas Electronics Corporation
- */
-
-#ifndef __RCAR_MIPI_DSI_H__
-#define __RCAR_MIPI_DSI_H__
-
-struct drm_bridge;
-
-#if IS_ENABLED(CONFIG_DRM_RCAR_MIPI_DSI)
-int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge);
-void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge);
-
-#else
-static inline int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
-{
- return -ENOSYS;
-}
-static inline void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge) { }
-
-#endif /* CONFIG_DRM_RCAR_MIPI_DSI */
-
-#endif /* __RCAR_MIPI_DSI_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RFC PATCH 16/15] rcar-du: dsi: Unexport clock functions
2021-06-23 11:00 ` [RFC PATCH 16/15] rcar-du: dsi: Unexport clock functions Kieran Bingham
@ 2021-06-23 13:11 ` Laurent Pinchart
0 siblings, 0 replies; 23+ messages in thread
From: Laurent Pinchart @ 2021-06-23 13:11 UTC (permalink / raw)
To: Kieran Bingham; +Cc: linux-renesas-soc, LUU HOAI
Hi Kieran,
Thank you for the patch.
On Wed, Jun 23, 2021 at 12:00:59PM +0100, Kieran Bingham wrote:
> The rcar_mipi_dsi_clk_enable and rcar_mipi_dsi_clk_disable functions
> are exported so that they can be operated directly from the DU CRTC.
>
> This is not required, and can be handled directly through the bridge.
>
> The functionality is split while moving, as the rcar_mipi_dsi_startup()
> and rcar_mipi_dsi_shutdown() are not handling the clocks and so
> shouldn't be left in the clock specific functions.
>
> Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
> ---
>
> This patch extends Laurent's series, and would ultimately be squashed
> into the DSI driver.
>
>
>
> drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 98 ++++++++++++++-----------
> drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h | 26 -------
> 2 files changed, 54 insertions(+), 70 deletions(-)
> delete mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> index 026026bbb367..4c5ef4de0ea7 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> @@ -5,8 +5,6 @@
> * Copyright (C) 2020 Renesas Electronics Corporation
> */
>
> -#include "rcar_mipi_dsi.h"
> -
> #include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/io.h>
> @@ -451,6 +449,33 @@ static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
> dev_dbg(dsi->dev, "DSI device is shutdown\n");
> }
>
> +static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
> +{
> + int ret;
> +
> + reset_control_deassert(dsi->rstc);
> +
> + ret = clk_prepare_enable(dsi->clocks.mod);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_prepare_enable(dsi->clocks.dsi);
> + if (ret < 0) {
> + clk_disable_unprepare(dsi->clocks.mod);
> + return ret;
> + }
I'll add a reset_control_assert() in the error paths.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> +
> + return 0;
> +}
> +
> +static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
> +{
> + clk_disable_unprepare(dsi->clocks.dsi);
> + clk_disable_unprepare(dsi->clocks.mod);
> +
> + reset_control_assert(dsi->rstc);
> +}
> +
> static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
> {
> /*
> @@ -542,13 +567,38 @@ static void rcar_mipi_dsi_enable(struct drm_bridge *bridge)
> struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
> int ret;
>
> + ret = rcar_mipi_dsi_clk_enable(dsi);
> + if (ret < 0) {
> + dev_err(dsi->dev, "failed to enable DSI clocks\n");
> + return;
> + }
> +
> + ret = rcar_mipi_dsi_startup(dsi);
> + if (ret < 0)
> + goto err_dsi_startup;
> +
> rcar_mipi_dsi_set_display_timing(dsi);
>
> ret = rcar_mipi_dsi_start_hs_clock(dsi);
> if (ret < 0)
> - return;
> + goto err_dsi_start_hs;
>
> rcar_mipi_dsi_start_video(dsi);
> +
> + return;
> +
> +err_dsi_start_hs:
> + rcar_mipi_dsi_shutdown(dsi);
> +err_dsi_startup:
> + rcar_mipi_dsi_clk_disable(dsi);
> +}
> +
> +static void rcar_mipi_dsi_disable(struct drm_bridge *bridge)
> +{
> + struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
> +
> + rcar_mipi_dsi_shutdown(dsi);
> + rcar_mipi_dsi_clk_disable(dsi);
> }
>
> static enum drm_mode_status
> @@ -566,6 +616,7 @@ static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
> .attach = rcar_mipi_dsi_attach,
> .mode_set = rcar_mipi_dsi_mode_set,
> .enable = rcar_mipi_dsi_enable,
> + .disable = rcar_mipi_dsi_disable,
> .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
> };
>
> @@ -573,47 +624,6 @@ static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
> * Clock Setting
> */
>
> -int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
> -{
> - struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
> - int ret;
> -
> - reset_control_deassert(dsi->rstc);
> -
> - ret = clk_prepare_enable(dsi->clocks.mod);
> - if (ret < 0)
> - return ret;
> -
> - ret = clk_prepare_enable(dsi->clocks.dsi);
> - if (ret < 0)
> - goto err_clock_mod;
> -
> - ret = rcar_mipi_dsi_startup(dsi);
> - if (ret < 0)
> - goto err_clock_dsi;
> -
> - return 0;
> -
> -err_clock_dsi:
> - clk_disable_unprepare(dsi->clocks.dsi);
> -err_clock_mod:
> - clk_disable_unprepare(dsi->clocks.mod);
> - return ret;
> -}
> -EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_enable);
> -
> -void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge)
> -{
> - struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
> -
> - rcar_mipi_dsi_shutdown(dsi);
> -
> - clk_disable_unprepare(dsi->clocks.dsi);
> - clk_disable_unprepare(dsi->clocks.mod);
> -
> - reset_control_assert(dsi->rstc);
> -}
> -EXPORT_SYMBOL_GPL(rcar_mipi_dsi_clk_disable);
>
> /* -----------------------------------------------------------------------------
> * Host setting
> diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
> deleted file mode 100644
> index a937ab7ddcd4..000000000000
> --- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * rcar_mipi_dsi.h -- R-Car MIPI_DSI Encoder
> - *
> - * Copyright (C) 2020 Renesas Electronics Corporation
> - */
> -
> -#ifndef __RCAR_MIPI_DSI_H__
> -#define __RCAR_MIPI_DSI_H__
> -
> -struct drm_bridge;
> -
> -#if IS_ENABLED(CONFIG_DRM_RCAR_MIPI_DSI)
> -int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge);
> -void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge);
> -
> -#else
> -static inline int rcar_mipi_dsi_clk_enable(struct drm_bridge *bridge)
> -{
> - return -ENOSYS;
> -}
> -static inline void rcar_mipi_dsi_clk_disable(struct drm_bridge *bridge) { }
> -
> -#endif /* CONFIG_DRM_RCAR_MIPI_DSI */
> -
> -#endif /* __RCAR_MIPI_DSI_H__ */
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [RFC PATCH 00/15] R-Car V3U: DSI encoder driver
2021-06-23 3:46 [RFC PATCH 00/15] R-Car V3U: DSI encoder driver Laurent Pinchart
` (15 preceding siblings ...)
2021-06-23 11:00 ` [RFC PATCH 16/15] rcar-du: dsi: Unexport clock functions Kieran Bingham
@ 2021-06-23 11:23 ` Kieran Bingham
16 siblings, 0 replies; 23+ messages in thread
From: Kieran Bingham @ 2021-06-23 11:23 UTC (permalink / raw)
To: Laurent Pinchart, linux-renesas-soc; +Cc: LUU HOAI
Hi Laurent,
These all look fine to me independently, so for the set:
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
and of course as I've been using them
Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com
As you've seen, I've posted an update to simplify the DSI startup so
that it doesn't need to be called directly from the crtc, which also
removes the header addition change I had in this series ;-)
Squashing these down, I still see a few checkpatch issues, but I think
they can be tackled as part of squashing so they don't need discussing here.
--
Kieran
On 23/06/2021 04:46, Laurent Pinchart wrote:
> Hello,
>
> This patch series adds a driver for the DSI encoder found in the R-Car
> V3U SoC, which is the first SoC in the family that supports DSI.
>
> The driver is based on an implementation from the BSP written by Luu
> Hoai, taken as-is in patch 02/15. The subsequent patches are cleanups.
> I'm posting this version as an RFC to allow Luu to review the cleanups,
> if desired. I've thus restricted the audience to the linux-renesas-soc
> mailing list. The next, non-RFC version will squash all driver patches
> into one and will be posted to dri-devel.
>
> There's one open question related to whether the DSI encoder clock needs
> to be controlled explicitly by the DU or not. Depending on the outcome
> of the tests, the driver could be further simplified.
>
> Kieran Bingham (2):
> drm: rcar-du: dsi: Use the correct compatible
> drm: rcar-du: dsi: Include the DSI header
>
> LUU HOAI (1):
> drm: rcar-du: Add R-Car DSI driver
>
> Laurent Pinchart (12):
> dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX
> drm: rcar-du: dsi: Reorganize probe function
> drm: rcar-du: dsi: Use dev_err_probe()
> drm: rcar-du: dsi: Shorten mipi_dsi variable name to dsi
> drm: rcar-du: dsi: Use dsi->dev consistently in probe()
> drm: rcar-du: dsi: Get next bridge in probe()
> drm: rcar-du: dsi: Simplify DT parsing
> drm: rcar-du: dsi: Add error handling in rcar_mipi_dsi_clk_enable()
> drm: rcar-du: dsi: Simplify error handling in rcar_mipi_dsi_enable()
> drm: rcar-du: dsi: Turn container_of() wrappers to inline functions
> drm: rcar-du: dsi: Various style and typo fixes
> drm: rcar-du: dsi: Use read_poll_timeout()
>
> .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 +++
> drivers/gpu/drm/rcar-du/Kconfig | 6 +
> drivers/gpu/drm/rcar-du/Makefile | 1 +
> drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 813 ++++++++++++++++++
> drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h | 26 +
> drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h | 172 ++++
> 6 files changed, 1136 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
> create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi.h
> create mode 100644 drivers/gpu/drm/rcar-du/rcar_mipi_dsi_regs.h
>
^ permalink raw reply [flat|nested] 23+ messages in thread