* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
@ 2018-04-06 22:24 Oscar Mateo
2018-04-06 22:24 ` [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
` (24 more replies)
0 siblings, 25 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:24 UTC (permalink / raw)
To: intel-gfx
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 19 ++++++++++++++++++-
6 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..1a4801e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2458,6 +2458,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+ else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6..6cd2f2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7184,6 +7184,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..ba8c137 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1467,6 +1467,29 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
return 0;
}
+static int icl_init_workarounds(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int init_workarounds_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1494,6 +1517,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
err = cfl_init_workarounds(engine);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_init_workarounds(engine);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_init_workarounds(engine);
else
err = 0;
if (err)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f60b61b..6ec4abf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1573,6 +1573,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19e82aa..4f4c7ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8499,6 +8499,21 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
CNP_PWM_CGE_GATING_DISABLE);
}
+static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 val;
@@ -9015,7 +9030,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-04-06 22:24 ` Oscar Mateo
2018-04-06 22:24 ` [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
` (23 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:24 UTC (permalink / raw)
To: intel-gfx
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cd2f2a..cd5da2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8196,8 +8196,9 @@ enum {
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
-#define GEN8_GARBCNTL _MMIO(0xB004)
-#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
+#define GEN8_GARBCNTL _MMIO(0xB004)
+#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f4c7ae..d1b98ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8512,6 +8512,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+ /* Wa_1405543622:icl
+ * Formerly known as WaGAPZPriorityScheme
+ */
+ I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+ GEN11_ARBITRATION_PRIO_ORDER_MASK));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-04-06 22:24 ` [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
@ 2018-04-06 22:24 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
` (22 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:24 UTC (permalink / raw)
To: intel-gfx
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd5da2b..78abb49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8200,6 +8200,11 @@ enum {
#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
+#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
+#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define GEN11_HASH_CTRL_BIT4 (1 << 12)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1b98ae..03c5de3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8518,6 +8518,11 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
*/
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+ /* WaModifyGamTlbPartitioning:icl */
+ I915_WRITE(GEN11_GACB_PERF_CTRL,
+ ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-04-06 22:24 ` [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
2018-04-06 22:24 ` [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
` (21 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++----
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78abb49..10ed35f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8199,6 +8199,12 @@ enum {
#define GEN8_GARBCNTL _MMIO(0xB004)
#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
+#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
+#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 0)
+#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x3f << 5)
#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03c5de3..58974fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,11 +8513,23 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
- /* Wa_1405543622:icl
- * Formerly known as WaGAPZPriorityScheme
+ I915_WRITE(GEN8_GARBCNTL,
+ /* Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
+ */
+ ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+ GEN11_HASH_CTRL_EXCL_BIT0 |
+ /* Wa_1405543622:icl
+ * Formerly known as WaGAPZPriorityScheme
+ */
+ GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+ /* Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
*/
- I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
- GEN11_ARBITRATION_PRIO_ORDER_MASK));
+ I915_WRITE(GEN11_GLBLINVL,
+ ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0));
/* WaModifyGamTlbPartitioning:icl */
I915_WRITE(GEN11_GACB_PERF_CTRL,
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (2 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
` (20 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10ed35f..699135b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7178,8 +7178,9 @@ enum {
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
#define GEN8_L3SQCREG4 _MMIO(0xb118)
-#define GEN8_LQSC_RO_PERF_DIS (1<<27)
-#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
+#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
+#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
+#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58974fa..84d9910 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,6 +8513,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+ /* Wa_1405733216:icl
+ * Formerly known as WaDisableCleanEvicts
+ */
+ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+ GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
/* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (3 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
` (19 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 699135b..67664d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8249,8 +8249,9 @@ enum {
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
-#define DOP_CLOCK_GATING_DISABLE (1<<0)
-#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
+#define DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
+#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index ba8c137..eb2f46e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1487,6 +1487,13 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
*/
WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+ /* Wa_2006611047:icl (pre-prod)
+ * Formerly known as WaDisableImprovedTdlClkGating
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (4 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
` (18 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67664d0..cb5d117 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8212,6 +8212,10 @@ enum {
#define GEN11_HASH_CTRL_BIT0 (1 << 0)
#define GEN11_HASH_CTRL_BIT4 (1 << 12)
+#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84d9910..3843c28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8541,6 +8541,13 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+ /* Wa_1405766107:icl
+ * Formerly known as WaCL2SFHalfMaxAlloc
+ */
+ I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 08/22] drm/i915/icl: WaDisCtxReload
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (5 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
` (17 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb5d117..004a4db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8216,6 +8216,9 @@ enum {
#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3843c28..c5bf71b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,6 +8519,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+ /* Wa_220166154:icl
+ * Formerly known as WaDisCtxReload
+ */
+ I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+ GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
/* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (6 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
` (16 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index eb2f46e..884df09 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1470,6 +1470,7 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
static int icl_init_workarounds(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ int ret;
/* Wa_1604370585:icl (pre-prod)
* Formerly known as WaPushConstantDereferenceHoldDisable
@@ -1494,6 +1495,11 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+ /* WaSendPushConstantsFromMMIO:icl */
+ ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (7 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
` (15 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 884df09..ada80c1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1500,6 +1500,11 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
+ /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+ ret = wa_ring_whitelist_reg(engine, HALF_SLICE_CHICKEN2);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (8 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
` (14 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index ada80c1..7fb7283 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1505,6 +1505,11 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ ret = wa_ring_whitelist_reg(engine, GEN9_HALF_SLICE_CHICKEN7);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (9 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
` (13 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 004a4db..04f2dd5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8219,6 +8219,9 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7fb7283..9400f4f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1510,6 +1510,14 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
+ /* WaAllowUmdWriteTRTTRootTable:icl */
+ ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+ if (ret)
+ return ret;
+ ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (10 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
` (12 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04f2dd5..f2ae3cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8222,6 +8222,8 @@ enum {
#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 9400f4f..8337301 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1518,6 +1518,11 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
+ /* WaAllowUMDToModifySamplerMode:icl */
+ ret = wa_ring_whitelist_reg(engine, GEN10_SAMPLER_MODE);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (11 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 15/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
` (11 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ae3cf..3bec6b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7150,6 +7150,7 @@ enum {
#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8337301..d0c382e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1495,6 +1495,10 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+ /* WaEnableStateCacheRedirectToCS:icl */
+ WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 15/22] drm/i915/icl: Enable Sampler DFR
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (12 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 16/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
` (10 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Praveen Paneri
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3bec6b1..f2a42a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8220,6 +8220,9 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define DFR_DISABLE (1 << 9)
+
#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c5bf71b..8f1d028 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8505,6 +8505,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+ /* This is not an Wa. Enable to reduce Sampler power */
+ I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+ (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 16/22] drm/i915/icl: Wa_1405779004
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (13 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 15/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
` (9 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2a42a3..18f8c41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3825,6 +3825,7 @@ enum {
#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
+#define MSCUNIT_CLKGATE_DIS (1 << 10)
#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define GWUNIT_CLKGATE_DIS (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f1d028..68f1b60 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8558,6 +8558,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+ /* Wa_1405779004:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+ (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+ MSCUNIT_CLKGATE_DIS));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (14 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 16/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 18/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
` (8 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 68f1b60..2b7b88b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8564,6 +8564,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
(I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+ /* Wa_1406680159:icl */
+ /* Wa_2201832410:icl (pre-prod, only until C0) */
+ I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+ (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+ GWUNIT_CLKGATE_DIS));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 18/22] drm/i915/icl: Wa_1604302699
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (15 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 19/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
` (7 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Disable I2M Write for performance reasons.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18f8c41..b1894f6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7174,7 +7174,9 @@ enum {
#define GEN7_L3CNTLREG3 _MMIO(0xB024)
#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
-#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
+#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+#define GEN11_I2M_WRITE_DISABLE (1 << 28)
#define GEN7_L3SQCREG4 _MMIO(0xb034)
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b7b88b..9771f56 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8570,6 +8570,11 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
(I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS));
+
+ /* Wa_1604302699:icl */
+ I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+ (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+ GEN11_I2M_WRITE_DISABLE));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 19/22] drm/i915/icl: Wa_2006665173
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (16 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 18/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 20/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
` (6 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Disable blend embellishment in RCC.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++-------
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1894f6..84e5a59 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7135,13 +7135,17 @@ enum {
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
-#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
+ #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
+ #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
+ #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
+ #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+ #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d0c382e..872dd15 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1499,6 +1499,11 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
GEN11_STATE_CACHE_REDIRECT_TO_CS);
+ /* Wa_2006665173:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 20/22] drm/i915/icl: Wa_1406838659
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (17 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 19/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
` (5 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Disable CGPSF unit clock gating to prevent an issue.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++-----
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84e5a59..af4fee2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3823,15 +3823,18 @@ enum {
* GEN10 clock gating regs
*/
#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
-#define SARBUNIT_CLKGATE_DIS (1 << 5)
-#define RCCUNIT_CLKGATE_DIS (1 << 7)
-#define MSCUNIT_CLKGATE_DIS (1 << 10)
+#define SARBUNIT_CLKGATE_DIS (1 << 5)
+#define RCCUNIT_CLKGATE_DIS (1 << 7)
+#define MSCUNIT_CLKGATE_DIS (1 << 10)
#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
-#define GWUNIT_CLKGATE_DIS (1 << 16)
+#define GWUNIT_CLKGATE_DIS (1 << 16)
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
-#define VFUNIT_CLKGATE_DIS (1 << 20)
+#define VFUNIT_CLKGATE_DIS (1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define CGPSF_CLKGATE_DIS (1 << 3)
/*
* Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9771f56..1acc719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8575,6 +8575,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
(I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE));
+
+ /* Wa_1406838659:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+ I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+ (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+ CGPSF_CLKGATE_DIS));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (18 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 20/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:25 ` [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
` (4 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Avoids a hang during soft reset.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af4fee2..408697b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9703,6 +9703,11 @@ enum skl_power_gate {
#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
+#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
+#define PMFLUSHDONE_LNICRSDROP (1 << 20)
+#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
+#define PMFLUSHDONE_LNEBLK (1 << 22)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1acc719..b1c00e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8581,6 +8581,14 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
(I915_READ(INF_UNIT_LEVEL_CLKGATE) |
CGPSF_CLKGATE_DIS));
+
+ /* WaForwardProgressSoftReset:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ I915_WRITE(GEN10_SCRATCH_LNCF2,
+ (I915_READ(GEN10_SCRATCH_LNCF2) |
+ PMFLUSHDONE_LNICRSDROP |
+ PMFLUSH_GAPL3UNBLOCK |
+ PMFLUSHDONE_LNEBLK));
}
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (19 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-04-06 22:25 ` Oscar Mateo
2018-04-06 22:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
` (3 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-06 22:25 UTC (permalink / raw)
To: intel-gfx
Enables blend optimization for floating point RTs
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 408697b..c5a1b18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2651,6 +2651,9 @@ enum i915_power_well_id {
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
+#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
+#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 872dd15..c35f40b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1504,6 +1504,9 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+ /* WaEnableFloatBlendOptimization:icl */
+ WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (20 preceding siblings ...)
2018-04-06 22:25 ` [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
@ 2018-04-06 22:43 ` Patchwork
2018-04-06 22:58 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
24 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2018-04-06 22:43 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:2467:
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 112 lines checked
dfd92fa235cd drm/i915/icl: WaGAPZPriorityScheme
6b5802730b5d drm/i915/icl: WaModifyGamTlbPartitioning
6c99c36530dd drm/i915/icl: WaL3BankAddressHashing
f3018a4d2c5b drm/i915/icl: WaDisableCleanEvicts
1d0fa9e70616 drm/i915/icl: WaDisableImprovedTdlClkGating
97c509b92d34 drm/i915/icl: WaCL2SFHalfMaxAlloc
3c456f385e81 drm/i915/icl: WaDisCtxReload
117d3028b83a drm/i915/icl: WaSendPushConstantsFromMMIO
18a761359036 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
dfbd6e5e21fe drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
b17203f3ce71 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
1a1f183539f7 drm/i915/icl: WaAllowUMDToModifySamplerMode
81ff9ff8112e drm/i915/icl: WaEnableStateCacheRedirectToCS
a131ad41470f drm/i915/icl: Enable Sampler DFR
569a254c2ba9 drm/i915/icl: Wa_1405779004
1adc09d57d75 drm/i915/icl: Wa_1406680159 and Wa_2201832410
e745da174634 drm/i915/icl: Wa_1604302699
e02a3689a546 drm/i915/icl: Wa_2006665173
0d55385321e3 drm/i915/icl: Wa_1406838659
0c932d845446 drm/i915/icl: WaForwardProgressSoftReset
89766d724bb6 drm/i915/icl: WaEnableFloatBlendOptimization
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (21 preceding siblings ...)
2018-04-06 22:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
@ 2018-04-06 22:58 ` Patchwork
2018-04-07 4:34 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-09 19:53 ` [PATCH 01/22] " Chris Wilson
24 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2018-04-06 22:58 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : success
== Summary ==
Series 41311v1 series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
https://patchwork.freedesktop.org/api/1.0/series/41311/revisions/1/mbox/
---- Known issues:
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-bxt-dsi) fdo#103927
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:429s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:443s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:379s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:535s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:297s
fi-bxt-dsi total:243 pass:216 dwarn:0 dfail:0 fail:0 skip:26
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:514s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:522s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:510s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:408s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:560s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:512s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:585s
fi-elk-e7500 total:285 pass:226 dwarn:0 dfail:0 fail:0 skip:59 time:424s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:314s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:542s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:487s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:420s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:469s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:433s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:462s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:511s
fi-pnv-d510 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:680s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:438s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:539s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:501s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:516s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:445s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:603s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:399s
e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC integration manifest
89766d724bb6 drm/i915/icl: WaEnableFloatBlendOptimization
0c932d845446 drm/i915/icl: WaForwardProgressSoftReset
0d55385321e3 drm/i915/icl: Wa_1406838659
e02a3689a546 drm/i915/icl: Wa_2006665173
e745da174634 drm/i915/icl: Wa_1604302699
1adc09d57d75 drm/i915/icl: Wa_1406680159 and Wa_2201832410
569a254c2ba9 drm/i915/icl: Wa_1405779004
a131ad41470f drm/i915/icl: Enable Sampler DFR
81ff9ff8112e drm/i915/icl: WaEnableStateCacheRedirectToCS
1a1f183539f7 drm/i915/icl: WaAllowUMDToModifySamplerMode
b17203f3ce71 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
dfbd6e5e21fe drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
18a761359036 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
117d3028b83a drm/i915/icl: WaSendPushConstantsFromMMIO
3c456f385e81 drm/i915/icl: WaDisCtxReload
97c509b92d34 drm/i915/icl: WaCL2SFHalfMaxAlloc
1d0fa9e70616 drm/i915/icl: WaDisableImprovedTdlClkGating
f3018a4d2c5b drm/i915/icl: WaDisableCleanEvicts
6c99c36530dd drm/i915/icl: WaL3BankAddressHashing
6b5802730b5d drm/i915/icl: WaModifyGamTlbPartitioning
dfd92fa235cd drm/i915/icl: WaGAPZPriorityScheme
080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8632/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (22 preceding siblings ...)
2018-04-06 22:58 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-07 4:34 ` Patchwork
2018-04-09 19:53 ` [PATCH 01/22] " Chris Wilson
24 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2018-04-07 4:34 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : failure
== Summary ==
---- Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail -> PASS (shard-snb)
Test kms_chv_cursor_fail:
Subgroup pipe-c-256x256-top-edge:
pass -> FAIL (shard-apl)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail -> PASS (shard-snb)
Subgroup cursor-256x256-offscreen:
fail -> PASS (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail -> PASS (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail -> PASS (shard-snb)
Subgroup fbc-modesetfrombusy:
fail -> PASS (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail -> SKIP (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail -> SKIP (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail -> SKIP (shard-snb)
Test kms_mmap_write_crc:
fail -> PASS (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail -> PASS (shard-snb)
---- Known issues:
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail -> PASS (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail -> SKIP (shard-snb) fdo#103167
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-apl total:2680 pass:1835 dwarn:1 dfail:0 fail:8 skip:836 time:12719s
shard-hsw total:2680 pass:1787 dwarn:1 dfail:0 fail:0 skip:891 time:11531s
shard-snb total:2680 pass:1377 dwarn:1 dfail:0 fail:3 skip:1299 time:6900s
Blacklisted hosts:
shard-kbl total:2680 pass:1954 dwarn:10 dfail:0 fail:6 skip:710 time:9048s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8632/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
` (23 preceding siblings ...)
2018-04-07 4:34 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-04-09 19:53 ` Chris Wilson
2018-04-09 21:33 ` Oscar Mateo
24 siblings, 1 reply; 35+ messages in thread
From: Chris Wilson @ 2018-04-09 19:53 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Quoting Oscar Mateo (2018-04-06 23:24:57)
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
Speaking of the workarounds, where do we stand with at least landing the
split out of init_workarounds_ring()?
Rebuilding the invariant wa_regs[] on every reset is annoying, and how
many of the general mmio need to be reemitted everytime? I would dearly
like to get the flow of the gt/context workarounds improved.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
@ 2018-04-13 16:00 Oscar Mateo
0 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
To: intel-gfx
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 47 ++++++++++++++++++++++++++++++++
6 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e50d958..b08a22a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+ else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c8513..675c19d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1633,6 +1633,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..cfa03ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,6 +9123,8 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index bbbf4ed..8c2d17c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return 0;
}
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
err = cfl_ctx_workarounds_init(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_ctx_workarounds_init(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_ctx_workarounds_init(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
cfl_gt_workarounds_apply(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
cnl_gt_workarounds_apply(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ icl_gt_workarounds_apply(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
}
@@ -818,6 +858,11 @@ static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
return 0;
}
+static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
+{
+ return 0;
+}
+
int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -845,6 +890,8 @@ int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
err = cfl_whitelist_workarounds_apply(engine);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_whitelist_workarounds_apply(engine);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_whitelist_workarounds_apply(engine);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v4 00/22] Workarounds for Icelake
@ 2018-04-20 20:33 Oscar Mateo
2018-04-20 20:33 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-04-20 20:33 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
List of GT workarounds for Icelake that we have been carrying in internal.
Can we get eyes on these please?
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i915/icl: WaModifyGamTlbPartitioning
drm/i915/icl: WaDisableCleanEvicts
drm/i915/icl: WaCL2SFHalfMaxAlloc
drm/i915/icl: WaDisCtxReload
drm/i915/icl: Wa_1405779004
drm/i915/icl: Wa_1406680159 and Wa_2201832410
drm/i915/icl: Wa_1604302699
drm/i915/icl: Wa_1406838659
drm/i915/icl: WaForwardProgressSoftReset
drm/i915/icl: WaDisableImprovedTdlClkGating
drm/i915/icl: WaEnableStateCacheRedirectToCS
drm/i915/icl: Wa_2006665173
drm/i915/icl: WaEnableFloatBlendOptimization
drm/i915/icl: WaSendPushConstantsFromMMIO
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
drm/i915/icl: WaAllowUmdWriteTRTTRootTable
drm/i915/icl: WaAllowUMDToModifySamplerMode
drivers/gpu/drm/i915/i915_drv.h | 9 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 85 +++++++++++++----
drivers/gpu/drm/i915/intel_lrc.c | 2 +
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 7 +-
drivers/gpu/drm/i915/intel_workarounds.c | 157 +++++++++++++++++++++++++++++++
7 files changed, 245 insertions(+), 23 deletions(-)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-20 20:33 [PATCH v4 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-04-20 20:33 ` Oscar Mateo
2018-04-26 15:01 ` Mika Kuoppala
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-04-20 20:33 UTC (permalink / raw)
To: intel-gfx
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
7 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0286911..1dc157f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+ else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a..2d6572a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..3b7d804 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
* in the hope that the original ack will be delivered along with
* the fallback ack.
*
- * This workaround is described in HSDES #1604254524
+ * This workaround is described in HSDES #1604254524 and it's known as:
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * although the name is a bit misleading.
*/
pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11) {
int i;
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_fallback;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..3f00623 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return 0;
}
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
err = cfl_ctx_workarounds_init(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_ctx_workarounds_init(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_ctx_workarounds_init(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
cfl_gt_workarounds_apply(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
cnl_gt_workarounds_apply(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ icl_gt_workarounds_apply(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
}
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_CS_CHICKEN1);
}
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
struct whitelist *w)
{
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
cfl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
+ else if (IS_ICELAKE(i915))
+ icl_whitelist_build(w);
else
MISSING_CASE(INTEL_GEN(i915));
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-20 20:33 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-04-26 15:01 ` Mika Kuoppala
2018-04-30 17:12 ` Oscar Mateo
0 siblings, 1 reply; 35+ messages in thread
From: Mika Kuoppala @ 2018-04-26 15:01 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
> - Squashed with this patch:
> drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni <paulo.r.zanoni@intel.com>
> - Squashed with this patch:
> drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo <oscar.mateo@intel.com>
> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
> - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
> - Wrap the commit message
> - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
> 7 files changed, 68 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0286911..1dc157f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_CNL_REVID(p, since, until) \
> (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1
Just noted that for some reason bspec puts A0 and A2 under
same revid. Bspec err?
> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
> /*
> * The genX designation typically refers to the render engine, so render
> * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 21d72f6..221b873 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> * called on driver load and after a GPU reset, so you can place
> * workarounds here even if they get overwritten by GPU reset.
> */
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..f2ee225 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7203,6 +7203,7 @@ enum {
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 029901a..2d6572a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return -EINVAL;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
> case 10:
> wa_bb_fn[0] = gen10_init_indirectctx_bb;
> wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4baab85..3b7d804 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = nop_init_clock_gating;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv))
> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
> * in the hope that the original ack will be delivered along with
> * the fallback ack.
> *
> - * This workaround is described in HSDES #1604254524
> + * This workaround is described in HSDES #1604254524 and it's known as:
> + * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> + * although the name is a bit misleading.
Just for the record:
When I implemented this there was recommendation to do both, delaying
for ack and then this method of using a reserver bit. My interpretation
was that the delay was used as a first weapon to combat the issue. And
then later, reserve bit method appeared.
I did not use WaRsForcewakeAddDelayForAck as I thought that this will be
named differently. And also I think this method is a superset,
making delaying irrelevant. As we fallback to reserve is we miss ack
so no need to delay before polling. And adding delay to hotpath should
be the last resort anyways.
I think this is the evolution of WaRsForcewakeAddDelayForAck
(v2) and there is no better name, we should keep it.
> */
>
> pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 11) {
> int i;
>
> - dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> + dev_priv->uncore.funcs.force_wake_get =
> + fw_domains_get_with_fallback;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..3f00623 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> + /* Wa_1604370585:icl (pre-prod)
> + * Formerly known as WaPushConstantDereferenceHoldDisable
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + PUSH_CONSTANT_DEREF_DISABLE);
Inherited from CNL and had to check if we have that on cnl. We do.
> +
> + /* WaForceEnableNonCoherent:icl
> + * This is not the same workaround as in early Gen9 platforms, where
> + * lacking this could cause system hangs, but coherency performance
> + * overhead is high and only a few compute workloads really need it
> + * (the register is whitelisted in hardware now, so UMDs can opt in
> + * for coherency if they have a good reason).
> + */
> + WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
Right, but the register name should be ICL_HDC_MODE.
> +
> + return 0;
> +}
> +
> int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> {
> int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> err = cfl_ctx_workarounds_init(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> err = cnl_ctx_workarounds_init(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + err = icl_ctx_workarounds_init(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> + /* This is not an Wa. Enable for better image quality */
> + I915_WRITE(_3D_CHICKEN3,
> + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> + /* WaInPlaceDecompressionHang:icl */
> + I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> +
> + /* WaPipelineFlushCoherentLines:icl */
> + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> + GEN8_LQSC_FLUSH_COHERENT_LINES));
Didn't find a HSDES entry for this. The workaround name and the reg/bit
matches tho.
But the real question in here is that do we need to set this through
indirect bb like we do with gen[8,9].
And just to note that cnl is missing this too. But that can be done
as a followup when we first figure out that should we use the indirect
bb for all >= gen8.
-Mika
> +}
> +
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> {
> if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> cfl_gt_workarounds_apply(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_gt_workarounds_apply(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + icl_gt_workarounds_apply(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
> whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> struct whitelist *w)
> {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> cfl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> + else if (IS_ICELAKE(i915))
> + icl_whitelist_build(w);
> else
> MISSING_CASE(INTEL_GEN(i915));
>
> --
> 1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-04-26 15:01 ` Mika Kuoppala
@ 2018-04-30 17:12 ` Oscar Mateo
0 siblings, 0 replies; 35+ messages in thread
From: Oscar Mateo @ 2018-04-30 17:12 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
On 04/26/2018 08:01 AM, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> Inherit workarounds from previous platforms that are still valid for
>> Icelake.
>>
>> v2: GEN7_ROW_CHICKEN2 is masked
>> v3:
>> - Since it has been fixed already in upstream, removed the TODO
>> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>> - Squashed with this patch:
>> drm/i915/icl: add icelake_init_clock_gating()
>> from Paulo Zanoni <paulo.r.zanoni@intel.com>
>> - Squashed with this patch:
>> drm/i915/icl: WaForceEnableNonCoherent
>> from Oscar Mateo <oscar.mateo@intel.com>
>> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
>> applies to B0 as well.
>> - WaPipeControlBefore3DStateSamplePattern WABB was being applied
>> to ICL incorrectly.
>> v4:
>> - Wrap the commit message
>> - s/dev_priv/p to please checkpatch
>> v5: Rebased on top of the WA refactoring
>> v6: Rebased on top of further whitelist registers refactoring (Michel)
>> v7: Added WaRsForcewakeAddDelayForAck
>>
>> Cc: Tomasz Lis <tomasz.lis@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
>> drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
>> drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
>> 7 files changed, 68 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 0286911..1dc157f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
>> #define IS_CNL_REVID(p, since, until) \
>> (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>>
>> +#define ICL_REVID_A0 0x0
>> +#define ICL_REVID_A2 0x1
> Just noted that for some reason bspec puts A0 and A2 under
> same revid. Bspec err?
That's what I hope. I have opened a bug against the BSpec to be 100% sure.
>> +#define ICL_REVID_B0 0x3
>> +#define ICL_REVID_B2 0x4
>> +#define ICL_REVID_C0 0x5
>> +
>> +#define IS_ICL_REVID(p, since, until) \
>> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
>> +
>> /*
>> * The genX designation typically refers to the render engine, so render
>> * capability related checks should use IS_GEN, while display and other checks
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 21d72f6..221b873 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>> * called on driver load and after a GPU reset, so you can place
>> * workarounds here even if they get overwritten by GPU reset.
>> */
>> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
>> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>> if (IS_BROADWELL(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>> else if (IS_CHERRYVIEW(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
>> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
>> + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>> else if (IS_GEN9_LP(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fb10602..f2ee225 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7203,6 +7203,7 @@ enum {
>> /* GEN8 chicken */
>> #define HDC_CHICKEN0 _MMIO(0x7300)
>> #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
>> +#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
>> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
>> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
>> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 029901a..2d6572a 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>> return -EINVAL;
>>
>> switch (INTEL_GEN(engine->i915)) {
>> + case 11:
>> + return 0;
>> case 10:
>> wa_bb_fn[0] = gen10_init_indirectctx_bb;
>> wa_bb_fn[1] = NULL;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4baab85..3b7d804 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>> */
>> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>> {
>> - if (IS_CANNONLAKE(dev_priv))
>> + if (IS_ICELAKE(dev_priv))
>> + dev_priv->display.init_clock_gating = nop_init_clock_gating;
>> + else if (IS_CANNONLAKE(dev_priv))
>> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>> else if (IS_COFFEELAKE(dev_priv))
>> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index d6e20f0..448293e 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -139,7 +139,9 @@ enum ack_type {
>> * in the hope that the original ack will be delivered along with
>> * the fallback ack.
>> *
>> - * This workaround is described in HSDES #1604254524
>> + * This workaround is described in HSDES #1604254524 and it's known as:
>> + * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
>> + * although the name is a bit misleading.
> Just for the record:
>
> When I implemented this there was recommendation to do both, delaying
> for ack and then this method of using a reserver bit. My interpretation
> was that the delay was used as a first weapon to combat the issue. And
> then later, reserve bit method appeared.
>
> I did not use WaRsForcewakeAddDelayForAck as I thought that this will be
> named differently. And also I think this method is a superset,
> making delaying irrelevant. As we fallback to reserve is we miss ack
> so no need to delay before polling. And adding delay to hotpath should
> be the last resort anyways.
>
> I think this is the evolution of WaRsForcewakeAddDelayForAck
> (v2) and there is no better name, we should keep it.
Yes, I read the mailing lists comments about this. AFAICT, there is no
better name.
>> */
>>
>> pass = 1;
>> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>> if (INTEL_GEN(dev_priv) >= 11) {
>> int i;
>>
>> - dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>> + dev_priv->uncore.funcs.force_wake_get =
>> + fw_domains_get_with_fallback;
>> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>> FORCEWAKE_RENDER_GEN9,
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index ec9d340..3f00623 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> return 0;
>> }
>>
>> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> +{
>> + /* Wa_1604370585:icl (pre-prod)
>> + * Formerly known as WaPushConstantDereferenceHoldDisable
>> + */
>> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
>> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> + PUSH_CONSTANT_DEREF_DISABLE);
> Inherited from CNL and had to check if we have that on cnl. We do.
>
>> +
>> + /* WaForceEnableNonCoherent:icl
>> + * This is not the same workaround as in early Gen9 platforms, where
>> + * lacking this could cause system hangs, but coherency performance
>> + * overhead is high and only a few compute workloads really need it
>> + * (the register is whitelisted in hardware now, so UMDs can opt in
>> + * for coherency if they have a good reason).
>> + */
>> + WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
> Right, but the register name should be ICL_HDC_MODE.
ACK
>> +
>> + return 0;
>> +}
>> +
>> int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> {
>> int err = 0;
>> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> err = cfl_ctx_workarounds_init(dev_priv);
>> else if (IS_CANNONLAKE(dev_priv))
>> err = cnl_ctx_workarounds_init(dev_priv);
>> + else if (IS_ICELAKE(dev_priv))
>> + err = icl_ctx_workarounds_init(dev_priv);
>> else
>> MISSING_CASE(INTEL_GEN(dev_priv));
>> if (err)
>> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
>> }
>>
>> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> +{
>> + /* This is not an Wa. Enable for better image quality */
>> + I915_WRITE(_3D_CHICKEN3,
>> + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>> +
>> + /* WaInPlaceDecompressionHang:icl */
>> + I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
>> +
>> + /* WaPipelineFlushCoherentLines:icl */
>> + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>> + GEN8_LQSC_FLUSH_COHERENT_LINES));
> Didn't find a HSDES entry for this. The workaround name and the reg/bit
> matches tho.
>
> But the real question in here is that do we need to set this through
> indirect bb like we do with gen[8,9].
>
> And just to note that cnl is missing this too. But that can be done
> as a followup when we first figure out that should we use the indirect
> bb for all >= gen8.
>
> -Mika
Hmmmm... looking at it more carefully: isn't that a slightly different
WA: WaPipelineFlushCoherentLines (not needed starting CNL)?
This is equivalent to a different WA: WaOCLCoherentLineFlush.
But indeed, it seems to be required for CNL as well. In fact, I'm pretty
sure I added it to this patch because I saw it in CNL. Did it get lost?
>> +}
>> +
>> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> {
>> if (INTEL_GEN(dev_priv) < 8)
>> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> cfl_gt_workarounds_apply(dev_priv);
>> else if (IS_CANNONLAKE(dev_priv))
>> cnl_gt_workarounds_apply(dev_priv);
>> + else if (IS_ICELAKE(dev_priv))
>> + icl_gt_workarounds_apply(dev_priv);
>> else
>> MISSING_CASE(INTEL_GEN(dev_priv));
>> }
>> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
>> whitelist_reg(w, GEN8_CS_CHICKEN1);
>> }
>>
>> +static void icl_whitelist_build(struct whitelist *w)
>> +{
>> +}
>> +
>> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>> struct whitelist *w)
>> {
>> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>> cfl_whitelist_build(w);
>> else if (IS_CANNONLAKE(i915))
>> cnl_whitelist_build(w);
>> + else if (IS_ICELAKE(i915))
>> + icl_whitelist_build(w);
>> else
>> MISSING_CASE(INTEL_GEN(i915));
>>
>> --
>> 1.9.1
_______________________________________________
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 00/22] Workarounds for Icelake
@ 2018-05-02 20:33 Oscar Mateo
2018-05-02 20:34 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-05-02 20:33 UTC (permalink / raw)
To: intel-gfx
List of GT workarounds for Icelake that we have been carrying in internal.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i915/icl: WaModifyGamTlbPartitioning
drm/i915/icl: WaDisableCleanEvicts
drm/i915/icl: WaCL2SFHalfMaxAlloc
drm/i915/icl: WaDisCtxReload
drm/i915/icl: Wa_1405779004
drm/i915/icl: Wa_1406680159
drm/i915/icl: Wa_1604302699
drm/i915/icl: Wa_1406838659
drm/i915/icl: WaForwardProgressSoftReset
drm/i915/icl: WaDisableImprovedTdlClkGating
drm/i915/icl: WaEnableStateCacheRedirectToCS
drm/i915/icl: Wa_2006665173
drm/i915/icl: WaEnableFloatBlendOptimization
drm/i915/icl: WaSendPushConstantsFromMMIO
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
drm/i915/icl: WaAllowUmdWriteTRTTRootTable
drm/i915/icl: WaAllowUMDToModifySamplerMode
drivers/gpu/drm/i915/i915_drv.h | 9 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 85 ++++++++++++++----
drivers/gpu/drm/i915/intel_lrc.c | 2 +
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +-
drivers/gpu/drm/i915/intel_workarounds.c | 150 +++++++++++++++++++++++++++++++
7 files changed, 245 insertions(+), 23 deletions(-)
--
1.9.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-02 20:33 [PATCH v2 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-05-02 20:34 ` Oscar Mateo
2018-05-04 16:31 ` Tvrtko Ursulin
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-05-02 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
7 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 193176b..7a3b0b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+ else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..454009f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_MODE _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 513aee6..d5fab47 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
* in the hope that the original ack will be delivered along with
* the fallback ack.
*
- * This workaround is described in HSDES #1604254524
+ * This workaround is described in HSDES #1604254524 and it's known as:
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * although the name is a bit misleading.
*/
pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11) {
int i;
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_fallback;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..9a793ac 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return 0;
}
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
err = cfl_ctx_workarounds_init(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_ctx_workarounds_init(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_ctx_workarounds_init(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
cfl_gt_workarounds_apply(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
cnl_gt_workarounds_apply(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ icl_gt_workarounds_apply(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
}
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_CS_CHICKEN1);
}
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
struct whitelist *w)
{
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
cfl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
+ else if (IS_ICELAKE(i915))
+ icl_whitelist_build(w);
else
MISSING_CASE(INTEL_GEN(i915));
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-02 20:34 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-05-04 16:31 ` Tvrtko Ursulin
0 siblings, 0 replies; 35+ messages in thread
From: Tvrtko Ursulin @ 2018-05-04 16:31 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx; +Cc: Rodrigo Vivi
On 02/05/2018 21:34, Oscar Mateo wrote:
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
> - Squashed with this patch:
> drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni <paulo.r.zanoni@intel.com>
> - Squashed with this patch:
> drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo <oscar.mateo@intel.com>
> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
> - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
> - Wrap the commit message
> - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
> v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
> 7 files changed, 68 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 193176b..7a3b0b1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_CNL_REVID(p, since, until) \
> (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1
> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
> /*
> * The genX designation typically refers to the render engine, so render
> * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 21d72f6..221b873 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> * called on driver load and after a GPU reset, so you can place
> * workarounds here even if they get overwritten by GPU reset.
> */
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
Sounds like:
if (IS_BROADWELL)
else if (IS_CHERRYVIEW)
else if (IS_GEN9_LP)
else if (IS_GEN >= 9) /* Here's the improvement */
Just a drive by, sorry. :)
Regards,
Tvrtko
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..454009f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7238,6 +7238,7 @@ enum {
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_MODE _MMIO(0xE5F4)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 513aee6..d5fab47 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return -EINVAL;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
> case 10:
> wa_bb_fn[0] = gen10_init_indirectctx_bb;
> wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4126132..9c6e48c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = nop_init_clock_gating;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv))
> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
> * in the hope that the original ack will be delivered along with
> * the fallback ack.
> *
> - * This workaround is described in HSDES #1604254524
> + * This workaround is described in HSDES #1604254524 and it's known as:
> + * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> + * although the name is a bit misleading.
> */
>
> pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 11) {
> int i;
>
> - dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> + dev_priv->uncore.funcs.force_wake_get =
> + fw_domains_get_with_fallback;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..9a793ac 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> + /* Wa_1604370585:icl (pre-prod)
> + * Formerly known as WaPushConstantDereferenceHoldDisable
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + PUSH_CONSTANT_DEREF_DISABLE);
> +
> + /* WaForceEnableNonCoherent:icl
> + * This is not the same workaround as in early Gen9 platforms, where
> + * lacking this could cause system hangs, but coherency performance
> + * overhead is high and only a few compute workloads really need it
> + * (the register is whitelisted in hardware now, so UMDs can opt in
> + * for coherency if they have a good reason).
> + */
> + WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
> +
> + return 0;
> +}
> +
> int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> {
> int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> err = cfl_ctx_workarounds_init(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> err = cnl_ctx_workarounds_init(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + err = icl_ctx_workarounds_init(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> + /* This is not an Wa. Enable for better image quality */
> + I915_WRITE(_3D_CHICKEN3,
> + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> + /* WaInPlaceDecompressionHang:icl */
> + I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> +
> + /* WaPipelineFlushCoherentLines:icl */
> + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> + GEN8_LQSC_FLUSH_COHERENT_LINES));
> +}
> +
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> {
> if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> cfl_gt_workarounds_apply(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_gt_workarounds_apply(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + icl_gt_workarounds_apply(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
> whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> struct whitelist *w)
> {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> cfl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> + else if (IS_ICELAKE(i915))
> + icl_whitelist_build(w);
> else
> MISSING_CASE(INTEL_GEN(i915));
>
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 00/22] Workarounds for Icelake
@ 2018-05-08 21:29 Oscar Mateo
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
List of GT workarounds for Icelake that we have been carrying in internal.
Applied lots of review comments from Mika and stamped rv-b's from him and
Rodrigo.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i915/icl: WaModifyGamTlbPartitioning
drm/i915/icl: WaDisableCleanEvicts
drm/i915/icl: WaCL2SFHalfMaxAlloc
drm/i915/icl: WaDisCtxReload
drm/i915/icl: Wa_1405779004
drm/i915/icl: Wa_1406680159
drm/i915/icl: Wa_1604302699
drm/i915/icl: Wa_1406838659
drm/i915/icl: WaForwardProgressSoftReset
drm/i915/icl: WaDisableImprovedTdlClkGating
drm/i915/icl: WaEnableStateCacheRedirectToCS
drm/i915/icl: Wa_2006665173
drm/i915/icl: WaEnableFloatBlendOptimization
drm/i915/icl: WaSendPushConstantsFromMMIO
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
drm/i915/icl: WaAllowUmdWriteTRTTRootTable
drm/i915/icl: WaAllowUMDToModifySamplerMode
drivers/gpu/drm/i915/i915_drv.h | 9 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 77 +++++++++++++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +-
drivers/gpu/drm/i915/intel_workarounds.c | 149 +++++++++++++++++++++++++++++++
7 files changed, 241 insertions(+), 20 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-11 12:37 ` Mika Kuoppala
0 siblings, 1 reply; 35+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
- C, not lisp (Chris)
- WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
7 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e2780..ad79d5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c879bfd..ea30e84 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
- I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+ else if (INTEL_GEN(dev_priv) >= 9)
+ I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
/*
* To support 64K PTEs we need to first enable the use of the
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 085928c..2b22d4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_MODE _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 911f288..920752a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
* in the hope that the original ack will be delivered along with
* the fallback ack.
*
- * This workaround is described in HSDES #1604254524
+ * This workaround is described in HSDES #1604254524 and it's known as:
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * although the name is a bit misleading.
*/
pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11) {
int i;
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_fallback;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..73d02d3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return 0;
}
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
err = cfl_ctx_workarounds_init(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_ctx_workarounds_init(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_ctx_workarounds_init(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
+}
+
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
cfl_gt_workarounds_apply(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
cnl_gt_workarounds_apply(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ icl_gt_workarounds_apply(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
}
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_CS_CHICKEN1);
}
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
struct whitelist *w)
{
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
cfl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
+ else if (IS_ICELAKE(i915))
+ icl_whitelist_build(w);
else
MISSING_CASE(INTEL_GEN(i915));
--
1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-05-11 12:37 ` Mika Kuoppala
0 siblings, 0 replies; 35+ messages in thread
From: Mika Kuoppala @ 2018-05-11 12:37 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx; +Cc: Rodrigo Vivi
Oscar Mateo <oscar.mateo@intel.com> writes:
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
> - Squashed with this patch:
> drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni <paulo.r.zanoni@intel.com>
> - Squashed with this patch:
> drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo <oscar.mateo@intel.com>
> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
> - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
> - Wrap the commit message
> - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
> v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
> v9:
> - C, not lisp (Chris)
> - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
> 7 files changed, 69 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 04e2780..ad79d5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_CNL_REVID(p, since, until) \
> (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1
> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
> /*
> * The genX designation typically refers to the render engine, so render
> * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c879bfd..ea30e84 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> * called on driver load and after a GPU reset, so you can place
> * workarounds here even if they get overwritten by GPU reset.
> */
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> - I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> + else if (INTEL_GEN(dev_priv) >= 9)
> + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>
> /*
> * To support 64K PTEs we need to first enable the use of the
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 085928c..2b22d4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7238,6 +7238,7 @@ enum {
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_MODE _MMIO(0xE5F4)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 911f288..920752a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return -EINVAL;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
> case 10:
> wa_bb_fn[0] = gen10_init_indirectctx_bb;
> wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4126132..9c6e48c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = nop_init_clock_gating;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv))
> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
> * in the hope that the original ack will be delivered along with
> * the fallback ack.
> *
> - * This workaround is described in HSDES #1604254524
> + * This workaround is described in HSDES #1604254524 and it's known as:
> + * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> + * although the name is a bit misleading.
> */
>
> pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 11) {
> int i;
>
> - dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> + dev_priv->uncore.funcs.force_wake_get =
> + fw_domains_get_with_fallback;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..73d02d3 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> + /* Wa_1604370585:icl (pre-prod)
> + * Formerly known as WaPushConstantDereferenceHoldDisable
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + PUSH_CONSTANT_DEREF_DISABLE);
> +
> + /* WaForceEnableNonCoherent:icl
> + * This is not the same workaround as in early Gen9 platforms, where
> + * lacking this could cause system hangs, but coherency performance
> + * overhead is high and only a few compute workloads really need it
> + * (the register is whitelisted in hardware now, so UMDs can opt in
> + * for coherency if they have a good reason).
> + */
> + WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
> +
> + return 0;
> +}
> +
> int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> {
> int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> err = cfl_ctx_workarounds_init(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> err = cnl_ctx_workarounds_init(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + err = icl_ctx_workarounds_init(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> + /* This is not an Wa. Enable for better image quality */
> + I915_WRITE(_3D_CHICKEN3,
> + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> + /* WaInPlaceDecompressionHang:icl */
> + I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> + /* WaPipelineFlushCoherentLines:icl */
> + I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
> + GEN8_LQSC_FLUSH_COHERENT_LINES);
Ok, for icl, this is needed. And like you said, it is different
than what the WaFlushCoherentL3CacheLinesAtContextSwitch does.
There is more to this saga, as WaPipelineFlushCoherentLines
is needed also for other platforms, and we don't have it.
And it will collide with how we do per bb workarounds around this reg.
A thing we much recheck also on icl, if we add indirect context bb's.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> +}
> +
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> {
> if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> cfl_gt_workarounds_apply(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_gt_workarounds_apply(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + icl_gt_workarounds_apply(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
> whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> struct whitelist *w)
> {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> cfl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> + else if (IS_ICELAKE(i915))
> + icl_whitelist_build(w);
> else
> MISSING_CASE(INTEL_GEN(i915));
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2018-05-11 12:37 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-06 22:24 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-04-06 22:24 ` [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
2018-04-06 22:24 ` [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
2018-04-06 22:25 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
2018-04-06 22:25 ` [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
2018-04-06 22:25 ` [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
2018-04-06 22:25 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
2018-04-06 22:25 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
2018-04-06 22:25 ` [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
2018-04-06 22:25 ` [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
2018-04-06 22:25 ` [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
2018-04-06 22:25 ` [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
2018-04-06 22:25 ` [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
2018-04-06 22:25 ` [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
2018-04-06 22:25 ` [PATCH 15/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
2018-04-06 22:25 ` [PATCH 16/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
2018-04-06 22:25 ` [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
2018-04-06 22:25 ` [PATCH 18/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
2018-04-06 22:25 ` [PATCH 19/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
2018-04-06 22:25 ` [PATCH 20/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
2018-04-06 22:25 ` [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
2018-04-06 22:25 ` [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
2018-04-06 22:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
2018-04-06 22:58 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-07 4:34 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-09 19:53 ` [PATCH 01/22] " Chris Wilson
2018-04-09 21:33 ` Oscar Mateo
2018-04-13 16:00 Oscar Mateo
2018-04-20 20:33 [PATCH v4 00/22] Workarounds for Icelake Oscar Mateo
2018-04-20 20:33 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-04-26 15:01 ` Mika Kuoppala
2018-04-30 17:12 ` Oscar Mateo
2018-05-02 20:33 [PATCH v2 00/22] Workarounds for Icelake Oscar Mateo
2018-05-02 20:34 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-05-04 16:31 ` Tvrtko Ursulin
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-05-11 12:37 ` Mika Kuoppala
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