From: Jose Abreu <Jose.Abreu@synopsys.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Jose Abreu <Jose.Abreu@synopsys.com> Cc: Mark Yao <mark.yao@rock-chips.com>, <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>, Archit Taneja <architt@codeaurora.org>, Andrzej Hajda <a.hajda@samsung.com>, "Carlos Palminha" <CARLOS.PALMINHA@synopsys.com> Subject: Re: [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY Date: Tue, 13 Jun 2017 15:11:27 +0100 [thread overview] Message-ID: <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> (raw) In-Reply-To: <3690108.zYIGBGnVBz@avalon> Hi Laurent, Sorry for the late reply! On 10-06-2017 09:50, Laurent Pinchart wrote: > Hi Jose, > > On Friday 09 Jun 2017 13:53:12 Jose Abreu wrote: >> On 09-06-2017 12:04, Jose Abreu wrote: >>> Currently HDMI 2.0 PHYs do not have a default configuration function. >>> >>> As these PHYs have the same register layout as the 3D PHYs we can >>> safely use the default configuration function. >> I may have been a little to fast arriving at this conclusion. I >> mean most of the registers match but in the configuration >> function there are registers that do not match. Did you actually >> test this configuration function with an HDMI 2.0 phy? And did >> you test with different video modes? From my experience the phy >> may be wrongly configured and sometimes work anyway. >> >> Do please retest with as many video modes as you can and give me >> your phy ID (read from controller config reg HDMI_CONFIG2_ID). > The Renesas R-Car Gen3 HDMI PHY reports an DWC HDMI 2.0 TX PHY ID, but has a > configuration function (rcar_hdmi_phy_configure() in drivers/gpu/drm/rcar- > du/rcar_dw_hdmi.c) that doesn't match hdmi_phy_configure_dwc_hdmi_3d_tx(). > From the information I have been given the layout of the configuration > registers haven't been changed by Renesas. I know we've briefly discussed this > in the past, but I'd appreciate if you could have a second look and tell me > what you think. Yup, yours seems correct. Though at the time you submitted I found it odd that only 3 registers needed to be written whilst for HDMI 2.0 phys I have here 6 registers, but you said it is working so I though your phy was different ... Even so, one thing I would like to know is what was the max resolution you tested? I see you have clock values up to 297MHz, so 4k@30Hz? If I send a patch with a general config function for HDMI 2.0 phys can you test it on your platform? Best regards, Jose Miguel Abreu > >>> If, for some reason, >>> >>> the PHY is custom this change will not make any impact because >>> in configuration function we prefer the pdata provided configuration >>> function over the internal one. >>> >>> This patch is based on today's drm-misc-next branch. >>> >>> Signed-off-by: Jose Abreu <joabreu@synopsys.com> >>> Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >>> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> >>> Cc: Archit Taneja <architt@codeaurora.org> >>> Cc: Andrzej Hajda <a.hajda@samsung.com> >>> Cc: Mark Yao <mark.yao@rock-chips.com> >>> Cc: Carlos Palminha <palminha@synopsys.com> >>> --- >>> >>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index ead1124..10c8d8c 100644 >>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> @@ -2170,6 +2170,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void >>> *dev_id) >>> .name = "DWC HDMI 2.0 TX PHY", >>> .gen = 2, >>> .has_svsret = true, >>> + .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, >>> }, { >>> .type = DW_HDMI_PHY_VENDOR_PHY, >>> .name = "Vendor PHY",
WARNING: multiple messages have this Message-ID (diff)
From: Jose Abreu <Jose.Abreu@synopsys.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Jose Abreu <Jose.Abreu@synopsys.com> Cc: Mark Yao <mark.yao@rock-chips.com>, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>, Archit Taneja <architt@codeaurora.org>, Andrzej Hajda <a.hajda@samsung.com>, Carlos Palminha <CARLOS.PALMINHA@synopsys.com> Subject: Re: [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY Date: Tue, 13 Jun 2017 15:11:27 +0100 [thread overview] Message-ID: <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> (raw) In-Reply-To: <3690108.zYIGBGnVBz@avalon> Hi Laurent, Sorry for the late reply! On 10-06-2017 09:50, Laurent Pinchart wrote: > Hi Jose, > > On Friday 09 Jun 2017 13:53:12 Jose Abreu wrote: >> On 09-06-2017 12:04, Jose Abreu wrote: >>> Currently HDMI 2.0 PHYs do not have a default configuration function. >>> >>> As these PHYs have the same register layout as the 3D PHYs we can >>> safely use the default configuration function. >> I may have been a little to fast arriving at this conclusion. I >> mean most of the registers match but in the configuration >> function there are registers that do not match. Did you actually >> test this configuration function with an HDMI 2.0 phy? And did >> you test with different video modes? From my experience the phy >> may be wrongly configured and sometimes work anyway. >> >> Do please retest with as many video modes as you can and give me >> your phy ID (read from controller config reg HDMI_CONFIG2_ID). > The Renesas R-Car Gen3 HDMI PHY reports an DWC HDMI 2.0 TX PHY ID, but has a > configuration function (rcar_hdmi_phy_configure() in drivers/gpu/drm/rcar- > du/rcar_dw_hdmi.c) that doesn't match hdmi_phy_configure_dwc_hdmi_3d_tx(). > From the information I have been given the layout of the configuration > registers haven't been changed by Renesas. I know we've briefly discussed this > in the past, but I'd appreciate if you could have a second look and tell me > what you think. Yup, yours seems correct. Though at the time you submitted I found it odd that only 3 registers needed to be written whilst for HDMI 2.0 phys I have here 6 registers, but you said it is working so I though your phy was different ... Even so, one thing I would like to know is what was the max resolution you tested? I see you have clock values up to 297MHz, so 4k@30Hz? If I send a patch with a general config function for HDMI 2.0 phys can you test it on your platform? Best regards, Jose Miguel Abreu > >>> If, for some reason, >>> >>> the PHY is custom this change will not make any impact because >>> in configuration function we prefer the pdata provided configuration >>> function over the internal one. >>> >>> This patch is based on today's drm-misc-next branch. >>> >>> Signed-off-by: Jose Abreu <joabreu@synopsys.com> >>> Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> >>> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> >>> Cc: Archit Taneja <architt@codeaurora.org> >>> Cc: Andrzej Hajda <a.hajda@samsung.com> >>> Cc: Mark Yao <mark.yao@rock-chips.com> >>> Cc: Carlos Palminha <palminha@synopsys.com> >>> --- >>> >>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index ead1124..10c8d8c 100644 >>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>> @@ -2170,6 +2170,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void >>> *dev_id) >>> .name = "DWC HDMI 2.0 TX PHY", >>> .gen = 2, >>> .has_svsret = true, >>> + .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, >>> }, { >>> .type = DW_HDMI_PHY_VENDOR_PHY, >>> .name = "Vendor PHY",
next prev parent reply other threads:[~2017-06-13 14:11 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-09 11:04 [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY Jose Abreu 2017-06-09 12:53 ` Jose Abreu 2017-06-09 12:53 ` Jose Abreu 2017-06-10 8:50 ` Laurent Pinchart 2017-06-13 14:11 ` Jose Abreu [this message] 2017-06-13 14:11 ` Jose Abreu 2017-06-22 8:25 ` Mark yao 2017-06-22 8:25 ` Mark yao 2017-06-22 8:59 ` Zheng Yang 2017-06-22 14:28 ` Laurent Pinchart 2017-06-22 14:28 ` Laurent Pinchart 2017-06-20 14:17 ` Heiko Stübner
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