From: Anshuman Khandual <anshuman.khandual@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com>, linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Date: Wed, 6 May 2020 12:03:03 +0530 [thread overview] Message-ID: <197bddfb-d63f-7824-63eb-cc38ae729efe@arm.com> (raw) In-Reply-To: <4c6e9f6e-fffa-8fdf-ad1a-f0c6514c3571@arm.com> On 05/05/2020 02:54 PM, Suzuki K Poulose wrote: > On 05/02/2020 02:34 PM, Anshuman Khandual wrote: >> Enable the following features bits in ID_AA64PFR1 register as per ARM DDI >> 0487F.a specification. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> >> Suggested-by: Will Deacon <will@kernel.org> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 4 ++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index c93ea6613f51..f1c0d874220a 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -666,7 +666,11 @@ >> #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 >> /* id_aa64pfr1 */ >> +#define ID_AA64PFR1_MPAMFRAC_SHIFT 16 >> +#define ID_AA64PFR1_RASFRAC_SHIFT 12 >> +#define ID_AA64PFR1_MTE_SHIFT 8 >> #define ID_AA64PFR1_SSBS_SHIFT 4 >> +#define ID_AA64PFR1_BT_SHIFT 0 >> #define ID_AA64PFR1_SSBS_PSTATE_NI 0 >> #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index f5a39e040804..181e09d62147 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -233,7 +233,11 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { >> }; >> static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), > > These should be hidden as well. Will change. > >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, 0), >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), > > I would say remove the MTE, BTI fields for now. As they must be VISIBLE, but with the kernel support for these merged. They will be added with their respective series. Sure, will drop above changes from the series. > > Suzuki >
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com>, linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Date: Wed, 6 May 2020 12:03:03 +0530 [thread overview] Message-ID: <197bddfb-d63f-7824-63eb-cc38ae729efe@arm.com> (raw) In-Reply-To: <4c6e9f6e-fffa-8fdf-ad1a-f0c6514c3571@arm.com> On 05/05/2020 02:54 PM, Suzuki K Poulose wrote: > On 05/02/2020 02:34 PM, Anshuman Khandual wrote: >> Enable the following features bits in ID_AA64PFR1 register as per ARM DDI >> 0487F.a specification. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> >> Suggested-by: Will Deacon <will@kernel.org> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 4 ++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index c93ea6613f51..f1c0d874220a 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -666,7 +666,11 @@ >> #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 >> /* id_aa64pfr1 */ >> +#define ID_AA64PFR1_MPAMFRAC_SHIFT 16 >> +#define ID_AA64PFR1_RASFRAC_SHIFT 12 >> +#define ID_AA64PFR1_MTE_SHIFT 8 >> #define ID_AA64PFR1_SSBS_SHIFT 4 >> +#define ID_AA64PFR1_BT_SHIFT 0 >> #define ID_AA64PFR1_SSBS_PSTATE_NI 0 >> #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index f5a39e040804..181e09d62147 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -233,7 +233,11 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { >> }; >> static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), > > These should be hidden as well. Will change. > >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, 0), >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), > > I would say remove the MTE, BTI fields for now. As they must be VISIBLE, but with the kernel support for these merged. They will be added with their respective series. Sure, will drop above changes from the series. > > Suzuki > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-06 6:33 UTC|newest] Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-04 20:24 ` Will Deacon 2020-05-04 20:24 ` Will Deacon 2020-05-05 6:50 ` Anshuman Khandual 2020-05-05 6:50 ` Anshuman Khandual 2020-05-05 10:42 ` Will Deacon 2020-05-05 10:42 ` Will Deacon 2020-05-08 4:25 ` Anshuman Khandual 2020-05-08 4:25 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-05 11:10 ` Will Deacon 2020-05-05 11:10 ` Will Deacon 2020-05-08 4:59 ` Anshuman Khandual 2020-05-08 4:59 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-05 11:12 ` Will Deacon 2020-05-05 11:12 ` Will Deacon 2020-05-05 11:12 ` Will Deacon 2020-05-05 11:16 ` Mark Rutland 2020-05-05 11:16 ` Mark Rutland 2020-05-05 11:16 ` Mark Rutland 2020-05-05 11:18 ` Mark Rutland 2020-05-05 11:18 ` Mark Rutland 2020-05-05 11:18 ` Mark Rutland 2020-05-05 11:27 ` Will Deacon 2020-05-05 11:27 ` Will Deacon 2020-05-05 11:27 ` Will Deacon 2020-05-05 11:50 ` Mark Rutland 2020-05-05 11:50 ` Mark Rutland 2020-05-05 11:50 ` Mark Rutland 2020-05-05 12:12 ` Will Deacon 2020-05-05 12:12 ` Will Deacon 2020-05-05 12:12 ` Will Deacon 2020-05-05 12:49 ` Mark Rutland 2020-05-05 12:49 ` Mark Rutland 2020-05-05 12:49 ` Mark Rutland 2020-05-08 8:32 ` Anshuman Khandual 2020-05-08 8:32 ` Anshuman Khandual 2020-05-08 8:32 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-03 21:35 ` Suzuki K Poulose 2020-05-03 21:35 ` Suzuki K Poulose 2020-05-03 21:35 ` Suzuki K Poulose 2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-04 20:33 ` Will Deacon 2020-05-04 20:33 ` Will Deacon 2020-05-04 20:33 ` Will Deacon 2020-05-05 7:01 ` Anshuman Khandual 2020-05-05 7:01 ` Anshuman Khandual 2020-05-05 7:01 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-05 11:14 ` Will Deacon 2020-05-05 11:14 ` Will Deacon 2020-05-06 6:43 ` Anshuman Khandual 2020-05-06 6:43 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-05 4:54 ` Suzuki K Poulose 2020-05-05 4:54 ` Suzuki K Poulose 2020-05-05 7:06 ` Anshuman Khandual 2020-05-05 7:06 ` Anshuman Khandual 2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual 2020-05-02 13:33 ` Anshuman Khandual 2020-05-05 4:59 ` Suzuki K Poulose 2020-05-05 4:59 ` Suzuki K Poulose 2020-05-06 6:35 ` Anshuman Khandual 2020-05-06 6:35 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual 2020-05-05 9:24 ` Suzuki K Poulose 2020-05-05 9:24 ` Suzuki K Poulose 2020-05-06 6:33 ` Anshuman Khandual [this message] 2020-05-06 6:33 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual 2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual 2020-05-02 13:34 ` Anshuman Khandual
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=197bddfb-d63f-7824-63eb-cc38ae729efe@arm.com \ --to=anshuman.khandual@arm.com \ --cc=catalin.marinas@arm.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=suzuki.poulose@arm.com \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.