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From: Mark Rutland <mark.rutland@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-kernel@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register
Date: Tue, 5 May 2020 12:18:37 +0100	[thread overview]
Message-ID: <20200505111837.GB82823@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20200505111607.GA82823@C02TD0UTHF1T.local>

On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote:
> On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote:
> > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote:
> > > This adds basic building blocks required for ID_PFR2 CPU register which
> > > provides information about the AArch32 programmers model which must be
> > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added
> > > per ARM DDI 0487F.a specification.
> > > 
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: James Morse <james.morse@arm.com>
> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Cc: kvmarm@lists.cs.columbia.edu
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > Cc: linux-kernel@vger.kernel.org
> > > 
> > > Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >  arch/arm64/include/asm/cpu.h    |  1 +
> > >  arch/arm64/include/asm/sysreg.h |  4 ++++
> > >  arch/arm64/kernel/cpufeature.c  | 11 +++++++++++
> > >  arch/arm64/kernel/cpuinfo.c     |  1 +
> > >  arch/arm64/kvm/sys_regs.c       |  2 +-
> > >  5 files changed, 18 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> > > index b4a40535a3d8..464e828a994d 100644
> > > --- a/arch/arm64/include/asm/cpu.h
> > > +++ b/arch/arm64/include/asm/cpu.h
> > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 {
> > >  	u32		reg_id_mmfr3;
> > >  	u32		reg_id_pfr0;
> > >  	u32		reg_id_pfr1;
> > > +	u32		reg_id_pfr2;
> > >  
> > >  	u32		reg_mvfr0;
> > >  	u32		reg_mvfr1;
> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > index e5317a6367b6..c977449e02db 100644
> > > --- a/arch/arm64/include/asm/sysreg.h
> > > +++ b/arch/arm64/include/asm/sysreg.h
> > > @@ -153,6 +153,7 @@
> > >  #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
> > >  #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
> > >  #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
> > > +#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
> > 
> > nit: but please group these defines by name rather than encoding.
> 
> So far we've *always* grouped these by encoding in this file, so can we
> keep things that way for now? Otherwise we're inconsistent with both
> schemes.

Unless you just meant "please put a newline before this" to avoid
grouping without affecting ordering, in which case agreed!

Mark.

WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register
Date: Tue, 5 May 2020 12:18:37 +0100	[thread overview]
Message-ID: <20200505111837.GB82823@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20200505111607.GA82823@C02TD0UTHF1T.local>

On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote:
> On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote:
> > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote:
> > > This adds basic building blocks required for ID_PFR2 CPU register which
> > > provides information about the AArch32 programmers model which must be
> > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added
> > > per ARM DDI 0487F.a specification.
> > > 
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: James Morse <james.morse@arm.com>
> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Cc: kvmarm@lists.cs.columbia.edu
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > Cc: linux-kernel@vger.kernel.org
> > > 
> > > Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >  arch/arm64/include/asm/cpu.h    |  1 +
> > >  arch/arm64/include/asm/sysreg.h |  4 ++++
> > >  arch/arm64/kernel/cpufeature.c  | 11 +++++++++++
> > >  arch/arm64/kernel/cpuinfo.c     |  1 +
> > >  arch/arm64/kvm/sys_regs.c       |  2 +-
> > >  5 files changed, 18 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> > > index b4a40535a3d8..464e828a994d 100644
> > > --- a/arch/arm64/include/asm/cpu.h
> > > +++ b/arch/arm64/include/asm/cpu.h
> > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 {
> > >  	u32		reg_id_mmfr3;
> > >  	u32		reg_id_pfr0;
> > >  	u32		reg_id_pfr1;
> > > +	u32		reg_id_pfr2;
> > >  
> > >  	u32		reg_mvfr0;
> > >  	u32		reg_mvfr1;
> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > index e5317a6367b6..c977449e02db 100644
> > > --- a/arch/arm64/include/asm/sysreg.h
> > > +++ b/arch/arm64/include/asm/sysreg.h
> > > @@ -153,6 +153,7 @@
> > >  #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
> > >  #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
> > >  #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
> > > +#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
> > 
> > nit: but please group these defines by name rather than encoding.
> 
> So far we've *always* grouped these by encoding in this file, so can we
> keep things that way for now? Otherwise we're inconsistent with both
> schemes.

Unless you just meant "please put a newline before this" to avoid
grouping without affecting ordering, in which case agreed!

Mark.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register
Date: Tue, 5 May 2020 12:18:37 +0100	[thread overview]
Message-ID: <20200505111837.GB82823@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20200505111607.GA82823@C02TD0UTHF1T.local>

On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote:
> On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote:
> > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote:
> > > This adds basic building blocks required for ID_PFR2 CPU register which
> > > provides information about the AArch32 programmers model which must be
> > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added
> > > per ARM DDI 0487F.a specification.
> > > 
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: James Morse <james.morse@arm.com>
> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Cc: kvmarm@lists.cs.columbia.edu
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > Cc: linux-kernel@vger.kernel.org
> > > 
> > > Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >  arch/arm64/include/asm/cpu.h    |  1 +
> > >  arch/arm64/include/asm/sysreg.h |  4 ++++
> > >  arch/arm64/kernel/cpufeature.c  | 11 +++++++++++
> > >  arch/arm64/kernel/cpuinfo.c     |  1 +
> > >  arch/arm64/kvm/sys_regs.c       |  2 +-
> > >  5 files changed, 18 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> > > index b4a40535a3d8..464e828a994d 100644
> > > --- a/arch/arm64/include/asm/cpu.h
> > > +++ b/arch/arm64/include/asm/cpu.h
> > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 {
> > >  	u32		reg_id_mmfr3;
> > >  	u32		reg_id_pfr0;
> > >  	u32		reg_id_pfr1;
> > > +	u32		reg_id_pfr2;
> > >  
> > >  	u32		reg_mvfr0;
> > >  	u32		reg_mvfr1;
> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > index e5317a6367b6..c977449e02db 100644
> > > --- a/arch/arm64/include/asm/sysreg.h
> > > +++ b/arch/arm64/include/asm/sysreg.h
> > > @@ -153,6 +153,7 @@
> > >  #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
> > >  #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
> > >  #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
> > > +#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
> > 
> > nit: but please group these defines by name rather than encoding.
> 
> So far we've *always* grouped these by encoding in this file, so can we
> keep things that way for now? Otherwise we're inconsistent with both
> schemes.

Unless you just meant "please put a newline before this" to avoid
grouping without affecting ordering, in which case agreed!

Mark.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-05-05 11:18 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-04 20:24   ` Will Deacon
2020-05-04 20:24     ` Will Deacon
2020-05-05  6:50     ` Anshuman Khandual
2020-05-05  6:50       ` Anshuman Khandual
2020-05-05 10:42       ` Will Deacon
2020-05-05 10:42         ` Will Deacon
2020-05-08  4:25         ` Anshuman Khandual
2020-05-08  4:25           ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-05 11:10   ` Will Deacon
2020-05-05 11:10     ` Will Deacon
2020-05-08  4:59     ` Anshuman Khandual
2020-05-08  4:59       ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-05 11:12   ` Will Deacon
2020-05-05 11:12     ` Will Deacon
2020-05-05 11:12     ` Will Deacon
2020-05-05 11:16     ` Mark Rutland
2020-05-05 11:16       ` Mark Rutland
2020-05-05 11:16       ` Mark Rutland
2020-05-05 11:18       ` Mark Rutland [this message]
2020-05-05 11:18         ` Mark Rutland
2020-05-05 11:18         ` Mark Rutland
2020-05-05 11:27       ` Will Deacon
2020-05-05 11:27         ` Will Deacon
2020-05-05 11:27         ` Will Deacon
2020-05-05 11:50         ` Mark Rutland
2020-05-05 11:50           ` Mark Rutland
2020-05-05 11:50           ` Mark Rutland
2020-05-05 12:12           ` Will Deacon
2020-05-05 12:12             ` Will Deacon
2020-05-05 12:12             ` Will Deacon
2020-05-05 12:49             ` Mark Rutland
2020-05-05 12:49               ` Mark Rutland
2020-05-05 12:49               ` Mark Rutland
2020-05-08  8:32     ` Anshuman Khandual
2020-05-08  8:32       ` Anshuman Khandual
2020-05-08  8:32       ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-03 21:35   ` Suzuki K Poulose
2020-05-03 21:35     ` Suzuki K Poulose
2020-05-03 21:35     ` Suzuki K Poulose
2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-04 20:33   ` Will Deacon
2020-05-04 20:33     ` Will Deacon
2020-05-04 20:33     ` Will Deacon
2020-05-05  7:01     ` Anshuman Khandual
2020-05-05  7:01       ` Anshuman Khandual
2020-05-05  7:01       ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-05 11:14   ` Will Deacon
2020-05-05 11:14     ` Will Deacon
2020-05-06  6:43     ` Anshuman Khandual
2020-05-06  6:43       ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-05  4:54   ` Suzuki K Poulose
2020-05-05  4:54     ` Suzuki K Poulose
2020-05-05  7:06     ` Anshuman Khandual
2020-05-05  7:06       ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-02 13:33   ` Anshuman Khandual
2020-05-05  4:59   ` Suzuki K Poulose
2020-05-05  4:59     ` Suzuki K Poulose
2020-05-06  6:35     ` Anshuman Khandual
2020-05-06  6:35       ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual
2020-05-05  9:24   ` Suzuki K Poulose
2020-05-05  9:24     ` Suzuki K Poulose
2020-05-06  6:33     ` Anshuman Khandual
2020-05-06  6:33       ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-02 13:34   ` Anshuman Khandual

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