[PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[Pierre-Clément Tosi]

Swap the arguments as that seems to have been the author's intention.

Note: This fix wasn't tested on hardware and will result in more bits
      being set by the underlying writel() in rk_clrsetreg(), which
      might bring unexpected behavioural changes.

Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
---
 drivers/net/gmac_rockchip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 04008d2b19..0ecbcdf641 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 	struct px30_grf *grf;
 	enum {
 		PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
-		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
+		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 		PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
 	};
 
-- 
2.35.1.723.g4982287a31-goog

[PATCH 2/9] lib: crypt: Avoid redefining static_assert

[Pierre-Clément Tosi]

Use the macro introduced by commit ef0f4e834c66 ("build_bug.h: add
wrapper for _Static_assert") by importing <linux/build_bug.h>.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
---
 lib/crypt/crypt-port.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/lib/crypt/crypt-port.h b/lib/crypt/crypt-port.h
index 6b9542d75b..e85d3c132c 100644
--- a/lib/crypt/crypt-port.h
+++ b/lib/crypt/crypt-port.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Copyright (C) 2020 Steffen Jaeckel <jaeckel-floss@eyet-services.de> */
 
+#include <linux/build_bug.h>
 #include <linux/types.h>
 #include <vsprintf.h>
 
@@ -10,8 +11,6 @@
 
 #define ARG_UNUSED(x) (x)
 
-#define static_assert(a, b) _Static_assert(a, b)
-
 #define strtoul(cp, endp, base) simple_strtoul(cp, endp, base)
 
 extern const unsigned char ascii64[65];
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 2/9] lib: crypt: Avoid redefining static_assert

[Simon Glass]

On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Use the macro introduced by commit ef0f4e834c66 ("build_bug.h: add
> wrapper for _Static_assert") by importing <linux/build_bug.h>.
>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
> ---
>  lib/crypt/crypt-port.h | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

Re: [PATCH 2/9] lib: crypt: Avoid redefining static_assert

[Steffen Jaeckel]

On 3/16/22 20:23, Simon Glass wrote:
> On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
>>
>> Use the macro introduced by commit ef0f4e834c66 ("build_bug.h: add
>> wrapper for _Static_assert") by importing <linux/build_bug.h>.
>>
>> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
>> Cc: Simon Glass <sjg@chromium.org>
>> Cc: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
>> ---
>>   lib/crypt/crypt-port.h | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>

[PATCH 3/9] scripts: Makefile.lib: Pass __UBOOT__ to DTC's CPP

[Pierre-Clément Tosi]

Some headers included (possibly indirectly) from .dts files might have
U-Boot specific content relying on the __UBOOT__ macro passed to CPP
when building C code. In that case, it would be sensible for DTC to see
that content instead of the non-U-Boot one. To do so, pass the macro to
the pre-processor when generate DTC inputs.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
---
 scripts/Makefile.lib | 1 +
 1 file changed, 1 insertion(+)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index c14da10de7..d7b548dce8 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -192,6 +192,7 @@ dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
 		 -I$(srctree)/arch/$(ARCH)/include                       \
 		 -include $(srctree)/include/linux/kconfig.h             \
 		 -D__ASSEMBLY__                                          \
+		 -D__UBOOT__                                             \
 		 -undef -D__DTS__
 
 # Finds the multi-part object the current object will be linked into
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 3/9] scripts: Makefile.lib: Pass __UBOOT__ to DTC's CPP

[Simon Glass]

Hi Pierre-Clément,

On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Some headers included (possibly indirectly) from .dts files might have
> U-Boot specific content relying on the __UBOOT__ macro passed to CPP
> when building C code. In that case, it would be sensible for DTC to see
> that content instead of the non-U-Boot one. To do so, pass the macro to
> the pre-processor when generate DTC inputs.

Can you give an example of such a situation?

>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> ---
>  scripts/Makefile.lib | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass <sjg@chromium.org>


>
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index c14da10de7..d7b548dce8 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -192,6 +192,7 @@ dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
>                  -I$(srctree)/arch/$(ARCH)/include                       \
>                  -include $(srctree)/include/linux/kconfig.h             \
>                  -D__ASSEMBLY__                                          \
> +                -D__UBOOT__                                             \
>                  -undef -D__DTS__
>
>  # Finds the multi-part object the current object will be linked into
> --
> 2.35.1.723.g4982287a31-goog
>

Re: [PATCH 3/9] scripts: Makefile.lib: Pass __UBOOT__ to DTC's CPP

[Pierre-Clément Tosi]

On Wed, Mar 16, 2022 at 01:23:43PM -0600, Simon Glass wrote:
> Hi Pierre-Clément,
> 
> On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
> >
> > Some headers included (possibly indirectly) from .dts files might have
> > U-Boot specific content relying on the __UBOOT__ macro passed to CPP
> > when building C code. In that case, it would be sensible for DTC to see
> > that content instead of the non-U-Boot one. To do so, pass the macro to
> > the pre-processor when generate DTC inputs.
> 
> Can you give an example of such a situation?

This patch isn't fixing an existing issue. Instead, it preempts one that
following patches, adding "#ifndef __UBOOT__/{code not supported in U-Boot}" in
Linux headers, would bring. But IMO (and IIUC), it makes sense on its own given
the meaning that CPP macro has in C code and how it's systematically set through
KBUILD_CPPFLAGS.

> 
> >
> > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > Cc: Simon Glass <sjg@chromium.org>
> > ---
> >  scripts/Makefile.lib | 1 +
> >  1 file changed, 1 insertion(+)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> 
> >
> > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> > index c14da10de7..d7b548dce8 100644
> > --- a/scripts/Makefile.lib
> > +++ b/scripts/Makefile.lib
> > @@ -192,6 +192,7 @@ dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
> >                  -I$(srctree)/arch/$(ARCH)/include                       \
> >                  -include $(srctree)/include/linux/kconfig.h             \
> >                  -D__ASSEMBLY__                                          \
> > +                -D__UBOOT__                                             \
> >                  -undef -D__DTS__
> >
> >  # Finds the multi-part object the current object will be linked into
> > --
> > 2.35.1.723.g4982287a31-goog
> >

-- 
Pierre

[PATCH 4/9] linux/const.h: Upgrade & Merge vDSO and uAPI

[Pierre-Clément Tosi]

Import the header from version 5.16 of the kernel:

    commit df0cc57e057f18e44dac8e6c18aba47ab53202f9

Inline <vdso/const.h> and <uapi/linux/const.h>. This is wrapped in
"#ifndef __UBOOT__/#include/#else/{inline}" to better document the
origin of the code being added to the U-Boot header (but not present in
the original header) and make diff tools happier when comparing the file
with its reference, which should be useful when porting future changes
from the Linux header and/or if we decide to also import those included
headers into the U-Boot codebase.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
---
 include/linux/const.h | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/include/linux/const.h b/include/linux/const.h
index 379c889232..3e3803d767 100644
--- a/include/linux/const.h
+++ b/include/linux/const.h
@@ -2,8 +2,13 @@
 #ifndef _LINUX_CONST_H
 #define _LINUX_CONST_H
 
-/* const.h: Macros for dealing with constants.  */
+#ifndef __UBOOT__
+#include <vdso/const.h>
+#else
 
+#ifndef __UBOOT__
+#include <uapi/linux/const.h>
+#else
 /* Some constant macros are used in both assembler and
  * C code.  Therefore we cannot annotate them always with
  * 'UL' and other type specifiers unilaterally.  We
@@ -28,7 +33,22 @@
 #define _BITUL(x)	(_UL(1) << (x))
 #define _BITULL(x)	(_ULL(1) << (x))
 
+#define __ALIGN_KERNEL(x, a)		__ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
+#define __ALIGN_KERNEL_MASK(x, mask)	(((x) + (mask)) & ~(mask))
+
+#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+#endif
+
 #define UL(x)		(_UL(x))
 #define ULL(x)		(_ULL(x))
+#endif
+
+/*
+ * This returns a constant expression while determining if an argument is
+ * a constant expression, most importantly without evaluating the argument.
+ * Glory to Martin Uecker <Martin.Uecker@med.uni-goettingen.de>
+ */
+#define __is_constexpr(x) \
+	(sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
 
 #endif /* _LINUX_CONST_H */
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 4/9] linux/const.h: Upgrade & Merge vDSO and uAPI

[Simon Glass]

Hi Pierre-Clément,

On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Import the header from version 5.16 of the kernel:
>
>     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
>
> Inline <vdso/const.h> and <uapi/linux/const.h>. This is wrapped in
> "#ifndef __UBOOT__/#include/#else/{inline}" to better document the
> origin of the code being added to the U-Boot header (but not present in
> the original header) and make diff tools happier when comparing the file
> with its reference, which should be useful when porting future changes
> from the Linux header and/or if we decide to also import those included
> headers into the U-Boot codebase.
>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  include/linux/const.h | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/include/linux/const.h b/include/linux/const.h
> index 379c889232..3e3803d767 100644
> --- a/include/linux/const.h
> +++ b/include/linux/const.h
> @@ -2,8 +2,13 @@
>  #ifndef _LINUX_CONST_H
>  #define _LINUX_CONST_H
>
> -/* const.h: Macros for dealing with constants.  */
> +#ifndef __UBOOT__
> +#include <vdso/const.h>
> +#else
>
> +#ifndef __UBOOT__
> +#include <uapi/linux/const.h>
> +#else
>  /* Some constant macros are used in both assembler and
>   * C code.  Therefore we cannot annotate them always with
>   * 'UL' and other type specifiers unilaterally.  We
> @@ -28,7 +33,22 @@
>  #define _BITUL(x)      (_UL(1) << (x))
>  #define _BITULL(x)     (_ULL(1) << (x))
>
> +#define __ALIGN_KERNEL(x, a)           __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
> +#define __ALIGN_KERNEL_MASK(x, mask)   (((x) + (mask)) & ~(mask))

How does this compare to the existing ALIGN()? It looks the same to me.

> +
> +#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
> +#endif
> +
>  #define UL(x)          (_UL(x))
>  #define ULL(x)         (_ULL(x))
> +#endif
> +
> +/*
> + * This returns a constant expression while determining if an argument is
> + * a constant expression, most importantly without evaluating the argument.
> + * Glory to Martin Uecker <Martin.Uecker@med.uni-goettingen.de>
> + */
> +#define __is_constexpr(x) \
> +       (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
>
>  #endif /* _LINUX_CONST_H */
> --
> 2.35.1.723.g4982287a31-goog
>

REgards,
Simon

Re: [PATCH 4/9] linux/const.h: Upgrade & Merge vDSO and uAPI

[Pierre-Clément Tosi]

On Wed, Mar 16, 2022 at 01:23:44PM -0600, Simon Glass wrote:
> Hi Pierre-Clément,
> 
> On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
> >
> > Import the header from version 5.16 of the kernel:
> >
> >     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> >
> > Inline <vdso/const.h> and <uapi/linux/const.h>. This is wrapped in
> > "#ifndef __UBOOT__/#include/#else/{inline}" to better document the
> > origin of the code being added to the U-Boot header (but not present in
> > the original header) and make diff tools happier when comparing the file
> > with its reference, which should be useful when porting future changes
> > from the Linux header and/or if we decide to also import those included
> > headers into the U-Boot codebase.
> >
> > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > Cc: Simon Glass <sjg@chromium.org>
> > Cc: Tom Rini <trini@konsulko.com>
> > ---
> >  include/linux/const.h | 22 +++++++++++++++++++++-
> >  1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/linux/const.h b/include/linux/const.h
> > index 379c889232..3e3803d767 100644
> > --- a/include/linux/const.h
> > +++ b/include/linux/const.h
> > @@ -2,8 +2,13 @@
> >  #ifndef _LINUX_CONST_H
> >  #define _LINUX_CONST_H
> >
> > -/* const.h: Macros for dealing with constants.  */
> > +#ifndef __UBOOT__
> > +#include <vdso/const.h>
> > +#else
> >
> > +#ifndef __UBOOT__
> > +#include <uapi/linux/const.h>
> > +#else
> >  /* Some constant macros are used in both assembler and
> >   * C code.  Therefore we cannot annotate them always with
> >   * 'UL' and other type specifiers unilaterally.  We
> > @@ -28,7 +33,22 @@
> >  #define _BITUL(x)      (_UL(1) << (x))
> >  #define _BITULL(x)     (_ULL(1) << (x))
> >
> > +#define __ALIGN_KERNEL(x, a)           __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
> > +#define __ALIGN_KERNEL_MASK(x, mask)   (((x) + (mask)) & ~(mask))
> 
> How does this compare to the existing ALIGN()? It looks the same to me.
> 

__ALIGN_KERNEL() is the uAPI counterpart to the ALIGN() kernel macro (or is it
the other way around?) so they're intended to be similar in implementation; the
key difference being the double-leading-underscore notation, which bears a
special meaning as per the C Standard, and allows __ALIGN_KERNEL() to be
considerably easier to export. In fact, the kernel currently defines

    #define ALIGN(x, a)        __ALIGN_KERNEL((x), (a))

For the reason why this patch introduces it here, I've taken the conservative
approach of meticulously copying the original headers over, in their entirety
(as far as feasible), in order to make future upgrades as smooth as possible.

This patch inlines those vDSO and uAPI headers instead of bringing them as the
stand-alone files they are in the kernel as it looks like no other kernel header
of that kind has been imported but IMO, it would make more sense to do the
later. What do you think?

> > +
> > +#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
> > +#endif
> > +
> >  #define UL(x)          (_UL(x))
> >  #define ULL(x)         (_ULL(x))
> > +#endif
> > +
> > +/*
> > + * This returns a constant expression while determining if an argument is
> > + * a constant expression, most importantly without evaluating the argument.
> > + * Glory to Martin Uecker <Martin.Uecker@med.uni-goettingen.de>
> > + */
> > +#define __is_constexpr(x) \
> > +       (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
> >
> >  #endif /* _LINUX_CONST_H */
> > --
> > 2.35.1.723.g4982287a31-goog
> >
> 
> REgards,
> Simon

-- 
Pierre

Re: [PATCH 4/9] linux/const.h: Upgrade & Merge vDSO and uAPI

[Simon Glass]

Hi Pierre-Clément,

On Thu, 17 Mar 2022 at 05:00, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> On Wed, Mar 16, 2022 at 01:23:44PM -0600, Simon Glass wrote:
> > Hi Pierre-Clément,
> >
> > On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
> > >
> > > Import the header from version 5.16 of the kernel:
> > >
> > >     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> > >
> > > Inline <vdso/const.h> and <uapi/linux/const.h>. This is wrapped in
> > > "#ifndef __UBOOT__/#include/#else/{inline}" to better document the
> > > origin of the code being added to the U-Boot header (but not present in
> > > the original header) and make diff tools happier when comparing the file
> > > with its reference, which should be useful when porting future changes
> > > from the Linux header and/or if we decide to also import those included
> > > headers into the U-Boot codebase.
> > >
> > > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > > Cc: Simon Glass <sjg@chromium.org>
> > > Cc: Tom Rini <trini@konsulko.com>
> > > ---
> > >  include/linux/const.h | 22 +++++++++++++++++++++-
> > >  1 file changed, 21 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/linux/const.h b/include/linux/const.h
> > > index 379c889232..3e3803d767 100644
> > > --- a/include/linux/const.h
> > > +++ b/include/linux/const.h
> > > @@ -2,8 +2,13 @@
> > >  #ifndef _LINUX_CONST_H
> > >  #define _LINUX_CONST_H
> > >
> > > -/* const.h: Macros for dealing with constants.  */
> > > +#ifndef __UBOOT__
> > > +#include <vdso/const.h>
> > > +#else
> > >
> > > +#ifndef __UBOOT__
> > > +#include <uapi/linux/const.h>
> > > +#else
> > >  /* Some constant macros are used in both assembler and
> > >   * C code.  Therefore we cannot annotate them always with
> > >   * 'UL' and other type specifiers unilaterally.  We
> > > @@ -28,7 +33,22 @@
> > >  #define _BITUL(x)      (_UL(1) << (x))
> > >  #define _BITULL(x)     (_ULL(1) << (x))
> > >
> > > +#define __ALIGN_KERNEL(x, a)           __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
> > > +#define __ALIGN_KERNEL_MASK(x, mask)   (((x) + (mask)) & ~(mask))
> >
> > How does this compare to the existing ALIGN()? It looks the same to me.
> >
>
> __ALIGN_KERNEL() is the uAPI counterpart to the ALIGN() kernel macro (or is it
> the other way around?) so they're intended to be similar in implementation; the
> key difference being the double-leading-underscore notation, which bears a
> special meaning as per the C Standard, and allows __ALIGN_KERNEL() to be
> considerably easier to export. In fact, the kernel currently defines
>
>     #define ALIGN(x, a)        __ALIGN_KERNEL((x), (a))
>
> For the reason why this patch introduces it here, I've taken the conservative
> approach of meticulously copying the original headers over, in their entirety
> (as far as feasible), in order to make future upgrades as smooth as possible.
>
> This patch inlines those vDSO and uAPI headers instead of bringing them as the
> stand-alone files they are in the kernel as it looks like no other kernel header
> of that kind has been imported but IMO, it would make more sense to do the
> later. What do you think?

OK I see. Using stand-alone files makes it easier to keep things in
sync in the future, but I don't have a strong opinion on it.

Reviewed-by: Simon Glass <sjg@chromium.org>

>
> > > +
> > > +#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
> > > +#endif
> > > +
> > >  #define UL(x)          (_UL(x))
> > >  #define ULL(x)         (_ULL(x))
> > > +#endif
> > > +
> > > +/*
> > > + * This returns a constant expression while determining if an argument is
> > > + * a constant expression, most importantly without evaluating the argument.
> > > + * Glory to Martin Uecker <Martin.Uecker@med.uni-goettingen.de>
> > > + */
> > > +#define __is_constexpr(x) \
> > > +       (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
> > >
> > >  #endif /* _LINUX_CONST_H */
> > > --
> > > 2.35.1.723.g4982287a31-goog

Regards,
Simon

[PATCH 5/9] include: Import <linux/bits.h> & Update bitops.h

[Pierre-Clément Tosi]

Import the header from version 5.16 of the kernel:

    commit df0cc57e057f18e44dac8e6c18aba47ab53202f9

Inline the included <vdso/bits.h> and prevent U-Boot from including
<asm/bitsperlong.h> as BITS_PER_LONG is defined in <asm/types.h>.

Remove now-duplicate definitions from <linux/bitops.h>.

Note: This brings extra compile-time checks through GENMASK_INPUT_CHECK.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
---
 include/linux/bitops.h | 27 ++++++---------------
 include/linux/bits.h   | 55 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+), 20 deletions(-)
 create mode 100644 include/linux/bits.h

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index d2e5ca026e..6d465077d6 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -5,37 +5,24 @@
 
 #include <asm/types.h>
 #include <asm-generic/bitsperlong.h>
+#include <linux/bits.h>
 #include <linux/compiler.h>
 
 #ifdef	__KERNEL__
-#define BIT(nr)			(1UL << (nr))
-#define BIT_ULL(nr)		(1ULL << (nr))
-#define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
-#define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
-#define BIT_ULL_MASK(nr)	(1ULL << ((nr) % BITS_PER_LONG_LONG))
-#define BIT_ULL_WORD(nr)	((nr) / BITS_PER_LONG_LONG)
-#define BITS_PER_BYTE		8
 #define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
 #endif
 
 /* kernel.h includes log.h which include bitops.h */
 #include <linux/kernel.h>
 
-/*
- * Create a contiguous bitmask starting at bit position @l and ending at
- * position @h. For example
- * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
- */
 #ifdef CONFIG_SANDBOX
-#define GENMASK(h, l) \
-	(((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h))))
-#else
-#define GENMASK(h, l) \
-	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+#ifdef __GENMASK
+#undef __GENMASK
+#endif
+#define __GENMASK(h, l) \
+	(((~UL(0)) - (UL(1) << (l)) + 1) & \
+	 (~UL(0) >> (CONFIG_SANDBOX_BITS_PER_LONG  - 1 - (h))))
 #endif
-
-#define GENMASK_ULL(h, l) \
-	(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
 
 /*
  * ffs: find first bit set. This is defined the same way as
diff --git a/include/linux/bits.h b/include/linux/bits.h
new file mode 100644
index 0000000000..04e7dae7f9
--- /dev/null
+++ b/include/linux/bits.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_BITS_H
+#define __LINUX_BITS_H
+
+#include <linux/const.h>
+#ifndef __UBOOT__
+#include <vdso/bits.h>
+#else
+#define BIT(nr)                 (UL(1) << (nr))
+#endif
+#ifndef __UBOOT__
+#include <asm/bitsperlong.h>
+#else
+/* U-Boot defines BITS_PER_LONG in <asm/types.h>. */
+#include <asm/types.h>
+#endif
+
+#define BIT_ULL(nr)		(ULL(1) << (nr))
+#define BIT_MASK(nr)		(UL(1) << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
+#define BIT_ULL_MASK(nr)	(ULL(1) << ((nr) % BITS_PER_LONG_LONG))
+#define BIT_ULL_WORD(nr)	((nr) / BITS_PER_LONG_LONG)
+#define BITS_PER_BYTE		8
+
+/*
+ * Create a contiguous bitmask starting at bit position @l and ending at
+ * position @h. For example
+ * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
+ */
+#if !defined(__ASSEMBLY__)
+#include <linux/build_bug.h>
+#define GENMASK_INPUT_CHECK(h, l) \
+	(BUILD_BUG_ON_ZERO(__builtin_choose_expr( \
+		__is_constexpr((l) > (h)), (l) > (h), 0)))
+#else
+/*
+ * BUILD_BUG_ON_ZERO is not available in h files included from asm files,
+ * disable the input check if that is the case.
+ */
+#define GENMASK_INPUT_CHECK(h, l) 0
+#endif
+
+#define __GENMASK(h, l) \
+	(((~UL(0)) - (UL(1) << (l)) + 1) & \
+	 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
+#define GENMASK(h, l) \
+	(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
+
+#define __GENMASK_ULL(h, l) \
+	(((~ULL(0)) - (ULL(1) << (l)) + 1) & \
+	 (~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h))))
+#define GENMASK_ULL(h, l) \
+	(GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l))
+
+#endif	/* __LINUX_BITS_H */
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 5/9] include: Import <linux/bits.h> & Update bitops.h

[Simon Glass]

On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Import the header from version 5.16 of the kernel:
>
>     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
>
> Inline the included <vdso/bits.h> and prevent U-Boot from including
> <asm/bitsperlong.h> as BITS_PER_LONG is defined in <asm/types.h>.
>
> Remove now-duplicate definitions from <linux/bitops.h>.
>
> Note: This brings extra compile-time checks through GENMASK_INPUT_CHECK.
>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  include/linux/bitops.h | 27 ++++++---------------
>  include/linux/bits.h   | 55 ++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 62 insertions(+), 20 deletions(-)
>  create mode 100644 include/linux/bits.h
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[PATCH 6/9] include: Carve <linux/export.h> out of compat.h

[Pierre-Clément Tosi]

As Linux source code might include that header directly and as it is a
simple "leaf header" (probably won't include other headers) that is
unlikely to be relevant to U-Boot, replicate the upstream header
definitions in a dedicated <linux/export.h> and include it in the
pre-existing compat.h for existing users.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
---
 include/linux/compat.h |  4 +---
 include/linux/export.h | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/export.h

diff --git a/include/linux/compat.h b/include/linux/compat.h
index 3d0acbd582..d34f2ebdf4 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -9,6 +9,7 @@
 
 #include <linux/types.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/kernel.h>
 
 #ifdef CONFIG_XEN
@@ -175,13 +176,10 @@ typedef unsigned long blkcnt_t;
 #endif
 
 /* module */
-#define THIS_MODULE		0
 #define try_module_get(...)	1
 #define module_put(...)		do { } while (0)
 #define module_init(...)
 #define module_exit(...)
-#define EXPORT_SYMBOL(...)
-#define EXPORT_SYMBOL_GPL(...)
 #define module_param(...)
 #define module_param_call(...)
 #define MODULE_PARM_DESC(...)
diff --git a/include/linux/export.h b/include/linux/export.h
new file mode 100644
index 0000000000..31111bcd35
--- /dev/null
+++ b/include/linux/export.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _LINUX_EXPORT_H
+#define _LINUX_EXPORT_H
+
+/*
+ * Export symbols from the kernel to modules.  Forked from module.h
+ * to reduce the amount of pointless cruft we feed to gcc when only
+ * exporting a simple symbol or two.
+ *
+ * Try not to add #includes here.  It slows compilation and makes kernel
+ * hackers place grumpy comments in header files.
+ */
+
+#ifndef __ASSEMBLY__
+
+#define THIS_MODULE	0
+
+#define EXPORT_SYMBOL(...)
+#define EXPORT_SYMBOL_GPL(...)
+#define EXPORT_SYMBOL_NS(...)
+#define EXPORT_SYMBOL_NS_GPL(...)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _LINUX_EXPORT_H */
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 6/9] include: Carve <linux/export.h> out of compat.h

[Simon Glass]

On Wed, 16 Mar 2022 at 09:41, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> As Linux source code might include that header directly and as it is a
> simple "leaf header" (probably won't include other headers) that is
> unlikely to be relevant to U-Boot, replicate the upstream header
> definitions in a dedicated <linux/export.h> and include it in the
> pre-existing compat.h for existing users.
>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  include/linux/compat.h |  4 +---
>  include/linux/export.h | 25 +++++++++++++++++++++++++
>  2 files changed, 26 insertions(+), 3 deletions(-)
>  create mode 100644 include/linux/export.h

Reviewed-by: Simon Glass <sjg@chromium.org>

[PATCH 7/9] include: Upgrade <linux/typecheck.h>

[Pierre-Clément Tosi]

Upgrade the header to version 5.16 of the kernel:

    commit df0cc57e057f18e44dac8e6c18aba47ab53202f9

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
---
 include/linux/typecheck.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
index eb5b74a575..46b15e2aae 100644
--- a/include/linux/typecheck.h
+++ b/include/linux/typecheck.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 #ifndef TYPECHECK_H_INCLUDED
 #define TYPECHECK_H_INCLUDED
 
@@ -21,4 +22,13 @@
 	(void)__tmp; \
 })
 
+/*
+ * Check at compile time that something is a pointer type.
+ */
+#define typecheck_pointer(x) \
+({	typeof(x) __dummy; \
+	(void)sizeof(*__dummy); \
+	1; \
+})
+
 #endif		/* TYPECHECK_H_INCLUDED */
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 7/9] include: Upgrade <linux/typecheck.h>

[Simon Glass]

Hi,

On Wed, 16 Mar 2022 at 09:41, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Upgrade the header to version 5.16 of the kernel:
>
>     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
>
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  include/linux/typecheck.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

But I don't understand how this works at all. Could you add a comment?

>
> diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
> index eb5b74a575..46b15e2aae 100644
> --- a/include/linux/typecheck.h
> +++ b/include/linux/typecheck.h
> @@ -1,3 +1,4 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
>  #ifndef TYPECHECK_H_INCLUDED
>  #define TYPECHECK_H_INCLUDED
>
> @@ -21,4 +22,13 @@
>         (void)__tmp; \
>  })
>
> +/*
> + * Check at compile time that something is a pointer type.
> + */
> +#define typecheck_pointer(x) \
> +({     typeof(x) __dummy; \
> +       (void)sizeof(*__dummy); \
> +       1; \
> +})
> +
>  #endif         /* TYPECHECK_H_INCLUDED */
> --
> 2.35.1.723.g4982287a31-goog
>

Regards,
Simon

Re: [PATCH 7/9] include: Upgrade <linux/typecheck.h>

[Pierre-Clément Tosi]

On Wed, Mar 16, 2022 at 01:23:38PM -0600, Simon Glass wrote:
> Hi,
> 
> On Wed, 16 Mar 2022 at 09:41, Pierre-Clément Tosi <ptosi@google.com> wrote:
> >
> > Upgrade the header to version 5.16 of the kernel:
> >
> >     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> >
> > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > Cc: Simon Glass <sjg@chromium.org>
> > Cc: Tom Rini <trini@konsulko.com>
> > ---
> >  include/linux/typecheck.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> But I don't understand how this works at all. Could you add a comment?

This patch is a simple upgrade of the header. I needed it for another patch
stack and, given how trivial and self-contained it is, I thought I would slip it
into this one.

If your "this" refers to the macro itself, an error should be generated by the
compiler when dereferencing a non-pointer and it avoids introducing side effects
through the use of __dummy but I'm not sure what the sizeof is there for; is it
perhaps compliant for an implementation to keep generating code when
encountering a dereferenced non-pointer (leading to a bogus result, from UB) so
that sizeof forces it to depend on that expression being of a valid type? Or is
it to do with catching variables of incomplete type e.g. arrays of unknown size?
It was introduced by commit cb0f80039fb7 ("bitops: Add non-atomic bitops for
pointers"), which doesn't provide much information either.

> 
> >
> > diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
> > index eb5b74a575..46b15e2aae 100644
> > --- a/include/linux/typecheck.h
> > +++ b/include/linux/typecheck.h
> > @@ -1,3 +1,4 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> >  #ifndef TYPECHECK_H_INCLUDED
> >  #define TYPECHECK_H_INCLUDED
> >
> > @@ -21,4 +22,13 @@
> >         (void)__tmp; \
> >  })
> >
> > +/*
> > + * Check at compile time that something is a pointer type.
> > + */
> > +#define typecheck_pointer(x) \
> > +({     typeof(x) __dummy; \
> > +       (void)sizeof(*__dummy); \
> > +       1; \
> > +})
> > +
> >  #endif         /* TYPECHECK_H_INCLUDED */
> > --
> > 2.35.1.723.g4982287a31-goog
> >
> 
> Regards,
> Simon

-- 
Pierre

Re: [PATCH 7/9] include: Upgrade <linux/typecheck.h>

[Simon Glass]

Hi Pierre-Clément,

On Thu, 17 Mar 2022 at 05:46, Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> On Wed, Mar 16, 2022 at 01:23:38PM -0600, Simon Glass wrote:
> > Hi,
> >
> > On Wed, 16 Mar 2022 at 09:41, Pierre-Clément Tosi <ptosi@google.com> wrote:
> > >
> > > Upgrade the header to version 5.16 of the kernel:
> > >
> > >     commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> > >
> > > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > > Cc: Simon Glass <sjg@chromium.org>
> > > Cc: Tom Rini <trini@konsulko.com>
> > > ---
> > >  include/linux/typecheck.h | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> >
> > Reviewed-by: Simon Glass <sjg@chromium.org>
> >
> > But I don't understand how this works at all. Could you add a comment?
>
> This patch is a simple upgrade of the header. I needed it for another patch
> stack and, given how trivial and self-contained it is, I thought I would slip it
> into this one.
>
> If your "this" refers to the macro itself, an error should be generated by the
> compiler when dereferencing a non-pointer and it avoids introducing side effects
> through the use of __dummy but I'm not sure what the sizeof is there for; is it
> perhaps compliant for an implementation to keep generating code when
> encountering a dereferenced non-pointer (leading to a bogus result, from UB) so
> that sizeof forces it to depend on that expression being of a valid type? Or is
> it to do with catching variables of incomplete type e.g. arrays of unknown size?
> It was introduced by commit cb0f80039fb7 ("bitops: Add non-atomic bitops for
> pointers"), which doesn't provide much information either.

Hmm OK. The Linux people are quite averse to comments. If you have
time you could send a patch to comment the macro and see if someone
responds and dispels the uncertainty.

>
> >
> > >
> > > diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
> > > index eb5b74a575..46b15e2aae 100644
> > > --- a/include/linux/typecheck.h
> > > +++ b/include/linux/typecheck.h
> > > @@ -1,3 +1,4 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > >  #ifndef TYPECHECK_H_INCLUDED
> > >  #define TYPECHECK_H_INCLUDED
> > >
> > > @@ -21,4 +22,13 @@
> > >         (void)__tmp; \
> > >  })
> > >
> > > +/*
> > > + * Check at compile time that something is a pointer type.
> > > + */
> > > +#define typecheck_pointer(x) \
> > > +({     typeof(x) __dummy; \
> > > +       (void)sizeof(*__dummy); \
> > > +       1; \
> > > +})
> > > +
> > >  #endif         /* TYPECHECK_H_INCLUDED */
> > > --
> > > 2.35.1.723.g4982287a31-goog
Regards,
Simon

[PATCH 8/9] arm64: Import <asm/sysreg.h> from Linux

[Pierre-Clément Tosi]

Import the header and its companion <asm/gpr-num.h> from version 5.16:

    commit df0cc57e057f18e44dac8e6c18aba47ab53202f9

Prevent U-Boot from including <linux/kasan-tags.h> and
<asm/alternative.h> as those are not relevant.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Tom Rini <trini@konsulko.com>
---
 arch/arm/include/asm/gpr-num.h |   26 +
 arch/arm/include/asm/sysreg.h  | 1317 ++++++++++++++++++++++++++++++++
 2 files changed, 1343 insertions(+)
 create mode 100644 arch/arm/include/asm/gpr-num.h
 create mode 100644 arch/arm/include/asm/sysreg.h

diff --git a/arch/arm/include/asm/gpr-num.h b/arch/arm/include/asm/gpr-num.h
new file mode 100644
index 0000000000..05da4a7c57
--- /dev/null
+++ b/arch/arm/include/asm/gpr-num.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_GPR_NUM_H
+#define __ASM_GPR_NUM_H
+
+#ifdef __ASSEMBLY__
+
+	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+	.equ	.L__gpr_num_x\num, \num
+	.equ	.L__gpr_num_w\num, \num
+	.endr
+	.equ	.L__gpr_num_xzr, 31
+	.equ	.L__gpr_num_wzr, 31
+
+#else /* __ASSEMBLY__ */
+
+#define __DEFINE_ASM_GPR_NUMS					\
+"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
+"	.equ	.L__gpr_num_x\\num, \\num\n"			\
+"	.equ	.L__gpr_num_w\\num, \\num\n"			\
+"	.endr\n"						\
+"	.equ	.L__gpr_num_xzr, 31\n"				\
+"	.equ	.L__gpr_num_wzr, 31\n"
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_GPR_NUM_H */
diff --git a/arch/arm/include/asm/sysreg.h b/arch/arm/include/asm/sysreg.h
new file mode 100644
index 0000000000..40eb2a315b
--- /dev/null
+++ b/arch/arm/include/asm/sysreg.h
@@ -0,0 +1,1317 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Macros for accessing system registers with older binutils.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ */
+
+#ifndef __ASM_SYSREG_H
+#define __ASM_SYSREG_H
+
+#include <linux/bits.h>
+#include <linux/stringify.h>
+#ifndef __UBOOT__
+#include <linux/kasan-tags.h>
+#endif
+
+#include <asm/gpr-num.h>
+
+/*
+ * ARMv8 ARM reserves the following encoding for system registers:
+ * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
+ *  C5.2, version:ARM DDI 0487A.f)
+ *	[20-19] : Op0
+ *	[18-16] : Op1
+ *	[15-12] : CRn
+ *	[11-8]  : CRm
+ *	[7-5]   : Op2
+ */
+#define Op0_shift	19
+#define Op0_mask	0x3
+#define Op1_shift	16
+#define Op1_mask	0x7
+#define CRn_shift	12
+#define CRn_mask	0xf
+#define CRm_shift	8
+#define CRm_mask	0xf
+#define Op2_shift	5
+#define Op2_mask	0x7
+
+#define sys_reg(op0, op1, crn, crm, op2) \
+	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
+	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
+	 ((op2) << Op2_shift))
+
+#define sys_insn	sys_reg
+
+#define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
+#define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
+#define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
+#define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
+#define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
+
+#ifndef CONFIG_BROKEN_GAS_INST
+
+#ifdef __ASSEMBLY__
+// The space separator is omitted so that __emit_inst(x) can be parsed as
+// either an assembler directive or an assembler macro argument.
+#define __emit_inst(x)			.inst(x)
+#else
+#define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
+#endif
+
+#else  /* CONFIG_BROKEN_GAS_INST */
+
+#ifndef CONFIG_CPU_BIG_ENDIAN
+#define __INSTR_BSWAP(x)		(x)
+#else  /* CONFIG_CPU_BIG_ENDIAN */
+#define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
+					 (((x) <<  8) & 0x00ff0000)	| \
+					 (((x) >>  8) & 0x0000ff00)	| \
+					 (((x) >> 24) & 0x000000ff))
+#endif	/* CONFIG_CPU_BIG_ENDIAN */
+
+#ifdef __ASSEMBLY__
+#define __emit_inst(x)			.long __INSTR_BSWAP(x)
+#else  /* __ASSEMBLY__ */
+#define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_BROKEN_GAS_INST */
+
+/*
+ * Instructions for modifying PSTATE fields.
+ * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
+ * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
+ * for accessing PSTATE fields have the following encoding:
+ *	Op0 = 0, CRn = 4
+ *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
+ *	CRm = Imm4 for the instruction.
+ *	Rt = 0x1f
+ */
+#define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
+#define PSTATE_Imm_shift		CRm_shift
+
+#define PSTATE_PAN			pstate_field(0, 4)
+#define PSTATE_UAO			pstate_field(0, 3)
+#define PSTATE_SSBS			pstate_field(3, 1)
+#define PSTATE_TCO			pstate_field(3, 4)
+
+#define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
+
+#define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
+#define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
+#define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
+
+#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
+	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
+
+#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
+
+#define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
+#define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
+#define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
+
+/*
+ * System registers, organised loosely by encoding but grouped together
+ * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
+ */
+#define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
+#define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
+#define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
+#define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
+#define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
+#define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
+#define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
+#define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
+#define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
+#define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
+#define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
+#define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
+#define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
+#define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
+#define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
+#define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
+#define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
+#define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
+#define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
+#define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
+#define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
+#define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
+
+#define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
+#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
+#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
+
+#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
+#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
+#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
+#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
+#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
+#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
+#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
+#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
+#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
+#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
+#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
+#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
+
+#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
+#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
+#define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
+#define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
+#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
+#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
+#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
+
+#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
+#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
+#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
+
+#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
+#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
+#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
+
+#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
+#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
+
+#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
+#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
+
+#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
+#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
+
+#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
+#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
+#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
+
+#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
+#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
+#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
+#define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
+#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
+
+#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
+
+#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
+#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
+#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
+
+#define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
+#define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
+#define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
+#define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
+
+#define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
+#define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
+#define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
+#define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
+
+#define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
+#define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
+
+#define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
+#define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
+
+#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
+
+#define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
+#define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
+#define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
+
+#define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
+#define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
+#define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
+#define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
+#define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
+#define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
+#define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
+#define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
+#define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
+#define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
+
+#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
+#define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
+
+#define SYS_PAR_EL1_F			BIT(0)
+#define SYS_PAR_EL1_FST			GENMASK(6, 1)
+
+/*** Statistical Profiling Extension ***/
+/* ID registers */
+#define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
+#define SYS_PMSIDR_EL1_FE_SHIFT		0
+#define SYS_PMSIDR_EL1_FT_SHIFT		1
+#define SYS_PMSIDR_EL1_FL_SHIFT		2
+#define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
+#define SYS_PMSIDR_EL1_LDS_SHIFT	4
+#define SYS_PMSIDR_EL1_ERND_SHIFT	5
+#define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
+#define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
+#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
+#define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
+#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
+#define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
+
+#define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
+#define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
+#define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
+#define SYS_PMBIDR_EL1_P_SHIFT		4
+#define SYS_PMBIDR_EL1_F_SHIFT		5
+
+/* Sampling controls */
+#define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
+#define SYS_PMSCR_EL1_E0SPE_SHIFT	0
+#define SYS_PMSCR_EL1_E1SPE_SHIFT	1
+#define SYS_PMSCR_EL1_CX_SHIFT		3
+#define SYS_PMSCR_EL1_PA_SHIFT		4
+#define SYS_PMSCR_EL1_TS_SHIFT		5
+#define SYS_PMSCR_EL1_PCT_SHIFT		6
+
+#define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
+#define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
+#define SYS_PMSCR_EL2_E2SPE_SHIFT	1
+#define SYS_PMSCR_EL2_CX_SHIFT		3
+#define SYS_PMSCR_EL2_PA_SHIFT		4
+#define SYS_PMSCR_EL2_TS_SHIFT		5
+#define SYS_PMSCR_EL2_PCT_SHIFT		6
+
+#define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
+
+#define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
+#define SYS_PMSIRR_EL1_RND_SHIFT	0
+#define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
+#define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
+
+/* Filtering controls */
+#define SYS_PMSNEVFR_EL1		sys_reg(3, 0, 9, 9, 1)
+
+#define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
+#define SYS_PMSFCR_EL1_FE_SHIFT		0
+#define SYS_PMSFCR_EL1_FT_SHIFT		1
+#define SYS_PMSFCR_EL1_FL_SHIFT		2
+#define SYS_PMSFCR_EL1_B_SHIFT		16
+#define SYS_PMSFCR_EL1_LD_SHIFT		17
+#define SYS_PMSFCR_EL1_ST_SHIFT		18
+
+#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
+#define SYS_PMSEVFR_EL1_RES0_8_2	\
+	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
+	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
+#define SYS_PMSEVFR_EL1_RES0_8_3	\
+	(SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
+
+#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
+#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
+
+/* Buffer controls */
+#define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
+#define SYS_PMBLIMITR_EL1_E_SHIFT	0
+#define SYS_PMBLIMITR_EL1_FM_SHIFT	1
+#define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
+#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
+
+#define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
+
+/* Buffer error reporting */
+#define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
+#define SYS_PMBSR_EL1_COLL_SHIFT	16
+#define SYS_PMBSR_EL1_S_SHIFT		17
+#define SYS_PMBSR_EL1_EA_SHIFT		18
+#define SYS_PMBSR_EL1_DL_SHIFT		19
+#define SYS_PMBSR_EL1_EC_SHIFT		26
+#define SYS_PMBSR_EL1_EC_MASK		0x3fUL
+
+#define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
+#define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
+#define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
+
+#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
+#define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
+
+#define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
+#define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
+
+#define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
+
+/*** End of Statistical Profiling Extension ***/
+
+/*
+ * TRBE Registers
+ */
+#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
+#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
+#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
+#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
+#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
+#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
+#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
+
+#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
+#define TRBLIMITR_LIMIT_SHIFT		12
+#define TRBLIMITR_NVM			BIT(5)
+#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
+#define TRBLIMITR_TRIG_MODE_SHIFT	3
+#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
+#define TRBLIMITR_FILL_MODE_SHIFT	1
+#define TRBLIMITR_ENABLE		BIT(0)
+#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
+#define TRBPTR_PTR_SHIFT		0
+#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
+#define TRBBASER_BASE_SHIFT		12
+#define TRBSR_EC_MASK			GENMASK(5, 0)
+#define TRBSR_EC_SHIFT			26
+#define TRBSR_IRQ			BIT(22)
+#define TRBSR_TRG			BIT(21)
+#define TRBSR_WRAP			BIT(20)
+#define TRBSR_ABORT			BIT(18)
+#define TRBSR_STOP			BIT(17)
+#define TRBSR_MSS_MASK			GENMASK(15, 0)
+#define TRBSR_MSS_SHIFT			0
+#define TRBSR_BSC_MASK			GENMASK(5, 0)
+#define TRBSR_BSC_SHIFT			0
+#define TRBSR_FSC_MASK			GENMASK(5, 0)
+#define TRBSR_FSC_SHIFT			0
+#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
+#define TRBMAR_SHARE_SHIFT		8
+#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
+#define TRBMAR_OUTER_SHIFT		4
+#define TRBMAR_INNER_MASK		GENMASK(3, 0)
+#define TRBMAR_INNER_SHIFT		0
+#define TRBTRG_TRG_MASK			GENMASK(31, 0)
+#define TRBTRG_TRG_SHIFT		0
+#define TRBIDR_FLAG			BIT(5)
+#define TRBIDR_PROG			BIT(4)
+#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
+#define TRBIDR_ALIGN_SHIFT		0
+
+#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
+#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
+
+#define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
+
+#define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
+#define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
+
+#define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)
+#define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)
+#define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)
+#define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)
+#define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)
+
+#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
+#define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
+
+#define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
+#define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
+#define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
+#define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
+#define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
+#define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
+#define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
+#define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
+#define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
+#define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
+#define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
+#define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
+#define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
+#define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
+#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
+#define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
+#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
+#define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
+#define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
+#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
+#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
+#define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
+#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
+#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
+#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
+#define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
+#define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
+
+#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
+#define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
+
+#define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
+
+#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
+
+#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
+#define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
+#define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
+#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
+
+#define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
+
+#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
+#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
+
+#define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
+#define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
+
+#define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
+#define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
+#define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
+#define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
+#define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
+#define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
+#define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
+#define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
+#define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
+#define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
+#define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
+#define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
+#define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
+
+#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
+#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
+
+#define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
+
+/* Definitions for system register interface to AMU for ARMv8.4 onwards */
+#define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
+#define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
+#define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
+#define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
+#define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
+#define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
+#define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
+#define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
+#define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
+
+/*
+ * Group 0 of activity monitors (architected):
+ *                op0  op1  CRn   CRm       op2
+ * Counter:       11   011  1101  010:n<3>  n<2:0>
+ * Type:          11   011  1101  011:n<3>  n<2:0>
+ * n: 0-15
+ *
+ * Group 1 of activity monitors (auxiliary):
+ *                op0  op1  CRn   CRm       op2
+ * Counter:       11   011  1101  110:n<3>  n<2:0>
+ * Type:          11   011  1101  111:n<3>  n<2:0>
+ * n: 0-15
+ */
+
+#define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
+#define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
+#define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
+#define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
+
+/* AMU v1: Fixed (architecturally defined) activity monitors */
+#define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
+#define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
+#define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
+#define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
+
+#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
+
+#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
+#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
+
+#define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
+#define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
+#define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
+
+#define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
+#define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
+
+#define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
+#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
+#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
+
+#define __PMEV_op2(n)			((n) & 0x7)
+#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
+#define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
+#define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
+#define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
+
+#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
+
+#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
+#define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
+#define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
+#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
+#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
+#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
+#define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
+#define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
+#define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
+#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
+#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
+#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
+#define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
+#define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
+#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
+#define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
+#define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
+
+#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
+#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
+#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
+#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
+#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
+#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
+
+#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
+#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
+#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
+#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
+#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
+
+#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
+#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
+#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
+#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
+#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
+#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
+#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
+#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
+
+#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
+#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
+#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
+#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
+#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
+#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
+#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
+#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
+#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
+
+#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
+#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
+#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
+#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
+#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
+#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
+#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
+#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
+#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
+
+/* VHE encodings for architectural EL0/1 system registers */
+#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
+#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
+#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
+#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
+#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
+#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
+#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
+#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
+#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
+#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
+#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
+#define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
+#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
+#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
+#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
+#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
+#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
+#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
+#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
+#define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
+#define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
+#define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
+#define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
+#define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
+
+/* Common SCTLR_ELx flags. */
+#define SCTLR_ELx_DSSBS	(BIT(44))
+#define SCTLR_ELx_ATA	(BIT(43))
+
+#define SCTLR_ELx_TCF_SHIFT	40
+#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
+
+#define SCTLR_ELx_ENIA_SHIFT	31
+
+#define SCTLR_ELx_ITFSB	(BIT(37))
+#define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
+#define SCTLR_ELx_ENIB	(BIT(30))
+#define SCTLR_ELx_ENDA	(BIT(27))
+#define SCTLR_ELx_EE    (BIT(25))
+#define SCTLR_ELx_IESB	(BIT(21))
+#define SCTLR_ELx_WXN	(BIT(19))
+#define SCTLR_ELx_ENDB	(BIT(13))
+#define SCTLR_ELx_I	(BIT(12))
+#define SCTLR_ELx_SA	(BIT(3))
+#define SCTLR_ELx_C	(BIT(2))
+#define SCTLR_ELx_A	(BIT(1))
+#define SCTLR_ELx_M	(BIT(0))
+
+/* SCTLR_EL2 specific flags. */
+#define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
+			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
+			 (BIT(29)))
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ENDIAN_SET_EL2		SCTLR_ELx_EE
+#else
+#define ENDIAN_SET_EL2		0
+#endif
+
+#define INIT_SCTLR_EL2_MMU_ON						\
+	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
+	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
+	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
+
+#define INIT_SCTLR_EL2_MMU_OFF \
+	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
+
+/* SCTLR_EL1 specific flags. */
+#define SCTLR_EL1_EPAN		(BIT(57))
+#define SCTLR_EL1_ATA0		(BIT(42))
+
+#define SCTLR_EL1_TCF0_SHIFT	38
+#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
+
+#define SCTLR_EL1_BT1		(BIT(36))
+#define SCTLR_EL1_BT0		(BIT(35))
+#define SCTLR_EL1_UCI		(BIT(26))
+#define SCTLR_EL1_E0E		(BIT(24))
+#define SCTLR_EL1_SPAN		(BIT(23))
+#define SCTLR_EL1_NTWE		(BIT(18))
+#define SCTLR_EL1_NTWI		(BIT(16))
+#define SCTLR_EL1_UCT		(BIT(15))
+#define SCTLR_EL1_DZE		(BIT(14))
+#define SCTLR_EL1_UMA		(BIT(9))
+#define SCTLR_EL1_SED		(BIT(8))
+#define SCTLR_EL1_ITD		(BIT(7))
+#define SCTLR_EL1_CP15BEN	(BIT(5))
+#define SCTLR_EL1_SA0		(BIT(4))
+
+#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
+			 (BIT(29)))
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
+#else
+#define ENDIAN_SET_EL1		0
+#endif
+
+#define INIT_SCTLR_EL1_MMU_OFF \
+	(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
+
+#define INIT_SCTLR_EL1_MMU_ON \
+	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
+	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
+	 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
+	 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
+
+/* MAIR_ELx memory attributes (used by Linux) */
+#define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
+#define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
+#define MAIR_ATTR_NORMAL_NC		UL(0x44)
+#define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
+#define MAIR_ATTR_NORMAL		UL(0xff)
+#define MAIR_ATTR_MASK			UL(0xff)
+
+/* Position the attr at the correct index */
+#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
+
+/* id_aa64isar0 */
+#define ID_AA64ISAR0_RNDR_SHIFT		60
+#define ID_AA64ISAR0_TLB_SHIFT		56
+#define ID_AA64ISAR0_TS_SHIFT		52
+#define ID_AA64ISAR0_FHM_SHIFT		48
+#define ID_AA64ISAR0_DP_SHIFT		44
+#define ID_AA64ISAR0_SM4_SHIFT		40
+#define ID_AA64ISAR0_SM3_SHIFT		36
+#define ID_AA64ISAR0_SHA3_SHIFT		32
+#define ID_AA64ISAR0_RDM_SHIFT		28
+#define ID_AA64ISAR0_ATOMICS_SHIFT	20
+#define ID_AA64ISAR0_CRC32_SHIFT	16
+#define ID_AA64ISAR0_SHA2_SHIFT		12
+#define ID_AA64ISAR0_SHA1_SHIFT		8
+#define ID_AA64ISAR0_AES_SHIFT		4
+
+#define ID_AA64ISAR0_TLB_RANGE_NI	0x0
+#define ID_AA64ISAR0_TLB_RANGE		0x2
+
+/* id_aa64isar1 */
+#define ID_AA64ISAR1_I8MM_SHIFT		52
+#define ID_AA64ISAR1_DGH_SHIFT		48
+#define ID_AA64ISAR1_BF16_SHIFT		44
+#define ID_AA64ISAR1_SPECRES_SHIFT	40
+#define ID_AA64ISAR1_SB_SHIFT		36
+#define ID_AA64ISAR1_FRINTTS_SHIFT	32
+#define ID_AA64ISAR1_GPI_SHIFT		28
+#define ID_AA64ISAR1_GPA_SHIFT		24
+#define ID_AA64ISAR1_LRCPC_SHIFT	20
+#define ID_AA64ISAR1_FCMA_SHIFT		16
+#define ID_AA64ISAR1_JSCVT_SHIFT	12
+#define ID_AA64ISAR1_API_SHIFT		8
+#define ID_AA64ISAR1_APA_SHIFT		4
+#define ID_AA64ISAR1_DPB_SHIFT		0
+
+#define ID_AA64ISAR1_APA_NI			0x0
+#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
+#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
+#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
+#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_API_NI			0x0
+#define ID_AA64ISAR1_API_IMP_DEF		0x1
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_GPA_NI			0x0
+#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_GPI_NI			0x0
+#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
+
+/* id_aa64pfr0 */
+#define ID_AA64PFR0_CSV3_SHIFT		60
+#define ID_AA64PFR0_CSV2_SHIFT		56
+#define ID_AA64PFR0_DIT_SHIFT		48
+#define ID_AA64PFR0_AMU_SHIFT		44
+#define ID_AA64PFR0_MPAM_SHIFT		40
+#define ID_AA64PFR0_SEL2_SHIFT		36
+#define ID_AA64PFR0_SVE_SHIFT		32
+#define ID_AA64PFR0_RAS_SHIFT		28
+#define ID_AA64PFR0_GIC_SHIFT		24
+#define ID_AA64PFR0_ASIMD_SHIFT		20
+#define ID_AA64PFR0_FP_SHIFT		16
+#define ID_AA64PFR0_EL3_SHIFT		12
+#define ID_AA64PFR0_EL2_SHIFT		8
+#define ID_AA64PFR0_EL1_SHIFT		4
+#define ID_AA64PFR0_EL0_SHIFT		0
+
+#define ID_AA64PFR0_AMU			0x1
+#define ID_AA64PFR0_SVE			0x1
+#define ID_AA64PFR0_RAS_V1		0x1
+#define ID_AA64PFR0_RAS_V1P1		0x2
+#define ID_AA64PFR0_FP_NI		0xf
+#define ID_AA64PFR0_FP_SUPPORTED	0x0
+#define ID_AA64PFR0_ASIMD_NI		0xf
+#define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
+#define ID_AA64PFR0_ELx_64BIT_ONLY	0x1
+#define ID_AA64PFR0_ELx_32BIT_64BIT	0x2
+
+/* id_aa64pfr1 */
+#define ID_AA64PFR1_MPAMFRAC_SHIFT	16
+#define ID_AA64PFR1_RASFRAC_SHIFT	12
+#define ID_AA64PFR1_MTE_SHIFT		8
+#define ID_AA64PFR1_SSBS_SHIFT		4
+#define ID_AA64PFR1_BT_SHIFT		0
+
+#define ID_AA64PFR1_SSBS_PSTATE_NI	0
+#define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
+#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
+#define ID_AA64PFR1_BT_BTI		0x1
+
+#define ID_AA64PFR1_MTE_NI		0x0
+#define ID_AA64PFR1_MTE_EL0		0x1
+#define ID_AA64PFR1_MTE			0x2
+#define ID_AA64PFR1_MTE_ASYMM		0x3
+
+/* id_aa64zfr0 */
+#define ID_AA64ZFR0_F64MM_SHIFT		56
+#define ID_AA64ZFR0_F32MM_SHIFT		52
+#define ID_AA64ZFR0_I8MM_SHIFT		44
+#define ID_AA64ZFR0_SM4_SHIFT		40
+#define ID_AA64ZFR0_SHA3_SHIFT		32
+#define ID_AA64ZFR0_BF16_SHIFT		20
+#define ID_AA64ZFR0_BITPERM_SHIFT	16
+#define ID_AA64ZFR0_AES_SHIFT		4
+#define ID_AA64ZFR0_SVEVER_SHIFT	0
+
+#define ID_AA64ZFR0_F64MM		0x1
+#define ID_AA64ZFR0_F32MM		0x1
+#define ID_AA64ZFR0_I8MM		0x1
+#define ID_AA64ZFR0_BF16		0x1
+#define ID_AA64ZFR0_SM4			0x1
+#define ID_AA64ZFR0_SHA3		0x1
+#define ID_AA64ZFR0_BITPERM		0x1
+#define ID_AA64ZFR0_AES			0x1
+#define ID_AA64ZFR0_AES_PMULL		0x2
+#define ID_AA64ZFR0_SVEVER_SVE2		0x1
+
+/* id_aa64mmfr0 */
+#define ID_AA64MMFR0_ECV_SHIFT		60
+#define ID_AA64MMFR0_FGT_SHIFT		56
+#define ID_AA64MMFR0_EXS_SHIFT		44
+#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40
+#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36
+#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32
+#define ID_AA64MMFR0_TGRAN4_SHIFT	28
+#define ID_AA64MMFR0_TGRAN64_SHIFT	24
+#define ID_AA64MMFR0_TGRAN16_SHIFT	20
+#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
+#define ID_AA64MMFR0_SNSMEM_SHIFT	12
+#define ID_AA64MMFR0_BIGENDEL_SHIFT	8
+#define ID_AA64MMFR0_ASID_SHIFT		4
+#define ID_AA64MMFR0_PARANGE_SHIFT	0
+
+#define ID_AA64MMFR0_ASID_8		0x0
+#define ID_AA64MMFR0_ASID_16		0x2
+
+#define ID_AA64MMFR0_TGRAN4_NI			0xf
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7
+#define ID_AA64MMFR0_TGRAN64_NI			0xf
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7
+#define ID_AA64MMFR0_TGRAN16_NI			0x0
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf
+
+#define ID_AA64MMFR0_PARANGE_32		0x0
+#define ID_AA64MMFR0_PARANGE_36		0x1
+#define ID_AA64MMFR0_PARANGE_40		0x2
+#define ID_AA64MMFR0_PARANGE_42		0x3
+#define ID_AA64MMFR0_PARANGE_44		0x4
+#define ID_AA64MMFR0_PARANGE_48		0x5
+#define ID_AA64MMFR0_PARANGE_52		0x6
+
+#define ARM64_MIN_PARANGE_BITS		32
+
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7
+
+#ifdef CONFIG_ARM64_PA_BITS_52
+#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
+#else
+#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
+#endif
+
+/* id_aa64mmfr1 */
+#define ID_AA64MMFR1_ETS_SHIFT		36
+#define ID_AA64MMFR1_TWED_SHIFT		32
+#define ID_AA64MMFR1_XNX_SHIFT		28
+#define ID_AA64MMFR1_SPECSEI_SHIFT	24
+#define ID_AA64MMFR1_PAN_SHIFT		20
+#define ID_AA64MMFR1_LOR_SHIFT		16
+#define ID_AA64MMFR1_HPD_SHIFT		12
+#define ID_AA64MMFR1_VHE_SHIFT		8
+#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
+#define ID_AA64MMFR1_HADBS_SHIFT	0
+
+#define ID_AA64MMFR1_VMIDBITS_8		0
+#define ID_AA64MMFR1_VMIDBITS_16	2
+
+/* id_aa64mmfr2 */
+#define ID_AA64MMFR2_E0PD_SHIFT		60
+#define ID_AA64MMFR2_EVT_SHIFT		56
+#define ID_AA64MMFR2_BBM_SHIFT		52
+#define ID_AA64MMFR2_TTL_SHIFT		48
+#define ID_AA64MMFR2_FWB_SHIFT		40
+#define ID_AA64MMFR2_IDS_SHIFT		36
+#define ID_AA64MMFR2_AT_SHIFT		32
+#define ID_AA64MMFR2_ST_SHIFT		28
+#define ID_AA64MMFR2_NV_SHIFT		24
+#define ID_AA64MMFR2_CCIDX_SHIFT	20
+#define ID_AA64MMFR2_LVA_SHIFT		16
+#define ID_AA64MMFR2_IESB_SHIFT		12
+#define ID_AA64MMFR2_LSM_SHIFT		8
+#define ID_AA64MMFR2_UAO_SHIFT		4
+#define ID_AA64MMFR2_CNP_SHIFT		0
+
+/* id_aa64dfr0 */
+#define ID_AA64DFR0_MTPMU_SHIFT		48
+#define ID_AA64DFR0_TRBE_SHIFT		44
+#define ID_AA64DFR0_TRACE_FILT_SHIFT	40
+#define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
+#define ID_AA64DFR0_PMSVER_SHIFT	32
+#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
+#define ID_AA64DFR0_WRPS_SHIFT		20
+#define ID_AA64DFR0_BRPS_SHIFT		12
+#define ID_AA64DFR0_PMUVER_SHIFT	8
+#define ID_AA64DFR0_TRACEVER_SHIFT	4
+#define ID_AA64DFR0_DEBUGVER_SHIFT	0
+
+#define ID_AA64DFR0_PMUVER_8_0		0x1
+#define ID_AA64DFR0_PMUVER_8_1		0x4
+#define ID_AA64DFR0_PMUVER_8_4		0x5
+#define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
+
+#define ID_AA64DFR0_PMSVER_8_2		0x1
+#define ID_AA64DFR0_PMSVER_8_3		0x2
+
+#define ID_DFR0_PERFMON_SHIFT		24
+
+#define ID_DFR0_PERFMON_8_0		0x3
+#define ID_DFR0_PERFMON_8_1		0x4
+#define ID_DFR0_PERFMON_8_4		0x5
+#define ID_DFR0_PERFMON_8_5		0x6
+
+#define ID_ISAR4_SWP_FRAC_SHIFT		28
+#define ID_ISAR4_PSR_M_SHIFT		24
+#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20
+#define ID_ISAR4_BARRIER_SHIFT		16
+#define ID_ISAR4_SMC_SHIFT		12
+#define ID_ISAR4_WRITEBACK_SHIFT	8
+#define ID_ISAR4_WITHSHIFTS_SHIFT	4
+#define ID_ISAR4_UNPRIV_SHIFT		0
+
+#define ID_DFR1_MTPMU_SHIFT		0
+
+#define ID_ISAR0_DIVIDE_SHIFT		24
+#define ID_ISAR0_DEBUG_SHIFT		20
+#define ID_ISAR0_COPROC_SHIFT		16
+#define ID_ISAR0_CMPBRANCH_SHIFT	12
+#define ID_ISAR0_BITFIELD_SHIFT		8
+#define ID_ISAR0_BITCOUNT_SHIFT		4
+#define ID_ISAR0_SWAP_SHIFT		0
+
+#define ID_ISAR5_RDM_SHIFT		24
+#define ID_ISAR5_CRC32_SHIFT		16
+#define ID_ISAR5_SHA2_SHIFT		12
+#define ID_ISAR5_SHA1_SHIFT		8
+#define ID_ISAR5_AES_SHIFT		4
+#define ID_ISAR5_SEVL_SHIFT		0
+
+#define ID_ISAR6_I8MM_SHIFT		24
+#define ID_ISAR6_BF16_SHIFT		20
+#define ID_ISAR6_SPECRES_SHIFT		16
+#define ID_ISAR6_SB_SHIFT		12
+#define ID_ISAR6_FHM_SHIFT		8
+#define ID_ISAR6_DP_SHIFT		4
+#define ID_ISAR6_JSCVT_SHIFT		0
+
+#define ID_MMFR0_INNERSHR_SHIFT		28
+#define ID_MMFR0_FCSE_SHIFT		24
+#define ID_MMFR0_AUXREG_SHIFT		20
+#define ID_MMFR0_TCM_SHIFT		16
+#define ID_MMFR0_SHARELVL_SHIFT		12
+#define ID_MMFR0_OUTERSHR_SHIFT		8
+#define ID_MMFR0_PMSA_SHIFT		4
+#define ID_MMFR0_VMSA_SHIFT		0
+
+#define ID_MMFR4_EVT_SHIFT		28
+#define ID_MMFR4_CCIDX_SHIFT		24
+#define ID_MMFR4_LSM_SHIFT		20
+#define ID_MMFR4_HPDS_SHIFT		16
+#define ID_MMFR4_CNP_SHIFT		12
+#define ID_MMFR4_XNX_SHIFT		8
+#define ID_MMFR4_AC2_SHIFT		4
+#define ID_MMFR4_SPECSEI_SHIFT		0
+
+#define ID_MMFR5_ETS_SHIFT		0
+
+#define ID_PFR0_DIT_SHIFT		24
+#define ID_PFR0_CSV2_SHIFT		16
+#define ID_PFR0_STATE3_SHIFT		12
+#define ID_PFR0_STATE2_SHIFT		8
+#define ID_PFR0_STATE1_SHIFT		4
+#define ID_PFR0_STATE0_SHIFT		0
+
+#define ID_DFR0_PERFMON_SHIFT		24
+#define ID_DFR0_MPROFDBG_SHIFT		20
+#define ID_DFR0_MMAPTRC_SHIFT		16
+#define ID_DFR0_COPTRC_SHIFT		12
+#define ID_DFR0_MMAPDBG_SHIFT		8
+#define ID_DFR0_COPSDBG_SHIFT		4
+#define ID_DFR0_COPDBG_SHIFT		0
+
+#define ID_PFR2_SSBS_SHIFT		4
+#define ID_PFR2_CSV3_SHIFT		0
+
+#define MVFR0_FPROUND_SHIFT		28
+#define MVFR0_FPSHVEC_SHIFT		24
+#define MVFR0_FPSQRT_SHIFT		20
+#define MVFR0_FPDIVIDE_SHIFT		16
+#define MVFR0_FPTRAP_SHIFT		12
+#define MVFR0_FPDP_SHIFT		8
+#define MVFR0_FPSP_SHIFT		4
+#define MVFR0_SIMD_SHIFT		0
+
+#define MVFR1_SIMDFMAC_SHIFT		28
+#define MVFR1_FPHP_SHIFT		24
+#define MVFR1_SIMDHP_SHIFT		20
+#define MVFR1_SIMDSP_SHIFT		16
+#define MVFR1_SIMDINT_SHIFT		12
+#define MVFR1_SIMDLS_SHIFT		8
+#define MVFR1_FPDNAN_SHIFT		4
+#define MVFR1_FPFTZ_SHIFT		0
+
+#define ID_PFR1_GIC_SHIFT		28
+#define ID_PFR1_VIRT_FRAC_SHIFT		24
+#define ID_PFR1_SEC_FRAC_SHIFT		20
+#define ID_PFR1_GENTIMER_SHIFT		16
+#define ID_PFR1_VIRTUALIZATION_SHIFT	12
+#define ID_PFR1_MPROGMOD_SHIFT		8
+#define ID_PFR1_SECURITY_SHIFT		4
+#define ID_PFR1_PROGMOD_SHIFT		0
+
+#if defined(CONFIG_ARM64_4K_PAGES)
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT
+#elif defined(CONFIG_ARM64_16K_PAGES)
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT
+#elif defined(CONFIG_ARM64_64K_PAGES)
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT
+#endif
+
+#define MVFR2_FPMISC_SHIFT		4
+#define MVFR2_SIMDMISC_SHIFT		0
+
+#define DCZID_DZP_SHIFT			4
+#define DCZID_BS_SHIFT			0
+
+/*
+ * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
+ * are reserved by the SVE architecture for future expansion of the LEN
+ * field, with compatible semantics.
+ */
+#define ZCR_ELx_LEN_SHIFT	0
+#define ZCR_ELx_LEN_SIZE	9
+#define ZCR_ELx_LEN_MASK	0x1ff
+
+#define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
+#define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
+#define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
+
+/* TCR EL1 Bit Definitions */
+#define SYS_TCR_EL1_TCMA1	(BIT(58))
+#define SYS_TCR_EL1_TCMA0	(BIT(57))
+
+/* GCR_EL1 Definitions */
+#define SYS_GCR_EL1_RRND	(BIT(16))
+#define SYS_GCR_EL1_EXCL_MASK	0xffffUL
+
+#ifdef CONFIG_KASAN_HW_TAGS
+/*
+ * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
+ * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
+ */
+#define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
+#define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
+#define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
+#define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
+#else
+#define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
+#endif
+
+#define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
+
+/* RGSR_EL1 Definitions */
+#define SYS_RGSR_EL1_TAG_MASK	0xfUL
+#define SYS_RGSR_EL1_SEED_SHIFT	8
+#define SYS_RGSR_EL1_SEED_MASK	0xffffUL
+
+/* GMID_EL1 field definitions */
+#define SYS_GMID_EL1_BS_SHIFT	0
+#define SYS_GMID_EL1_BS_SIZE	4
+
+/* TFSR{,E0}_EL1 bit definitions */
+#define SYS_TFSR_EL1_TF0_SHIFT	0
+#define SYS_TFSR_EL1_TF1_SHIFT	1
+#define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
+#define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
+
+/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
+#define SYS_MPIDR_SAFE_VAL	(BIT(31))
+
+#define TRFCR_ELx_TS_SHIFT		5
+#define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX			BIT(3)
+#define TRFCR_ELx_ExTRE			BIT(1)
+#define TRFCR_ELx_E0TRE			BIT(0)
+
+
+/* GIC Hypervisor interface registers */
+/* ICH_MISR_EL2 bit definitions */
+#define ICH_MISR_EOI		(1 << 0)
+#define ICH_MISR_U		(1 << 1)
+
+/* ICH_LR*_EL2 bit definitions */
+#define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
+
+#define ICH_LR_EOI		(1ULL << 41)
+#define ICH_LR_GROUP		(1ULL << 60)
+#define ICH_LR_HW		(1ULL << 61)
+#define ICH_LR_STATE		(3ULL << 62)
+#define ICH_LR_PENDING_BIT	(1ULL << 62)
+#define ICH_LR_ACTIVE_BIT	(1ULL << 63)
+#define ICH_LR_PHYS_ID_SHIFT	32
+#define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
+#define ICH_LR_PRIORITY_SHIFT	48
+#define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
+
+/* ICH_HCR_EL2 bit definitions */
+#define ICH_HCR_EN		(1 << 0)
+#define ICH_HCR_UIE		(1 << 1)
+#define ICH_HCR_NPIE		(1 << 3)
+#define ICH_HCR_TC		(1 << 10)
+#define ICH_HCR_TALL0		(1 << 11)
+#define ICH_HCR_TALL1		(1 << 12)
+#define ICH_HCR_TDIR		(1 << 14)
+#define ICH_HCR_EOIcount_SHIFT	27
+#define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
+
+/* ICH_VMCR_EL2 bit definitions */
+#define ICH_VMCR_ACK_CTL_SHIFT	2
+#define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
+#define ICH_VMCR_FIQ_EN_SHIFT	3
+#define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
+#define ICH_VMCR_CBPR_SHIFT	4
+#define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_EOIM_SHIFT	9
+#define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
+#define ICH_VMCR_BPR1_SHIFT	18
+#define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
+#define ICH_VMCR_BPR0_SHIFT	21
+#define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
+#define ICH_VMCR_PMR_SHIFT	24
+#define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
+#define ICH_VMCR_ENG0_SHIFT	0
+#define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
+#define ICH_VMCR_ENG1_SHIFT	1
+#define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
+
+/* ICH_VTR_EL2 bit definitions */
+#define ICH_VTR_PRI_BITS_SHIFT	29
+#define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
+#define ICH_VTR_ID_BITS_SHIFT	23
+#define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
+#define ICH_VTR_SEIS_SHIFT	22
+#define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
+#define ICH_VTR_A3V_SHIFT	21
+#define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
+#define ICH_VTR_TDS_SHIFT	19
+#define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
+
+#define ARM64_FEATURE_FIELD_BITS	4
+
+/* Create a mask for the feature bits of the specified feature. */
+#define ARM64_FEATURE_MASK(x)	(GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
+
+#ifdef __ASSEMBLY__
+
+	.macro	mrs_s, rt, sreg
+	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
+	.endm
+
+	.macro	msr_s, sreg, rt
+	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
+	.endm
+
+#else
+
+#include <linux/build_bug.h>
+#include <linux/types.h>
+#ifndef __UBOOT__
+#include <asm/alternative.h>
+#endif
+
+#define DEFINE_MRS_S						\
+	__DEFINE_ASM_GPR_NUMS					\
+"	.macro	mrs_s, rt, sreg\n"				\
+	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
+"	.endm\n"
+
+#define DEFINE_MSR_S						\
+	__DEFINE_ASM_GPR_NUMS					\
+"	.macro	msr_s, sreg, rt\n"				\
+	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
+"	.endm\n"
+
+#define UNDEFINE_MRS_S						\
+"	.purgem	mrs_s\n"
+
+#define UNDEFINE_MSR_S						\
+"	.purgem	msr_s\n"
+
+#define __mrs_s(v, r)						\
+	DEFINE_MRS_S						\
+"	mrs_s " v ", " __stringify(r) "\n"			\
+	UNDEFINE_MRS_S
+
+#define __msr_s(r, v)						\
+	DEFINE_MSR_S						\
+"	msr_s " __stringify(r) ", " v "\n"			\
+	UNDEFINE_MSR_S
+
+/*
+ * Unlike read_cpuid, calls to read_sysreg are never expected to be
+ * optimized away or replaced with synthetic values.
+ */
+#define read_sysreg(r) ({					\
+	u64 __val;						\
+	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
+	__val;							\
+})
+
+/*
+ * The "Z" constraint normally means a zero immediate, but when combined with
+ * the "%x0" template means XZR.
+ */
+#define write_sysreg(v, r) do {					\
+	u64 __val = (u64)(v);					\
+	asm volatile("msr " __stringify(r) ", %x0"		\
+		     : : "rZ" (__val));				\
+} while (0)
+
+/*
+ * For registers without architectural names, or simply unsupported by
+ * GAS.
+ */
+#define read_sysreg_s(r) ({						\
+	u64 __val;							\
+	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
+	__val;								\
+})
+
+#define write_sysreg_s(v, r) do {					\
+	u64 __val = (u64)(v);						\
+	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
+} while (0)
+
+/*
+ * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
+ * set mask are set. Other bits are left as-is.
+ */
+#define sysreg_clear_set(sysreg, clear, set) do {			\
+	u64 __scs_val = read_sysreg(sysreg);				\
+	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
+	if (__scs_new != __scs_val)					\
+		write_sysreg(__scs_new, sysreg);			\
+} while (0)
+
+#define sysreg_clear_set_s(sysreg, clear, set) do {			\
+	u64 __scs_val = read_sysreg_s(sysreg);				\
+	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
+	if (__scs_new != __scs_val)					\
+		write_sysreg_s(__scs_new, sysreg);			\
+} while (0)
+
+#ifndef __UBOOT__
+#define read_sysreg_par() ({						\
+	u64 par;							\
+	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
+	par = read_sysreg(par_el1);					\
+	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
+	par;								\
+})
+#endif
+
+#endif
+
+#endif	/* __ASM_SYSREG_H */
-- 
2.35.1.723.g4982287a31-goog

[PATCH 9/9] arm64: Import <asm/esr.h> from Linux

[Pierre-Clément Tosi]

Import the header from version 5.16 of the kernel:

    commit df0cc57e057f18e44dac8e6c18aba47ab53202f9

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Cc: Tom Rini <trini@konsulko.com>
---
 arch/arm/include/asm/esr.h | 343 +++++++++++++++++++++++++++++++++++++
 1 file changed, 343 insertions(+)
 create mode 100644 arch/arm/include/asm/esr.h

diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h
new file mode 100644
index 0000000000..d52a0b269e
--- /dev/null
+++ b/arch/arm/include/asm/esr.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ */
+
+#ifndef __ASM_ESR_H
+#define __ASM_ESR_H
+
+#include <asm/memory.h>
+#include <asm/sysreg.h>
+
+#define ESR_ELx_EC_UNKNOWN	(0x00)
+#define ESR_ELx_EC_WFx		(0x01)
+/* Unallocated EC: 0x02 */
+#define ESR_ELx_EC_CP15_32	(0x03)
+#define ESR_ELx_EC_CP15_64	(0x04)
+#define ESR_ELx_EC_CP14_MR	(0x05)
+#define ESR_ELx_EC_CP14_LS	(0x06)
+#define ESR_ELx_EC_FP_ASIMD	(0x07)
+#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
+#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
+/* Unallocated EC: 0x0A - 0x0B */
+#define ESR_ELx_EC_CP14_64	(0x0C)
+#define ESR_ELx_EC_BTI		(0x0D)
+#define ESR_ELx_EC_ILL		(0x0E)
+/* Unallocated EC: 0x0F - 0x10 */
+#define ESR_ELx_EC_SVC32	(0x11)
+#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
+#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
+/* Unallocated EC: 0x14 */
+#define ESR_ELx_EC_SVC64	(0x15)
+#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
+#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
+#define ESR_ELx_EC_SYS64	(0x18)
+#define ESR_ELx_EC_SVE		(0x19)
+#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
+/* Unallocated EC: 0x1B */
+#define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
+/* Unallocated EC: 0x1D - 0x1E */
+#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
+#define ESR_ELx_EC_IABT_LOW	(0x20)
+#define ESR_ELx_EC_IABT_CUR	(0x21)
+#define ESR_ELx_EC_PC_ALIGN	(0x22)
+/* Unallocated EC: 0x23 */
+#define ESR_ELx_EC_DABT_LOW	(0x24)
+#define ESR_ELx_EC_DABT_CUR	(0x25)
+#define ESR_ELx_EC_SP_ALIGN	(0x26)
+/* Unallocated EC: 0x27 */
+#define ESR_ELx_EC_FP_EXC32	(0x28)
+/* Unallocated EC: 0x29 - 0x2B */
+#define ESR_ELx_EC_FP_EXC64	(0x2C)
+/* Unallocated EC: 0x2D - 0x2E */
+#define ESR_ELx_EC_SERROR	(0x2F)
+#define ESR_ELx_EC_BREAKPT_LOW	(0x30)
+#define ESR_ELx_EC_BREAKPT_CUR	(0x31)
+#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
+#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
+#define ESR_ELx_EC_WATCHPT_LOW	(0x34)
+#define ESR_ELx_EC_WATCHPT_CUR	(0x35)
+/* Unallocated EC: 0x36 - 0x37 */
+#define ESR_ELx_EC_BKPT32	(0x38)
+/* Unallocated EC: 0x39 */
+#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
+/* Unallocated EC: 0x3B */
+#define ESR_ELx_EC_BRK64	(0x3C)
+/* Unallocated EC: 0x3D - 0x3F */
+#define ESR_ELx_EC_MAX		(0x3F)
+
+#define ESR_ELx_EC_SHIFT	(26)
+#define ESR_ELx_EC_WIDTH	(6)
+#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
+#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
+
+#define ESR_ELx_IL_SHIFT	(25)
+#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
+#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
+
+/* ISS field definitions shared by different classes */
+#define ESR_ELx_WNR_SHIFT	(6)
+#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
+
+/* Asynchronous Error Type */
+#define ESR_ELx_IDS_SHIFT	(24)
+#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
+#define ESR_ELx_AET_SHIFT	(10)
+#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
+
+#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
+#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
+#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
+#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
+#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
+
+/* Shared ISS field definitions for Data/Instruction aborts */
+#define ESR_ELx_SET_SHIFT	(11)
+#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
+#define ESR_ELx_FnV_SHIFT	(10)
+#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
+#define ESR_ELx_EA_SHIFT	(9)
+#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
+#define ESR_ELx_S1PTW_SHIFT	(7)
+#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
+
+/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
+#define ESR_ELx_FSC		(0x3F)
+#define ESR_ELx_FSC_TYPE	(0x3C)
+#define ESR_ELx_FSC_LEVEL	(0x03)
+#define ESR_ELx_FSC_EXTABT	(0x10)
+#define ESR_ELx_FSC_MTE		(0x11)
+#define ESR_ELx_FSC_SERROR	(0x11)
+#define ESR_ELx_FSC_ACCESS	(0x08)
+#define ESR_ELx_FSC_FAULT	(0x04)
+#define ESR_ELx_FSC_PERM	(0x0C)
+
+/* ISS field definitions for Data Aborts */
+#define ESR_ELx_ISV_SHIFT	(24)
+#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
+#define ESR_ELx_SAS_SHIFT	(22)
+#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
+#define ESR_ELx_SSE_SHIFT	(21)
+#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
+#define ESR_ELx_SRT_SHIFT	(16)
+#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
+#define ESR_ELx_SF_SHIFT	(15)
+#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
+#define ESR_ELx_AR_SHIFT	(14)
+#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
+#define ESR_ELx_CM_SHIFT	(8)
+#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
+
+/* ISS field definitions for exceptions taken in to Hyp */
+#define ESR_ELx_CV		(UL(1) << 24)
+#define ESR_ELx_COND_SHIFT	(20)
+#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
+#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
+#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
+#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
+#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
+
+#define DISR_EL1_IDS		(UL(1) << 24)
+/*
+ * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
+ * different things in the future...
+ */
+#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
+
+/* ESR value templates for specific events */
+#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
+#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
+				 ESR_ELx_WFx_ISS_WFI)
+
+/* BRK instruction trap from AArch64 state */
+#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
+
+/* ISS field definitions for System instruction traps */
+#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
+#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
+#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
+#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
+#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
+
+#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
+#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
+#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
+#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
+#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
+#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
+#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
+#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
+#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
+#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
+#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
+#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
+#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
+					 ESR_ELx_SYS64_ISS_OP1_MASK | \
+					 ESR_ELx_SYS64_ISS_OP2_MASK | \
+					 ESR_ELx_SYS64_ISS_CRN_MASK | \
+					 ESR_ELx_SYS64_ISS_CRM_MASK)
+#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
+					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
+					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
+					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
+					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
+					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
+
+#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
+					 ESR_ELx_SYS64_ISS_DIR_MASK)
+#define ESR_ELx_SYS64_ISS_RT(esr) \
+	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
+/*
+ * User space cache operations have the following sysreg encoding
+ * in System instructions.
+ * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
+ */
+#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
+#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
+
+#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
+						 ESR_ELx_SYS64_ISS_OP1_MASK | \
+						 ESR_ELx_SYS64_ISS_OP2_MASK | \
+						 ESR_ELx_SYS64_ISS_CRN_MASK | \
+						 ESR_ELx_SYS64_ISS_DIR_MASK)
+#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
+				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
+				 ESR_ELx_SYS64_ISS_DIR_WRITE)
+/*
+ * User space MRS operations which are supported for emulation
+ * have the following sysreg encoding in System instructions.
+ * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
+ */
+#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
+						 ESR_ELx_SYS64_ISS_OP1_MASK | \
+						 ESR_ELx_SYS64_ISS_CRN_MASK | \
+						 ESR_ELx_SYS64_ISS_DIR_MASK)
+#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
+				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
+				 ESR_ELx_SYS64_ISS_DIR_READ)
+
+#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
+#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
+					 ESR_ELx_SYS64_ISS_DIR_READ)
+
+#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
+					 ESR_ELx_SYS64_ISS_DIR_READ)
+
+#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
+					 ESR_ELx_SYS64_ISS_DIR_READ)
+
+#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
+					 ESR_ELx_SYS64_ISS_DIR_READ)
+
+#define esr_sys64_to_sysreg(e)					\
+	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
+
+#define esr_cp15_to_sysreg(e)					\
+	sys_reg(3,						\
+		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
+		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
+		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
+
+/*
+ * ISS field definitions for floating-point exception traps
+ * (FP_EXC_32/FP_EXC_64).
+ *
+ * (The FPEXC_* constants are used instead for common bits.)
+ */
+
+#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
+
+/*
+ * ISS field definitions for CP15 accesses
+ */
+#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
+#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
+#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
+
+#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
+#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
+#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
+#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
+#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
+#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
+#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
+#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
+#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
+#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
+
+#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
+					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
+					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
+					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
+					 ESR_ELx_CP15_32_ISS_DIR_MASK)
+#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
+					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
+					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
+					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
+					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
+
+#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
+#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
+#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
+
+#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
+#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
+#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
+#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
+#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
+#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
+					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
+					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
+
+#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
+					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
+					 ESR_ELx_CP15_64_ISS_DIR_MASK)
+
+#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
+					 ESR_ELx_CP15_64_ISS_DIR_READ)
+
+#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
+					 ESR_ELx_CP15_64_ISS_DIR_READ)
+
+#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
+					 ESR_ELx_CP15_32_ISS_DIR_READ)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+static inline bool esr_is_data_abort(u32 esr)
+{
+	const u32 ec = ESR_ELx_EC(esr);
+
+	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
+}
+
+const char *esr_get_class_string(u32 esr);
+#endif /* __ASSEMBLY */
+
+#endif /* __ASM_ESR_H */
-- 
2.35.1.723.g4982287a31-goog

Re: [PATCH 9/9] arm64: Import <asm/esr.h> from Linux

[Sean Anderson]

On 3/16/22 11:39 AM, Pierre-Clément Tosi wrote:
> Import the header from version 5.16 of the kernel:
> 
>      commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> 
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>   arch/arm/include/asm/esr.h | 343 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 343 insertions(+)
>   create mode 100644 arch/arm/include/asm/esr.h
> 
> diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h
> new file mode 100644
> index 0000000000..d52a0b269e
> --- /dev/null
> +++ b/arch/arm/include/asm/esr.h
> @@ -0,0 +1,343 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2013 - ARM Ltd
> + * Author: Marc Zyngier <marc.zyngier@arm.com>
> + */
> +
> +#ifndef __ASM_ESR_H
> +#define __ASM_ESR_H
> +
> +#include <asm/memory.h>
> +#include <asm/sysreg.h>

I think this is just needed for the UL macros. See e.g. [1].

--Sean

[1] https://lore.kernel.org/u-boot/20220310205059.499269-22-sean.anderson@seco.com/

> +
> +#define ESR_ELx_EC_UNKNOWN	(0x00)
> +#define ESR_ELx_EC_WFx		(0x01)
> +/* Unallocated EC: 0x02 */
> +#define ESR_ELx_EC_CP15_32	(0x03)
> +#define ESR_ELx_EC_CP15_64	(0x04)
> +#define ESR_ELx_EC_CP14_MR	(0x05)
> +#define ESR_ELx_EC_CP14_LS	(0x06)
> +#define ESR_ELx_EC_FP_ASIMD	(0x07)
> +#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
> +#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
> +/* Unallocated EC: 0x0A - 0x0B */
> +#define ESR_ELx_EC_CP14_64	(0x0C)
> +#define ESR_ELx_EC_BTI		(0x0D)
> +#define ESR_ELx_EC_ILL		(0x0E)
> +/* Unallocated EC: 0x0F - 0x10 */
> +#define ESR_ELx_EC_SVC32	(0x11)
> +#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
> +#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
> +/* Unallocated EC: 0x14 */
> +#define ESR_ELx_EC_SVC64	(0x15)
> +#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
> +#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
> +#define ESR_ELx_EC_SYS64	(0x18)
> +#define ESR_ELx_EC_SVE		(0x19)
> +#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
> +/* Unallocated EC: 0x1B */
> +#define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
> +/* Unallocated EC: 0x1D - 0x1E */
> +#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
> +#define ESR_ELx_EC_IABT_LOW	(0x20)
> +#define ESR_ELx_EC_IABT_CUR	(0x21)
> +#define ESR_ELx_EC_PC_ALIGN	(0x22)
> +/* Unallocated EC: 0x23 */
> +#define ESR_ELx_EC_DABT_LOW	(0x24)
> +#define ESR_ELx_EC_DABT_CUR	(0x25)
> +#define ESR_ELx_EC_SP_ALIGN	(0x26)
> +/* Unallocated EC: 0x27 */
> +#define ESR_ELx_EC_FP_EXC32	(0x28)
> +/* Unallocated EC: 0x29 - 0x2B */
> +#define ESR_ELx_EC_FP_EXC64	(0x2C)
> +/* Unallocated EC: 0x2D - 0x2E */
> +#define ESR_ELx_EC_SERROR	(0x2F)
> +#define ESR_ELx_EC_BREAKPT_LOW	(0x30)
> +#define ESR_ELx_EC_BREAKPT_CUR	(0x31)
> +#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
> +#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
> +#define ESR_ELx_EC_WATCHPT_LOW	(0x34)
> +#define ESR_ELx_EC_WATCHPT_CUR	(0x35)
> +/* Unallocated EC: 0x36 - 0x37 */
> +#define ESR_ELx_EC_BKPT32	(0x38)
> +/* Unallocated EC: 0x39 */
> +#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
> +/* Unallocated EC: 0x3B */
> +#define ESR_ELx_EC_BRK64	(0x3C)
> +/* Unallocated EC: 0x3D - 0x3F */
> +#define ESR_ELx_EC_MAX		(0x3F)
> +
> +#define ESR_ELx_EC_SHIFT	(26)
> +#define ESR_ELx_EC_WIDTH	(6)
> +#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
> +#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
> +
> +#define ESR_ELx_IL_SHIFT	(25)
> +#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
> +#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
> +
> +/* ISS field definitions shared by different classes */
> +#define ESR_ELx_WNR_SHIFT	(6)
> +#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
> +
> +/* Asynchronous Error Type */
> +#define ESR_ELx_IDS_SHIFT	(24)
> +#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
> +#define ESR_ELx_AET_SHIFT	(10)
> +#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
> +
> +#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
> +#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
> +#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
> +#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
> +#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
> +
> +/* Shared ISS field definitions for Data/Instruction aborts */
> +#define ESR_ELx_SET_SHIFT	(11)
> +#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
> +#define ESR_ELx_FnV_SHIFT	(10)
> +#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
> +#define ESR_ELx_EA_SHIFT	(9)
> +#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
> +#define ESR_ELx_S1PTW_SHIFT	(7)
> +#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
> +
> +/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
> +#define ESR_ELx_FSC		(0x3F)
> +#define ESR_ELx_FSC_TYPE	(0x3C)
> +#define ESR_ELx_FSC_LEVEL	(0x03)
> +#define ESR_ELx_FSC_EXTABT	(0x10)
> +#define ESR_ELx_FSC_MTE		(0x11)
> +#define ESR_ELx_FSC_SERROR	(0x11)
> +#define ESR_ELx_FSC_ACCESS	(0x08)
> +#define ESR_ELx_FSC_FAULT	(0x04)
> +#define ESR_ELx_FSC_PERM	(0x0C)
> +
> +/* ISS field definitions for Data Aborts */
> +#define ESR_ELx_ISV_SHIFT	(24)
> +#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
> +#define ESR_ELx_SAS_SHIFT	(22)
> +#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
> +#define ESR_ELx_SSE_SHIFT	(21)
> +#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
> +#define ESR_ELx_SRT_SHIFT	(16)
> +#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
> +#define ESR_ELx_SF_SHIFT	(15)
> +#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
> +#define ESR_ELx_AR_SHIFT	(14)
> +#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
> +#define ESR_ELx_CM_SHIFT	(8)
> +#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
> +
> +/* ISS field definitions for exceptions taken in to Hyp */
> +#define ESR_ELx_CV		(UL(1) << 24)
> +#define ESR_ELx_COND_SHIFT	(20)
> +#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
> +#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
> +#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
> +#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
> +#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
> +
> +#define DISR_EL1_IDS		(UL(1) << 24)
> +/*
> + * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
> + * different things in the future...
> + */
> +#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
> +
> +/* ESR value templates for specific events */
> +#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
> +#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
> +				 ESR_ELx_WFx_ISS_WFI)
> +
> +/* BRK instruction trap from AArch64 state */
> +#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
> +
> +/* ISS field definitions for System instruction traps */
> +#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
> +#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
> +#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
> +#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
> +#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
> +
> +#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
> +#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
> +#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
> +#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
> +#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
> +#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
> +#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
> +#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
> +#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
> +#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
> +#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
> +#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
> +#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> +					 ESR_ELx_SYS64_ISS_OP1_MASK | \
> +					 ESR_ELx_SYS64_ISS_OP2_MASK | \
> +					 ESR_ELx_SYS64_ISS_CRN_MASK | \
> +					 ESR_ELx_SYS64_ISS_CRM_MASK)
> +#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
> +					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
> +					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
> +					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
> +					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
> +					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
> +
> +#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
> +					 ESR_ELx_SYS64_ISS_DIR_MASK)
> +#define ESR_ELx_SYS64_ISS_RT(esr) \
> +	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
> +/*
> + * User space cache operations have the following sysreg encoding
> + * in System instructions.
> + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
> + */
> +#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
> +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
> +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
> +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
> +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
> +#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
> +
> +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> +						 ESR_ELx_SYS64_ISS_OP1_MASK | \
> +						 ESR_ELx_SYS64_ISS_OP2_MASK | \
> +						 ESR_ELx_SYS64_ISS_CRN_MASK | \
> +						 ESR_ELx_SYS64_ISS_DIR_MASK)
> +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
> +				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
> +				 ESR_ELx_SYS64_ISS_DIR_WRITE)
> +/*
> + * User space MRS operations which are supported for emulation
> + * have the following sysreg encoding in System instructions.
> + * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
> + */
> +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> +						 ESR_ELx_SYS64_ISS_OP1_MASK | \
> +						 ESR_ELx_SYS64_ISS_CRN_MASK | \
> +						 ESR_ELx_SYS64_ISS_DIR_MASK)
> +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
> +				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
> +				 ESR_ELx_SYS64_ISS_DIR_READ)
> +
> +#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
> +#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
> +					 ESR_ELx_SYS64_ISS_DIR_READ)
> +
> +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
> +					 ESR_ELx_SYS64_ISS_DIR_READ)
> +
> +#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
> +					 ESR_ELx_SYS64_ISS_DIR_READ)
> +
> +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
> +					 ESR_ELx_SYS64_ISS_DIR_READ)
> +
> +#define esr_sys64_to_sysreg(e)					\
> +	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
> +
> +#define esr_cp15_to_sysreg(e)					\
> +	sys_reg(3,						\
> +		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
> +		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
> +		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
> +
> +/*
> + * ISS field definitions for floating-point exception traps
> + * (FP_EXC_32/FP_EXC_64).
> + *
> + * (The FPEXC_* constants are used instead for common bits.)
> + */
> +
> +#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
> +
> +/*
> + * ISS field definitions for CP15 accesses
> + */
> +#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
> +#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
> +#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
> +
> +#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
> +#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
> +#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
> +#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
> +#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
> +#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
> +#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
> +#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
> +#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
> +#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
> +
> +#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
> +					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
> +					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
> +					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
> +					 ESR_ELx_CP15_32_ISS_DIR_MASK)
> +#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
> +					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
> +					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
> +					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
> +					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
> +
> +#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
> +#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
> +#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
> +
> +#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
> +#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
> +
> +#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
> +#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
> +
> +#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
> +#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
> +#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
> +#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
> +
> +#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
> +					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
> +					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
> +
> +#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
> +					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
> +					 ESR_ELx_CP15_64_ISS_DIR_MASK)
> +
> +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
> +					 ESR_ELx_CP15_64_ISS_DIR_READ)
> +
> +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
> +					 ESR_ELx_CP15_64_ISS_DIR_READ)
> +
> +#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
> +					 ESR_ELx_CP15_32_ISS_DIR_READ)
> +
> +#ifndef __ASSEMBLY__
> +#include <asm/types.h>
> +
> +static inline bool esr_is_data_abort(u32 esr)
> +{
> +	const u32 ec = ESR_ELx_EC(esr);
> +
> +	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
> +}
> +
> +const char *esr_get_class_string(u32 esr);
> +#endif /* __ASSEMBLY */
> +
> +#endif /* __ASM_ESR_H */
> 

Re: [PATCH 9/9] arm64: Import <asm/esr.h> from Linux

[Pierre-Clément Tosi]

On Wed, Mar 16, 2022 at 03:47:57PM -0400, Sean Anderson wrote:
> On 3/16/22 11:39 AM, Pierre-Clément Tosi wrote:
> > Import the header from version 5.16 of the kernel:
> > 
> >      commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
> > 
> > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> > Cc: Tom Rini <trini@konsulko.com>
> > ---
> >   arch/arm/include/asm/esr.h | 343 +++++++++++++++++++++++++++++++++++++
> >   1 file changed, 343 insertions(+)
> >   create mode 100644 arch/arm/include/asm/esr.h
> > 
> > diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h
> > new file mode 100644
> > index 0000000000..d52a0b269e
> > --- /dev/null
> > +++ b/arch/arm/include/asm/esr.h
> > @@ -0,0 +1,343 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2013 - ARM Ltd
> > + * Author: Marc Zyngier <marc.zyngier@arm.com>
> > + */
> > +
> > +#ifndef __ASM_ESR_H
> > +#define __ASM_ESR_H
> > +
> > +#include <asm/memory.h>
> > +#include <asm/sysreg.h>
> 
> I think this is just needed for the UL macros. See e.g. [1].

I think you're right about <asm/memory.h> being included for UL(), as pointed
out by commit d7a33f4fbd12 ("arm64/debug: Add missing #includes"), which could
(should?) be replaced by <linux/const.h>. But the esr_*_to_sysreg() macros
require <asm/sysreg.h> and, even if it's unlikely for U-Boot to use them, that
header brings many useful macros of its own anyway.

> 
> --Sean
> 
> [1] https://lore.kernel.org/u-boot/20220310205059.499269-22-sean.anderson@seco.com/

Thanks, I wasn't aware of that patch; should I drop this one or instead rebase
it on top of yours to re-#include sysreg.h once it's been made available by this
series?

> 
> > +
> > +#define ESR_ELx_EC_UNKNOWN	(0x00)
> > +#define ESR_ELx_EC_WFx		(0x01)
> > +/* Unallocated EC: 0x02 */
> > +#define ESR_ELx_EC_CP15_32	(0x03)
> > +#define ESR_ELx_EC_CP15_64	(0x04)
> > +#define ESR_ELx_EC_CP14_MR	(0x05)
> > +#define ESR_ELx_EC_CP14_LS	(0x06)
> > +#define ESR_ELx_EC_FP_ASIMD	(0x07)
> > +#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
> > +#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
> > +/* Unallocated EC: 0x0A - 0x0B */
> > +#define ESR_ELx_EC_CP14_64	(0x0C)
> > +#define ESR_ELx_EC_BTI		(0x0D)
> > +#define ESR_ELx_EC_ILL		(0x0E)
> > +/* Unallocated EC: 0x0F - 0x10 */
> > +#define ESR_ELx_EC_SVC32	(0x11)
> > +#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
> > +#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
> > +/* Unallocated EC: 0x14 */
> > +#define ESR_ELx_EC_SVC64	(0x15)
> > +#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
> > +#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
> > +#define ESR_ELx_EC_SYS64	(0x18)
> > +#define ESR_ELx_EC_SVE		(0x19)
> > +#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
> > +/* Unallocated EC: 0x1B */
> > +#define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
> > +/* Unallocated EC: 0x1D - 0x1E */
> > +#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
> > +#define ESR_ELx_EC_IABT_LOW	(0x20)
> > +#define ESR_ELx_EC_IABT_CUR	(0x21)
> > +#define ESR_ELx_EC_PC_ALIGN	(0x22)
> > +/* Unallocated EC: 0x23 */
> > +#define ESR_ELx_EC_DABT_LOW	(0x24)
> > +#define ESR_ELx_EC_DABT_CUR	(0x25)
> > +#define ESR_ELx_EC_SP_ALIGN	(0x26)
> > +/* Unallocated EC: 0x27 */
> > +#define ESR_ELx_EC_FP_EXC32	(0x28)
> > +/* Unallocated EC: 0x29 - 0x2B */
> > +#define ESR_ELx_EC_FP_EXC64	(0x2C)
> > +/* Unallocated EC: 0x2D - 0x2E */
> > +#define ESR_ELx_EC_SERROR	(0x2F)
> > +#define ESR_ELx_EC_BREAKPT_LOW	(0x30)
> > +#define ESR_ELx_EC_BREAKPT_CUR	(0x31)
> > +#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
> > +#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
> > +#define ESR_ELx_EC_WATCHPT_LOW	(0x34)
> > +#define ESR_ELx_EC_WATCHPT_CUR	(0x35)
> > +/* Unallocated EC: 0x36 - 0x37 */
> > +#define ESR_ELx_EC_BKPT32	(0x38)
> > +/* Unallocated EC: 0x39 */
> > +#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
> > +/* Unallocated EC: 0x3B */
> > +#define ESR_ELx_EC_BRK64	(0x3C)
> > +/* Unallocated EC: 0x3D - 0x3F */
> > +#define ESR_ELx_EC_MAX		(0x3F)
> > +
> > +#define ESR_ELx_EC_SHIFT	(26)
> > +#define ESR_ELx_EC_WIDTH	(6)
> > +#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
> > +#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
> > +
> > +#define ESR_ELx_IL_SHIFT	(25)
> > +#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
> > +#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
> > +
> > +/* ISS field definitions shared by different classes */
> > +#define ESR_ELx_WNR_SHIFT	(6)
> > +#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
> > +
> > +/* Asynchronous Error Type */
> > +#define ESR_ELx_IDS_SHIFT	(24)
> > +#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
> > +#define ESR_ELx_AET_SHIFT	(10)
> > +#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
> > +
> > +#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
> > +#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
> > +#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
> > +#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
> > +#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
> > +
> > +/* Shared ISS field definitions for Data/Instruction aborts */
> > +#define ESR_ELx_SET_SHIFT	(11)
> > +#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
> > +#define ESR_ELx_FnV_SHIFT	(10)
> > +#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
> > +#define ESR_ELx_EA_SHIFT	(9)
> > +#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
> > +#define ESR_ELx_S1PTW_SHIFT	(7)
> > +#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
> > +
> > +/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
> > +#define ESR_ELx_FSC		(0x3F)
> > +#define ESR_ELx_FSC_TYPE	(0x3C)
> > +#define ESR_ELx_FSC_LEVEL	(0x03)
> > +#define ESR_ELx_FSC_EXTABT	(0x10)
> > +#define ESR_ELx_FSC_MTE		(0x11)
> > +#define ESR_ELx_FSC_SERROR	(0x11)
> > +#define ESR_ELx_FSC_ACCESS	(0x08)
> > +#define ESR_ELx_FSC_FAULT	(0x04)
> > +#define ESR_ELx_FSC_PERM	(0x0C)
> > +
> > +/* ISS field definitions for Data Aborts */
> > +#define ESR_ELx_ISV_SHIFT	(24)
> > +#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
> > +#define ESR_ELx_SAS_SHIFT	(22)
> > +#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
> > +#define ESR_ELx_SSE_SHIFT	(21)
> > +#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
> > +#define ESR_ELx_SRT_SHIFT	(16)
> > +#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
> > +#define ESR_ELx_SF_SHIFT	(15)
> > +#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
> > +#define ESR_ELx_AR_SHIFT	(14)
> > +#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
> > +#define ESR_ELx_CM_SHIFT	(8)
> > +#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
> > +
> > +/* ISS field definitions for exceptions taken in to Hyp */
> > +#define ESR_ELx_CV		(UL(1) << 24)
> > +#define ESR_ELx_COND_SHIFT	(20)
> > +#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
> > +#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
> > +#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
> > +#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
> > +#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
> > +
> > +#define DISR_EL1_IDS		(UL(1) << 24)
> > +/*
> > + * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
> > + * different things in the future...
> > + */
> > +#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
> > +
> > +/* ESR value templates for specific events */
> > +#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
> > +#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
> > +				 ESR_ELx_WFx_ISS_WFI)
> > +
> > +/* BRK instruction trap from AArch64 state */
> > +#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
> > +
> > +/* ISS field definitions for System instruction traps */
> > +#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
> > +#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
> > +#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
> > +#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
> > +
> > +#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
> > +#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
> > +#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
> > +#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
> > +#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
> > +#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
> > +#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
> > +#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> > +					 ESR_ELx_SYS64_ISS_OP1_MASK | \
> > +					 ESR_ELx_SYS64_ISS_OP2_MASK | \
> > +					 ESR_ELx_SYS64_ISS_CRN_MASK | \
> > +					 ESR_ELx_SYS64_ISS_CRM_MASK)
> > +#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
> > +					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
> > +					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
> > +					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
> > +					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
> > +					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
> > +
> > +#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
> > +					 ESR_ELx_SYS64_ISS_DIR_MASK)
> > +#define ESR_ELx_SYS64_ISS_RT(esr) \
> > +	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
> > +/*
> > + * User space cache operations have the following sysreg encoding
> > + * in System instructions.
> > + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
> > + */
> > +#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
> > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
> > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
> > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
> > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
> > +#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
> > +
> > +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> > +						 ESR_ELx_SYS64_ISS_OP1_MASK | \
> > +						 ESR_ELx_SYS64_ISS_OP2_MASK | \
> > +						 ESR_ELx_SYS64_ISS_CRN_MASK | \
> > +						 ESR_ELx_SYS64_ISS_DIR_MASK)
> > +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
> > +				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
> > +				 ESR_ELx_SYS64_ISS_DIR_WRITE)
> > +/*
> > + * User space MRS operations which are supported for emulation
> > + * have the following sysreg encoding in System instructions.
> > + * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
> > + */
> > +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
> > +						 ESR_ELx_SYS64_ISS_OP1_MASK | \
> > +						 ESR_ELx_SYS64_ISS_CRN_MASK | \
> > +						 ESR_ELx_SYS64_ISS_DIR_MASK)
> > +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
> > +				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
> > +				 ESR_ELx_SYS64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
> > +#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
> > +					 ESR_ELx_SYS64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
> > +					 ESR_ELx_SYS64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
> > +					 ESR_ELx_SYS64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
> > +					 ESR_ELx_SYS64_ISS_DIR_READ)
> > +
> > +#define esr_sys64_to_sysreg(e)					\
> > +	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
> > +
> > +#define esr_cp15_to_sysreg(e)					\
> > +	sys_reg(3,						\
> > +		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
> > +		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
> > +		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
> > +
> > +/*
> > + * ISS field definitions for floating-point exception traps
> > + * (FP_EXC_32/FP_EXC_64).
> > + *
> > + * (The FPEXC_* constants are used instead for common bits.)
> > + */
> > +
> > +#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
> > +
> > +/*
> > + * ISS field definitions for CP15 accesses
> > + */
> > +#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
> > +#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
> > +#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
> > +
> > +#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
> > +#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
> > +#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
> > +#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
> > +#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
> > +#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
> > +#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
> > +#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
> > +#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
> > +#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
> > +
> > +#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
> > +					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
> > +					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
> > +					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
> > +					 ESR_ELx_CP15_32_ISS_DIR_MASK)
> > +#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
> > +					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
> > +					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
> > +					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
> > +					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
> > +
> > +#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
> > +#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
> > +#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
> > +
> > +#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
> > +#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
> > +
> > +#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
> > +#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
> > +
> > +#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
> > +#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
> > +#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
> > +#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
> > +
> > +#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
> > +					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
> > +					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
> > +
> > +#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
> > +					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
> > +					 ESR_ELx_CP15_64_ISS_DIR_MASK)
> > +
> > +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
> > +					 ESR_ELx_CP15_64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
> > +					 ESR_ELx_CP15_64_ISS_DIR_READ)
> > +
> > +#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
> > +					 ESR_ELx_CP15_32_ISS_DIR_READ)
> > +
> > +#ifndef __ASSEMBLY__
> > +#include <asm/types.h>
> > +
> > +static inline bool esr_is_data_abort(u32 esr)
> > +{
> > +	const u32 ec = ESR_ELx_EC(esr);
> > +
> > +	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
> > +}
> > +
> > +const char *esr_get_class_string(u32 esr);
> > +#endif /* __ASSEMBLY */
> > +
> > +#endif /* __ASM_ESR_H */
> > 
> 
> 

-- 
Pierre

Re: [PATCH 9/9] arm64: Import <asm/esr.h> from Linux

[Sean Anderson]

On 3/17/22 1:39 PM, Pierre-Clément Tosi wrote:
> On Wed, Mar 16, 2022 at 03:47:57PM -0400, Sean Anderson wrote:
>> On 3/16/22 11:39 AM, Pierre-Clément Tosi wrote:
>> > Import the header from version 5.16 of the kernel:
>> > 
>> >      commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
>> > 
>> > Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
>> > Cc: Tom Rini <trini@konsulko.com>
>> > ---
>> >   arch/arm/include/asm/esr.h | 343 +++++++++++++++++++++++++++++++++++++
>> >   1 file changed, 343 insertions(+)
>> >   create mode 100644 arch/arm/include/asm/esr.h
>> > 
>> > diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h
>> > new file mode 100644
>> > index 0000000000..d52a0b269e
>> > --- /dev/null
>> > +++ b/arch/arm/include/asm/esr.h
>> > @@ -0,0 +1,343 @@
>> > +/* SPDX-License-Identifier: GPL-2.0-only */
>> > +/*
>> > + * Copyright (C) 2013 - ARM Ltd
>> > + * Author: Marc Zyngier <marc.zyngier@arm.com>
>> > + */
>> > +
>> > +#ifndef __ASM_ESR_H
>> > +#define __ASM_ESR_H
>> > +
>> > +#include <asm/memory.h>
>> > +#include <asm/sysreg.h>
>> 
>> I think this is just needed for the UL macros. See e.g. [1].
> 
> I think you're right about <asm/memory.h> being included for UL(), as pointed
> out by commit d7a33f4fbd12 ("arm64/debug: Add missing #includes"), which could
> (should?) be replaced by <linux/const.h>. But the esr_*_to_sysreg() macros
> require <asm/sysreg.h> and, even if it's unlikely for U-Boot to use them, that
> header brings many useful macros of its own anyway.
> 
>> 
>> --Sean
>> 
>> [1] https://lore.kernel.org/u-boot/20220310205059.499269-22-sean.anderson@seco.com/
> 
> Thanks, I wasn't aware of that patch; should I drop this one or instead rebase
> it on top of yours to re-#include sysreg.h once it's been made available by this
> series?

That would be best. checkpatch does not like sysreg.h very much :)

--Sean

Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[Ramon Fried]

On Wed, Mar 16, 2022 at 5:40 PM Pierre-Clément Tosi <ptosi@google.com> wrote:
>
> Swap the arguments as that seems to have been the author's intention.
>
> Note: This fix wasn't tested on hardware and will result in more bits
>       being set by the underlying writel() in rk_clrsetreg(), which
>       might bring unexpected behavioural changes.
>
> Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Kever Yang <kever.yang@rock-chips.com>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  drivers/net/gmac_rockchip.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index 04008d2b19..0ecbcdf641 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
>         struct px30_grf *grf;
>         enum {
>                 PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
> -               PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
> +               PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
>                 PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
>         };
>
> --
> 2.35.1.723.g4982287a31-goog
>
I would love to see tested-by before I merge this.

Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[Kever Yang]

Add David,

Hi David,

     Could you help to check this patch?


Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
> Swap the arguments as that seems to have been the author's intention.
>
> Note: This fix wasn't tested on hardware and will result in more bits
>        being set by the underlying writel() in rk_clrsetreg(), which
>        might bring unexpected behavioural changes.
>
> Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Kever Yang <kever.yang@rock-chips.com>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>   drivers/net/gmac_rockchip.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index 04008d2b19..0ecbcdf641 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
>   	struct px30_grf *grf;
>   	enum {
>   		PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
> -		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
> +		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
>   		PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
>   	};
>   

Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[David Wu]

Hi Pierre-Clément,

Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu <david.wu@rock-chips.com>

在 2022/4/6 23:08, Kever Yang 写道:
> Add David,
> 
> Hi David,
> 
>      Could you help to check this patch?
> 
> 
> Thanks,
> - Kever
> On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
>> Swap the arguments as that seems to have been the author's intention.
>>
>> Note: This fix wasn't tested on hardware and will result in more bits
>>        being set by the underlying writel() in rk_clrsetreg(), which
>>        might bring unexpected behavioural changes.
>>
>> Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
>> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
>> Cc: Joe Hershberger <joe.hershberger@ni.com>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Kever Yang <kever.yang@rock-chips.com>
>> Cc: Tom Rini <trini@konsulko.com>
>> ---
>>   drivers/net/gmac_rockchip.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
>> index 04008d2b19..0ecbcdf641 100644
>> --- a/drivers/net/gmac_rockchip.c
>> +++ b/drivers/net/gmac_rockchip.c
>> @@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct 
>> gmac_rockchip_plat *pdata)
>>       struct px30_grf *grf;
>>       enum {
>>           PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
>> -        PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
>> +        PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
>>           PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
>>       };