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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros
Date: Tue,  8 Dec 2020 14:56:33 -0800	[thread overview]
Message-ID: <1b78dbf9afd11bc9e47ce112a0096521a744133c.1607467819.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1607467819.git.alistair.francis@wdc.com>

The helper functions defined in helper.h specify that the argument is of
type target_long. Let's change the implementation to match the header
definition.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/fpu_helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a8249..507d7fe7fa 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -224,13 +224,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_uint64(frs1, &env->fp_status);
@@ -248,12 +248,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
 }
@@ -337,12 +337,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_uint64(frs1, &env->fp_status);
 }
@@ -359,12 +359,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
 {
     return int64_to_float64(rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
 {
     return uint64_to_float64(rs1, &env->fp_status);
 }
-- 
2.29.2



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com
Subject: [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros
Date: Tue,  8 Dec 2020 14:56:33 -0800	[thread overview]
Message-ID: <1b78dbf9afd11bc9e47ce112a0096521a744133c.1607467819.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1607467819.git.alistair.francis@wdc.com>

The helper functions defined in helper.h specify that the argument is of
type target_long. Let's change the implementation to match the header
definition.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/fpu_helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a8249..507d7fe7fa 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -224,13 +224,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_uint64(frs1, &env->fp_status);
@@ -248,12 +248,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
 }
@@ -337,12 +337,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_uint64(frs1, &env->fp_status);
 }
@@ -359,12 +359,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
 }
 
 #if defined(TARGET_RISCV64)
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
 {
     return int64_to_float64(rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
 {
     return uint64_to_float64(rs1, &env->fp_status);
 }
-- 
2.29.2



  parent reply	other threads:[~2020-12-08 23:15 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-08 22:56 [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-12-08 22:56 ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 03/15] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 04/15] riscv: virt: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 15:50   ` Richard Henderson
2020-12-09 15:50     ` Richard Henderson
2020-12-09 22:19     ` Alistair Francis
2020-12-09 22:19       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 06/15] hw/riscv: virt: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 07/15] hw/riscv: spike: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 08/15] hw/riscv: sifive_u: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` Alistair Francis [this message]
2020-12-08 22:56   ` [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-09 15:56   ` Richard Henderson
2020-12-09 15:56     ` Richard Henderson
2020-12-09 22:22     ` Alistair Francis
2020-12-09 22:22       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 15:59   ` Richard Henderson
2020-12-09 15:59     ` Richard Henderson
2020-12-09 22:26     ` Alistair Francis
2020-12-09 22:26       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:03   ` Richard Henderson
2020-12-09 16:03     ` Richard Henderson
2020-12-09 22:29     ` Alistair Francis
2020-12-09 22:29       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:03   ` Richard Henderson
2020-12-09 16:03     ` Richard Henderson
2020-12-08 22:56 ` [PATCH v2 13/15] target/riscv: cpu_helper: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:07   ` Richard Henderson
2020-12-09 16:07     ` Richard Henderson
2020-12-08 22:56 ` [PATCH v2 14/15] target/riscv: csr: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 17:34   ` Richard Henderson
2020-12-09 17:34     ` Richard Henderson
2020-12-09 22:34     ` Alistair Francis
2020-12-09 22:34       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-15  0:26 ` [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess Palmer Dabbelt
2020-12-15  0:26   ` Palmer Dabbelt

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