All of lore.kernel.org
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs
Date: Wed, 9 Dec 2020 10:03:12 -0600	[thread overview]
Message-ID: <1de03a6f-47d9-6032-ec66-eddea15b1760@linaro.org> (raw)
In-Reply-To: <3f1ff73c70b003826bf436ae4c937b62cac79bdc.1607467819.git.alistair.francis@wdc.com>

On 12/8/20 4:56 PM, Alistair Francis wrote:
> +#ifdef TARGET_RISCV64
> +static void rv64_sifive_u_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
> -    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>  }
>  
> -static void rvxx_sifive_e_cpu_init(Object *obj)
> +static void rv64_sifive_e_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
> -    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> +    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>  }
> +#else

I guess it isn't much duplication, but you could retain the rvxx functions and
pass in xlen as an argument.  Either way,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: Re: [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs
Date: Wed, 9 Dec 2020 10:03:12 -0600	[thread overview]
Message-ID: <1de03a6f-47d9-6032-ec66-eddea15b1760@linaro.org> (raw)
In-Reply-To: <3f1ff73c70b003826bf436ae4c937b62cac79bdc.1607467819.git.alistair.francis@wdc.com>

On 12/8/20 4:56 PM, Alistair Francis wrote:
> +#ifdef TARGET_RISCV64
> +static void rv64_sifive_u_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
> -    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>  }
>  
> -static void rvxx_sifive_e_cpu_init(Object *obj)
> +static void rv64_sifive_e_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
> -    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> +    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>  }
> +#else

I guess it isn't much duplication, but you could retain the rvxx functions and
pass in xlen as an argument.  Either way,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


  reply	other threads:[~2020-12-09 16:05 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-08 22:56 [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-12-08 22:56 ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 03/15] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 04/15] riscv: virt: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 15:50   ` Richard Henderson
2020-12-09 15:50     ` Richard Henderson
2020-12-09 22:19     ` Alistair Francis
2020-12-09 22:19       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 06/15] hw/riscv: virt: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 07/15] hw/riscv: spike: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 08/15] hw/riscv: sifive_u: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 15:56   ` Richard Henderson
2020-12-09 15:56     ` Richard Henderson
2020-12-09 22:22     ` Alistair Francis
2020-12-09 22:22       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 15:59   ` Richard Henderson
2020-12-09 15:59     ` Richard Henderson
2020-12-09 22:26     ` Alistair Francis
2020-12-09 22:26       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:03   ` Richard Henderson [this message]
2020-12-09 16:03     ` Richard Henderson
2020-12-09 22:29     ` Alistair Francis
2020-12-09 22:29       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:03   ` Richard Henderson
2020-12-09 16:03     ` Richard Henderson
2020-12-08 22:56 ` [PATCH v2 13/15] target/riscv: cpu_helper: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 16:07   ` Richard Henderson
2020-12-09 16:07     ` Richard Henderson
2020-12-08 22:56 ` [PATCH v2 14/15] target/riscv: csr: " Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-09 17:34   ` Richard Henderson
2020-12-09 17:34     ` Richard Henderson
2020-12-09 22:34     ` Alistair Francis
2020-12-09 22:34       ` Alistair Francis
2020-12-08 22:56 ` [PATCH v2 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-08 22:56   ` Alistair Francis
2020-12-15  0:26 ` [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess Palmer Dabbelt
2020-12-15  0:26   ` Palmer Dabbelt

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1de03a6f-47d9-6032-ec66-eddea15b1760@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=bmeng.cn@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.