* [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
@ 2022-08-04 10:29 Ankit Nautiyal
2022-08-04 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
0 siblings, 2 replies; 4+ messages in thread
From: Ankit Nautiyal @ 2022-08-04 10:29 UTC (permalink / raw)
To: intel-gfx
WA_14014367875 : When Display PHY is configured in continuous
DCC calibration mode, the DCC (duty cycle correction) for the clock
erroneously goes through a state where the DCC code is 0x00 when it is
supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
distortion in the clock, which leads to a bit error. The issue is known
to be causing flickering with eDP HBR3 panels.
The work around configures the DCC in one-time-update mode.
This mode updates the DCC code one time during training and then
it does not change. This will prevent on-the-fly updates so that the
glitch does not occur.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 64890f39c3cc..1b8bdc47671d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -242,9 +242,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
ICL_PORT_TX_DW8_ODCC_CLK_SEL |
ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
+ /* WA_14014367875 Set DCC calibration mode to Read once*/
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
DCC_MODE_SELECT_MASK,
- DCC_MODE_SELECT_CONTINUOSLY);
+ ~DCC_MODE_SELECT_MASK);
}
ret &= icl_verify_procmon_ref_values(dev_priv, phy);
@@ -366,8 +367,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+
+ /* WA_14014367875 Set DCC calibration mode to Read once*/
val &= ~DCC_MODE_SELECT_MASK;
- val |= DCC_MODE_SELECT_CONTINUOSLY;
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
2022-08-04 10:29 [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels Ankit Nautiyal
@ 2022-08-04 11:41 ` Patchwork
2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-08-04 11:41 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10254 bytes --]
== Series Details ==
Series: drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
URL : https://patchwork.freedesktop.org/series/106967/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11966 -> Patchwork_106967v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_106967v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_106967v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (2): bat-rpls-1 bat-jsl-3
Missing (2): fi-kbl-soraka fi-rkl-11600
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_106967v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@basic-rte:
- fi-adl-ddr5: [PASS][1] -> [DMESG-WARN][2] +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-adl-ddr5/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-adl-ddr5/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [PASS][3] -> [DMESG-WARN][4] +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- fi-rkl-guc: [PASS][5] -> [DMESG-WARN][6] +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-rkl-guc/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-rkl-guc/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [PASS][7] -> [DMESG-WARN][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
- {bat-rpls-2}: [PASS][9] -> [DMESG-WARN][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@i915_pm_rpm@basic-rte.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rpls-2/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- {bat-adlp-6}: [PASS][11] -> [DMESG-WARN][12] +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-adlp-6/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-adlp-6/igt@i915_pm_rpm@module-reload.html
- {bat-adlm-1}: [PASS][13] -> [DMESG-WARN][14] +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-adlm-1/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-adlm-1/igt@i915_pm_rpm@module-reload.html
- {bat-rpls-1}: NOTRUN -> [DMESG-WARN][15] +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rpls-1/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_106967v1 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-kbl-8809g: [FAIL][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-kbl-8809g/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-kbl-8809g/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_pm_backlight@basic-brightness:
- fi-kbl-8809g: NOTRUN -> [SKIP][20] ([fdo#109271]) +26 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-kbl-8809g/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][21] -> [DMESG-FAIL][22] ([i915#4494] / [i915#4957])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][23] -> [DMESG-FAIL][24] ([i915#4528])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-blb-e6850/igt@i915_selftest@live@requests.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-8809g: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-kbl-8809g/igt@kms_chamelium@dp-hpd-fast.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][26] ([i915#4312])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][27] ([i915#2582]) -> [PASS][28] +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@fbdev@read.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rpls-2/igt@fbdev@read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][29] ([i915#6298]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][31] ([i915#1849]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][33] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-------------
* Linux: CI_DRM_11966 -> Patchwork_106967v1
CI-20190529: 20190529
CI_DRM_11966: f3c1d1b53388aaa69e20a1b72f8307ad57116565 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6613: 209230467200f2fa63a6f71fe6299996470dd813 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106967v1: f3c1d1b53388aaa69e20a1b72f8307ad57116565 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
3bc825442efb drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106967v1/index.html
[-- Attachment #2: Type: text/html, Size: 10633 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
2022-08-04 10:29 [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels Ankit Nautiyal
2022-08-04 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
@ 2022-08-04 15:44 ` Imre Deak
2022-08-04 16:00 ` Nautiyal, Ankit K
1 sibling, 1 reply; 4+ messages in thread
From: Imre Deak @ 2022-08-04 15:44 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
On Thu, Aug 04, 2022 at 03:59:11PM +0530, Ankit Nautiyal wrote:
> WA_14014367875 : When Display PHY is configured in continuous
> DCC calibration mode, the DCC (duty cycle correction) for the clock
> erroneously goes through a state where the DCC code is 0x00 when it is
> supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
> distortion in the clock, which leads to a bit error. The issue is known
> to be causing flickering with eDP HBR3 panels.
>
> The work around configures the DCC in one-time-update mode.
> This mode updates the DCC code one time during training and then
> it does not change. This will prevent on-the-fly updates so that the
> glitch does not occur.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 64890f39c3cc..1b8bdc47671d 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -242,9 +242,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
> ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
>
> + /* WA_14014367875 Set DCC calibration mode to Read once*/
The usual format is 'Wa_<lineage>:<platforms>', so Wa_22012718247:...
'read once' is 'run once' afaics.
> ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
> DCC_MODE_SELECT_MASK,
> - DCC_MODE_SELECT_CONTINUOSLY);
> + ~DCC_MODE_SELECT_MASK);
I can see this WA listed only for ADL_P/N/S and TGL (and not for DG2/RKL
for instance). ~DCC_MODE_SELECT_MASK should be 0, maybe add a
dcc_calibration_mode() that could be used below as well.
Could you file a ticket at
https://gfxspecs.intel.com/Predator/Home/Index/49291
which specifies this programming explicitly for each platform, but is
incorrect now wrt. the above WA?
> }
>
> ret &= icl_verify_procmon_ref_values(dev_priv, phy);
> @@ -366,8 +367,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
>
> val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> +
> + /* WA_14014367875 Set DCC calibration mode to Read once*/
> val &= ~DCC_MODE_SELECT_MASK;
> - val |= DCC_MODE_SELECT_CONTINUOSLY;
> intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
> }
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
@ 2022-08-04 16:00 ` Nautiyal, Ankit K
0 siblings, 0 replies; 4+ messages in thread
From: Nautiyal, Ankit K @ 2022-08-04 16:00 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Thanks Imre, for the comments, please find my response inline:
On 8/4/2022 9:14 PM, Imre Deak wrote:
> On Thu, Aug 04, 2022 at 03:59:11PM +0530, Ankit Nautiyal wrote:
>> WA_14014367875 : When Display PHY is configured in continuous
>> DCC calibration mode, the DCC (duty cycle correction) for the clock
>> erroneously goes through a state where the DCC code is 0x00 when it is
>> supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
>> distortion in the clock, which leads to a bit error. The issue is known
>> to be causing flickering with eDP HBR3 panels.
>>
>> The work around configures the DCC in one-time-update mode.
>> This mode updates the DCC code one time during training and then
>> it does not change. This will prevent on-the-fly updates so that the
>> glitch does not occur.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
>> index 64890f39c3cc..1b8bdc47671d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
>> @@ -242,9 +242,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>> ICL_PORT_TX_DW8_ODCC_CLK_SEL |
>> ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
>>
>> + /* WA_14014367875 Set DCC calibration mode to Read once*/
> The usual format is 'Wa_<lineage>:<platforms>', so Wa_22012718247:...
> 'read once' is 'run once' afaics.
Indeed. Will fix the format and the typo here.
>
>> ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
>> DCC_MODE_SELECT_MASK,
>> - DCC_MODE_SELECT_CONTINUOSLY);
>> + ~DCC_MODE_SELECT_MASK);
> I can see this WA listed only for ADL_P/N/S and TGL (and not for DG2/RKL
Alright, so perhaps need to use Platform check.
> for instance). ~DCC_MODE_SELECT_MASK should be 0, maybe add a
> dcc_calibration_mode() that could be used below as well.
Yes right, I did realize mask should have been 0. Will do the suggested
changes.
>
> Could you file a ticket at
> https://gfxspecs.intel.com/Predator/Home/Index/49291
> which specifies this programming explicitly for each platform, but is
> incorrect now wrt. the above WA?
Makes sense, will file a bspec ticket.
Regards,
Ankit
>
>> }
>>
>> ret &= icl_verify_procmon_ref_values(dev_priv, phy);
>> @@ -366,8 +367,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>> intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
>>
>> val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
>> +
>> + /* WA_14014367875 Set DCC calibration mode to Read once*/
>> val &= ~DCC_MODE_SELECT_MASK;
>> - val |= DCC_MODE_SELECT_CONTINUOSLY;
>> intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
>> }
>>
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-08-04 10:29 [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels Ankit Nautiyal
2022-08-04 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
2022-08-04 16:00 ` Nautiyal, Ankit K
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