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* [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
@ 2022-08-04 10:29 Ankit Nautiyal
  2022-08-04 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
  2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
  0 siblings, 2 replies; 4+ messages in thread
From: Ankit Nautiyal @ 2022-08-04 10:29 UTC (permalink / raw)
  To: intel-gfx

WA_14014367875 : When Display PHY is configured in continuous
DCC calibration mode, the DCC (duty cycle correction) for the clock
erroneously goes through a state where the DCC code is 0x00 when it is
supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
distortion in the clock, which leads to a bit error. The issue is known
to be causing flickering with eDP HBR3 panels.

The work around configures the DCC in one-time-update mode.
This mode updates the DCC code one time during training and then
it does not change.  This will prevent on-the-fly updates so that the
glitch does not occur.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 64890f39c3cc..1b8bdc47671d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -242,9 +242,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
 
+		/* WA_14014367875 Set DCC calibration mode to Read once*/
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
 				     DCC_MODE_SELECT_MASK,
-				     DCC_MODE_SELECT_CONTINUOSLY);
+				     ~DCC_MODE_SELECT_MASK);
 	}
 
 	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
@@ -366,8 +367,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
 
 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+
+			/* WA_14014367875 Set DCC calibration mode to Read once*/
 			val &= ~DCC_MODE_SELECT_MASK;
-			val |= DCC_MODE_SELECT_CONTINUOSLY;
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
 		}
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-08-04 16:03 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-04 10:29 [Intel-gfx] [PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels Ankit Nautiyal
2022-08-04 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-08-04 15:44 ` [Intel-gfx] [PATCH] " Imre Deak
2022-08-04 16:00   ` Nautiyal, Ankit K

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