[PATCH v4 00/39] Qualcomm generic board support

[PATCH v4 00/39] Qualcomm generic board support

[Caleb Connolly]

Historically, Qualcomm boards in U-Boot have all had their own
board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their
own hardcoded sysmap-xyz.c file, and their own U-Boot specific
devicetree with little/no compatibility with upstream DT.

This series makes a few final prepatory changes, and then replaces
almost all of the board specific code with generic alternatives. The end
result is that all Qualcomm boards both current and future (with the
exception of the db410c and db820c) can be supported by a single U-Boot
binary by just providing the correct DT. New boards can be added without
introducing any addition mach/ or board/ code or config options.

Due to the nature of this change, the patch ("mach-snapdragon:
generalise board support") has become pretty big, I tried a few
different ways to represent this in git history, but the other methods
(e.g. adding a stub "generic" target and removing it again) were more
confusing and made for much messier git history. The current patch is
mostly atomic, but requires regenerating the config.

The QCS404 EVB board had some code to enable the USB VBUS regulator,
this is dropped in favour of a adding a new vbus-supply property to the
dwc3-generic driver. This will also be used by the dragonboard845c in a
future patch. This handles the common case of a board requiring some
regulator be enabled for USB host mode.

A more detailed description of the changes is below.

== Memory map ==

The memory map was historically hardcoded into U-Boot, this meant that
U-Boot had to be built for a specific variant of a device. This is
changed to instead read the memory map from the DT /memory node.

Additionally, most boards mapped addresss 0x0 as valid, as a result if a
null pointer access happens then it will cause a bus stall (and board
hang). This is fixed so that null pointer accesses will now correctly
throw an exception.

== DT loading ==

Previously, boards used the FDT blob embedded into U-Boot (via
OF_SEPARATE). However, most Qualcomm boards run U-Boot as a secondary
bootloader, so we can instead rely on the first-stage bootloader to
populate some useful FDT properties for us (notably the /memory node and
KASLR seed) and fetch the DTB that it provides. Combined with the memory
map changes above, this let's us entirely avoid configuring the memory
map explicitly.

== defconfig ==

Most of the board defconfigs and config headers were quite similar, to
simplify maintenance going forward, all the fully generic boards (sdm845
and qcs404-evb so far) are adapted to use the new qcom_defconfig. Going
forward, all new Qualcomm boards should be supported by this defconfig.
A notable exception is for specific usecases (like U-Boot as the primary
bootloader).

== The older dragonboards ==

The db410c and db820c both have some custom board init code, as a result
they aren't yet binary compatible. mach-snapdragon is adjusted so
that all the necessary config options (e.g. CONFIG_SYS_BOARD) can be set
from their defconfigs, this makes it possible to enable support for new
boards without introducing additional config options.

The db410c can run U-Boot either chainloaded like the other boards, or
as a first-stage bootloader replacing aboot. However it was hardcoded to
only build for the latter option. This series introduces a new
"chainloaded" defconfig to enable easier testing via fastboot.

== dynamic environment variables ==

This series also introduces runtime-allocated load addresses via the lmb
allocator. This allows for booting on boards with vastly different
memory layouts without any pre-calculation or macro magic in the config
header. This feature is based on similar code in mach-apple.

The soc, board, and fdtfile environment variables are also generated
automatically. Many Qualcomm boards follow a similar scheme for DTB
naming such that the name can often be derived from the root compatible
properties. This is intended to cover the most common cases and be a
simple solution for booting generic distro images without having to
explicitly choose the right DTB. The U-Boot DTS can be tweaked if
necessary to produce the correct name, the variable can be overwritten,
or a bootloader like GRUB can load the devicetree instead.

== Upstream DT ==

All Qualcomm boards have had their devicetree files replaced with the
upstream versions. Previous patch series made the necessary driver
adjustments to fully support the upstream DT format. All future
Qualcomm boards should use upstream DTS by default.

Once Sumit's work to import dt-rebasing has been merged, we will drop
the imported DT and bindings again.

---
I have tested this series on the Dragonboard410c, Dragonboard820c, and
Dragonboard845c. I unfortunately don't have access to a QCS404 EVB board
to test.

This series is based on the qcom-next branch [1] and depends on my PMIC
fixes series [2], an integration branch for testing can be found at [3].
The non-qualcomm-specific changes (patches 1 and 2) don't have any
dependencies.

[1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon
[2]: https://lore.kernel.org/u-boot/20231114-b4-qcom-dt-compat-v3-0-88a92f8f00ba@linaro.org/
[3]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-common-target

---
Changes in v4:
- Drop unreachable return in ehci_usb_of_bind()
- Adjust error reporting in msm_sdc_clk_init() to not print ret which
  will always be 0.
- Simplify qcom_pmic_gpio and associated pinctrrl driver.
- Fix the bit clock divider on QCS404 (thanks Sumit).
- Make QCS404 pinctrl driver compatible with upstream DT.
- Fix qcs404_clk_set_rate() return values + move some things that should
  be in enable.
- Optimise reserved memory carveout algorithm and fix the last regions
  always getting skipped.
- Adjust APQ8016 to probe the pinctrl driver pre-relocation so that UART
  can be initialised.
- Stub in support for special pins in the Qualcomm pinctrl driver - we
  don't support them yet but in most cases they're already configured
  correctly and can be safely skipped.
- Improve readability of sdhci msm_sdc_clk_init() and use log_warning()
  instead of printf().
- Add missing CONFIG_SAVE_PREV_BL options to qcom_defconfig
- Document known issue only affecting qcs404 where in the msm_sdhci driver
  the xo_board clock somehow becomes associated with the qcom_clock device
  resulting in qcs404_clk_set_rate() being called for clock id 0. This
  doesn't seem to cause any issues but has proven somewhat elusive to debug.
- Add a link to the APQ8016 TRM in doc/board/qualcomm/dragonboard410c.rst
- Link to v3: https://lore.kernel.org/r/20240130-b4-qcom-common-target-v3-0-e523cbf9e556@linaro.org

Changes in v3:
- Remove dragonboard410c.dts file
- Introduce generic board_usb_init() function.
- Remove db410c specific dead code (smem RAM layout)
- Fix pinctrl DT compatibility for msm8916/msm8996
- Reference git tag where DT and headers were taken from Linux.
- Adjust ramdisk allocation size to 128M
- Improve documentation wording, reference buildman
- Fix mapping for reserved regions to avoid speculative pre-fetching
- Apply quicksort to memory banks read from DT to ensure ordering
- Link to v2: https://lore.kernel.org/r/20231219-b4-qcom-common-target-v2-0-b6dd9704219e@linaro.org

Changes in v2:
- Split DTS changes to reduce patch size.
- Import full board DTS files from Linux too, and introduce -u-boot.dtsi
  files where necessary to make any U-Boot specific changes.
- Add a pinctrl driver for qcom PMIC GPIOs
- Always enable LINUX_KERNEL_IMAGE_HEADER
- Link to v1: https://lore.kernel.org/r/20231121-b4-qcom-common-target-v1-0-9492198e0c15@linaro.org

To: Neil Armstrong <neil.armstrong@linaro.org>
To: Sumit Garg <sumit.garg@linaro.org>
To: Ramon Fried <rfried.dev@gmail.com>
Cc: Marek Vasut <marex@denx.de>
To: Dzmitry Sankouski <dsankouski@gmail.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
To: Peng Fan <peng.fan@nxp.com>
To: Jaehoon Chung <jh80.chung@samsung.com>
To: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
To: Lukasz Majewski <lukma@denx.de>
To: Sean Anderson <seanga2@gmail.com>
To: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
To: Stephan Gerhold <stephan@gerhold.net>
Cc:  <u-boot@lists.denx.de>

---
Caleb Connolly (39):
      arm: init: export prev_bl_fdt_addr
      usb: dwc3-generic: support external vbus regulator
      mmc: msm_sdhci: use modern clock handling
      dt-bindings: drop msm_sdhci binding
      clk/qcom: use upstream compatible properties
      clock/qcom: qcs404: fix clk_set_rate
      serial: msm: add debug UART
      serial: msm: fix clock handling and pinctrl
      gpio: qcom_pmic: 1-based GPIOs
      gpio: qcom_pmic: add a quirk to skip GPIO configuration
      gpio: qcom_pmic: add pinctrl driver
      sandbox: dts: fix qcom pmic gpio
      pinctrl: qcom: stub support for special GPIOs
      pinctrl: qcom: fix DT compatibility
      pinctrl: qcom: apq8016: init pre-reloaction
      board: dragonboard410c: add chainloaded config fragment
      board: dragonboard410c: upstream DT compat
      board: dragonboard410c: import board code from mach-snapdragon
      board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER
      mach-snapdragon: generalise board support
      mach-snapdragon: dynamic load addresses
      mach-snapdragon: generate fdtfile automatically
      mach-snapdragon: carve out no-map regions
      board: qcs404-evb: drop board code
      doc: board/qualcomm: document generic targets
      doc: board/qualcomm: link to APQ8016 TRM
      dt-bindings: import headers for SDM845
      dts: sdm845: import supporting dtsi files
      dts: sdm845: replace with upstream DTS
      dt-bindings: import headers for MSM8916
      dts: msm8916: import PMIC dtsi files
      dts: msm8916: replace with upstream DTS
      dt-bindings: import headers for MSM8996
      dts: msm8996: import PMIC dtsi files
      dts: dragonboard820c: use correct bindings for clocks
      dts: msm8996: replace with upstream DTS
      dt-bindings: import headers for qcs404
      dts: qcs404-evb: replace with upstream DT
      MAINTAINERS: Qualcomm: add some missing paths

 MAINTAINERS                                        |   12 +-
 arch/arm/Kconfig                                   |    4 +
 arch/arm/dts/Makefile                              |    9 +-
 arch/arm/dts/apq8016-sbc-u-boot.dtsi               |   20 +
 arch/arm/dts/apq8016-sbc.dts                       |  729 +++
 arch/arm/dts/apq8096-db820c-u-boot.dtsi            |   14 +
 arch/arm/dts/apq8096-db820c.dts                    | 1137 ++++
 arch/arm/dts/dragonboard410c-uboot.dtsi            |   44 -
 arch/arm/dts/dragonboard410c.dts                   |  209 -
 arch/arm/dts/dragonboard820c-uboot.dtsi            |   32 -
 arch/arm/dts/dragonboard820c.dts                   |  151 -
 arch/arm/dts/dragonboard845c-uboot.dtsi            |   26 -
 arch/arm/dts/dragonboard845c.dts                   |   48 -
 arch/arm/dts/msm8916-pm8916.dtsi                   |  157 +
 arch/arm/dts/msm8916.dtsi                          | 2702 +++++++++
 arch/arm/dts/msm8996.dtsi                          | 3884 +++++++++++++
 arch/arm/dts/pm8916.dtsi                           |  178 +
 arch/arm/dts/pm8994.dtsi                           |  152 +
 arch/arm/dts/pm8998.dtsi                           |  130 +
 arch/arm/dts/pmi8994.dtsi                          |   65 +
 arch/arm/dts/pmi8998.dtsi                          |   98 +
 arch/arm/dts/pms405.dtsi                           |  149 +
 arch/arm/dts/qcs404-evb-4000-u-boot.dtsi           |   48 +
 arch/arm/dts/qcs404-evb-4000.dts                   |   96 +
 arch/arm/dts/qcs404-evb-uboot.dtsi                 |   30 -
 arch/arm/dts/qcs404-evb.dts                        |  390 --
 arch/arm/dts/qcs404-evb.dtsi                       |  389 ++
 arch/arm/dts/qcs404.dtsi                           | 1829 ++++++
 arch/arm/dts/sdm845-db845c.dts                     | 1190 ++++
 .../arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi |   16 +
 arch/arm/dts/sdm845-samsung-starqltechn.dts        |  460 ++
 arch/arm/dts/sdm845-wcd9340.dtsi                   |   86 +
 arch/arm/dts/sdm845.dtsi                           | 5801 +++++++++++++++++++-
 arch/arm/dts/starqltechn-uboot.dtsi                |   27 -
 arch/arm/dts/starqltechn.dts                       |   68 -
 arch/arm/lib/save_prev_bl_data.c                   |    5 +
 arch/arm/mach-snapdragon/Kconfig                   |   95 +-
 arch/arm/mach-snapdragon/Makefile                  |    8 +-
 arch/arm/mach-snapdragon/board.c                   |  468 ++
 arch/arm/mach-snapdragon/dram.c                    |   99 -
 arch/arm/mach-snapdragon/include/mach/dram.h       |   12 -
 arch/arm/mach-snapdragon/include/mach/gpio.h       |    2 +
 arch/arm/mach-snapdragon/include/mach/misc.h       |   13 -
 arch/arm/mach-snapdragon/init_sdm845.c             |   73 -
 arch/arm/mach-snapdragon/misc.c                    |   55 -
 arch/arm/mach-snapdragon/sysmap-apq8016.c          |   31 -
 arch/arm/mach-snapdragon/sysmap-apq8096.c          |   31 -
 arch/arm/mach-snapdragon/sysmap-qcs404.c           |   43 -
 arch/arm/mach-snapdragon/sysmap-sdm845.c           |   31 -
 arch/sandbox/dts/sandbox.dtsi                      |    9 +-
 board/qualcomm/dragonboard410c/Kconfig             |   15 -
 board/qualcomm/dragonboard410c/Makefile            |    2 +-
 .../dragonboard410c/configs/chainloaded.config     |    7 +
 board/qualcomm/dragonboard410c/dragonboard410c.c   |  130 +-
 board/qualcomm/dragonboard820c/Kconfig             |   15 -
 board/qualcomm/dragonboard820c/Makefile            |    1 -
 board/qualcomm/dragonboard820c/dragonboard820c.c   |   39 +-
 board/qualcomm/dragonboard820c/head.S              |   33 -
 board/qualcomm/dragonboard820c/u-boot.lds          |  111 -
 board/qualcomm/dragonboard845c/Kconfig             |   12 -
 board/qualcomm/qcs404-evb/Kconfig                  |   15 -
 board/qualcomm/qcs404-evb/Makefile                 |    6 -
 board/qualcomm/qcs404-evb/qcs404-evb.c             |   62 -
 configs/dragonboard410c_defconfig                  |    8 +-
 configs/dragonboard820c_defconfig                  |    8 +-
 configs/dragonboard845c_defconfig                  |   29 -
 configs/qcom_defconfig                             |   67 +
 configs/qcs404evb_defconfig                        |   55 -
 configs/starqltechn_defconfig                      |   41 -
 doc/board/qualcomm/board.rst                       |  125 +
 doc/board/qualcomm/debugging.rst                   |   61 +
 doc/board/qualcomm/dragonboard410c.rst             |    2 +
 doc/board/qualcomm/index.rst                       |    4 +-
 doc/board/qualcomm/qcs404.rst                      |   79 -
 doc/board/qualcomm/sdm845.rst                      |  167 -
 doc/device-tree-bindings/mmc/msm_sdhci.txt         |   25 -
 doc/device-tree-bindings/usb/ehci-msm.txt          |   10 -
 drivers/clk/qcom/clock-apq8016.c                   |    9 +-
 drivers/clk/qcom/clock-apq8096.c                   |    7 +-
 drivers/clk/qcom/clock-qcs404.c                    |   25 +-
 drivers/gpio/msm_gpio.c                            |   20 +
 drivers/gpio/qcom_pmic_gpio.c                      |  275 +-
 drivers/mmc/msm_sdhci.c                            |   69 +-
 drivers/phy/qcom/msm8916-usbh-phy.c                |    4 +-
 drivers/pinctrl/qcom/pinctrl-apq8016.c             |   29 +-
 drivers/pinctrl/qcom/pinctrl-apq8096.c             |   16 +-
 drivers/pinctrl/qcom/pinctrl-qcom.c                |   12 +
 drivers/pinctrl/qcom/pinctrl-qcs404.c              |   58 +-
 drivers/serial/Kconfig                             |    8 +
 drivers/serial/serial_msm.c                        |   62 +-
 drivers/usb/dwc3/dwc3-generic.c                    |   12 +
 drivers/usb/host/ehci-msm.c                        |   22 +-
 include/configs/dragonboard845c.h                  |   20 -
 include/configs/qcom.h                             |   21 +
 include/configs/qcs404-evb.h                       |   20 -
 include/configs/sdm845.h                           |   26 -
 include/dt-bindings/arm/coresight-cti-dt.h         |   37 +
 include/dt-bindings/clock/qcom,camcc-sdm845.h      |  116 +
 include/dt-bindings/clock/qcom,dispcc-sdm845.h     |   56 +
 include/dt-bindings/clock/qcom,gcc-msm8916.h       |  179 +
 include/dt-bindings/clock/qcom,gcc-msm8996.h       |  362 ++
 include/dt-bindings/clock/qcom,gpucc-sdm845.h      |   24 +
 include/dt-bindings/clock/qcom,lpass-sdm845.h      |   15 +
 include/dt-bindings/clock/qcom,mmcc-msm8996.h      |  295 +
 include/dt-bindings/clock/qcom,rpmcc.h             |  174 +
 include/dt-bindings/clock/qcom,rpmh.h              |   37 +
 include/dt-bindings/clock/qcom,turingcc-qcs404.h   |   15 +
 include/dt-bindings/clock/qcom,videocc-sdm845.h    |   35 +
 include/dt-bindings/dma/qcom-gpi.h                 |   11 +
 include/dt-bindings/firmware/qcom,scm.h            |   39 +
 include/dt-bindings/iio/qcom,spmi-vadc.h           |  300 +
 include/dt-bindings/interconnect/qcom,msm8916.h    |  100 +
 .../dt-bindings/interconnect/qcom,msm8996-cbf.h    |   12 +
 include/dt-bindings/interconnect/qcom,msm8996.h    |  163 +
 include/dt-bindings/interconnect/qcom,osm-l3.h     |   15 +
 include/dt-bindings/interconnect/qcom,sdm845.h     |  150 +
 include/dt-bindings/phy/phy-qcom-qmp.h             |   20 +
 include/dt-bindings/phy/phy-qcom-qusb2.h           |   37 +
 include/dt-bindings/pinctrl/qcom,pmic-gpio.h       |  164 +
 include/dt-bindings/pinctrl/qcom,pmic-mpp.h        |  106 +
 include/dt-bindings/power/qcom-rpmpd.h             |  412 ++
 .../dt-bindings/regulator/qcom,rpmh-regulator.h    |   36 +
 include/dt-bindings/reset/qcom,gcc-msm8916.h       |  100 +
 include/dt-bindings/reset/qcom,sdm845-aoss.h       |   17 +
 include/dt-bindings/reset/qcom,sdm845-pdc.h        |   22 +
 include/dt-bindings/soc/qcom,apr.h                 |   28 +
 include/dt-bindings/soc/qcom,rpmh-rsc.h            |   14 +
 include/dt-bindings/sound/apq8016-lpass.h          |    9 +
 include/dt-bindings/sound/qcom,lpass.h             |   46 +
 include/dt-bindings/sound/qcom,q6afe.h             |    9 +
 include/dt-bindings/sound/qcom,q6asm.h             |   26 +
 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h |  234 +
 include/dt-bindings/sound/qcom,wcd9335.h           |   15 +
 include/init.h                                     |   11 +
 134 files changed, 23997 insertions(+), 2643 deletions(-)
---
base-commit: 22f391e8be11986bae824509470cf11e7bac31b0

// Caleb (they/them)

[PATCH v4 01/39] arm: init: export prev_bl_fdt_addr

[Caleb Connolly]

When booting U-Boot on board with a locked down first-stage bootloader,
we emulate the Linux boot header. By passing the U-Boot FDT through this
first-stage bootloader and retrieving it afterwards we can pre-populate
the memory nodes and other info like the KASLR address.

Add a function to export the FDT addr so that boards can use it over the
built-in FDT.

Don't check is_addr_accessible() here because we might not yet have a
valid mem_map if it's going to be populated from the FDT, let the board
do their own validation instead.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/lib/save_prev_bl_data.c |  5 +++++
 include/init.h                   | 11 +++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c
index f7b23faf0d66..b286bac9bf00 100644
--- a/arch/arm/lib/save_prev_bl_data.c
+++ b/arch/arm/lib/save_prev_bl_data.c
@@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr)
 	return false;
 }
 
+phys_addr_t get_prev_bl_fdt_addr(void)
+{
+	return reg0;
+}
+
 int save_prev_bl_data(void)
 {
 	struct fdt_header *fdt_blob;
diff --git a/include/init.h b/include/init.h
index 9a1951d10a01..630d86729c4e 100644
--- a/include/init.h
+++ b/include/init.h
@@ -168,6 +168,17 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)
  * Return: 0 if ok; -ENODATA on error
  */
 int save_prev_bl_data(void);
+
+/**
+ * get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address
+ * of the FDT passed by the previous bootloader.
+ *
+ * Return: the address of the FDT passed by the previous bootloader
+ * or 0 if not found.
+ */
+phys_addr_t get_prev_bl_fdt_addr(void);
+#else
+#define get_prev_bl_fdt_addr() 0LLU
 #endif
 
 /**

-- 
2.43.1

[PATCH v4 02/39] usb: dwc3-generic: support external vbus regulator

[Caleb Connolly]

Add support for a vbus-supply regulator specified in devicetree. This
provides generic support to avoid hardcoded GPIO configuration in board
init code.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
This patch has no dependencies

Cc: Marek Vasut <marex@denx.de>
---
 drivers/usb/dwc3/dwc3-generic.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 6fb2de8a5ace..48da621ba966 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -21,6 +21,7 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <malloc.h>
+#include <power/regulator.h>
 #include <usb.h>
 #include "core.h"
 #include "gadget.h"
@@ -47,6 +48,7 @@ struct dwc3_generic_priv {
 struct dwc3_generic_host_priv {
 	struct xhci_ctrl xhci_ctrl;
 	struct dwc3_generic_priv gen_priv;
+	struct udevice *vbus_dev;
 };
 
 static int dwc3_generic_probe(struct udevice *dev,
@@ -240,6 +242,13 @@ static int dwc3_generic_host_probe(struct udevice *dev)
 	if (rc)
 		return rc;
 
+	rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_dev);
+	if (rc)
+		debug("%s: No vbus regulator found: %d\n", dev->name, rc);
+
+	if (priv->vbus_dev)
+		regulator_set_enable(priv->vbus_dev, true);
+
 	hccr = (struct xhci_hccr *)priv->gen_priv.base;
 	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
@@ -256,6 +265,9 @@ static int dwc3_generic_host_remove(struct udevice *dev)
 	if (rc)
 		return rc;
 
+	if (priv->vbus_dev)
+		regulator_set_enable(priv->vbus_dev, false);
+
 	return dwc3_generic_remove(dev, &priv->gen_priv);
 }
 

-- 
2.43.1

[PATCH v4 03/39] mmc: msm_sdhci: use modern clock handling

[Caleb Connolly]

Use the clk_* helper functions and the correct property name for clocks.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 47 insertions(+), 22 deletions(-)

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index fe1e754bfde0..b63538fce20c 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -44,6 +44,7 @@ struct msm_sdhc_plat {
 struct msm_sdhc {
 	struct sdhci_host host;
 	void *base;
+	struct clk_bulk clks;
 };
 
 struct msm_sdhc_variant_info {
@@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int msm_sdc_clk_init(struct udevice *dev)
 {
-	int node = dev_of_offset(dev);
-	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
-					400000);
-	uint clkd[2]; /* clk_id and clk_no */
-	int clk_offset;
-	struct udevice *clk_dev;
-	struct clk clk;
-	int ret;
+	struct msm_sdhc *prv = dev_get_priv(dev);
+	ofnode node = dev_ofnode(dev);
+	uint clk_rate;
+	int ret, i = 0, n_clks;
+	const char *clk_name;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
+	ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
 	if (ret)
-		return ret;
+		clk_rate = 400000;
 
-	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
-	if (clk_offset < 0)
-		return clk_offset;
-
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
-	if (ret)
+	ret = clk_get_bulk(dev, &prv->clks);
+	if (ret) {
+		log_warning("Couldn't get mmc clocks: %d\n", ret);
 		return ret;
+	}
 
-	clk.id = clkd[1];
-	ret = clk_request(clk_dev, &clk);
-	if (ret < 0)
+	ret = clk_enable_bulk(&prv->clks);
+	if (ret) {
+		log_warning("Couldn't enable mmc clocks: %d\n", ret);
 		return ret;
+	}
 
-	ret = clk_set_rate(&clk, clk_rate);
-	if (ret < 0)
-		return ret;
+	/* If clock-names is unspecified, then the first clock is the core clock */
+	if (!ofnode_get_property(node, "clock-names", &n_clks)) {
+		if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
+			log_warning("Couldn't set core clock rate: %d\n", ret);
+			return -EINVAL;
+		}
+	}
+
+	/* Find the index of the "core" clock */
+	while (i < n_clks) {
+		ofnode_read_string_index(node, "clock-names", i, &clk_name);
+		if (!strcmp(clk_name, "core"))
+			break;
+		i++;
+	}
+
+	if (i >= prv->clks.count) {
+		log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
+		       prv->clks.count);
+		return -EINVAL;
+	}
+
+	/* The clock is already enabled by the clk_bulk above */
+	ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
+	/* If we get a rate of 0 then something has probably gone wrong. */
+	if (ret == 0) {
+		log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev)
 	if (!var_info->mci_removed)
 		writel(0, priv->base + SDCC_MCI_HC_MODE);
 
+	clk_release_bulk(&priv->clks);
+
 	return 0;
 }
 

-- 
2.43.1

[PATCH v4 04/39] dt-bindings: drop msm_sdhci binding

[Caleb Connolly]

The upstream DT is supported here, so drop the U-Boot specific binding
docs.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 -------------------------
 1 file changed, 25 deletions(-)

diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt b/doc/device-tree-bindings/mmc/msm_sdhci.txt
deleted file mode 100644
index 08a290c66931..000000000000
--- a/doc/device-tree-bindings/mmc/msm_sdhci.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm Snapdragon SDHCI controller
-
-Required properties:
-- compatible : "qcom,sdhci-msm-v4"
-- reg: Base address and length of registers:
-	- Host controller registers (SDHCI)
-	- SD Core registers
-- clock: interface clock (must accept SD bus clock as a frequency)
-
-Optional properties:
-- index: If there is more than one controller - controller index (required
-	by generic SDHCI code).
-- bus_width: Width of SD/eMMC bus (default 4)
-- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
-
-Example:
-
-sdhci@07864000 {
-	compatible = "qcom,sdhci-msm-v4";
-	reg = <0x7864900 0x11c 0x7864000 0x800>;
-	index = <0x1>;
-	bus-width = <0x4>;
-	clock = <&clkc 1>;
-	clock-frequency = <200000000>;
-};

-- 
2.43.1

[PATCH v4 05/39] clk/qcom: use upstream compatible properties

[Caleb Connolly]

Adjust the apq8016 and apq8096 drivers to use the upstream compatible
properties, and adjust the associated dts files in U-Boot.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/dragonboard410c.dts | 2 +-
 drivers/clk/qcom/clock-apq8016.c | 2 +-
 drivers/clk/qcom/clock-apq8096.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 6a4e3ccf17b1..02c824d0226c 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -75,7 +75,7 @@
 			};
 		};
 		clkc: qcom,gcc@1800000 {
-			compatible = "qcom,gcc-apq8016";
+			compatible = "qcom,gcc-msm8916";
 			reg = <0x1800000 0x80000>;
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index c0ce570edc79..0af7191cff52 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -145,7 +145,7 @@ static struct msm_clk_data apq8016_clk_data = {
 
 static const struct udevice_id gcc_apq8016_of_match[] = {
 	{
-		.compatible = "qcom,gcc-apq8016",
+		.compatible = "qcom,gcc-msm8916",
 		.data = (ulong)&apq8016_clk_data,
 	},
 	{ }
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index cf1a347309a5..1e6fdb5cd42d 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -123,7 +123,7 @@ static struct msm_clk_data apq8096_clk_data = {
 
 static const struct udevice_id gcc_apq8096_of_match[] = {
 	{
-		.compatible = "qcom,gcc-apq8096",
+		.compatible = "qcom,gcc-msm8996",
 		.data = (ulong)&apq8096_clk_data,
 	},
 	{ }

-- 
2.43.1

[PATCH v4 06/39] clock/qcom: qcs404: fix clk_set_rate

[Caleb Connolly]

We should be returning the rate that we set the clock to, drivers like
MMC rely on this. So fix it.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-qcs404.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index f5b352803927..958312b88842 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
 
 	switch (clk->id) {
 	case GCC_BLSP1_UART2_APPS_CLK:
-		/* UART: 115200 */
+		/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
 		clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
 				     CFG_CLK_SRC_CXO, 16);
 		clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
-		break;
-	case GCC_BLSP1_AHB_CLK:
-		clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
-		break;
+		return 1843200;
 	case GCC_SDCC1_APPS_CLK:
 		/* SDCC1: 200MHz */
 		clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
 				     CFG_CLK_SRC_GPLL0, 8);
 		clk_enable_gpll0(priv->base, &gpll0_vote_clk);
 		clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
-		break;
-	case GCC_SDCC1_AHB_CLK:
-		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
-		break;
+		return rate;
 	case GCC_ETH_RGMII_CLK:
 		if (rate == 250000000)
 			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
@@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
 		else if (rate == 5000000)
 			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
 					     CFG_CLK_SRC_GPLL1, 8);
-		break;
-	default:
-		return 0;
+		return rate;
 	}
 
+	/* There is a bug only seeming to affect this board where the MMC driver somehow calls
+	 * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
+	 * The only clock with ID 0 is the xo_board clock which should not be associated with
+	 * this device...
+	 */
+	log_debug("Unknown clock id %ld\n", clk->id);
 	return 0;
 }
 
@@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
 		clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
 				 CFG_CLK_SRC_CXO);
 		break;
+	case GCC_SDCC1_AHB_CLK:
+		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
+		break;
 	default:
 		return 0;
 	}

-- 
2.43.1

[PATCH v4 07/39] serial: msm: add debug UART

[Caleb Connolly]

Introduce support for early debugging. This relies on the previous stage
bootloader to initialise the UART clocks, when running with U-Boot as
the primary bootloader this feature doesn't work. It will require a way
to configure the clocks before the driver model is available.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/serial/Kconfig      |  8 ++++++++
 drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 26460c4e0cab..fbd351a47859 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -319,6 +319,14 @@ config DEBUG_UART_S5P
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 
+config DEBUG_UART_MSM
+	bool "Qualcomm QUP UART debug"
+	depends on ARCH_SNAPDRAGON
+	help
+	  Select this to enable a debug UART using the serial_msm driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver-model serial is running.
+
 config DEBUG_UART_MSM_GENI
 	bool "Qualcomm snapdragon"
 	depends on ARCH_SNAPDRAGON
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index f4d96313b931..44b93bd7ff21 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = {
 	.probe = msm_serial_probe,
 	.ops	= &msm_serial_ops,
 };
+
+#ifdef CONFIG_DEBUG_UART_MSM
+
+static struct msm_serial_data init_serial_data = {
+	.base = CONFIG_VAL(DEBUG_UART_BASE),
+	.clk_rate = 7372800,
+};
+
+#include <debug_uart.h>
+
+/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
+//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+
+static inline void _debug_uart_init(void)
+{
+	/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
+	//apq8016_clk_init_uart(0x1800000);
+	uart_dm_init(&init_serial_data);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct msm_serial_data *priv = &init_serial_data;
+
+	while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
+	       !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
+		;
+
+	writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
+
+	writel(1, priv->base + UARTDM_NCF_TX);
+	writel(ch, priv->base + UARTDM_TF);
+}
+
+DEBUG_UART_FUNCS
+
+#endif

-- 
2.43.1

[PATCH v4 08/39] serial: msm: fix clock handling and pinctrl

[Caleb Connolly]

Use the modern helpers to fetch the clock and use the correct property
("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
as no boards have a "uart" pinctrl state and this prints confusing
errors.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/dragonboard410c.dts |  3 ++-
 arch/arm/dts/dragonboard820c.dts |  3 ++-
 drivers/serial/serial_msm.c      | 25 +++++--------------------
 3 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 02c824d0226c..c395e6cc0427 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -84,7 +84,8 @@
 		serial@78b0000 {
 			compatible = "qcom,msm-uartdm-v1.4";
 			reg = <0x78b0000 0x200>;
-			clock = <&clkc 4>;
+			clocks = <&clkc 4>;
+			clock-names = "core";
 			pinctrl-names = "uart";
 			pinctrl-0 = <&blsp1_uart>;
 		};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 146a0af8aafe..86b7f83d36d6 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -78,7 +78,8 @@
 		blsp2_uart2: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
-			clock = <&gcc 4>;
+			clocks = <&gcc 4>;
+			clock-names = "core";
 			pinctrl-names = "uart";
 			pinctrl-0 = <&blsp8_uart>;
 		};
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 44b93bd7ff21..ac4280c6c4c2 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev)
 {
 	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 					"clock-frequency", 115200);
-	uint clkd[2]; /* clk_id and clk_no */
-	int clk_offset;
-	struct udevice *clk_dev;
 	struct clk clk;
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
-				   clkd, 2);
-	if (ret)
-		return ret;
-
-	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
-	if (clk_offset < 0)
-		return clk_offset;
-
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
-	if (ret)
-		return ret;
-
-	clk.id = clkd[1];
-	ret = clk_request(clk_dev, &clk);
-	if (ret < 0)
+	ret = clk_get_by_name(dev, "core", &clk);
+	if (ret < 0) {
+		pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
 		return ret;
+	}
 
 	ret = clk_set_rate(&clk, clk_rate);
 	if (ret < 0)
@@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	pinctrl_select_state(dev, "uart");
 	uart_dm_init(priv);
 
 	return 0;
@@ -251,6 +235,7 @@ U_BOOT_DRIVER(serial_msm) = {
 	.priv_auto	= sizeof(struct msm_serial_data),
 	.probe = msm_serial_probe,
 	.ops	= &msm_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
 
 #ifdef CONFIG_DEBUG_UART_MSM

-- 
2.43.1

[PATCH v4 09/39] gpio: qcom_pmic: 1-based GPIOs

[Caleb Connolly]

Qualcomm PMICs number their GPIOs starting from 1, implement a custom
.xlate method to handle this.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/gpio/qcom_pmic_gpio.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 6167c8411678..2a4fef8d28cb 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -209,12 +209,34 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
 				       REG_CTL_OUTPUT_MASK, !!value);
 }
 
+static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			   struct ofnode_phandle_args *args)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (args->args_count < 1)
+		return -EINVAL;
+
+	/* GPIOs in DT are 1-based */
+	desc->offset = args->args[0] - 1;
+	if (desc->offset >= uc_priv->gpio_count)
+		return -EINVAL;
+
+	if (args->args_count < 2)
+		return 0;
+
+	desc->flags = gpio_flags_xlate(args->args[1]);
+
+	return 0;
+}
+
 static const struct dm_gpio_ops qcom_gpio_ops = {
 	.direction_input	= qcom_gpio_direction_input,
 	.direction_output	= qcom_gpio_direction_output,
 	.get_value		= qcom_gpio_get_value,
 	.set_value		= qcom_gpio_set_value,
 	.get_function		= qcom_gpio_get_function,
+	.xlate			= qcom_gpio_xlate,
 };
 
 static int qcom_gpio_probe(struct udevice *dev)

-- 
2.43.1

[PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration

[Caleb Connolly]

Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 2a4fef8d28cb..198cd84bc31e 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -64,6 +64,15 @@
 #define REG_EN_CTL             0x46
 #define REG_EN_CTL_ENABLE      (1 << 7)
 
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
+ */
+enum pmic_gpio_quirks {
+	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
 struct qcom_gpio_bank {
 	uint32_t pid; /* Peripheral ID on SPMI bus */
 	bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
 	struct qcom_gpio_bank *priv = dev_get_priv(dev);
 	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
 	uint32_t reg_ctl_val;
-	int ret;
+	ulong quirks = dev_get_driver_data(dev);
+	int ret = 0;
+
+	/* Some PMICs don't like their GPIOs being configured */
+	if (quirks & QCOM_PMIC_QUIRK_READONLY)
+		return 0;
 
 	/* Disable the GPIO */
 	ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
@@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
 static const struct udevice_id qcom_gpio_ids[] = {
 	{ .compatible = "qcom,pm8916-gpio" },
 	{ .compatible = "qcom,pm8994-gpio" },	/* 22 GPIO's */
-	{ .compatible = "qcom,pm8998-gpio" },
+	{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
 	{ .compatible = "qcom,pms405-gpio" },
 	{ }
 };

-- 
2.43.1

[PATCH v4 11/39] gpio: qcom_pmic: add pinctrl driver

[Caleb Connolly]

Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
necessary to make proper use of upstream DT bindings specifically on the
dragonboard410c where they're used to switch between USB host and device
modes.

Only support for driving the pins as output low or high is enabled for
now.

To minimise duplicated code and allow for sharing common DT data, the
pinctrl driver is initialised as a child of the existing GPIO driver.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/gpio/qcom_pmic_gpio.c | 257 +++++++++++++++++++++++++++++-------------
 1 file changed, 176 insertions(+), 81 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 198cd84bc31e..9eca1556c356 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -7,10 +7,14 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
 #include <log.h>
 #include <power/pmic.h>
 #include <spmi/spmi.h>
 #include <asm/io.h>
+#include <stdlib.h>
 #include <asm/gpio.h>
 #include <linux/bitops.h>
 
@@ -73,17 +77,54 @@ enum pmic_gpio_quirks {
 	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
 };
 
-struct qcom_gpio_bank {
+struct qcom_pmic_gpio_data {
 	uint32_t pid; /* Peripheral ID on SPMI bus */
 	bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
+	u32 pin_count;
+	struct udevice *pmic; /* Reference to pmic device for read/write */
 };
 
-static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
+/* dev can be the GPIO or pinctrl device */
+static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
+{
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	u32 gpio_base = plat->pid + REG_OFFSET(offset);
+	u32 reg_ctl_val;
+	int ret = 0;
+
+	/* Select the mode and output */
+	if (plat->lv_mv_type) {
+		if (input)
+			reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
+		else
+			reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
+	} else {
+		if (input)
+			reg_ctl_val = REG_CTL_MODE_INPUT;
+		else
+			reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
+	}
+
+	ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
+	if (ret < 0)
+		return ret;
+
+	if (plat->lv_mv_type && !input) {
+		ret = pmic_reg_write(plat->pmic,
+				     gpio_base + REG_LV_MV_OUTPUT_CTL,
+				     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
 				   bool input, int value)
 {
-	struct qcom_gpio_bank *priv = dev_get_priv(dev);
-	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
-	uint32_t reg_ctl_val;
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
 	ulong quirks = dev_get_driver_data(dev);
 	int ret = 0;
 
@@ -97,33 +138,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
 	if (ret < 0)
 		return ret;
 
-	/* Select the mode and output */
-	if (priv->lv_mv_type) {
-		if (input)
-			reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
-		else
-			reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
-	} else {
-		if (input)
-			reg_ctl_val = REG_CTL_MODE_INPUT;
-		else
-			reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
-	}
-
-	ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
-	if (ret < 0)
-		return ret;
-
-	if (priv->lv_mv_type && !input) {
-		ret = pmic_reg_write(dev->parent,
-				     gpio_base + REG_LV_MV_OUTPUT_CTL,
-				     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
-		if (ret < 0)
-			return ret;
-	}
+	_qcom_gpio_set_direction(dev, offset, input, value);
 
 	/* Set the right pull (no pull) */
-	ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
 			     REG_DIG_PULL_NO_PU);
 	if (ret < 0)
 		return ret;
@@ -131,13 +149,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
 	/* Configure output pin drivers if needed */
 	if (!input) {
 		/* Select the VIN - VIN0, pin is input so it doesn't matter */
-		ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
 				     REG_DIG_VIN_VIN0);
 		if (ret < 0)
 			return ret;
 
 		/* Set the right dig out control */
-		ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
+		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
 				     REG_DIG_OUT_CTL_CMOS |
 				     REG_DIG_OUT_CTL_DRIVE_L);
 		if (ret < 0)
@@ -162,15 +180,15 @@ static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
 
 static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
 {
-	struct qcom_gpio_bank *priv = dev_get_priv(dev);
-	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
 	int reg;
 
-	reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
+	reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
 	if (reg < 0)
 		return reg;
 
-	if (priv->lv_mv_type) {
+	if (plat->lv_mv_type) {
 		switch (reg & REG_CTL_LV_MV_MODE_MASK) {
 		case REG_CTL_LV_MV_MODE_INPUT:
 			return GPIOF_INPUT;
@@ -195,11 +213,11 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
 
 static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
 {
-	struct qcom_gpio_bank *priv = dev_get_priv(dev);
-	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
 	int reg;
 
-	reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
+	reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
 	if (reg < 0)
 		return reg;
 
@@ -209,11 +227,11 @@ static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
 static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
 			       int value)
 {
-	struct qcom_gpio_bank *priv = dev_get_priv(dev);
-	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
 
 	/* Set the output value of the gpio */
-	if (priv->lv_mv_type)
+	if (plat->lv_mv_type)
 		return pmic_clrsetbits(dev->parent,
 				       gpio_base + REG_LV_MV_OUTPUT_CTL,
 				       REG_LV_MV_OUTPUT_CTL_MASK,
@@ -253,63 +271,74 @@ static const struct dm_gpio_ops qcom_gpio_ops = {
 	.xlate			= qcom_gpio_xlate,
 };
 
+static int qcom_gpio_bind(struct udevice *dev)
+{
+	
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	ulong quirks = dev_get_driver_data(dev);
+	struct udevice *child;
+	struct driver *drv;
+	int ret;
+
+	drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
+	if (!drv) {
+		log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
+		return -ENOENT;
+	}
+
+	/* Bind the GPIO driver as a child of the PMIC. */
+	ret = device_bind_with_driver_data(dev, drv,
+					   dev->name,
+					   quirks, dev_ofnode(dev), &child);
+	if (ret)
+		return log_msg_ret("bind", ret);
+
+	dev_set_plat(child, plat);
+
+	return 0;
+}
+
 static int qcom_gpio_probe(struct udevice *dev)
 {
-	struct qcom_gpio_bank *priv = dev_get_priv(dev);
-	int reg;
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	struct ofnode_phandle_args args;
+	int val, ret;
 	u64 pid;
 
+	plat->pmic = dev->parent;
+
 	pid = dev_read_addr(dev);
 	if (pid == FDT_ADDR_T_NONE)
 		return log_msg_ret("bad address", -EINVAL);
 
-	priv->pid = pid;
+	plat->pid = pid;
 
 	/* Do a sanity check */
-	reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
-	if (reg != REG_TYPE_VAL)
+	val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
+	if (val != REG_TYPE_VAL)
 		return log_msg_ret("bad type", -ENXIO);
 
-	reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
-	if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH &&
-	    reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV)
+	val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
+	if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
+	    val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
 		return log_msg_ret("bad subtype", -ENXIO);
 
-	priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV ||
-			   reg == REG_SUBTYPE_GPIO_MV;
-
-	return 0;
-}
-
-/*
- * Parse basic GPIO count specified via the gpio-ranges property
- * as specified in Linux devicetrees
- * Returns < 0 on error, otherwise gpio count
- */
-static int qcom_gpio_of_parse_ranges(struct udevice *dev)
-{
-	int ret;
-	struct ofnode_phandle_args args;
+	plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
+			   val == REG_SUBTYPE_GPIO_MV;
 
+	/*
+	 * Parse basic GPIO count specified via the gpio-ranges property
+	 * as specified in upstream devicetrees
+	 */
 	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
 					     NULL, 3, 0, &args);
 	if (ret)
 		return log_msg_ret("gpio-ranges", ret);
 
-	return args.args[2];
-}
-
-static int qcom_gpio_of_to_plat(struct udevice *dev)
-{
-	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-	int ret;
-
-	ret = qcom_gpio_of_parse_ranges(dev);
-	if (ret > 0)
-		uc_priv->gpio_count = ret;
-	else
-		return ret;
+	plat->pin_count = args.args[2];
 
+	uc_priv->gpio_count = plat->pin_count;
 	uc_priv->bank_name = "pmic";
 
 	return 0;
@@ -327,9 +356,75 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = {
 	.name	= "qcom_pmic_gpio",
 	.id	= UCLASS_GPIO,
 	.of_match = qcom_gpio_ids,
-	.of_to_plat = qcom_gpio_of_to_plat,
-	.probe	= qcom_gpio_probe,
+	.bind	= qcom_gpio_bind,
+	.probe = qcom_gpio_probe,
 	.ops	= &qcom_gpio_ops,
-	.priv_auto	= sizeof(struct qcom_gpio_bank),
+	.plat_auto = sizeof(struct qcom_pmic_gpio_data),
+	.flags = DM_FLAG_ALLOC_PDATA,
 };
 
+static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
+	{ "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
+	{ "output-low", PIN_CONFIG_OUTPUT, 0 },
+};
+
+static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
+{
+	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+
+	return plat->pin_count;
+}
+
+static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+	static char name[8];
+
+	/* DT indexes from 1 */
+	snprintf(name, sizeof(name), "gpio%u", selector + 1);
+
+	return name;
+}
+
+static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
+					 unsigned int param, unsigned int arg)
+{
+	/* We only support configuring the pin as an output, either low or high */
+	return _qcom_gpio_set_direction(dev, selector, false,
+					param == PIN_CONFIG_OUTPUT_ENABLE);
+}
+
+static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector)
+{
+	if (!selector)
+		return "normal";
+	return NULL;
+}
+
+static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
+{
+	return 1;
+}
+
+static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
+						    unsigned int func_selector)
+{
+	return 0;
+}
+
+struct pinctrl_ops qcom_pmic_pinctrl_ops = {
+	.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
+	.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
+	.set_state = pinctrl_generic_set_state,
+	.pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
+	.pinconf_params = qcom_pmic_pinctrl_conf_params,
+	.pinconf_set = qcom_pmic_pinctrl_pinconf_set,
+	.get_function_name = qcom_pmic_pinctrl_get_function_name,
+	.get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
+	.pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
+};
+
+U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
+	.name	= "qcom_pmic_pinctrl",
+	.id	= UCLASS_PINCTRL,
+	.ops	= &qcom_pmic_pinctrl_ops,
+};

-- 
2.43.1

[PATCH v4 12/39] sandbox: dts: fix qcom pmic gpio

[Caleb Connolly]

Adjust the DT to match upstream bindings.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/sandbox/dts/sandbox.dtsi | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index 241f397ba6e7..c93ce7128942 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -419,17 +419,16 @@
 		#size-cells = <0x1>;
 		pm8916@0 {
 			compatible = "qcom,spmi-pmic";
-			reg = <0x0 0x1>;
+			reg = <0x0 0x0>;
 			#address-cells = <0x1>;
-			#size-cells = <0x1>;
+			#size-cells = <0x0>;
 
 			spmi_gpios: gpios@c000 {
 				compatible = "qcom,pm8916-gpio";
-				reg = <0xc000 0x400>;
+				reg = <0xc000>;
 				gpio-controller;
-				gpio-count = <4>;
+				gpio-ranges = <&spmi_gpios 0 0 4>;
 				#gpio-cells = <2>;
-				gpio-bank-name="spmi";
 			};
 		};
 	};

-- 
2.43.1

[PATCH v4 13/39] pinctrl: qcom: stub support for special GPIOs

[Caleb Connolly]

Most platforms have a handful of "special" GPIOs, like the MMC
clock/data lanes, UFS reset, etc. These don't follow the usually naming
scheme of "gpioX" and also have unique capabilities and registers. We
can get away without supporting them all for now, but DT compatibility
is still an issue.

Add support for allowing these to be specified after the other pins, and
make all pinmux/pinconf calls for them nop.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/mach-snapdragon/include/mach/gpio.h |  2 ++
 drivers/gpio/msm_gpio.c                      | 20 ++++++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-qcom.c          | 12 ++++++++++++
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
index 8dac62f870b9..c373f5a4cf3d 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -13,6 +13,8 @@
 struct msm_pin_data {
 	int pin_count;
 	const unsigned int *pin_offsets;
+	/* Index of first special pin, these are ignored for now */
+	unsigned int special_pins_start;
 };
 
 static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 80cd28bb231f..8a5e8730e911 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
 {
 	struct msm_gpio_bank *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (gpio >= priv->pin_data->special_pins_start)
+		return 0;
+
 	/* Disable OE bit */
 	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
 			GPIO_OE_MASK, GPIO_OE_DISABLE);
@@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
 {
 	struct msm_gpio_bank *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (gpio >= priv->pin_data->special_pins_start)
+		return 0;
+
 	value = !!value;
 	/* set value */
 	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
 {
 	struct msm_gpio_bank *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (gpio >= priv->pin_data->special_pins_start)
+		return 0;
+
 	value = !!value;
 	/* set value */
 	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
 {
 	struct msm_gpio_bank *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (gpio >= priv->pin_data->special_pins_start)
+		return 0;
+
 	return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
 }
 
@@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
 {
 	struct msm_gpio_bank *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (gpio >= priv->pin_data->special_pins_start)
+		return 0;
+
 	if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
 		return GPIOF_OUTPUT;
 
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index dc3d8c4d9034..1ea4d21c41fc 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -83,6 +83,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 {
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins, assume they're in the correct state */
+	if (pin_selector >= priv->data->pin_data.special_pins_start)
+		return 0;
+
 	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
 			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
 			priv->data->get_function_mux(func_selector) << 2);
@@ -94,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 {
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
+	/* Always NOP for special pins */
+	if (pin_selector >= priv->data->pin_data.special_pins_start)
+		return 0;
+
 	switch (param) {
 	case PIN_CONFIG_DRIVE_STRENGTH:
 		argument = (argument / 2) - 1;
@@ -136,6 +144,10 @@ int msm_pinctrl_bind(struct udevice *dev)
 	const char *name;
 	int ret;
 
+	/* Make sure we don't indadvertently treat all pins as special pins. */
+	if (!data->pin_data.special_pins_start)
+		data->pin_data.special_pins_start = data->pin_data.pin_count;
+
 	drv = lists_driver_lookup_name("pinctrl_qcom");
 	if (!drv)
 		return -ENOENT;

-- 
2.43.1

[PATCH v4 14/39] pinctrl: qcom: fix DT compatibility

[Caleb Connolly]

Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
for SoCs where we're now using upstream DT.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/pinctrl/qcom/pinctrl-apq8016.c | 26 +++++++--------
 drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +++++-----
 drivers/pinctrl/qcom/pinctrl-qcs404.c  | 58 ++++++++++++++++++++++++++++------
 3 files changed, 69 insertions(+), 31 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 8149ffd83cc4..10796710ba7a 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -14,18 +14,18 @@
 #define MAX_PIN_NAME_LEN 32
 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
 static const char * const msm_pinctrl_pins[] = {
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
-	"QDSD_CLK",
-	"QDSD_CMD",
-	"QDSD_DATA0",
-	"QDSD_DATA1",
-	"QDSD_DATA2",
-	"QDSD_DATA3",
+	"sdc1_clk",
+	"sdc1_cmd",
+	"sdc1_data",
+	"sdc2_clk",
+	"sdc2_cmd",
+	"sdc2_data",
+	"qdsd_clk",
+	"qdsd_cmd",
+	"qdsd_data0",
+	"qdsd_data1",
+	"qdsd_data2",
+	"qdsd_data3",
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
@@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
 					unsigned int selector)
 {
 	if (selector < 122) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
 		return pin_name;
 	} else {
 		return msm_pinctrl_pins[selector - 122];
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index d64ab1ff7bee..f2eeb4cf469a 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -14,13 +14,13 @@
 #define MAX_PIN_NAME_LEN 32
 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
 static const char * const msm_pinctrl_pins[] = {
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
-	"SDC1_RCLK",
+	"sdc1_clk",
+	"sdc1_cmd",
+	"sdc1_data",
+	"sdc2_clk",
+	"sdc2_cmd",
+	"sdc2_data",
+	"sdc1_rclk",
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
@@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
 					unsigned int selector)
 {
 	if (selector < 150) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
 		return pin_name;
 	} else {
 		return msm_pinctrl_pins[selector - 150];
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index ac00afa2a1f4..5066f2bba6b3 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -10,20 +10,24 @@
 
 #include "pinctrl-qcom.h"
 
+#define NORTH	0x00300000
+#define SOUTH	0x00000000
+#define EAST	0x06b00000
+
 #define MAX_PIN_NAME_LEN 32
 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
 static const char * const msm_pinctrl_pins[] = {
-	"SDC1_RCLK",
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
+	"sdc1_rclk",
+	"sdc1_clk",
+	"sdc1_cmd",
+	"sdc1_data",
+	"sdc2_clk",
+	"sdc2_cmd",
+	"sdc2_data",
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"blsp_uart2", 1},
+	{"gpio", 0},
 	{"rgmii_int", 1},
 	{"rgmii_ck", 1},
 	{"rgmii_tx", 1},
@@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
 	{"blsp_i2c_scl_a2", 3},
 	{"blsp_i2c3", 2},
 	{"blsp_i2c4", 1},
+	{"blsp_uart_tx_a2", 1},
+	{"blsp_uart_rx_a2", 1},
+};
+
+static const unsigned int qcs404_pin_offsets[] = {
+	[0] = SOUTH,    [1] = SOUTH,    [2] = SOUTH,    [3] = SOUTH,    [4] = SOUTH,
+	[5] = SOUTH,   [6] = SOUTH,   [7] = SOUTH,   [8] = SOUTH,    [9] = SOUTH,
+	[10] = SOUTH,   [11] = SOUTH,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
+	[15] = SOUTH,  [16] = SOUTH,  [17] = NORTH,  [18] = NORTH,  [19] = NORTH,
+	[20] = NORTH,  [21] = SOUTH,  [22] = NORTH,  [23] = NORTH,  [24] = NORTH,
+	[25] = NORTH,  [26] = EAST,  [27] = EAST,   [28] = EAST,   [29] = EAST,
+	[30] = NORTH,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = SOUTH,
+	[35] = SOUTH,  [36] = NORTH,  [37] = NORTH,  [38] = NORTH,  [39] = EAST,
+	[40] = EAST,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
+	[45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = EAST,
+	[50] = EAST,  [51] = EAST,  [52] = EAST,  [53] = EAST,  [54] = EAST,
+	[55] = EAST,  [56] = EAST,  [57] = EAST,  [58] = EAST,  [59] = EAST,
+	[60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
+	[65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = NORTH,
+	[70] = NORTH,   [71] = NORTH,   [72] = NORTH,   [73] = NORTH,   [74] = NORTH,
+	[75] = NORTH,   [76] = NORTH,   [77] = NORTH,   [78] = EAST,   [79] = EAST,
+	[80] = EAST,  [81] = EAST,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
+	[85] = NORTH,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = EAST,
+	[90] = EAST,  [91] = EAST,  [92] = EAST,  [93] = EAST,  [94] = EAST,
+	[95] = EAST,  [96] = EAST,  [97] = EAST,  [98] = EAST,  [99] = EAST,
+	[100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST,
+	[105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST,
+	[110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST,
+	[115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST,
+	/*
+	 * There's 126 pins but the last ones are special and have non-standard registers
+	 * so we leave them out here. The pinctrl and GPIO drivers both currently ignore
+	 * these pins.
+	 */
 };
 
 static const char *qcs404_get_function_name(struct udevice *dev,
@@ -49,7 +87,7 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
 				       unsigned int selector)
 {
 	if (selector < 120) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
 		return pin_name;
 	} else {
 		return msm_pinctrl_pins[selector - 120];
@@ -62,7 +100,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector)
 }
 
 static struct msm_pinctrl_data qcs404_data = {
-	.pin_data = { .pin_count = 126, },
+	.pin_data = { .pin_count = 126, .pin_offsets = qcs404_pin_offsets, .special_pins_start = 120, },
 	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
 	.get_function_name = qcs404_get_function_name,
 	.get_function_mux = qcs404_get_function_mux,

-- 
2.43.1

[PATCH v4 15/39] pinctrl: qcom: apq8016: init pre-reloaction

[Caleb Connolly]

On the DB410c we support running as a first stage bootloader. This
requires initialising the GPIOs which are muxed to UART before they can
be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
that we do this early enough.

This is required to prevent the first few lines of UART log from being
dropped.

Reported-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 10796710ba7a..df5bd1c19f6e 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -73,4 +73,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
 	.of_match	= msm_pinctrl_ids,
 	.ops		= &msm_pinctrl_ops,
 	.bind		= msm_pinctrl_bind,
+	.flags		= DM_FLAG_PRE_RELOC,
 };

-- 
2.43.1

[PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment

[Caleb Connolly]

Add a config fragment for building U-Boot such that it can be
chainloaded by aboot/LK rather than being flashed directly to the aboot
partition.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config
new file mode 100644
index 000000000000..3fd064924a1f
--- /dev/null
+++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config
@@ -0,0 +1,7 @@
+# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
+CONFIG_TEXT_BASE=0x0
+# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set
+# CONFIG_REMAKE_ELF is not set
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_INIT_SP_RELATIVE=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=524288

-- 
2.43.1

[PATCH v4 17/39] board: dragonboard410c: upstream DT compat

[Caleb Connolly]

Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.

Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.

This prepares us to switch to upstream DT in a future patch.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/dragonboard410c.dts                 |  25 +++-
 board/qualcomm/dragonboard410c/dragonboard410c.c |  93 +++---------
 doc/device-tree-bindings/usb/ehci-msm.txt        |  10 --
 drivers/clk/qcom/clock-apq8016.c                 |   7 +-
 drivers/phy/qcom/msm8916-usbh-phy.c              |   4 +-
 drivers/pinctrl/qcom/pinctrl-apq8016.c           |   2 +-
 drivers/usb/host/ehci-msm.c                      |  22 ++-
 include/dt-bindings/clock/qcom,gcc-msm8916.h     | 179 +++++++++++++++++++++++
 8 files changed, 246 insertions(+), 96 deletions(-)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index c395e6cc0427..453642b25705 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -12,7 +12,7 @@
 
 / {
 	model = "Qualcomm Technologies, Inc. Dragonboard 410c";
-	compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+	compatible = "qcom,apq8016-sbc", "qcom,apq8016";
 	qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
 	qcom,board-id = <0x10018 0x0>;
 	#address-cells = <0x2>;
@@ -79,6 +79,7 @@
 			reg = <0x1800000 0x80000>;
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
+			#clock-cells = <0x1>;
 		};
 
 		serial@78b0000 {
@@ -91,15 +92,25 @@
 		};
 
 		ehci@78d9000 {
-			compatible = "qcom,ehci-host";
+			compatible = "qcom,ci-hdrc";
 			reg = <0x78d9000 0x400>;
 			phys = <&ehci_phy>;
-		};
 
-		ehci_phy: ehci_phy@78d9000 {
-			compatible = "qcom,apq8016-usbphy";
-			reg = <0x78d9000 0x400>;
-			#phy-cells = <0>;
+			ulpi {
+				usb_hs_phy: phy {
+					compatible = "qcom,usb-hs-phy-msm8916",
+						     "qcom,usb-hs-phy";
+					#phy-cells = <0>;
+					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+					clock-names = "ref", "sleep";
+					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
+					reset-names = "phy", "por";
+					qcom,init-seq = /bits/ 8 <0x0 0x44>,
+								 <0x1 0x6b>,
+								 <0x2 0x24>,
+								 <0x3 0x13>;
+				};
+			};
 		};
 
 		sdhci@07824000 {
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 350e0e9e20aa..1adac07569ae 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
+#include <dm/pinctrl.h>
 #include <env.h>
 #include <init.h>
 #include <net.h>
@@ -23,84 +24,32 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
+#define USB_HUB_RESET_GPIO 2
+#define USB_SW_SELECT_GPIO 3
 
 int board_usb_init(int index, enum usb_init_type init)
 {
-	static struct udevice *pmic_gpio;
-	static struct gpio_desc hub_reset, usb_sel;
-	int ret = 0, node;
+	struct udevice *usb;
+	int ret = 0;
 
-	if (!pmic_gpio) {
-		ret = uclass_get_device_by_name(UCLASS_GPIO,
-						"pm8916_gpios@c000",
-						&pmic_gpio);
-		if (ret < 0) {
-			printf("Failed to find pm8916_gpios@c000 node.\n");
-			return ret;
-		}
+	/* USB device */
+	ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
+	if (ret) {
+		printf("Cannot find USB device\n");
+		return ret;
 	}
 
-	/* Try to request gpios needed to start usb host on dragonboard */
-	if (!dm_gpio_is_valid(&hub_reset)) {
-		node = fdt_subnode_offset(gd->fdt_blob,
-					  dev_of_offset(pmic_gpio),
-					  "usb_hub_reset_pm");
-		if (node < 0) {
-			printf("Failed to find usb_hub_reset_pm dt node.\n");
-			return node;
-		}
-		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
-						 "gpios", 0, &hub_reset, 0);
-		if (ret < 0) {
-			printf("Failed to request usb_hub_reset_pm gpio.\n");
-			return ret;
-		}
-	}
-
-	if (!dm_gpio_is_valid(&usb_sel)) {
-		node = fdt_subnode_offset(gd->fdt_blob,
-					  dev_of_offset(pmic_gpio),
-					  "usb_sw_sel_pm");
-		if (node < 0) {
-			printf("Failed to find usb_sw_sel_pm dt node.\n");
-			return 0;
-		}
-		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
-						 "gpios", 0, &usb_sel, 0);
-		if (ret < 0) {
-			printf("Failed to request usb_sw_sel_pm gpio.\n");
-			return ret;
-		}
-	}
-
-	if (init == USB_INIT_HOST) {
-		/* Start USB Hub */
-		dm_gpio_set_dir_flags(&hub_reset,
-				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-		mdelay(100);
-		/* Switch usb to host connectors */
-		dm_gpio_set_dir_flags(&usb_sel,
-				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-		mdelay(100);
-	} else { /* Device */
-		/* Disable hub */
-		dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
-		/* Switch back to device connector */
-		dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
+	/* Select "default" or "device" pinctrl */
+	switch (init) {
+	case USB_INIT_HOST:
+		pinctrl_select_state(usb, "default");
+		break;
+	case USB_INIT_DEVICE:
+		pinctrl_select_state(usb, "device");
+		break;
+	default:
+		debug("Unknown usb_init_type %d\n", init);
+		break;
 	}
 
 	return 0;
diff --git a/doc/device-tree-bindings/usb/ehci-msm.txt b/doc/device-tree-bindings/usb/ehci-msm.txt
deleted file mode 100644
index 205bb07220fb..000000000000
--- a/doc/device-tree-bindings/usb/ehci-msm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
-
-Required properties:
-- compatible: must be "qcom,ehci-host"
-- reg: start address and size of the registers
-
-ehci@78d9000 {
-	compatible = "qcom,ehci-host";
-	reg = <0x78d9000 0x400>;
-};
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 0af7191cff52..9de0ad5ed32d 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -13,6 +13,7 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
 
 #include "clock-qcom.h"
 
@@ -125,13 +126,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case 0: /* SDC1 */
+	case GCC_SDCC1_APPS_CLK: /* SDC1 */
 		return clk_init_sdc(priv, 0, rate);
 		break;
-	case 1: /* SDC2 */
+	case GCC_SDCC2_APPS_CLK: /* SDC2 */
 		return clk_init_sdc(priv, 1, rate);
 		break;
-	case 4: /* UART2 */
+	case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
 		return clk_init_uart(priv);
 		break;
 	default:
diff --git a/drivers/phy/qcom/msm8916-usbh-phy.c b/drivers/phy/qcom/msm8916-usbh-phy.c
index 7c9d030a4d8a..f52046f7cb02 100644
--- a/drivers/phy/qcom/msm8916-usbh-phy.c
+++ b/drivers/phy/qcom/msm8916-usbh-phy.c
@@ -74,7 +74,7 @@ static int msm_phy_probe(struct udevice *dev)
 {
 	struct msm_phy_priv *priv = dev_get_priv(dev);
 
-	priv->regs = dev_remap_addr(dev);
+	priv->regs = dev_remap_addr(dev_get_parent(dev));
 	if (!priv->regs)
 		return -EINVAL;
 
@@ -96,7 +96,7 @@ static struct phy_ops msm_phy_ops = {
 };
 
 static const struct udevice_id msm_phy_ids[] = {
-	{ .compatible = "qcom,apq8016-usbphy" },
+	{ .compatible = "qcom,usb-hs-phy-msm8916" },
 	{ }
 };
 
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index df5bd1c19f6e..c8f4eeae6082 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,7 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"blsp1_uart", 2},
+	{"blsp_uart2", 2},
 };
 
 static const char *apq8016_get_function_name(struct udevice *dev,
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index dd0d153500cb..98fe7bc3bcb1 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/lists.h>
 #include <errno.h>
 #include <usb.h>
 #include <usb/ehci-ci.h>
@@ -119,6 +120,24 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+static int ehci_usb_of_bind(struct udevice *dev)
+{
+	ofnode ulpi_node = ofnode_first_subnode(dev_ofnode(dev));
+	ofnode phy_node;
+
+	if (!ofnode_valid(ulpi_node))
+		return 0;
+
+	phy_node = ofnode_first_subnode(ulpi_node);
+	if (!ofnode_valid(phy_node)) {
+		printf("%s: ulpi subnode with no phy\n", __func__);
+		return -ENOENT;
+	}
+
+	return device_bind_driver_to_node(dev, "msm8916_usbphy", "msm8916_usbphy",
+					  phy_node, NULL);
+}
+
 #if defined(CONFIG_CI_UDC)
 /* Little quirk that MSM needs with Chipidea controller
  * Must reinit phy after reset
@@ -132,7 +151,7 @@ void ci_init_after_reset(struct ehci_ctrl *ctrl)
 #endif
 
 static const struct udevice_id ehci_usb_ids[] = {
-	{ .compatible = "qcom,ehci-host", },
+	{ .compatible = "qcom,ci-hdrc", },
 	{ }
 };
 
@@ -141,6 +160,7 @@ U_BOOT_DRIVER(usb_ehci) = {
 	.id	= UCLASS_USB,
 	.of_match = ehci_usb_ids,
 	.of_to_plat = ehci_usb_of_to_plat,
+	.bind = ehci_usb_of_bind,
 	.probe = ehci_usb_probe,
 	.remove = ehci_usb_remove,
 	.ops	= &ehci_usb_ops,
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..563034406184
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2015 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
+
+#define GPLL0					0
+#define GPLL0_VOTE				1
+#define BIMC_PLL				2
+#define BIMC_PLL_VOTE				3
+#define GPLL1					4
+#define GPLL1_VOTE				5
+#define GPLL2					6
+#define GPLL2_VOTE				7
+#define PCNOC_BFDCD_CLK_SRC			8
+#define SYSTEM_NOC_BFDCD_CLK_SRC		9
+#define CAMSS_AHB_CLK_SRC			10
+#define APSS_AHB_CLK_SRC			11
+#define CSI0_CLK_SRC				12
+#define CSI1_CLK_SRC				13
+#define GFX3D_CLK_SRC				14
+#define VFE0_CLK_SRC				15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC		16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC		17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC		18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC		19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC		20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC		21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC		22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC		23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC		24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC		25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC		26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC		27
+#define BLSP1_UART1_APPS_CLK_SRC		28
+#define BLSP1_UART2_APPS_CLK_SRC		29
+#define CCI_CLK_SRC				30
+#define CAMSS_GP0_CLK_SRC			31
+#define CAMSS_GP1_CLK_SRC			32
+#define JPEG0_CLK_SRC				33
+#define MCLK0_CLK_SRC				34
+#define MCLK1_CLK_SRC				35
+#define CSI0PHYTIMER_CLK_SRC			36
+#define CSI1PHYTIMER_CLK_SRC			37
+#define CPP_CLK_SRC				38
+#define CRYPTO_CLK_SRC				39
+#define GP1_CLK_SRC				40
+#define GP2_CLK_SRC				41
+#define GP3_CLK_SRC				42
+#define BYTE0_CLK_SRC				43
+#define ESC0_CLK_SRC				44
+#define MDP_CLK_SRC				45
+#define PCLK0_CLK_SRC				46
+#define VSYNC_CLK_SRC				47
+#define PDM2_CLK_SRC				48
+#define SDCC1_APPS_CLK_SRC			49
+#define SDCC2_APPS_CLK_SRC			50
+#define APSS_TCU_CLK_SRC			51
+#define USB_HS_SYSTEM_CLK_SRC			52
+#define VCODEC0_CLK_SRC				53
+#define GCC_BLSP1_AHB_CLK			54
+#define GCC_BLSP1_SLEEP_CLK			55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK		56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK		57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK		58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK		59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK		60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK		61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK		62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK		63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK		64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK		65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK		66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK		67
+#define GCC_BLSP1_UART1_APPS_CLK		68
+#define GCC_BLSP1_UART2_APPS_CLK		69
+#define GCC_BOOT_ROM_AHB_CLK			70
+#define GCC_CAMSS_CCI_AHB_CLK			71
+#define GCC_CAMSS_CCI_CLK			72
+#define GCC_CAMSS_CSI0_AHB_CLK			73
+#define GCC_CAMSS_CSI0_CLK			74
+#define GCC_CAMSS_CSI0PHY_CLK			75
+#define GCC_CAMSS_CSI0PIX_CLK			76
+#define GCC_CAMSS_CSI0RDI_CLK			77
+#define GCC_CAMSS_CSI1_AHB_CLK			78
+#define GCC_CAMSS_CSI1_CLK			79
+#define GCC_CAMSS_CSI1PHY_CLK			80
+#define GCC_CAMSS_CSI1PIX_CLK			81
+#define GCC_CAMSS_CSI1RDI_CLK			82
+#define GCC_CAMSS_CSI_VFE0_CLK			83
+#define GCC_CAMSS_GP0_CLK			84
+#define GCC_CAMSS_GP1_CLK			85
+#define GCC_CAMSS_ISPIF_AHB_CLK			86
+#define GCC_CAMSS_JPEG0_CLK			87
+#define GCC_CAMSS_JPEG_AHB_CLK			88
+#define GCC_CAMSS_JPEG_AXI_CLK			89
+#define GCC_CAMSS_MCLK0_CLK			90
+#define GCC_CAMSS_MCLK1_CLK			91
+#define GCC_CAMSS_MICRO_AHB_CLK			92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK		93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK		94
+#define GCC_CAMSS_AHB_CLK			95
+#define GCC_CAMSS_TOP_AHB_CLK			96
+#define GCC_CAMSS_CPP_AHB_CLK			97
+#define GCC_CAMSS_CPP_CLK			98
+#define GCC_CAMSS_VFE0_CLK			99
+#define GCC_CAMSS_VFE_AHB_CLK			100
+#define GCC_CAMSS_VFE_AXI_CLK			101
+#define GCC_CRYPTO_AHB_CLK			102
+#define GCC_CRYPTO_AXI_CLK			103
+#define GCC_CRYPTO_CLK				104
+#define GCC_OXILI_GMEM_CLK			105
+#define GCC_GP1_CLK				106
+#define GCC_GP2_CLK				107
+#define GCC_GP3_CLK				108
+#define GCC_MDSS_AHB_CLK			109
+#define GCC_MDSS_AXI_CLK			110
+#define GCC_MDSS_BYTE0_CLK			111
+#define GCC_MDSS_ESC0_CLK			112
+#define GCC_MDSS_MDP_CLK			113
+#define GCC_MDSS_PCLK0_CLK			114
+#define GCC_MDSS_VSYNC_CLK			115
+#define GCC_MSS_CFG_AHB_CLK			116
+#define GCC_OXILI_AHB_CLK			117
+#define GCC_OXILI_GFX3D_CLK			118
+#define GCC_PDM2_CLK				119
+#define GCC_PDM_AHB_CLK				120
+#define GCC_PRNG_AHB_CLK			121
+#define GCC_SDCC1_AHB_CLK			122
+#define GCC_SDCC1_APPS_CLK			123
+#define GCC_SDCC2_AHB_CLK			124
+#define GCC_SDCC2_APPS_CLK			125
+#define GCC_GTCU_AHB_CLK			126
+#define GCC_JPEG_TBU_CLK			127
+#define GCC_MDP_TBU_CLK				128
+#define GCC_SMMU_CFG_CLK			129
+#define GCC_VENUS_TBU_CLK			130
+#define GCC_VFE_TBU_CLK				131
+#define GCC_USB2A_PHY_SLEEP_CLK			132
+#define GCC_USB_HS_AHB_CLK			133
+#define GCC_USB_HS_SYSTEM_CLK			134
+#define GCC_VENUS0_AHB_CLK			135
+#define GCC_VENUS0_AXI_CLK			136
+#define GCC_VENUS0_VCODEC0_CLK			137
+#define BIMC_DDR_CLK_SRC			138
+#define GCC_APSS_TCU_CLK			139
+#define GCC_GFX_TCU_CLK				140
+#define BIMC_GPU_CLK_SRC			141
+#define GCC_BIMC_GFX_CLK			142
+#define GCC_BIMC_GPU_CLK			143
+#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC		144
+#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC		145
+#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC		146
+#define ULTAUDIO_XO_CLK_SRC			147
+#define ULTAUDIO_AHBFABRIC_CLK_SRC		148
+#define CODEC_DIGCODEC_CLK_SRC			149
+#define GCC_ULTAUDIO_PCNOC_MPORT_CLK		150
+#define GCC_ULTAUDIO_PCNOC_SWAY_CLK		151
+#define GCC_ULTAUDIO_AVSYNC_XO_CLK		152
+#define GCC_ULTAUDIO_STC_XO_CLK			153
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK	154
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK	155
+#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK		156
+#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK		157
+#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK		158
+#define GCC_CODEC_DIGCODEC_CLK			159
+#define GCC_MSS_Q6_BIMC_AXI_CLK			160
+
+/* Indexes for GDSCs */
+#define BIMC_GDSC				0
+#define VENUS_GDSC				1
+#define MDSS_GDSC				2
+#define JPEG_GDSC				3
+#define VFE_GDSC				4
+#define OXILI_GDSC				5
+
+#endif

-- 
2.43.1

[PATCH v4 18/39] board: dragonboard410c: import board code from mach-snapdragon

[Caleb Connolly]

Some of the db410c board support code was written to be generic and
placed in mach-snapdragon. However, as the db410c is the only board
using this, move the code out of mach-snapdragon. This makes is more
obvious what code is relevant for which targets and helps tidy things up
a little more.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/mach-snapdragon/Makefile                |  2 -
 arch/arm/mach-snapdragon/dram.c                  | 99 ------------------------
 arch/arm/mach-snapdragon/include/mach/dram.h     | 12 ---
 arch/arm/mach-snapdragon/include/mach/misc.h     | 13 ----
 arch/arm/mach-snapdragon/misc.c                  | 55 -------------
 board/qualcomm/dragonboard410c/Makefile          |  2 +-
 board/qualcomm/dragonboard410c/dragonboard410c.c | 48 +++++++++++-
 7 files changed, 45 insertions(+), 186 deletions(-)

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 3a3a297c1768..d02432df8b04 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,6 +6,4 @@ obj-$(CONFIG_SDM845) += sysmap-sdm845.o
 obj-$(CONFIG_SDM845) += init_sdm845.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-y += misc.o
-obj-y += dram.o
 obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
deleted file mode 100644
index 499dfdf0da6e..000000000000
--- a/arch/arm/mach-snapdragon/dram.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Onboard memory detection for Snapdragon boards
- *
- * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
- *
- */
-
-#include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <part.h>
-#include <smem.h>
-#include <fdt_support.h>
-#include <asm/arch/dram.h>
-
-#define SMEM_USABLE_RAM_PARTITION_TABLE 402
-#define RAM_PART_NAME_LENGTH            16
-#define RAM_NUM_PART_ENTRIES            32
-#define CATEGORY_SDRAM 0x0E
-#define TYPE_SYSMEM 0x01
-
-struct smem_ram_ptable_hdr {
-	u32 magic[2];
-	u32 version;
-	u32 reserved;
-	u32 len;
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptn {
-	char name[RAM_PART_NAME_LENGTH];
-	u64 start;
-	u64 size;
-	u32 attr;
-	u32 category;
-	u32 domain;
-	u32 type;
-	u32 num_partitions;
-	u32 reserved[3];
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptable {
-	struct smem_ram_ptable_hdr hdr;
-	u32 reserved;     /* Added for 8 bytes alignment of header */
-	struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
-} __attribute__ ((__packed__));
-
-#ifndef MEMORY_BANKS_MAX
-#define MEMORY_BANKS_MAX 4
-#endif
-
-int msm_fixup_memory(void *blob)
-{
-	u64 bank_start[MEMORY_BANKS_MAX];
-	u64 bank_size[MEMORY_BANKS_MAX];
-	size_t size;
-	int i;
-	int count = 0;
-	struct udevice *smem;
-	int ret;
-	struct smem_ram_ptable *ram_ptable;
-	struct smem_ram_ptn *p;
-
-	ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem);
-	if (ret < 0) {
-		printf("Failed to find SMEM node. Check device tree\n");
-		return 0;
-	}
-
-	ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size);
-
-	if (!ram_ptable) {
-		printf("Failed to find SMEM partition.\n");
-		return -ENODEV;
-	}
-
-	/* Check validy of RAM */
-	for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
-		p = &ram_ptable->parts[i];
-		if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
-			bank_start[count] = p->start;
-			bank_size[count] = p->size;
-			debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n",
-					count, p->start, p->size);
-			count++;
-		}
-	}
-
-	if (!count) {
-		printf("Failed to detect any memory bank\n");
-		return -ENODEV;
-	}
-
-	ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h b/arch/arm/mach-snapdragon/include/mach/dram.h
deleted file mode 100644
index 0a9eedda414c..000000000000
--- a/arch/arm/mach-snapdragon/include/mach/dram.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
- * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
- */
-
-#ifndef DRAM_H
-#define DRAM_H
-
-int msm_fixup_memory(void *blob);
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/misc.h b/arch/arm/mach-snapdragon/include/mach/misc.h
deleted file mode 100644
index c60e3e472470..000000000000
--- a/arch/arm/mach-snapdragon/include/mach/misc.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
- * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
- */
-
-#ifndef MISC_H
-#define MISC_H
-
-u32 msm_board_serial(void);
-void msm_generate_mac_addr(u8 *mac);
-
-#endif
diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c
deleted file mode 100644
index 7d452f4529b7..000000000000
--- a/arch/arm/mach-snapdragon/misc.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Miscellaneous Snapdragon functionality
- *
- * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
- *
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <asm/arch/misc.h>
-#include <asm/unaligned.h>
-
-/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
-#define UNSTUFF_BITS(resp, start, size) \
-	({ \
-		const int __size = size; \
-		const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1;	\
-		const int __off = 3 - ((start) / 32); \
-		const int __shft = (start) & 31; \
-		u32 __res; \
-					\
-		__res = resp[__off] >> __shft; \
-		if (__size + __shft > 32) \
-			__res |= resp[__off - 1] << ((32 - __shft) % 32); \
-		__res & __mask;	\
-	})
-
-u32 msm_board_serial(void)
-{
-	struct mmc *mmc_dev;
-
-	mmc_dev = find_mmc_device(0);
-	if (!mmc_dev)
-		return 0;
-
-	if (mmc_init(mmc_dev))
-		return 0;
-
-	return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
-}
-
-void msm_generate_mac_addr(u8 *mac)
-{
-	/* use locally adminstrated pool */
-	mac[0] = 0x02;
-	mac[1] = 0x00;
-
-	/*
-	 * Put the 32-bit serial number in the last 32-bit of the MAC address.
-	 * Use big endian order so it is consistent with the serial number
-	 * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
-	 */
-	put_unaligned_be32(msm_board_serial(), &mac[2]);
-}
diff --git a/board/qualcomm/dragonboard410c/Makefile b/board/qualcomm/dragonboard410c/Makefile
index 1b99c8b0efef..189f83813325 100644
--- a/board/qualcomm/dragonboard410c/Makefile
+++ b/board/qualcomm/dragonboard410c/Makefile
@@ -2,4 +2,4 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
-obj-y	:= dragonboard410c.o
+obj-y := dragonboard410c.o
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 1adac07569ae..40b5448c6ef1 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -12,14 +12,13 @@
 #include <dm/pinctrl.h>
 #include <env.h>
 #include <init.h>
+#include <mmc.h>
 #include <net.h>
 #include <usb.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <fdt_support.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/misc.h>
 #include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +54,49 @@ int board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
+/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
+#define UNSTUFF_BITS(resp, start, size) \
+	({ \
+		const int __size = size; \
+		const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1;	\
+		const int __off = 3 - ((start) / 32); \
+		const int __shft = (start) & 31; \
+		u32 __res; \
+					\
+		__res = resp[__off] >> __shft; \
+		if (__size + __shft > 32) \
+			__res |= resp[__off - 1] << ((32 - __shft) % 32); \
+		__res & __mask;	\
+	})
+
+static u32 msm_board_serial(void)
+{
+	struct mmc *mmc_dev;
+
+	mmc_dev = find_mmc_device(0);
+	if (!mmc_dev)
+		return 0;
+
+	if (mmc_init(mmc_dev))
+		return 0;
+
+	return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
+}
+
+static void msm_generate_mac_addr(u8 *mac)
+{
+	/* use locally adminstrated pool */
+	mac[0] = 0x02;
+	mac[1] = 0x00;
+
+	/*
+	 * Put the 32-bit serial number in the last 32-bit of the MAC address.
+	 * Use big endian order so it is consistent with the serial number
+	 * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
+	 */
+	put_unaligned_be32(msm_board_serial(), &mac[2]);
+}
+
 /* Check for vol- button - if pressed - stop autoboot */
 int misc_init_r(void)
 {
@@ -103,8 +145,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	u8 mac[ARP_HLEN];
 
-	msm_fixup_memory(blob);
-
 	if (!eth_env_get_enetaddr("wlanaddr", mac)) {
 		msm_generate_mac_addr(mac);
 	};

-- 
2.43.1

[PATCH v4 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER

[Caleb Connolly]

db820c predated support for prepending the kernel image header
automatically, drop it's custom linker script and head.S in favour of
this generic support.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/mach-snapdragon/Kconfig          |   1 +
 board/qualcomm/dragonboard820c/Makefile   |   1 -
 board/qualcomm/dragonboard820c/head.S     |  33 ---------
 board/qualcomm/dragonboard820c/u-boot.lds | 111 ------------------------------
 4 files changed, 1 insertion(+), 145 deletions(-)

diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index ad6671081910..f897c393464f 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C
 
 config TARGET_DRAGONBOARD820C
 	bool "96Boards Dragonboard 820C"
+	select LINUX_KERNEL_IMAGE_HEADER
 	imply CLK_QCOM_APQ8096
 	imply PINCTRL_QCOM_APQ8096
 	imply BUTTON_QCOM_PMIC
diff --git a/board/qualcomm/dragonboard820c/Makefile b/board/qualcomm/dragonboard820c/Makefile
index 643311f5b3ba..2ae6d16364aa 100644
--- a/board/qualcomm/dragonboard820c/Makefile
+++ b/board/qualcomm/dragonboard820c/Makefile
@@ -3,4 +3,3 @@
 # (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
 
 obj-y	:= dragonboard820c.o
-extra-y += head.o
diff --git a/board/qualcomm/dragonboard820c/head.S b/board/qualcomm/dragonboard820c/head.S
deleted file mode 100644
index b052a858fd32..000000000000
--- a/board/qualcomm/dragonboard820c/head.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ARM64 header for proper chain-loading with Little Kernel.
- *
- * Little Kernel shipped with Dragonboard820C boots standard Linux images for
- * ARM64. This file adds header that is required to boot U-Boot properly.
- *
- * For details see:
- * https://www.kernel.org/doc/Documentation/arm64/booting.txt
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-
-#include <config.h>
-
-/*
- *   per document in linux/Doc/arm64/booting.text
- */
-.global _arm64_header
-_arm64_header:
-	b _start
-	.word 0
-	.quad   CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
-	.quad   0    /* Effective size of kernel image, little-endian */
-	.quad   0    /* kernel flags, little-endian */
-	.quad   0    /* reserved */
-	.quad   0    /* reserved */
-	.quad   0    /* reserved */
-	.byte   0x41 /* Magic number, "ARM\x64" */
-	.byte   0x52
-	.byte   0x4d
-	.byte   0x64
-	.word   0    /* reserved (used for PE COFF offset) */
diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds
deleted file mode 100644
index 5251b59fbe76..000000000000
--- a/board/qualcomm/dragonboard820c/u-boot.lds
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Override linker script for fastboot-readable images
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- *
- * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
- */
-
-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
-OUTPUT_ARCH(aarch64)
-ENTRY(_arm64_header)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(8);
-	.text :
-	{
-		*(.__image_copy_start)
-		board/qualcomm/dragonboard820c/head.o (.text*)
-		CPUDIR/start.o (.text*)
-	}
-
-	/* This needs to come before *(.text*) */
-	.efi_runtime : {
-                __efi_runtime_start = .;
-		*(.text.efi_runtime*)
-		*(.rodata.efi_runtime*)
-		*(.data.efi_runtime*)
-                __efi_runtime_stop = .;
-	}
-
-	.text_rest :
-	{
-		*(.text*)
-	}
-
-	. = ALIGN(8);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(8);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(8);
-
-	. = .;
-
-	. = ALIGN(8);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
-	}
-
-	. = ALIGN(8);
-
-	.efi_runtime_rel : {
-                __efi_runtime_rel_start = .;
-		*(.rel*.efi_runtime)
-		*(.rel*.efi_runtime.*)
-                __efi_runtime_rel_stop = .;
-	}
-
-	. = ALIGN(8);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	. = ALIGN(8);
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rela.dyn : {
-		*(.rela*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-	. = ALIGN(8);
-
-	.bss_start : {
-		KEEP(*(.__bss_start));
-	}
-
-	.bss : {
-		*(.bss*)
-		 . = ALIGN(8);
-	}
-
-	.bss_end : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

-- 
2.43.1

[PATCH v4 20/39] mach-snapdragon: generalise board support

[Caleb Connolly]

Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot,
in many cases to the specific SoC but also to the board itself (e.g.
memory map). This has been largely resolved by modernising the Qualcomm
drivers in U-Boot, however the board code still largely follows this
model.

This patch removes the board specific memory maps and duplicated board
init code, replacing it with generic init code.

The memory map is now built at runtime based on data read from DT, this
allows for the memory map to be provided without having to recompile
U-Boot. Support is also added for booting with appended DTBs, so that
the first-stage bootloader can populate the memory map for us.

The sdm845 specific init code is dropped entirely, it set an environment
variable depending on if a button was pressed, but this variable wasn't
used in U-Boot, and could be written to use the button command instead.

The KASLR detection is also dropped as with appended dtb, the kaslr seed
can be read directly from the DTB passed to U-Boot.

A new qcom_defconfig is added, with the aim of providing a generic
U-Boot configuration that will work on as many Qualcomm boards as
possible. It replaces the defconfig files for the Dragonboard 845c,
Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as
they still have some board code left.

Similarly, the config headers for db845c, starqltechn, and qcs404-evb
are replaced by a single qcom header.

The previously db410c-specific board_usb_init() function is made to be
generic and is added to mach-snapdragon. While we lack proper modelling
for USB configuration, using a well-known named pinctrl state is a
reasonably generic middleground, and works using upstream DT. This
function will do nothing unless the USB node has a pinctrl state named
"device", in which case it will be set when entering USB peripheral
mode.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/Kconfig                                 |   3 +
 arch/arm/dts/Makefile                            |   9 +-
 arch/arm/mach-snapdragon/Kconfig                 |  96 ++--------
 arch/arm/mach-snapdragon/Makefile                |   6 +-
 arch/arm/mach-snapdragon/board.c                 | 215 +++++++++++++++++++++++
 arch/arm/mach-snapdragon/init_sdm845.c           |  73 --------
 arch/arm/mach-snapdragon/sysmap-apq8016.c        |  31 ----
 arch/arm/mach-snapdragon/sysmap-apq8096.c        |  31 ----
 arch/arm/mach-snapdragon/sysmap-qcs404.c         |  43 -----
 arch/arm/mach-snapdragon/sysmap-sdm845.c         |  31 ----
 board/qualcomm/dragonboard410c/Kconfig           |  15 --
 board/qualcomm/dragonboard410c/dragonboard410c.c |  41 -----
 board/qualcomm/dragonboard820c/Kconfig           |  15 --
 board/qualcomm/dragonboard820c/dragonboard820c.c |  39 +---
 board/qualcomm/dragonboard845c/Kconfig           |  12 --
 board/qualcomm/qcs404-evb/Kconfig                |  15 --
 board/qualcomm/qcs404-evb/qcs404-evb.c           |  21 +--
 configs/dragonboard410c_defconfig                |   6 +-
 configs/dragonboard820c_defconfig                |   6 +-
 configs/dragonboard845c_defconfig                |  29 ---
 configs/qcom_defconfig                           |  67 +++++++
 configs/qcs404evb_defconfig                      |   5 +-
 configs/starqltechn_defconfig                    |  41 -----
 include/configs/dragonboard845c.h                |  20 ---
 include/configs/qcom.h                           |  21 +++
 include/configs/qcs404-evb.h                     |  20 ---
 include/configs/sdm845.h                         |  26 ---
 27 files changed, 345 insertions(+), 592 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b072be24634..672577d0ddcc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1095,6 +1095,9 @@ config ARCH_SNAPDRAGON
 	select OF_SEPARATE
 	select SMEM
 	select SPMI
+	select OF_BOARD
+	select SAVE_PREV_BL_FDT_ADDR
+	select LINUX_KERNEL_IMAGE_HEADER
 	imply CMD_DM
 
 config ARCH_SOCFPGA
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3dbb07d..751035a577f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,10 +631,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
 
 dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 
-dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
-dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
-dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
-dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
+	dragonboard820c.dtb \
+	dragonboard845c.dtb \
+	starqltechn.dtb \
+	qcs404-evb.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index f897c393464f..96e44e2c5491 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -3,6 +3,9 @@ if ARCH_SNAPDRAGON
 config SYS_SOC
 	default "snapdragon"
 
+config SYS_VENDOR
+	default "qualcomm"
+
 config SYS_MALLOC_F_LEN
 	default 0x2000
 
@@ -12,91 +15,24 @@ config SPL_SYS_MALLOC_F
 config SPL_SYS_MALLOC_F_LEN
 	default 0x2000
 
-config SDM845
-	bool "Qualcomm Snapdragon 845 SoC"
-	select LINUX_KERNEL_IMAGE_HEADER
-	imply CLK_QCOM_SDM845
-	imply PINCTRL_QCOM_SDM845
-	imply BUTTON_QCOM_PMIC
-
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default 0x80000000
 
-choice
-	prompt "Snapdragon board select"
-
-config TARGET_DRAGONBOARD410C
-	bool "96Boards Dragonboard 410C"
-	select BOARD_LATE_INIT
-	select ENABLE_ARM_SOC_BOOT0_HOOK
-	imply CLK_QCOM_APQ8016
-	imply PINCTRL_QCOM_APQ8016
-	imply BUTTON_QCOM_PMIC
+config SYS_BOARD
+	string "Qualcomm custom board"
 	help
-	  Support for 96Boards Dragonboard 410C. This board complies with
-	  96Board Open Platform Specifications. Features:
-	  - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
-	  - 1GiB RAM
-	  - 8GiB eMMC, uSD slot
-	  - WiFi, Bluetooth and GPS module
-	  - 2x Host, 1x Device USB port
-	  - HDMI
-	  - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
+	  The Dragonboard 410c and 820c have additional board init
+	  code that isn't shared with other Qualcomm boards.
+	  Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will
+	  be used.
 
-config TARGET_DRAGONBOARD820C
-	bool "96Boards Dragonboard 820C"
-	select LINUX_KERNEL_IMAGE_HEADER
-	imply CLK_QCOM_APQ8096
-	imply PINCTRL_QCOM_APQ8096
-	imply BUTTON_QCOM_PMIC
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default SYS_BOARD if SYS_BOARD != ""
+	default "qcom"
 	help
-	  Support for 96Boards Dragonboard 820C. This board complies with
-	  96Board Open Platform Specifications. Features:
-	  - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
-	  - 3GiB RAM
-	  - 32GiB UFS drive
-
-config TARGET_DRAGONBOARD845C
-	bool "96Boards Dragonboard 845C"
-	help
-	  Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
-	  Platform. This board complies with 96Boards Open Platform
-	  Specifications. Features:
-	  - Qualcomm Snapdragon SDA845 SoC
-	  - 4GiB RAM
-	  - 64GiB UFS drive
-	select MISC_INIT_R
-	select SDM845
-
-config TARGET_STARQLTECHN
-	bool "Samsung S9 SM-G9600(starqltechn)"
-	help
-	  Support for Samsung S9 SM-G9600(starqltechn) board.
-	  Features:
-	  - Qualcomm Snapdragon SDM845 SoC
-	  - 4GiB RAM
-	  - 64GiB UFS drive
-	select MISC_INIT_R
-	select SDM845
-
-config TARGET_QCS404EVB
-	bool "Qualcomm Technologies, Inc. QCS404 EVB"
-	select LINUX_KERNEL_IMAGE_HEADER
-	imply CLK_QCOM_QCS404
-	imply PINCTRL_QCOM_QCS404
-	help
-	  Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
-	  Features:
-	  - Qualcomm Snapdragon QCS404 SoC
-	  - 1GiB RAM
-	  - 8GiB eMMC, uSD slot
-
-endchoice
-
-source "board/qualcomm/dragonboard410c/Kconfig"
-source "board/qualcomm/dragonboard820c/Kconfig"
-source "board/qualcomm/dragonboard845c/Kconfig"
-source "board/samsung/starqltechn/Kconfig"
-source "board/qualcomm/qcs404-evb/Kconfig"
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index d02432df8b04..857171e593da 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -2,8 +2,4 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
-obj-$(CONFIG_SDM845) += sysmap-sdm845.o
-obj-$(CONFIG_SDM845) += init_sdm845.o
-obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
+obj-y += board.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
new file mode 100644
index 000000000000..a1867852bcca
--- /dev/null
+++ b/arch/arm/mach-snapdragon/board.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common initialisation for Qualcomm Snapdragon boards.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#include "time.h"
+#include <asm/armv8/mmu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/system.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <dm/read.h>
+#include <env.h>
+#include <init.h>
+#include <linux/arm-smccc.h>
+#include <linux/bug.h>
+#include <linux/psci.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
+
+struct mm_region *mem_map = rbx_mem_map;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+static int ddr_bank_cmp(const void *v1, const void *v2)
+{
+	const struct {
+		phys_addr_t start;
+		phys_size_t size;
+	} *res1 = v1, *res2 = v2;
+
+	if (!res1->size)
+		return 1;
+	if (!res2->size)
+		return -1;
+
+	return (res1->start >> 24) - (res2->start >> 24);
+}
+
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret < 0)
+		return ret;
+
+	if (CONFIG_NR_DRAM_BANKS < 2)
+		return 0;
+
+	/* Sort our RAM banks -_- */
+	qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
+
+	return 0;
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	debug("PSCI:  v%ld.%ld\n",
+	      PSCI_VERSION_MAJOR(res.a0),
+	      PSCI_VERSION_MINOR(res.a0));
+}
+
+void *board_fdt_blob_setup(int *err)
+{
+	phys_addr_t fdt;
+	/* Return DTB pointer passed by ABL */
+	*err = 0;
+	fdt = get_prev_bl_fdt_addr();
+
+	/*
+	 * If we bail then the board will simply not boot, instead let's
+	 * try and use the FDT built into U-Boot if there is one...
+	 * This avoids having a hard dependency on the previous stage bootloader
+	 */
+	if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
+		debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
+		return (void *)gd->fdt_blob;
+	}
+
+	return (void *)fdt;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
+
+/*
+ * Some Qualcomm boards require GPIO configuration when switching USB modes.
+ * Support setting this configuration via pinctrl state.
+ */
+int board_usb_init(int index, enum usb_init_type init)
+{
+	struct udevice *usb;
+	int ret = 0;
+
+	/* USB device */
+	ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb);
+	if (ret) {
+		printf("Cannot find USB device\n");
+		return ret;
+	}
+
+	ret = dev_read_stringlist_search(usb, "pinctrl-names",
+					 "device");
+	/* No "device" pinctrl state, so just bail */
+	if (ret < 0)
+		return 0;
+
+	/* Select "default" or "device" pinctrl */
+	switch (init) {
+	case USB_INIT_HOST:
+		pinctrl_select_state(usb, "default");
+		break;
+	case USB_INIT_DEVICE:
+		pinctrl_select_state(usb, "device");
+		break;
+	default:
+		debug("Unknown usb_init_type %d\n", init);
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * Some boards still need board specific init code, they can implement that by
+ * overriding this function.
+ *
+ * FIXME: get rid of board specific init code
+ */
+void __weak qcom_board_init(void)
+{
+}
+
+int board_init(void)
+{
+	show_psci_version();
+	qcom_board_init();
+	return 0;
+}
+
+static void build_mem_map(void)
+{
+	int i;
+
+	/*
+	 * Ensure the peripheral block is sized to correctly cover the address range
+	 * up to the first memory bank.
+	 * Don't map the first page to ensure that we actually trigger an abort on a
+	 * null pointer access rather than just hanging.
+	 * FIXME: we should probably split this into more precise regions
+	 */
+	mem_map[0].phys = 0x1000;
+	mem_map[0].virt = mem_map[0].phys;
+	mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
+	mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+
+	debug("Configured memory map:\n");
+	debug("  0x%016llx - 0x%016llx: Peripheral block\n",
+	      mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
+
+	/*
+	 * Now add memory map entries for each DRAM bank, ensuring we don't
+	 * overwrite the list terminator
+	 */
+	for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
+		if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
+			log_warning("Too many DRAM banks!\n");
+			break;
+		}
+		mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
+		mem_map[i + 1].virt = mem_map[i + 1].phys;
+		mem_map[i + 1].size = gd->bd->bi_dram[i].size;
+		mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				     PTE_BLOCK_INNER_SHARE;
+
+		debug("  0x%016llx - 0x%016llx: DDR bank %d\n",
+		      mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
+	}
+}
+
+u64 get_page_table_size(void)
+{
+	return SZ_64K;
+}
+
+void enable_caches(void)
+{
+	build_mem_map();
+
+	icache_enable();
+	dcache_enable();
+}
diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c
deleted file mode 100644
index 067acc9a6f44..000000000000
--- a/arch/arm/mach-snapdragon/init_sdm845.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Common init part for boards based on SDM845
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- */
-
-#include <button.h>
-#include <init.h>
-#include <env.h>
-#include <common.h>
-#include <asm/system.h>
-#include <asm/gpio.h>
-#include <dm.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	return fdtdec_setup_mem_size_base();
-}
-
-void reset_cpu(void)
-{
-	psci_system_reset();
-}
-
-__weak int board_init(void)
-{
-	return 0;
-}
-
-/* Check for vol- and power buttons */
-__weak int misc_init_r(void)
-{
-	struct udevice *btn;
-	int ret;
-	enum button_state_t state;
-
-	ret = button_get_by_label("pwrkey", &btn);
-	if (ret < 0) {
-		printf("Couldn't find power button!\n");
-		return ret;
-	}
-
-	state = button_get_state(btn);
-	if (state == BUTTON_ON) {
-		env_set("key_power", "1");
-		printf("Power button pressed\n");
-	} else {
-		env_set("key_power", "0");
-	}
-
-	/*
-	 * search for kaslr address, set by primary bootloader by searching first
-	 * 0x100 relocated bytes at u-boot's initial load address range
-	 */
-	uintptr_t start = gd->ram_base;
-	uintptr_t end = start + 0x800000;
-	u8 *addr = (u8 *)start;
-	phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
-	u32 block_size = 0x1000;
-
-	while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
-		addr += block_size;
-
-	if ((uintptr_t)addr >= end)
-		printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
-	else
-		env_set_addr("KASLR", addr);
-
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c
deleted file mode 100644
index ffa3f9aa3532..000000000000
--- a/arch/arm/mach-snapdragon/sysmap-apq8016.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8016 memory map
- *
- * (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region apq8016_mem_map[] = {
-	{
-		.virt = 0x0UL, /* Peripheral block */
-		.phys = 0x0UL, /* Peripheral block */
-		.size = 0x8000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL, /* DDR */
-		.phys = 0x80000000UL, /* DDR */
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = apq8016_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c
deleted file mode 100644
index 0614f8308d02..000000000000
--- a/arch/arm/mach-snapdragon/sysmap-apq8096.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8096 memory map
- *
- * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region apq8096_mem_map[] = {
-	{
-		.virt = 0x0UL, /* Peripheral block */
-		.phys = 0x0UL, /* Peripheral block */
-		.size = 0x10000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL, /* DDR */
-		.phys = 0x80000000UL, /* DDR */
-		.size = 0xC0000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = apq8096_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
deleted file mode 100644
index 64ca4adf1bd1..000000000000
--- a/arch/arm/mach-snapdragon/sysmap-qcs404.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm QCS404 memory map
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region qcs404_mem_map[] = {
-	{
-		.virt = 0x0UL, /* Peripheral block */
-		.phys = 0x0UL, /* Peripheral block */
-		.size = 0x8000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL, /* DDR */
-		.phys = 0x80000000UL, /* DDR */
-		.size = 0x05900000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x89600000UL, /* DDR */
-		.phys = 0x89600000UL, /* DDR */
-		.size = 0x162000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa0000000UL, /* DDR */
-		.phys = 0xa0000000UL, /* DDR */
-		.size = 0x20000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = qcs404_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c
deleted file mode 100644
index 721ac411665c..000000000000
--- a/arch/arm/mach-snapdragon/sysmap-sdm845.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm SDM845 memory map
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region sdm845_mem_map[] = {
-	{
-		.virt = 0x0UL, /* Peripheral block */
-		.phys = 0x0UL, /* Peripheral block */
-		.size = 0x10000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL, /* DDR */
-		.phys = 0x80000000UL, /* DDR */
-		.size = 0x200000000UL, /* 8GiB - maximum allowed memory */
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = sdm845_mem_map;
diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig
deleted file mode 100644
index 03bd7ae309cd..000000000000
--- a/board/qualcomm/dragonboard410c/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DRAGONBOARD410C
-
-config SYS_BOARD
-	default "dragonboard410c"
-
-config SYS_VENDOR
-	default "qualcomm"
-
-config SYS_SOC
-	default "apq8016"
-
-config SYS_CONFIG_NAME
-	default "dragonboard410c"
-
-endif
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 40b5448c6ef1..0136cc2237de 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -23,37 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define USB_HUB_RESET_GPIO 2
-#define USB_SW_SELECT_GPIO 3
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	struct udevice *usb;
-	int ret = 0;
-
-	/* USB device */
-	ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
-	if (ret) {
-		printf("Cannot find USB device\n");
-		return ret;
-	}
-
-	/* Select "default" or "device" pinctrl */
-	switch (init) {
-	case USB_INIT_HOST:
-		pinctrl_select_state(usb, "default");
-		break;
-	case USB_INIT_DEVICE:
-		pinctrl_select_state(usb, "device");
-		break;
-	default:
-		debug("Unknown usb_init_type %d\n", init);
-		break;
-	}
-
-	return 0;
-}
-
 /* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
 #define UNSTUFF_BITS(resp, start, size) \
 	({ \
@@ -119,11 +88,6 @@ int misc_init_r(void)
 	return 0;
 }
 
-int board_init(void)
-{
-	return 0;
-}
-
 int board_late_init(void)
 {
 	char serial[16];
@@ -166,8 +130,3 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 			   "local-bd-address", mac, ARP_HLEN, 1);
 	return 0;
 }
-
-void reset_cpu(void)
-{
-	psci_system_reset();
-}
diff --git a/board/qualcomm/dragonboard820c/Kconfig b/board/qualcomm/dragonboard820c/Kconfig
deleted file mode 100644
index aff9af527128..000000000000
--- a/board/qualcomm/dragonboard820c/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DRAGONBOARD820C
-
-config SYS_BOARD
-	default "dragonboard820c"
-
-config SYS_VENDOR
-	default "qualcomm"
-
-config SYS_SOC
-	default "apq8096"
-
-config SYS_CONFIG_NAME
-	default "dragonboard820c"
-
-endif
diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c
index 2f0db628368b..ac7de711c588 100644
--- a/board/qualcomm/dragonboard820c/dragonboard820c.c
+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c
@@ -27,24 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-
-	return 0;
-}
-
 static void sdhci_power_init(void)
 {
 	const u32 TLMM_PULL_MASK = 0x3;
@@ -113,28 +95,9 @@ static void sdhci_power_init(void)
 			rclk[i].val  << rclk[i].bit);
 }
 
-static void show_psci_version(void)
-{
-	struct arm_smccc_res res;
-
-	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
-
-	printf("PSCI:  v%ld.%ld\n",
-	       PSCI_VERSION_MAJOR(res.a0),
-		PSCI_VERSION_MINOR(res.a0));
-}
-
-int board_init(void)
+void qcom_board_init(void)
 {
 	sdhci_power_init();
-	show_psci_version();
-
-	return 0;
-}
-
-void reset_cpu(void)
-{
-	psci_system_reset();
 }
 
 /* Check for vol- button - if pressed - stop autoboot */
diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig
deleted file mode 100644
index 52fdff288d59..000000000000
--- a/board/qualcomm/dragonboard845c/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DRAGONBOARD845C
-
-config SYS_BOARD
-	default "dragonboard845c"
-
-config SYS_CONFIG_NAME
-	default "dragonboard845c"
-
-config SYS_VENDOR
-	default "qualcomm"
-
-endif
diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig
deleted file mode 100644
index 32657c7d5e31..000000000000
--- a/board/qualcomm/qcs404-evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_QCS404EVB
-
-config SYS_BOARD
-	default "qcs404-evb"
-
-config SYS_VENDOR
-	default "qualcomm"
-
-config SYS_SOC
-	default "qcs404"
-
-config SYS_CONFIG_NAME
-	default "qcs404-evb"
-
-endif
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
index 249dca7e72f1..1a4b1f97a3ae 100644
--- a/board/qualcomm/qcs404-evb/qcs404-evb.c
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.c
@@ -14,16 +14,10 @@
 #include <asm/gpio.h>
 #include <asm/global_data.h>
 #include <fdt_support.h>
-#include <asm/arch/dram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	return fdtdec_setup_mem_size_base();
-}
-
-int board_init(void)
+void qcom_board_init(void)
 {
 	struct udevice *pmic_gpio;
 	struct gpio_desc usb_vbus_boost_pin;
@@ -34,29 +28,22 @@ int board_init(void)
 					&pmic_gpio);
 	if (ret < 0) {
 		printf("Failed to find pms405_gpios@c000 node.\n");
-		return ret;
+		return;
 	}
 
 	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
 				  "usb_vbus_boost_pin");
 	if (node < 0) {
 		printf("Failed to find usb_hub_reset_pm dt node.\n");
-		return node;
+		return;
 	}
 	ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
 					 &usb_vbus_boost_pin, 0);
 	if (ret < 0) {
 		printf("Failed to request usb_hub_reset_pm gpio.\n");
-		return ret;
+		return;
 	}
 
 	dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
 			      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	return 0;
-}
-
-void reset_cpu(void)
-{
-	psci_system_reset();
 }
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 56a73893d3df..efdee8a40fa3 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -1,9 +1,10 @@
 CONFIG_ARM=y
+CONFIG_SYS_BOARD="dragonboard410c"
 CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ARCH_SNAPDRAGON=y
 CONFIG_TEXT_BASE=0x8f600000
 CONFIG_SYS_MALLOC_LEN=0x802000
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
 CONFIG_ENV_SIZE=0x2000
@@ -38,7 +39,9 @@ CONFIG_CMD_TIMER=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON_QCOM_PMIC=y
 CONFIG_CLK=y
+CONFIG_CLK_QCOM_APQ8016=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x91000000
 CONFIG_FASTBOOT_FLASH=y
@@ -52,6 +55,7 @@ CONFIG_MMC_SDHCI_MSM=y
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_APQ8016=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_MSM_SERIAL=y
diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index 7304ff97dd8e..89847ce0b307 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -1,14 +1,13 @@
 CONFIG_ARM=y
+CONFIG_SYS_BOARD="dragonboard820c"
 CONFIG_COUNTER_FREQUENCY=19000000
 CONFIG_ARCH_SNAPDRAGON=y
 CONFIG_TEXT_BASE=0x80080000
 CONFIG_SYS_MALLOC_LEN=0x804000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
-CONFIG_TARGET_DRAGONBOARD820C=y
 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
 CONFIG_SYS_LOAD_ADDR=0x80080000
 CONFIG_DISTRO_DEFAULTS=y
@@ -35,12 +34,15 @@ CONFIG_ENV_IS_IN_EXT4=y
 CONFIG_ENV_EXT4_INTERFACE="mmc"
 CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BUTTON_QCOM_PMIC=y
 CONFIG_CLK=y
+CONFIG_CLK_QCOM_APQ8096=y
 CONFIG_QCOM_PMIC_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MSM=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_APQ8096=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_MSM_SERIAL=y
diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig
deleted file mode 100644
index f29f11e342e7..000000000000
--- a/configs/dragonboard845c_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=19000000
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
-CONFIG_TARGET_DRAGONBOARD845C=y
-CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
-CONFIG_SYS_LOAD_ADDR=0x80000000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=5
-CONFIG_SAVE_PREV_BL_FDT_ADDR=y
-CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
-CONFIG_SYS_CBSIZE=512
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_GPIO=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_MSM_GPIO=y
-CONFIG_QCOM_PMIC_GPIO=y
-CONFIG_PINCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_QCOM=y
-CONFIG_MSM_GENI_SERIAL=y
-CONFIG_SPMI_MSM=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
new file mode 100644
index 000000000000..a84f5aee444e
--- /dev/null
+++ b/configs/qcom_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
+CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_BUTTON_CMD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_LOG_MAX_LEVEL=9
+CONFIG_LOG_DEFAULT_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_LOG=y
+# CONFIG_NET is not set
+CONFIG_BUTTON_QCOM_PMIC=y
+CONFIG_CLK=y
+CONFIG_CLK_QCOM_QCS404=y
+CONFIG_CLK_QCOM_SDM845=y
+CONFIG_MSM_GPIO=y
+CONFIG_QCOM_PMIC_GPIO=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_QCOM_QCS404=y
+CONFIG_PINCTRL_QCOM_SDM845=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_QCOM=y
+CONFIG_SCSI=y
+CONFIG_MSM_SERIAL=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_UFS=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_NO_FB_CLEAR=y
+CONFIG_VIDEO_SIMPLE=y
+CONFIG_HEXDUMP=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
index 700c024e8b6a..d85d193895b0 100644
--- a/configs/qcs404evb_defconfig
+++ b/configs/qcs404evb_defconfig
@@ -1,11 +1,10 @@
 CONFIG_ARM=y
+CONFIG_SYS_BOARD="qcs404-evb"
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=19000000
 CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_SNAPDRAGON=y
 CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
-CONFIG_DM_RESET=y
-CONFIG_TARGET_QCS404EVB=y
 CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
 CONFIG_SYS_LOAD_ADDR=0x80000000
 CONFIG_FIT=y
@@ -31,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 # CONFIG_NET is not set
 CONFIG_CLK=y
+CONFIG_CLK_QCOM_QCS404=y
 CONFIG_MSM_GPIO=y
 CONFIG_QCOM_PMIC_GPIO=y
 CONFIG_MISC=y
@@ -42,6 +42,7 @@ CONFIG_PHY=y
 CONFIG_PHY_QCOM_USB_HS_28NM=y
 CONFIG_PHY_QCOM_USB_SS=y
 CONFIG_PINCTRL=y
+CONFIG_PINCTRL_QCOM_QCS404=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_MSM_SERIAL=y
diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig
deleted file mode 100644
index 6980a8232667..000000000000
--- a/configs/starqltechn_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=19000000
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="starqltechn"
-CONFIG_TARGET_STARQLTECHN=y
-CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600"
-CONFIG_SYS_LOAD_ADDR=0x80000000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
-CONFIG_SAVE_PREV_BL_FDT_ADDR=y
-CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_BOOTMENU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_BMP=y
-# CONFIG_NET is not set
-CONFIG_BUTTON=y
-CONFIG_CLK=y
-CONFIG_MSM_GPIO=y
-CONFIG_QCOM_PMIC_GPIO=y
-CONFIG_DM_KEYBOARD=y
-CONFIG_BUTTON_KEYBOARD=y
-CONFIG_PINCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_QCOM=y
-CONFIG_MSM_GENI_SERIAL=y
-CONFIG_SPMI_MSM=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_FONT_8X16 is not set
-CONFIG_VIDEO_FONT_16X32=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_VIDEO_SIMPLE=y
-CONFIG_VIDEO_DT_SIMPLEFB=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
deleted file mode 100644
index 14a8a2ca049e..000000000000
--- a/include/configs/dragonboard845c.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-#ifndef __CONFIGS_SDM845_H
-#define __CONFIGS_SDM845_H
-
-#include <linux/sizes.h>
-
-#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
-
-#define CFG_EXTRA_ENV_SETTINGS \
-	"bootm_size=0x5000000\0"	\
-	"bootm_low=0x80000000\0"	\
-	"bootcmd=bootm $prevbl_initrd_start_addr\0"
-
-#endif
diff --git a/include/configs/qcom.h b/include/configs/qcom.h
new file mode 100644
index 000000000000..e50b3bce5cdd
--- /dev/null
+++ b/include/configs/qcom.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for Qualcomm Snapdragon boards
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#ifndef __CONFIGS_SNAPDRAGON_H
+#define __CONFIGS_SNAPDRAGON_H
+
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+
+/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */
+#define CFG_EXTRA_ENV_SETTINGS \
+	"stdin=serial,button-kbd\0"	\
+	"stdout=serial,vidconsole\0"	\
+	"stderr=serial,vidconsole\0" \
+	"bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+#endif
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
deleted file mode 100644
index 9501d43665e9..000000000000
--- a/include/configs/qcs404-evb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration file for QCS404 evaluation board
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-#ifndef __CONFIGS_QCS404EVB_H
-#define __CONFIGS_QCS404EVB_H
-
-#include <linux/sizes.h>
-
-#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
-
-#define CFG_EXTRA_ENV_SETTINGS \
-	"bootm_size=0x5000000\0"	\
-	"bootm_low=0x80000000\0"	\
-	"bootcmd=bootm $prevbl_initrd_start_addr\0"
-
-#endif
diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
deleted file mode 100644
index 5ad8569b2152..000000000000
--- a/include/configs/sdm845.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration file for boards, based on Qualcomm SDM845 chip
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- */
-
-#ifndef __CONFIGS_SDM845_H
-#define __CONFIGS_SDM845_H
-
-#include <linux/sizes.h>
-
-#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
-
-#define CFG_EXTRA_ENV_SETTINGS \
-	"bootm_size=0x4000000\0"	\
-	"bootm_low=0x80000000\0"	\
-	"stdin=serial,button-kbd\0"	\
-	"stdout=serial,vidconsole\0"	\
-	"stderr=serial,vidconsole\0"	\
-	"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
-	"bootcmd=source $prevbl_initrd_start_addr:bootscript\0"
-
-/* Size of malloc() pool */
-
-#endif

-- 
2.43.1

[PATCH v4 21/39] mach-snapdragon: dynamic load addresses

[Caleb Connolly]

Heavily inspired by Apple board code. Use the LMB allocator to configure
load addresses at runtime, and implement a lookup table for selecting a
devicetree.

As some Qualcomm RBx boards have different RAM capacities and base
addresses, it isn't possible to hardcode these regions.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/Kconfig                                 |  1 +
 arch/arm/mach-snapdragon/board.c                 | 34 ++++++++++++++++++++++++
 board/qualcomm/dragonboard410c/dragonboard410c.c |  2 +-
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 672577d0ddcc..0dba77f86b49 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1095,6 +1095,7 @@ config ARCH_SNAPDRAGON
 	select OF_SEPARATE
 	select SMEM
 	select SPMI
+	select BOARD_LATE_INIT
 	select OF_BOARD
 	select SAVE_PREV_BL_FDT_ADDR
 	select LINUX_KERNEL_IMAGE_HEADER
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index a1867852bcca..f445bed3af00 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -22,6 +22,7 @@
 #include <linux/bug.h>
 #include <linux/psci.h>
 #include <linux/sizes.h>
+#include <lmb.h>
 #include <malloc.h>
 #include <usb.h>
 
@@ -159,6 +160,39 @@ int board_init(void)
 	return 0;
 }
 
+void __weak qcom_late_init(void)
+{
+}
+
+#define KERNEL_COMP_SIZE	SZ_64M
+
+#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
+
+/* Stolen from arch/arm/mach-apple/board.c */
+int board_late_init(void)
+{
+	struct lmb lmb;
+	u32 status = 0;
+
+	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
+	/* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */
+	status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
+	status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
+	status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE));
+	status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
+	status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
+	status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
+	status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
+
+	if (status)
+		log_warning("%s: Failed to set run time variables\n", __func__);
+
+	qcom_late_init();
+
+	return 0;
+}
+
 static void build_mem_map(void)
 {
 	int i;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 0136cc2237de..fbbfc0e65e24 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -88,7 +88,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-int board_late_init(void)
+int qcom_late_init(void)
 {
 	char serial[16];
 

-- 
2.43.1

[PATCH v4 22/39] mach-snapdragon: generate fdtfile automatically

[Caleb Connolly]

With just a few basic rules, we can generate the $fdtfile environment
variable to match the format used in Linux. This uses the root
compatible property inside u-boot, with specific handling for the
Dragonboard845c which is a special case, and for the qrb robotics
boards.

This is known to work on supported platforms, and lets us avoid having a
big lookup table.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/mach-snapdragon/board.c | 101 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f445bed3af00..5a859aabd5c4 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -160,6 +160,106 @@ int board_init(void)
 	return 0;
 }
 
+/* Sets up the "board", and "soc" environment variables as well as constructing the devicetree
+ * path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a
+ * comprehensive solution to automatically picking the DTB, but aims to be correct for the
+ * majority case. For most devices it should be possible to make this algorithm work by
+ * adjusting the root compatible property in the U-Boot DTS. Handling devices with multiple
+ * variants that are all supported by a single U-Boot image will require implementing device-
+ * specific detection.
+ */
+static void configure_env(void)
+{
+	const char *first_compat, *last_compat;
+	char *tmp;
+	char buf[32] = { 0 };
+	/*
+	 * Most DTB filenames follow the scheme: qcom/<soc>-[vendor]-<board>.dtb
+	 * The vendor is skipped when it's a Qualcomm reference board, or the
+	 * db845c.
+	 */
+	char dt_path[64] = { 0 };
+	int compat_count, ret;
+	ofnode root;
+
+	root = ofnode_root();
+	/* This is almost always 2, but be explicit that we want the first and last compatibles
+	 * not the first and second.
+	 */
+	compat_count = ofnode_read_string_count(root, "compatible");
+	if (compat_count < 2) {
+		log_warning("%s: only one root compatible bailing!\n", __func__);
+		return;
+	}
+
+	/* The most specific device compatible (e.g. "thundercomm,db845c") */
+	ret = ofnode_read_string_index(root, "compatible", 0, &first_compat);
+	if (ret < 0) {
+		log_warning("Can't read first compatible\n");
+		return;
+	}
+
+	/* The last compatible is always the SoC compatible */
+	ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat);
+	if (ret < 0) {
+		log_warning("Can't read second compatible\n");
+		return;
+	}
+
+	/* Copy the second compat (e.g. "qcom,sdm845") into buf */
+	strlcpy(buf, last_compat, sizeof(buf) - 1);
+	tmp = buf;
+
+	/* strsep() is destructive, it replaces the comma with a \0 */
+	if (!strsep(&tmp, ",")) {
+		log_warning("second compatible '%s' has no ','\n", buf);
+		return;
+	}
+
+	/* tmp now points to just the "sdm845" part of the string */
+	env_set("soc", tmp);
+
+	/* Now figure out the "board" part from the first compatible */
+	memset(buf, 0, sizeof(buf));
+	strlcpy(buf, first_compat, sizeof(buf) - 1);
+	tmp = buf;
+
+	/* The Qualcomm reference boards (RBx, HDK, etc)  */
+	if (!strncmp("qcom", buf, strlen("qcom"))) {
+		/*
+		 * They all have the first compatible as "qcom,<soc>-<board>"
+		 * (e.g. "qcom,qrb5165-rb5"). We extract just the part after
+		 * the dash.
+		 */
+		if (!strsep(&tmp, "-")) {
+			log_warning("compatible '%s' has no '-'\n", buf);
+			return;
+		}
+		/* tmp is now "rb5" */
+		env_set("board", tmp);
+	} else {
+		if (!strsep(&tmp, ",")) {
+			log_warning("compatible '%s' has no ','\n", buf);
+			return;
+		}
+		/* for thundercomm we just want the bit after the comma (e.g. "db845c"),
+		 * for all other boards we replace the comma with a '-' and take both
+		 * (e.g. "oneplus-enchilada")
+		 */
+		if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
+			env_set("board", tmp);
+		} else {
+			*(tmp - 1) = '-';
+			env_set("board", buf);
+		}
+	}
+
+	/* Now build the full path name */
+	snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
+		 env_get("soc"), env_get("board"));
+	env_set("fdtfile", dt_path);
+}
+
 void __weak qcom_late_init(void)
 {
 }
@@ -188,6 +288,7 @@ int board_late_init(void)
 	if (status)
 		log_warning("%s: Failed to set run time variables\n", __func__);
 
+	configure_env();
 	qcom_late_init();
 
 	return 0;

-- 
2.43.1

[PATCH v4 23/39] mach-snapdragon: carve out no-map regions

[Caleb Connolly]

On Qualcomm platforms, the TZ may already have certain memory regions
under protection by the time U-Boot starts. There is a rare case on some
platforms where the prefetcher might speculatively access one of these
regions resulting in a board crash (TZ traps and then resets the board).

We shouldn't be accessing these regions from within U-Boot anyway, so
let's mark them all with PTE_TYPE_FAULT to prevent any speculative
access and correctly trap in EL1 rather than EL3.

This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
with caches on). So to minimise the impact this is only enabled on
QCS404 for now (where the issue is known to occur).

In the future, we should try to find a more efficient way to handle
this, perhaps by turning on the MMU in stages.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/mach-snapdragon/board.c | 162 +++++++++++++++++++++++++++++++++------
 1 file changed, 140 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 5a859aabd5c4..f12f5791a136 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -25,6 +25,7 @@
 #include <lmb.h>
 #include <malloc.h>
 #include <usb.h>
+#include <sort.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -296,7 +297,7 @@ int board_late_init(void)
 
 static void build_mem_map(void)
 {
-	int i;
+	int i, j;
 
 	/*
 	 * Ensure the peripheral block is sized to correctly cover the address range
@@ -312,28 +313,23 @@ static void build_mem_map(void)
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 
-	debug("Configured memory map:\n");
-	debug("  0x%016llx - 0x%016llx: Peripheral block\n",
-	      mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
-
-	/*
-	 * Now add memory map entries for each DRAM bank, ensuring we don't
-	 * overwrite the list terminator
-	 */
-	for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
-		if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
-			log_warning("Too many DRAM banks!\n");
-			break;
-		}
-		mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
-		mem_map[i + 1].virt = mem_map[i + 1].phys;
-		mem_map[i + 1].size = gd->bd->bi_dram[i].size;
-		mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-				     PTE_BLOCK_INNER_SHARE;
-
-		debug("  0x%016llx - 0x%016llx: DDR bank %d\n",
-		      mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
+	for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
+		mem_map[i].phys = gd->bd->bi_dram[j].start;
+		mem_map[i].virt = mem_map[i].phys;
+		mem_map[i].size = gd->bd->bi_dram[j].size;
+		mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
+				   PTE_BLOCK_INNER_SHARE;
 	}
+
+	mem_map[i].phys = UINT64_MAX;
+	mem_map[i].size = 0;
+
+#ifdef DEBUG
+	debug("Configured memory map:\n");
+	for (i = 0; mem_map[i].size; i++)
+		debug("  0x%016llx - 0x%016llx: entry %d\n",
+		      mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
+#endif
 }
 
 u64 get_page_table_size(void)
@@ -341,10 +337,132 @@ u64 get_page_table_size(void)
 	return SZ_64K;
 }
 
+static int fdt_cmp_res(const void *v1, const void *v2)
+{
+	const struct fdt_resource *res1 = v1, *res2 = v2;
+
+	return res1->start - res2->start;
+}
+
+#define N_RESERVED_REGIONS 32
+
+/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
+ * On some platforms this is enough to trigger a security violation and trap
+ * to EL3.
+ */
+static void carve_out_reserved_memory(void)
+{
+	static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
+	int parent, rmem, count, i = 0;
+	phys_addr_t start;
+	size_t size;
+
+	/* Some reserved nodes must be carved out, as the cache-prefetcher may otherwise
+	 * attempt to access them, causing a security exception.
+	 */
+	parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
+	if (parent <= 0) {
+		log_err("No reserved memory regions found\n");
+		return;
+	}
+
+	/* Collect the reserved memory regions */
+	fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
+		const fdt32_t *ptr;
+		int len;
+		if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL))
+			continue;
+
+		if (i == N_RESERVED_REGIONS) {
+			log_err("Too many reserved regions!\n");
+			break;
+		}
+
+		/* Read the address and size out from the reg property. Doing this "properly" with
+		 * fdt_get_resource() takes ~70ms on SDM845, but open-coding the happy path here
+		 * takes <1ms... Oh the woes of no dcache.
+		 */
+		ptr = fdt_getprop(gd->fdt_blob, rmem, "reg", &len);
+		if (ptr) {
+			/* Qualcomm devices use #address/size-cells = <2> but all reserved regions are within
+			 * the 32-bit address space. So we can cheat here for speed.
+			 */
+			res[i].start = fdt32_to_cpu(ptr[1]);
+			res[i].end = res[i].start + fdt32_to_cpu(ptr[3]);
+			i++;
+		}
+	}
+
+	/* Sort the reserved memory regions by address */
+	count = i;
+	qsort(res, count, sizeof(struct fdt_resource), fdt_cmp_res);
+
+	/* Now set the right attributes for them. Often a lot of the regions are tightly packed together
+	 * so we can optimise the number of calls to mmu_change_region_attr() by combining adjacent
+	 * regions.
+	 */
+	start = ALIGN_DOWN(res[0].start, SZ_2M);
+	size = ALIGN(res[0].end - start, SZ_2M);
+	for (i = 1; i <= count; i++) {
+		/* We ideally want to 2M align everything for more efficient pagetables, but we must avoid
+		 * overwriting reserved memory regions which shouldn't be mapped as FAULT (like those with
+		 * compatible properties).
+		 * If within 2M of the previous region, bump the size to include this region. Otherwise
+		 * start a new region.
+		 */
+		if (i == count || start + size < res[i].start - SZ_2M) {
+			debug("  0x%016llx - 0x%016llx: reserved\n",
+			      start, start + size);
+			mmu_change_region_attr(start, size, PTE_TYPE_FAULT);
+			/* If this is the final region then quit here before we index
+			 * out of bounds...
+			 */
+			if (i == count)
+				break;
+			start = ALIGN_DOWN(res[i].start, SZ_2M);
+			size = ALIGN(res[i].end - start, SZ_2M);
+		} else {
+			/* Bump size if this region is immediately after the previous one */
+			size = ALIGN(res[i].end - start, SZ_2M);
+		}
+	}
+}
+
+/* This function open-codes setup_all_pgtables() so that we can
+ * insert additional mappings *before* turning on the MMU.
+ */
 void enable_caches(void)
 {
+	u64 tlb_addr = gd->arch.tlb_addr;
+	u64 tlb_size = gd->arch.tlb_size;
+	u64 pt_size;
+	ulong carveout_start;
+
+	gd->arch.tlb_fillptr = tlb_addr;
+
 	build_mem_map();
 
 	icache_enable();
+
+	/* Create normal system page tables */
+	setup_pgtables();
+
+	pt_size = (uintptr_t)gd->arch.tlb_fillptr -
+		  (uintptr_t)gd->arch.tlb_addr;
+	debug("Primary pagetable size: %lluKiB\n", pt_size / 1024);
+
+	/* Create emergency page tables */
+	gd->arch.tlb_size -= pt_size;
+	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
+	setup_pgtables();
+	gd->arch.tlb_emerg = gd->arch.tlb_addr;
+	gd->arch.tlb_addr = tlb_addr;
+	gd->arch.tlb_size = tlb_size;
+
+	carveout_start = get_timer(0);
+	/* Takes ~20-50ms on SDM845 */
+	carve_out_reserved_memory();
+	debug("carveout time: %lums\n", get_timer(carveout_start));
+
 	dcache_enable();
 }

-- 
2.43.1

[PATCH v4 24/39] board: qcs404-evb: drop board code

[Caleb Connolly]

This board is entirely supported by the generic arch code and DTS. The
board code used to handle turning on the vbus regulator, however this is
now handled via DT.

With this, the board specific defconfig is also no longer needed, so
drop it as well.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 board/qualcomm/qcs404-evb/Makefile     |  6 ----
 board/qualcomm/qcs404-evb/qcs404-evb.c | 49 -----------------------------
 configs/qcs404evb_defconfig            | 56 ----------------------------------
 3 files changed, 111 deletions(-)

diff --git a/board/qualcomm/qcs404-evb/Makefile b/board/qualcomm/qcs404-evb/Makefile
deleted file mode 100644
index 4665827e0859..000000000000
--- a/board/qualcomm/qcs404-evb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
-#
-
-obj-y += qcs404-evb.o
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
deleted file mode 100644
index 1a4b1f97a3ae..000000000000
--- a/board/qualcomm/qcs404-evb/qcs404-evb.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board init file for QCS404-EVB
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <dm.h>
-#include <env.h>
-#include <init.h>
-#include <asm/cache.h>
-#include <asm/gpio.h>
-#include <asm/global_data.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void qcom_board_init(void)
-{
-	struct udevice *pmic_gpio;
-	struct gpio_desc usb_vbus_boost_pin;
-	int ret, node;
-
-	ret = uclass_get_device_by_name(UCLASS_GPIO,
-					"pms405_gpios@c000",
-					&pmic_gpio);
-	if (ret < 0) {
-		printf("Failed to find pms405_gpios@c000 node.\n");
-		return;
-	}
-
-	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
-				  "usb_vbus_boost_pin");
-	if (node < 0) {
-		printf("Failed to find usb_hub_reset_pm dt node.\n");
-		return;
-	}
-	ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
-					 &usb_vbus_boost_pin, 0);
-	if (ret < 0) {
-		printf("Failed to request usb_hub_reset_pm gpio.\n");
-		return;
-	}
-
-	dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
-			      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-}
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
deleted file mode 100644
index d85d193895b0..000000000000
--- a/configs/qcs404evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_BOARD="qcs404-evb"
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=19000000
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
-CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
-CONFIG_SYS_LOAD_ADDR=0x80000000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
-CONFIG_SAVE_PREV_BL_FDT_ADDR=y
-CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
-CONFIG_SYS_CBSIZE=512
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_CLK_QCOM_QCS404=y
-CONFIG_MSM_GPIO=y
-CONFIG_QCOM_PMIC_GPIO=y
-CONFIG_MISC=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_MSM=y
-CONFIG_PHY=y
-CONFIG_PHY_QCOM_USB_HS_28NM=y
-CONFIG_PHY_QCOM_USB_SS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_QCOM_QCS404=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_QCOM=y
-CONFIG_MSM_SERIAL=y
-CONFIG_SPMI_MSM=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_LMB_MAX_REGIONS=64

-- 
2.43.1

[PATCH v4 25/39] doc: board/qualcomm: document generic targets

[Caleb Connolly]

Replace the board specific docs with a generic board.rst file which
documents the build/boot process for the sdm845 and qcs404 boards now
that the only differences are the DTB in use.

At the same time, create a debugging page to document some useful
snippets and tips for working with Qualcomm platforms.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 doc/board/qualcomm/board.rst     | 125 +++++++++++++++++++++++++++++
 doc/board/qualcomm/debugging.rst |  61 ++++++++++++++
 doc/board/qualcomm/index.rst     |   4 +-
 doc/board/qualcomm/qcs404.rst    |  79 ------------------
 doc/board/qualcomm/sdm845.rst    | 167 ---------------------------------------
 5 files changed, 188 insertions(+), 248 deletions(-)

diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst
new file mode 100644
index 000000000000..4d793209f9e3
--- /dev/null
+++ b/doc/board/qualcomm/board.rst
@@ -0,0 +1,125 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
+
+Qualcomm generic boards
+=======================
+
+About this
+----------
+This document describes how to build and run U-Boot for Qualcomm generic
+boards. Right now the generic target supports the Snapdragon 845 SoC, however
+it's expected to support more SoCs going forward.
+
+SDM845 - high-end qualcomm chip, introduced in late 2017.
+Mostly used in flagship phones and tablets of 2018.
+
+The current boot flow support loading u-boot as an Android boot image via
+Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will
+be appended to the U-Boot image the same way as when booting Linux. U-Boot
+will then retrieve the DTB during init. This way the memory layout and KASLR
+offset will be populated by ABL.
+
+Installation
+------------
+Build
+^^^^^
+
+	$ ./tools/buildman/buildman -o .output qcom
+
+This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``.
+
+Generate FIT image (optional)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+See doc/uImage.FIT for more details
+
+Pack android boot image
+^^^^^^^^^^^^^^^^^^^^^^^
+We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux kernel,
+and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
+with appended dtb, so let's mimic linux to satisfy stock bootloader.
+
+Boards
+------
+
+starqlte
+^^^^^^^^
+
+The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
+based on the Qualcomm SDM845 SoC.
+
+This device is supported by the common qcom_defconfig.
+
+The DTB is called "sdm845-samsung-starqltechn.dtb"
+
+More information can be found on the `Samsung S9 page`_.
+
+dragonboard845c
+^^^^^^^^^^^^^^^
+
+The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
+the Qualcomm SDM845 SoC.
+
+This device is supported by the common qcom_defconfig
+
+The DTB is called "sdm845-db845c.dtb"
+
+More information can be found on the `DragonBoard 845c page`_.
+
+qcs404-evb
+^^^^^^^^^^
+
+The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm QCS404 SoC.
+
+This device is supported by the common qcom_defconfig
+
+The DTB is called "qcs404-evb-4000.dtb"
+
+Building steps
+--------------
+
+Steps:
+
+- Build u-boot
+
+As above::
+
+	./tools/buildman/buildman -o .output qcom
+
+Or for db410c (and other boards not supported by the generic target)::
+
+	make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig
+	make O=.output -j$(nproc)
+
+- gzip u-boot::
+
+	gzip u-boot-nodtb.bin
+
+- Append dtb to gzipped u-boot::
+
+	cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > u-boot-nodtb.bin.gz-dtb
+
+- If you chose to build a FIT image, A ``qcom.its`` file can be found in ``board/qualcomm/generic/``
+  directory. It expects a folder as ``qcom_imgs/`` in the main directory containing pre-built kernel,
+  dts and ramdisk images. See ``qcom.its`` for full path to images::
+
+	mkimage -f qcom.its qcom.itb
+
+- Now we've got everything to build android boot image::
+
+	mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \
+	--output boot.img --pagesize 4096 --base 0x80000000
+
+Or with no FIT image::
+
+	mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \
+	--output boot.img --pagesize 4096 --base 0x80000000
+
+- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB:
+
+  .. code-block:: bash
+
+	fastboot flash boot boot.img
+	fastboot erase dtbo
+
+.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
+.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/
diff --git a/doc/board/qualcomm/debugging.rst b/doc/board/qualcomm/debugging.rst
new file mode 100644
index 000000000000..1c35d1909d12
--- /dev/null
+++ b/doc/board/qualcomm/debugging.rst
@@ -0,0 +1,61 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org>
+
+Qualcomm debugging
+==================
+
+About this
+----------
+
+This page describes how to enable early UART and other debugging techniques
+for Qualcomm boards.
+
+Enable debug UART
+-----------------
+
+Newer boards (SDM845 and newer, those with GENI SE UART)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Open ``configs/qcom_defconfig`` and add the following snippet to the bottom:
+
+	CONFIG_BAUDRATE=115200
+
+	# Uncomment to enable UART pre-relocation
+	CONFIG_DEBUG_UART=y
+	CONFIG_DEBUG_UART_ANNOUNCE=y
+	# This is the address of the debug-uart peripheral
+	# The value here is for SDM845, other platforms will vary
+	CONFIG_DEBUG_UART_BASE=0xa84000
+	# Boards older than ~2018 pre-date the GENI driver and unfortunately
+	# aren't supported here
+	CONFIG_DEBUG_UART_MSM_GENI=y
+	# For sdm845 this is the UART clock rate
+	CONFIG_DEBUG_UART_CLOCK=7372800
+	# Most newer boards have an oversampling value of 16 instead
+	# of 32, they need the clock rate to be doubled
+	#CONFIG_DEBUG_UART_CLOCK=14745600
+
+Then build as normal (don't forget to ``make qcom_defconfig``` again).
+
+Older boards (db410c and db820c)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Open ``configs/dragonboard<BOARD>_defconfig``
+
+	CONFIG_BAUDRATE=115200
+	CONFIG_DEBUG_UART=y
+	CONFIG_DEBUG_UART_ANNOUNCE=y
+	# db410c - 0x78b0000
+	# db820c - 0x75b0000
+	CONFIG_DEBUG_UART_BASE=0x75b0000
+	CONFIG_DEBUG_UART_MSM=y
+	CONFIG_DEBUG_UART_CLOCK=7372800
+	#CONFIG_DEBUG_UART_SKIP_INIT=y
+
+	CONFIG_LOG=y
+	CONFIG_HEXDUMP=y
+	CONFIG_CMD_LOG=y
+	CONFIG_LOG_MAX_LEVEL=9
+	CONFIG_LOG_DEFAULT_LEVEL=9
+	CONFIG_LOGLEVEL=9
+
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 0f9c4299569a..4955274a39bc 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -7,5 +7,5 @@ Qualcomm
    :maxdepth: 2
 
    dragonboard410c
-   sdm845
-   qcs404
+   board
+   debugging
diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
deleted file mode 100644
index 0cb71d97c987..000000000000
--- a/doc/board/qualcomm/qcs404.rst
+++ /dev/null
@@ -1,79 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
-
-QCS404 EVB
-==========
-
-About this
-----------
-This document describes the information about Qualcomm QCS404 evaluation board
-and it's usage steps.
-
-The current boot flow support loading u-boot as an Android boot image via
-Qualcomm's UEFI-based ABL (Android) Bootloader.
-
-Installation
-------------
-Build
-^^^^^
-Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
-
-	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
-	$ make qcs404evb_defconfig
-	$ make
-
-This will build ``u-boot.bin`` in the configured output directory.
-
-Generate FIT image
-^^^^^^^^^^^^^^^^^^
-A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
-It expects a folder as ``qcs404_imgs/`` in the main directory containing
-pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
-images.
-
-- Build FIT image::
-
-	mkimage -f qcs404-evb.its qcs404-evb.itb
-
-Pack android boot image
-^^^^^^^^^^^^^^^^^^^^^^^
-We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
-and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
-with appended dtb, so let's mimic linux to satisfy stock bootloader:
-
-- create dump dtb::
-
-	workdir=/tmp/prepare_payload
-	mkdir -p "$workdir"
-	cd "$workdir"
-	mock_dtb="$workdir"/payload_mock.dtb
-
-	dtc -I dts -O dtb -o "$mock_dtb" << EOF
-	/dts-v1/;
-	/ {
-		model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
-		compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
-
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		memory@80000000 {
-			device_type = "memory";
-			/* We expect the bootloader to fill in the size */
-			reg = <0 0x80000000 0 0>;
-		};
-
-		chosen { };
-	};
-	EOF
-
-- gzip u-boot ``gzip u-boot.bin``
-- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
-
-Now we've got everything to build android boot image:::
-
-	mkbootimg --kernel u-boot.bin.gz-dtb \
-	--ramdisk qcs404-evb.itb --pagesize 4096 \
-	--base 0x80000000 --output boot.img
-
-Flash image on qcs404-evb using fastboot method.
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
deleted file mode 100644
index a65f00df39f5..000000000000
--- a/doc/board/qualcomm/sdm845.rst
+++ /dev/null
@@ -1,167 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
-
-Snapdragon 845
-==============
-
-About this
-----------
-
-This document describes the information about Qualcomm Snapdragon 845
-supported boards and it's usage steps.
-
-SDM845 - hi-end qualcomm chip, introduced in late 2017.
-Mostly used in flagship phones and tablets of 2018.
-
-The current boot flow support loading u-boot as an Android boot image via
-Qualcomm's UEFI-based ABL (Android) Bootloader.
-
-Installation
-------------
-
-Build
-^^^^^
-
-Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
-
-	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
-	$ make <your board name here, see Boards section>_defconfig
-	$ make
-
-This will build ``u-boot.bin`` in the configured output directory.
-
-Generate FIT image
-^^^^^^^^^^^^^^^^^^
-
-See doc/uImage.FIT for more details
-
-Pack android boot image
-^^^^^^^^^^^^^^^^^^^^^^^
-
-We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
-and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
-with appended dtb, so let's mimic linux to satisfy stock bootloader.
-
-Boards
-------
-
-starqlte
-^^^^^^^^
-
-The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
-based on the Qualcomm SDM845 SoC.
-
-Steps:
-
-- Build u-boot::
-
-	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
-	$ make starqltechn_defconfig
-	$ make
-
-- Create dump dtb::
-
-	workdir=/tmp/prepare_payload
-	mkdir -p "$workdir"
-	cd "$workdir"
-	mock_dtb="$workdir"/payload_mock.dtb
-
-	dtc -I dts -O dtb -o "$mock_dtb" << EOF
-	/dts-v1/;
-	/ {
-		memory {
-			/* We expect the bootloader to fill in the size */
-			reg = <0 0 0 0>;
-		};
-
-		chosen { };
-	};
-	EOF
-
-- gzip u-boot::
-
-	gzip u-boot.bin
-
-- Append dtb to gzipped u-boot::
-
-	cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
-
-- Now we've got everything to build android boot image::
-
-	mkbootimg --base 0x0 --kernel_offset 0x00008000 \
-	--ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
-	--pagesize 4096 --second_offset 0x00f00000 \
-	--ramdisk "$fit_image" \
-	--kernel u-boot.bin.gz-dtb \
-	-o boot.img
-
-- Flash image with your phone's flashing method.
-
-More information can be found on the `Samsung S9 page`_.
-
-dragonboard845c
-^^^^^^^^^^^^^^^
-
-The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
-the Qualcomm SDM845 SoC.
-
-Steps:
-
-- Build u-boot::
-
-	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
-	$ make dragonboard845c_defconfig
-	$ make
-
-- Create dummy dtb::
-
-	workdir=/tmp/prepare_payload
-	mkdir -p "$workdir"
-	mock_dtb="$workdir"/payload_mock.dtb
-
-	dtc -I dts -O dtb -o "$mock_dtb" << EOF
-	/dts-v1/;
-	/ {
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		memory@80000000 {
-			device_type = "memory";
-			/* We expect the bootloader to fill in the size */
-			reg = <0 0x80000000 0 0>;
-		};
-
-		chosen { };
-	};
-	EOF
-
-- gzip u-boot::
-
-	gzip u-boot.bin
-
-- Append dtb to gzipped u-boot::
-
-	 cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
-
-- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
-  directory. It expects a folder as ``db845c_imgs/`` in the main directory
-  containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
-  for full path to images::
-
-	mkimage -f db845c.its db845c.itb
-
-- Now we've got everything to build android boot image::
-
-	mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
-	--output boot.img --pagesize 4096 --base 0x80000000
-
-- Flash boot.img using db845c fastboot method:
-
-  .. code-block:: bash
-
-      sudo fastboot flash boot boot.img
-
-More information can be found on the `DragonBoard 845c page`_.
-
-.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
-.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/

-- 
2.43.1

[PATCH v4 26/39] doc: board/qualcomm: link to APQ8016 TRM

[Caleb Connolly]

The MSM8916/APQ8016 Technical Reference Manual is publicly available and
contains a lot of useful register maps for many core parts of the SoC.
Include an archive.org link to it in the dragonboard410c documentation.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 doc/board/qualcomm/dragonboard410c.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/doc/board/qualcomm/dragonboard410c.rst b/doc/board/qualcomm/dragonboard410c.rst
index d0de9dbcbc9a..34629241110c 100644
--- a/doc/board/qualcomm/dragonboard410c.rst
+++ b/doc/board/qualcomm/dragonboard410c.rst
@@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can replace LK entirely.
 
 .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/
 
+.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf
+
 Installation
 ------------
 First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``::

-- 
2.43.1

[PATCH v4 27/39] dt-bindings: import headers for SDM845

[Caleb Connolly]

Import the DT bindings headers that are used by SDM845 from Linux.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 include/dt-bindings/clock/qcom,camcc-sdm845.h      | 116 ++++++
 include/dt-bindings/clock/qcom,dispcc-sdm845.h     |  56 +++
 include/dt-bindings/clock/qcom,gpucc-sdm845.h      |  24 ++
 include/dt-bindings/clock/qcom,lpass-sdm845.h      |  15 +
 include/dt-bindings/clock/qcom,rpmh.h              |  37 ++
 include/dt-bindings/clock/qcom,videocc-sdm845.h    |  35 ++
 include/dt-bindings/dma/qcom-gpi.h                 |  11 +
 include/dt-bindings/firmware/qcom,scm.h            |  39 ++
 include/dt-bindings/iio/qcom,spmi-vadc.h           | 300 +++++++++++++++
 include/dt-bindings/interconnect/qcom,osm-l3.h     |  15 +
 include/dt-bindings/interconnect/qcom,sdm845.h     | 150 ++++++++
 include/dt-bindings/phy/phy-qcom-qmp.h             |  20 +
 include/dt-bindings/phy/phy-qcom-qusb2.h           |  37 ++
 include/dt-bindings/pinctrl/qcom,pmic-gpio.h       | 164 ++++++++
 include/dt-bindings/power/qcom-rpmpd.h             | 412 +++++++++++++++++++++
 .../dt-bindings/regulator/qcom,rpmh-regulator.h    |  36 ++
 include/dt-bindings/reset/qcom,sdm845-aoss.h       |  17 +
 include/dt-bindings/reset/qcom,sdm845-pdc.h        |  22 ++
 include/dt-bindings/soc/qcom,apr.h                 |  28 ++
 include/dt-bindings/soc/qcom,rpmh-rsc.h            |  14 +
 include/dt-bindings/sound/qcom,q6afe.h             |   9 +
 include/dt-bindings/sound/qcom,q6asm.h             |  26 ++
 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 234 ++++++++++++
 23 files changed, 1817 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
new file mode 100644
index 000000000000..4f7a2d2320bf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
+
+/* CAM_CC clock registers */
+#define CAM_CC_BPS_AHB_CLK				0
+#define CAM_CC_BPS_AREG_CLK				1
+#define CAM_CC_BPS_AXI_CLK				2
+#define CAM_CC_BPS_CLK					3
+#define CAM_CC_BPS_CLK_SRC				4
+#define CAM_CC_CAMNOC_ATB_CLK				5
+#define CAM_CC_CAMNOC_AXI_CLK				6
+#define CAM_CC_CCI_CLK					7
+#define CAM_CC_CCI_CLK_SRC				8
+#define CAM_CC_CPAS_AHB_CLK				9
+#define CAM_CC_CPHY_RX_CLK_SRC				10
+#define CAM_CC_CSI0PHYTIMER_CLK				11
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC			12
+#define CAM_CC_CSI1PHYTIMER_CLK				13
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC			14
+#define CAM_CC_CSI2PHYTIMER_CLK				15
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC			16
+#define CAM_CC_CSI3PHYTIMER_CLK				17
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC			18
+#define CAM_CC_CSIPHY0_CLK				19
+#define CAM_CC_CSIPHY1_CLK				20
+#define CAM_CC_CSIPHY2_CLK				21
+#define CAM_CC_CSIPHY3_CLK				22
+#define CAM_CC_FAST_AHB_CLK_SRC				23
+#define CAM_CC_FD_CORE_CLK				24
+#define CAM_CC_FD_CORE_CLK_SRC				25
+#define CAM_CC_FD_CORE_UAR_CLK				26
+#define CAM_CC_ICP_APB_CLK				27
+#define CAM_CC_ICP_ATB_CLK				28
+#define CAM_CC_ICP_CLK					29
+#define CAM_CC_ICP_CLK_SRC				30
+#define CAM_CC_ICP_CTI_CLK				31
+#define CAM_CC_ICP_TS_CLK				32
+#define CAM_CC_IFE_0_AXI_CLK				33
+#define CAM_CC_IFE_0_CLK				34
+#define CAM_CC_IFE_0_CLK_SRC				35
+#define CAM_CC_IFE_0_CPHY_RX_CLK			36
+#define CAM_CC_IFE_0_CSID_CLK				37
+#define CAM_CC_IFE_0_CSID_CLK_SRC			38
+#define CAM_CC_IFE_0_DSP_CLK				39
+#define CAM_CC_IFE_1_AXI_CLK				40
+#define CAM_CC_IFE_1_CLK				41
+#define CAM_CC_IFE_1_CLK_SRC				42
+#define CAM_CC_IFE_1_CPHY_RX_CLK			43
+#define CAM_CC_IFE_1_CSID_CLK				44
+#define CAM_CC_IFE_1_CSID_CLK_SRC			45
+#define CAM_CC_IFE_1_DSP_CLK				46
+#define CAM_CC_IFE_LITE_CLK				47
+#define CAM_CC_IFE_LITE_CLK_SRC				48
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK			49
+#define CAM_CC_IFE_LITE_CSID_CLK			50
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC			51
+#define CAM_CC_IPE_0_AHB_CLK				52
+#define CAM_CC_IPE_0_AREG_CLK				53
+#define CAM_CC_IPE_0_AXI_CLK				54
+#define CAM_CC_IPE_0_CLK				55
+#define CAM_CC_IPE_0_CLK_SRC				56
+#define CAM_CC_IPE_1_AHB_CLK				57
+#define CAM_CC_IPE_1_AREG_CLK				58
+#define CAM_CC_IPE_1_AXI_CLK				59
+#define CAM_CC_IPE_1_CLK				60
+#define CAM_CC_IPE_1_CLK_SRC				61
+#define CAM_CC_JPEG_CLK					62
+#define CAM_CC_JPEG_CLK_SRC				63
+#define CAM_CC_LRME_CLK					64
+#define CAM_CC_LRME_CLK_SRC				65
+#define CAM_CC_MCLK0_CLK				66
+#define CAM_CC_MCLK0_CLK_SRC				67
+#define CAM_CC_MCLK1_CLK				68
+#define CAM_CC_MCLK1_CLK_SRC				69
+#define CAM_CC_MCLK2_CLK				70
+#define CAM_CC_MCLK2_CLK_SRC				71
+#define CAM_CC_MCLK3_CLK				72
+#define CAM_CC_MCLK3_CLK_SRC				73
+#define CAM_CC_PLL0					74
+#define CAM_CC_PLL0_OUT_EVEN				75
+#define CAM_CC_PLL1					76
+#define CAM_CC_PLL1_OUT_EVEN				77
+#define CAM_CC_PLL2					78
+#define CAM_CC_PLL2_OUT_EVEN				79
+#define CAM_CC_PLL3					80
+#define CAM_CC_PLL3_OUT_EVEN				81
+#define CAM_CC_SLOW_AHB_CLK_SRC				82
+#define CAM_CC_SOC_AHB_CLK				83
+#define CAM_CC_SYS_TMR_CLK				84
+
+/* CAM_CC Resets */
+#define TITAN_CAM_CC_CCI_BCR				0
+#define TITAN_CAM_CC_CPAS_BCR				1
+#define TITAN_CAM_CC_CSI0PHY_BCR			2
+#define TITAN_CAM_CC_CSI1PHY_BCR			3
+#define TITAN_CAM_CC_CSI2PHY_BCR			4
+#define TITAN_CAM_CC_MCLK0_BCR				5
+#define TITAN_CAM_CC_MCLK1_BCR				6
+#define TITAN_CAM_CC_MCLK2_BCR				7
+#define TITAN_CAM_CC_MCLK3_BCR				8
+#define TITAN_CAM_CC_TITAN_TOP_BCR			9
+
+/* CAM_CC GDSCRs */
+#define BPS_GDSC					0
+#define IPE_0_GDSC					1
+#define IPE_1_GDSC					2
+#define IFE_0_GDSC					3
+#define IFE_1_GDSC					4
+#define TITAN_TOP_GDSC					5
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index 000000000000..4016fd1d5b46
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK					0
+#define DISP_CC_MDSS_AXI_CLK					1
+#define DISP_CC_MDSS_BYTE0_CLK					2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				4
+#define DISP_CC_MDSS_BYTE1_CLK					5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				7
+#define DISP_CC_MDSS_ESC0_CLK					8
+#define DISP_CC_MDSS_ESC0_CLK_SRC				9
+#define DISP_CC_MDSS_ESC1_CLK					10
+#define DISP_CC_MDSS_ESC1_CLK_SRC				11
+#define DISP_CC_MDSS_MDP_CLK					12
+#define DISP_CC_MDSS_MDP_CLK_SRC				13
+#define DISP_CC_MDSS_MDP_LUT_CLK				14
+#define DISP_CC_MDSS_PCLK0_CLK					15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				16
+#define DISP_CC_MDSS_PCLK1_CLK					17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				18
+#define DISP_CC_MDSS_ROT_CLK					19
+#define DISP_CC_MDSS_ROT_CLK_SRC				20
+#define DISP_CC_MDSS_RSCC_AHB_CLK				21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
+#define DISP_CC_MDSS_VSYNC_CLK					23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				24
+#define DISP_CC_PLL0						25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
+#define DISP_CC_MDSS_DP_AUX_CLK					28
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC				29
+#define DISP_CC_MDSS_DP_CRYPTO_CLK				30
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				31
+#define DISP_CC_MDSS_DP_LINK_CLK				32
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC				33
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK				34
+#define DISP_CC_MDSS_DP_PIXEL1_CLK				35
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				36
+#define DISP_CC_MDSS_DP_PIXEL_CLK				37
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				38
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR					0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
new file mode 100644
index 000000000000..9690d901b50a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_CX_GMU_CLK			0
+#define GPU_CC_CXO_CLK				1
+#define GPU_CC_GMU_CLK_SRC			2
+#define GPU_CC_PLL1				3
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_CX_BCR			0
+#define GPUCC_GPU_CC_GMU_BCR			1
+#define GPUCC_GPU_CC_XO_BCR			2
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC				0
+#define GPU_GX_GDSC				1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h
new file mode 100644
index 000000000000..659050846f61
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lpass-sdm845.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
+
+#define LPASS_Q6SS_AHBM_AON_CLK				0
+#define LPASS_Q6SS_AHBS_AON_CLK				1
+#define LPASS_QDSP6SS_XO_CLK				2
+#define LPASS_QDSP6SS_SLEEP_CLK				3
+#define LPASS_QDSP6SS_CORE_CLK				4
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 000000000000..0a7d1be0d124
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK				0
+#define RPMH_CXO_CLK_A				1
+#define RPMH_LN_BB_CLK2				2
+#define RPMH_LN_BB_CLK2_A			3
+#define RPMH_LN_BB_CLK3				4
+#define RPMH_LN_BB_CLK3_A			5
+#define RPMH_RF_CLK1				6
+#define RPMH_RF_CLK1_A				7
+#define RPMH_RF_CLK2				8
+#define RPMH_RF_CLK2_A				9
+#define RPMH_RF_CLK3				10
+#define RPMH_RF_CLK3_A				11
+#define RPMH_IPA_CLK				12
+#define RPMH_LN_BB_CLK1				13
+#define RPMH_LN_BB_CLK1_A			14
+#define RPMH_CE_CLK				15
+#define RPMH_QPIC_CLK				16
+#define RPMH_DIV_CLK1				17
+#define RPMH_DIV_CLK1_A				18
+#define RPMH_RF_CLK4				19
+#define RPMH_RF_CLK4_A				20
+#define RPMH_RF_CLK5				21
+#define RPMH_RF_CLK5_A				22
+#define RPMH_PKA_CLK				23
+#define RPMH_HWKM_CLK				24
+#define RPMH_QLINK_CLK				25
+#define RPMH_QLINK_CLK_A			26
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 000000000000..1b868165e8ce
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+
+/* VIDEO_CC clock registers */
+#define VIDEO_CC_APB_CLK		0
+#define VIDEO_CC_AT_CLK			1
+#define VIDEO_CC_QDSS_TRIG_CLK		2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK	3
+#define VIDEO_CC_VCODEC0_AXI_CLK	4
+#define VIDEO_CC_VCODEC0_CORE_CLK	5
+#define VIDEO_CC_VCODEC1_AXI_CLK	6
+#define VIDEO_CC_VCODEC1_CORE_CLK	7
+#define VIDEO_CC_VENUS_AHB_CLK		8
+#define VIDEO_CC_VENUS_CLK_SRC		9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK	10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK	11
+#define VIDEO_PLL0			12
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_VENUS_BCR		0
+#define VIDEO_CC_VCODEC0_BCR		1
+#define VIDEO_CC_VCODEC1_BCR		2
+#define VIDEO_CC_INTERFACE_BCR		3
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC			0
+#define VCODEC0_GDSC			1
+#define VCODEC1_GDSC			2
+
+#endif
diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h
new file mode 100644
index 000000000000..ebda2a37f52a
--- /dev/null
+++ b/include/dt-bindings/dma/qcom-gpi.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright (c) 2020, Linaro Ltd.  */
+
+#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
+#define __DT_BINDINGS_DMA_QCOM_GPI_H__
+
+#define QCOM_GPI_SPI		1
+#define QCOM_GPI_UART		2
+#define QCOM_GPI_I2C		3
+
+#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */
diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h
new file mode 100644
index 000000000000..6de8b08e1e79
--- /dev/null
+++ b/include/dt-bindings/firmware/qcom,scm.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
+#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
+
+#define QCOM_SCM_VMID_TZ		0x1
+#define QCOM_SCM_VMID_HLOS		0x3
+#define QCOM_SCM_VMID_SSC_Q6		0x5
+#define QCOM_SCM_VMID_ADSP_Q6		0x6
+#define QCOM_SCM_VMID_CP_TOUCH		0x8
+#define QCOM_SCM_VMID_CP_BITSTREAM	0x9
+#define QCOM_SCM_VMID_CP_PIXEL		0xA
+#define QCOM_SCM_VMID_CP_NON_PIXEL	0xB
+#define QCOM_SCM_VMID_CP_CAMERA		0xD
+#define QCOM_SCM_VMID_HLOS_FREE		0xE
+#define QCOM_SCM_VMID_MSS_MSA		0xF
+#define QCOM_SCM_VMID_MSS_NONMSA	0x10
+#define QCOM_SCM_VMID_CP_SEC_DISPLAY	0x11
+#define QCOM_SCM_VMID_CP_APP		0x12
+#define QCOM_SCM_VMID_LPASS		0x16
+#define QCOM_SCM_VMID_WLAN		0x18
+#define QCOM_SCM_VMID_WLAN_CE		0x19
+#define QCOM_SCM_VMID_CP_SPSS_SP	0x1A
+#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D
+#define QCOM_SCM_VMID_CDSP		0x1E
+#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22
+#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24
+#define QCOM_SCM_VMID_ADSP_HEAP		0x25
+#define QCOM_SCM_VMID_CP_CDSP		0x2A
+#define QCOM_SCM_VMID_NAV		0x2B
+#define QCOM_SCM_VMID_TVM		0x2D
+#define QCOM_SCM_VMID_OEMVM		0x31
+
+#endif
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
new file mode 100644
index 000000000000..08adfe25964c
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_H
+
+/* Voltage ADC channels */
+#define VADC_USBIN				0x00
+#define VADC_DCIN				0x01
+#define VADC_VCHG_SNS				0x02
+#define VADC_SPARE1_03				0x03
+#define VADC_USB_ID_MV				0x04
+#define VADC_VCOIN				0x05
+#define VADC_VBAT_SNS				0x06
+#define VADC_VSYS				0x07
+#define VADC_DIE_TEMP				0x08
+#define VADC_REF_625MV				0x09
+#define VADC_REF_1250MV				0x0a
+#define VADC_CHG_TEMP				0x0b
+#define VADC_SPARE1				0x0c
+#define VADC_SPARE2				0x0d
+#define VADC_GND_REF				0x0e
+#define VADC_VDD_VADC				0x0f
+
+#define VADC_P_MUX1_1_1				0x10
+#define VADC_P_MUX2_1_1				0x11
+#define VADC_P_MUX3_1_1				0x12
+#define VADC_P_MUX4_1_1				0x13
+#define VADC_P_MUX5_1_1				0x14
+#define VADC_P_MUX6_1_1				0x15
+#define VADC_P_MUX7_1_1				0x16
+#define VADC_P_MUX8_1_1				0x17
+#define VADC_P_MUX9_1_1				0x18
+#define VADC_P_MUX10_1_1			0x19
+#define VADC_P_MUX11_1_1			0x1a
+#define VADC_P_MUX12_1_1			0x1b
+#define VADC_P_MUX13_1_1			0x1c
+#define VADC_P_MUX14_1_1			0x1d
+#define VADC_P_MUX15_1_1			0x1e
+#define VADC_P_MUX16_1_1			0x1f
+
+#define VADC_P_MUX1_1_3				0x20
+#define VADC_P_MUX2_1_3				0x21
+#define VADC_P_MUX3_1_3				0x22
+#define VADC_P_MUX4_1_3				0x23
+#define VADC_P_MUX5_1_3				0x24
+#define VADC_P_MUX6_1_3				0x25
+#define VADC_P_MUX7_1_3				0x26
+#define VADC_P_MUX8_1_3				0x27
+#define VADC_P_MUX9_1_3				0x28
+#define VADC_P_MUX10_1_3			0x29
+#define VADC_P_MUX11_1_3			0x2a
+#define VADC_P_MUX12_1_3			0x2b
+#define VADC_P_MUX13_1_3			0x2c
+#define VADC_P_MUX14_1_3			0x2d
+#define VADC_P_MUX15_1_3			0x2e
+#define VADC_P_MUX16_1_3			0x2f
+
+#define VADC_LR_MUX1_BAT_THERM			0x30
+#define VADC_LR_MUX2_BAT_ID			0x31
+#define VADC_LR_MUX3_XO_THERM			0x32
+#define VADC_LR_MUX4_AMUX_THM1			0x33
+#define VADC_LR_MUX5_AMUX_THM2			0x34
+#define VADC_LR_MUX6_AMUX_THM3			0x35
+#define VADC_LR_MUX7_HW_ID			0x36
+#define VADC_LR_MUX8_AMUX_THM4			0x37
+#define VADC_LR_MUX9_AMUX_THM5			0x38
+#define VADC_LR_MUX10_USB_ID			0x39
+#define VADC_AMUX_PU1				0x3a
+#define VADC_AMUX_PU2				0x3b
+#define VADC_LR_MUX3_BUF_XO_THERM		0x3c
+
+#define VADC_LR_MUX1_PU1_BAT_THERM		0x70
+#define VADC_LR_MUX2_PU1_BAT_ID			0x71
+#define VADC_LR_MUX3_PU1_XO_THERM		0x72
+#define VADC_LR_MUX4_PU1_AMUX_THM1		0x73
+#define VADC_LR_MUX5_PU1_AMUX_THM2		0x74
+#define VADC_LR_MUX6_PU1_AMUX_THM3		0x75
+#define VADC_LR_MUX7_PU1_AMUX_HW_ID		0x76
+#define VADC_LR_MUX8_PU1_AMUX_THM4		0x77
+#define VADC_LR_MUX9_PU1_AMUX_THM5		0x78
+#define VADC_LR_MUX10_PU1_AMUX_USB_ID		0x79
+#define VADC_LR_MUX3_BUF_PU1_XO_THERM		0x7c
+
+#define VADC_LR_MUX1_PU2_BAT_THERM		0xb0
+#define VADC_LR_MUX2_PU2_BAT_ID			0xb1
+#define VADC_LR_MUX3_PU2_XO_THERM		0xb2
+#define VADC_LR_MUX4_PU2_AMUX_THM1		0xb3
+#define VADC_LR_MUX5_PU2_AMUX_THM2		0xb4
+#define VADC_LR_MUX6_PU2_AMUX_THM3		0xb5
+#define VADC_LR_MUX7_PU2_AMUX_HW_ID		0xb6
+#define VADC_LR_MUX8_PU2_AMUX_THM4		0xb7
+#define VADC_LR_MUX9_PU2_AMUX_THM5		0xb8
+#define VADC_LR_MUX10_PU2_AMUX_USB_ID		0xb9
+#define VADC_LR_MUX3_BUF_PU2_XO_THERM		0xbc
+
+#define VADC_LR_MUX1_PU1_PU2_BAT_THERM		0xf0
+#define VADC_LR_MUX2_PU1_PU2_BAT_ID		0xf1
+#define VADC_LR_MUX3_PU1_PU2_XO_THERM		0xf2
+#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1		0xf3
+#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2		0xf4
+#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3		0xf5
+#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID		0xf6
+#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4		0xf7
+#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5		0xf8
+#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9
+#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc
+
+/* ADC channels for SPMI PMIC5 */
+
+#define ADC5_REF_GND				0x00
+#define ADC5_1P25VREF				0x01
+#define ADC5_VREF_VADC				0x02
+#define ADC5_VREF_VADC5_DIV_3			0x82
+#define ADC5_VPH_PWR				0x83
+#define ADC5_VBAT_SNS				0x84
+#define ADC5_VCOIN				0x85
+#define ADC5_DIE_TEMP				0x06
+#define ADC5_USB_IN_I				0x07
+#define ADC5_USB_IN_V_16			0x08
+#define ADC5_CHG_TEMP				0x09
+#define ADC5_BAT_THERM				0x0a
+#define ADC5_BAT_ID				0x0b
+#define ADC5_XO_THERM				0x0c
+#define ADC5_AMUX_THM1				0x0d
+#define ADC5_AMUX_THM2				0x0e
+#define ADC5_AMUX_THM3				0x0f
+#define ADC5_AMUX_THM4				0x10
+#define ADC5_AMUX_THM5				0x11
+#define ADC5_GPIO1				0x12
+#define ADC5_GPIO2				0x13
+#define ADC5_GPIO3				0x14
+#define ADC5_GPIO4				0x15
+#define ADC5_GPIO5				0x16
+#define ADC5_GPIO6				0x17
+#define ADC5_GPIO7				0x18
+#define ADC5_SBUx				0x99
+#define ADC5_MID_CHG_DIV6			0x1e
+#define ADC5_OFF				0xff
+
+/* 30k pull-up1 */
+#define ADC5_BAT_THERM_30K_PU			0x2a
+#define ADC5_BAT_ID_30K_PU			0x2b
+#define ADC5_XO_THERM_30K_PU			0x2c
+#define ADC5_AMUX_THM1_30K_PU			0x2d
+#define ADC5_AMUX_THM2_30K_PU			0x2e
+#define ADC5_AMUX_THM3_30K_PU			0x2f
+#define ADC5_AMUX_THM4_30K_PU			0x30
+#define ADC5_AMUX_THM5_30K_PU			0x31
+#define ADC5_GPIO1_30K_PU			0x32
+#define ADC5_GPIO2_30K_PU			0x33
+#define ADC5_GPIO3_30K_PU			0x34
+#define ADC5_GPIO4_30K_PU			0x35
+#define ADC5_GPIO5_30K_PU			0x36
+#define ADC5_GPIO6_30K_PU			0x37
+#define ADC5_GPIO7_30K_PU			0x38
+#define ADC5_SBUx_30K_PU			0x39
+
+/* 100k pull-up2 */
+#define ADC5_BAT_THERM_100K_PU			0x4a
+#define ADC5_BAT_ID_100K_PU			0x4b
+#define ADC5_XO_THERM_100K_PU			0x4c
+#define ADC5_AMUX_THM1_100K_PU			0x4d
+#define ADC5_AMUX_THM2_100K_PU			0x4e
+#define ADC5_AMUX_THM3_100K_PU			0x4f
+#define ADC5_AMUX_THM4_100K_PU			0x50
+#define ADC5_AMUX_THM5_100K_PU			0x51
+#define ADC5_GPIO1_100K_PU			0x52
+#define ADC5_GPIO2_100K_PU			0x53
+#define ADC5_GPIO3_100K_PU			0x54
+#define ADC5_GPIO4_100K_PU			0x55
+#define ADC5_GPIO5_100K_PU			0x56
+#define ADC5_GPIO6_100K_PU			0x57
+#define ADC5_GPIO7_100K_PU			0x58
+#define ADC5_SBUx_100K_PU			0x59
+
+/* 400k pull-up3 */
+#define ADC5_BAT_THERM_400K_PU			0x6a
+#define ADC5_BAT_ID_400K_PU			0x6b
+#define ADC5_XO_THERM_400K_PU			0x6c
+#define ADC5_AMUX_THM1_400K_PU			0x6d
+#define ADC5_AMUX_THM2_400K_PU			0x6e
+#define ADC5_AMUX_THM3_400K_PU			0x6f
+#define ADC5_AMUX_THM4_400K_PU			0x70
+#define ADC5_AMUX_THM5_400K_PU			0x71
+#define ADC5_GPIO1_400K_PU			0x72
+#define ADC5_GPIO2_400K_PU			0x73
+#define ADC5_GPIO3_400K_PU			0x74
+#define ADC5_GPIO4_400K_PU			0x75
+#define ADC5_GPIO5_400K_PU			0x76
+#define ADC5_GPIO6_400K_PU			0x77
+#define ADC5_GPIO7_400K_PU			0x78
+#define ADC5_SBUx_400K_PU			0x79
+
+/* 1/3 Divider */
+#define ADC5_GPIO1_DIV3				0x92
+#define ADC5_GPIO2_DIV3				0x93
+#define ADC5_GPIO3_DIV3				0x94
+#define ADC5_GPIO4_DIV3				0x95
+#define ADC5_GPIO5_DIV3				0x96
+#define ADC5_GPIO6_DIV3				0x97
+#define ADC5_GPIO7_DIV3				0x98
+#define ADC5_SBUx_DIV3				0x99
+
+/* Current and combined current/voltage channels */
+#define ADC5_INT_EXT_ISENSE			0xa1
+#define ADC5_PARALLEL_ISENSE			0xa5
+#define ADC5_CUR_REPLICA_VDS			0xa7
+#define ADC5_CUR_SENS_BATFET_VDS_OFFSET		0xa9
+#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET	0xab
+#define ADC5_EXT_SENS_OFFSET			0xad
+
+#define ADC5_INT_EXT_ISENSE_VBAT_VDATA		0xb0
+#define ADC5_INT_EXT_ISENSE_VBAT_IDATA		0xb1
+#define ADC5_EXT_ISENSE_VBAT_VDATA		0xb2
+#define ADC5_EXT_ISENSE_VBAT_IDATA		0xb3
+#define ADC5_PARALLEL_ISENSE_VBAT_VDATA		0xb4
+#define ADC5_PARALLEL_ISENSE_VBAT_IDATA		0xb5
+
+#define ADC5_MAX_CHANNEL			0xc0
+
+/* ADC channels for ADC for PMIC7 */
+
+#define ADC7_REF_GND				0x00
+#define ADC7_1P25VREF				0x01
+#define ADC7_VREF_VADC				0x02
+#define ADC7_DIE_TEMP				0x03
+
+#define ADC7_AMUX_THM1				0x04
+#define ADC7_AMUX_THM2				0x05
+#define ADC7_AMUX_THM3				0x06
+#define ADC7_AMUX_THM4				0x07
+#define ADC7_AMUX_THM5				0x08
+#define ADC7_AMUX_THM6				0x09
+#define ADC7_GPIO1				0x0a
+#define ADC7_GPIO2				0x0b
+#define ADC7_GPIO3				0x0c
+#define ADC7_GPIO4				0x0d
+
+#define ADC7_CHG_TEMP				0x10
+#define ADC7_USB_IN_V_16			0x11
+#define ADC7_VDC_16				0x12
+#define ADC7_CC1_ID				0x13
+#define ADC7_VREF_BAT_THERM			0x15
+#define ADC7_IIN_FB				0x17
+
+/* 30k pull-up1 */
+#define ADC7_AMUX_THM1_30K_PU			0x24
+#define ADC7_AMUX_THM2_30K_PU			0x25
+#define ADC7_AMUX_THM3_30K_PU			0x26
+#define ADC7_AMUX_THM4_30K_PU			0x27
+#define ADC7_AMUX_THM5_30K_PU			0x28
+#define ADC7_AMUX_THM6_30K_PU			0x29
+#define ADC7_GPIO1_30K_PU			0x2a
+#define ADC7_GPIO2_30K_PU			0x2b
+#define ADC7_GPIO3_30K_PU			0x2c
+#define ADC7_GPIO4_30K_PU			0x2d
+#define ADC7_CC1_ID_30K_PU			0x33
+
+/* 100k pull-up2 */
+#define ADC7_AMUX_THM1_100K_PU			0x44
+#define ADC7_AMUX_THM2_100K_PU			0x45
+#define ADC7_AMUX_THM3_100K_PU			0x46
+#define ADC7_AMUX_THM4_100K_PU			0x47
+#define ADC7_AMUX_THM5_100K_PU			0x48
+#define ADC7_AMUX_THM6_100K_PU			0x49
+#define ADC7_GPIO1_100K_PU			0x4a
+#define ADC7_GPIO2_100K_PU			0x4b
+#define ADC7_GPIO3_100K_PU			0x4c
+#define ADC7_GPIO4_100K_PU			0x4d
+#define ADC7_CC1_ID_100K_PU			0x53
+
+/* 400k pull-up3 */
+#define ADC7_AMUX_THM1_400K_PU			0x64
+#define ADC7_AMUX_THM2_400K_PU			0x65
+#define ADC7_AMUX_THM3_400K_PU			0x66
+#define ADC7_AMUX_THM4_400K_PU			0x67
+#define ADC7_AMUX_THM5_400K_PU			0x68
+#define ADC7_AMUX_THM6_400K_PU			0x69
+#define ADC7_GPIO1_400K_PU			0x6a
+#define ADC7_GPIO2_400K_PU			0x6b
+#define ADC7_GPIO3_400K_PU			0x6c
+#define ADC7_GPIO4_400K_PU			0x6d
+#define ADC7_CC1_ID_400K_PU			0x73
+
+/* 1/3 Divider */
+#define ADC7_GPIO1_DIV3				0x8a
+#define ADC7_GPIO2_DIV3				0x8b
+#define ADC7_GPIO3_DIV3				0x8c
+#define ADC7_GPIO4_DIV3				0x8d
+
+#define ADC7_VPH_PWR				0x8e
+#define ADC7_VBAT_SNS				0x8f
+
+#define ADC7_SBUx				0x94
+#define ADC7_VBAT_2S_MID			0x96
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
new file mode 100644
index 000000000000..61ef649ae565
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+
+#define MASTER_OSM_L3_APPS	0
+#define SLAVE_OSM_L3		1
+
+#define MASTER_EPSS_L3_APPS	0
+#define SLAVE_EPSS_L3_SHARED	1
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
new file mode 100644
index 000000000000..67b500e24915
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sdm845.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm SDM845 interconnect IDs
+ *
+ * Copyright (c) 2018, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
+
+#define MASTER_A1NOC_CFG		0
+#define MASTER_TSIF			1
+#define MASTER_SDCC_2			2
+#define MASTER_SDCC_4			3
+#define MASTER_UFS_CARD			4
+#define MASTER_UFS_MEM			5
+#define MASTER_PCIE_0			6
+#define SLAVE_A1NOC_SNOC		7
+#define SLAVE_SERVICE_A1NOC		8
+#define SLAVE_ANOC_PCIE_A1NOC_SNOC	9
+#define MASTER_QUP_1			10
+
+#define MASTER_A2NOC_CFG		0
+#define MASTER_QDSS_BAM			1
+#define MASTER_CNOC_A2NOC		2
+#define MASTER_CRYPTO			3
+#define MASTER_IPA			4
+#define MASTER_PCIE_1			5
+#define MASTER_QDSS_ETR			6
+#define MASTER_USB3_0			7
+#define MASTER_USB3_1			8
+#define SLAVE_A2NOC_SNOC		9
+#define SLAVE_ANOC_PCIE_SNOC		10
+#define SLAVE_SERVICE_A2NOC		11
+#define MASTER_QUP_2			12
+
+#define MASTER_SPDM			0
+#define MASTER_TIC			1
+#define MASTER_SNOC_CNOC		2
+#define MASTER_QDSS_DAP			3
+#define SLAVE_A1NOC_CFG			4
+#define SLAVE_A2NOC_CFG			5
+#define SLAVE_AOP			6
+#define SLAVE_AOSS			7
+#define SLAVE_CAMERA_CFG		8
+#define SLAVE_CLK_CTL			9
+#define SLAVE_CDSP_CFG			10
+#define SLAVE_RBCPR_CX_CFG		11
+#define SLAVE_CRYPTO_0_CFG		12
+#define SLAVE_DCC_CFG			13
+#define SLAVE_CNOC_DDRSS		14
+#define SLAVE_DISPLAY_CFG		15
+#define SLAVE_GLM			16
+#define SLAVE_GFX3D_CFG			17
+#define SLAVE_IMEM_CFG			18
+#define SLAVE_IPA_CFG			19
+#define SLAVE_CNOC_MNOC_CFG		20
+#define SLAVE_PCIE_0_CFG		21
+#define SLAVE_PCIE_1_CFG		22
+#define SLAVE_PDM			23
+#define SLAVE_SOUTH_PHY_CFG		24
+#define SLAVE_PIMEM_CFG			25
+#define SLAVE_PRNG			26
+#define SLAVE_QDSS_CFG			27
+#define SLAVE_BLSP_2			28
+#define SLAVE_BLSP_1			29
+#define SLAVE_SDCC_2			30
+#define SLAVE_SDCC_4			31
+#define SLAVE_SNOC_CFG			32
+#define SLAVE_SPDM_WRAPPER		33
+#define SLAVE_SPSS_CFG			34
+#define SLAVE_TCSR			35
+#define SLAVE_TLMM_NORTH		36
+#define SLAVE_TLMM_SOUTH		37
+#define SLAVE_TSIF			38
+#define SLAVE_UFS_CARD_CFG		39
+#define SLAVE_UFS_MEM_CFG		40
+#define SLAVE_USB3_0			41
+#define SLAVE_USB3_1			42
+#define SLAVE_VENUS_CFG			43
+#define SLAVE_VSENSE_CTRL_CFG		44
+#define SLAVE_CNOC_A2NOC		45
+#define SLAVE_SERVICE_CNOC		46
+
+#define MASTER_CNOC_DC_NOC		0
+#define SLAVE_LLCC_CFG			1
+#define SLAVE_MEM_NOC_CFG		2
+
+#define MASTER_APPSS_PROC		0
+#define MASTER_GNOC_CFG			1
+#define SLAVE_GNOC_SNOC			2
+#define SLAVE_GNOC_MEM_NOC		3
+#define SLAVE_SERVICE_GNOC		4
+
+#define MASTER_TCU_0			0
+#define MASTER_MEM_NOC_CFG		1
+#define MASTER_GNOC_MEM_NOC		2
+#define MASTER_MNOC_HF_MEM_NOC		3
+#define MASTER_MNOC_SF_MEM_NOC		4
+#define MASTER_SNOC_GC_MEM_NOC		5
+#define MASTER_SNOC_SF_MEM_NOC		6
+#define MASTER_GFX3D			7
+#define SLAVE_MSS_PROC_MS_MPU_CFG	8
+#define SLAVE_MEM_NOC_GNOC		9
+#define SLAVE_LLCC			10
+#define SLAVE_MEM_NOC_SNOC		11
+#define SLAVE_SERVICE_MEM_NOC		12
+#define MASTER_LLCC			13
+#define SLAVE_EBI1			14
+
+#define MASTER_CNOC_MNOC_CFG		0
+#define MASTER_CAMNOC_HF0		1
+#define MASTER_CAMNOC_HF1		2
+#define MASTER_CAMNOC_SF		3
+#define MASTER_MDP0			4
+#define MASTER_MDP1			5
+#define MASTER_ROTATOR			6
+#define MASTER_VIDEO_P0			7
+#define MASTER_VIDEO_P1			8
+#define MASTER_VIDEO_PROC		9
+#define SLAVE_MNOC_SF_MEM_NOC		10
+#define SLAVE_MNOC_HF_MEM_NOC		11
+#define SLAVE_SERVICE_MNOC		12
+#define MASTER_CAMNOC_HF0_UNCOMP	13
+#define MASTER_CAMNOC_HF1_UNCOMP	14
+#define MASTER_CAMNOC_SF_UNCOMP		15
+#define SLAVE_CAMNOC_UNCOMP		16
+
+#define MASTER_SNOC_CFG			0
+#define MASTER_A1NOC_SNOC		1
+#define MASTER_A2NOC_SNOC		2
+#define MASTER_GNOC_SNOC		3
+#define MASTER_MEM_NOC_SNOC		4
+#define MASTER_ANOC_PCIE_SNOC		5
+#define MASTER_PIMEM			6
+#define MASTER_GIC			7
+#define SLAVE_APPSS			8
+#define SLAVE_SNOC_CNOC			9
+#define SLAVE_SNOC_MEM_NOC_GC		10
+#define SLAVE_SNOC_MEM_NOC_SF		11
+#define SLAVE_IMEM			12
+#define SLAVE_PCIE_0			13
+#define SLAVE_PCIE_1			14
+#define SLAVE_PIMEM			15
+#define SLAVE_SERVICE_SNOC		16
+#define SLAVE_QDSS_STM			17
+#define SLAVE_TCU			18
+
+#endif
diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
new file mode 100644
index 000000000000..4edec4c5b224
--- /dev/null
+++ b/include/dt-bindings/phy/phy-qcom-qmp.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
+/*
+ * Qualcomm QMP PHY constants
+ *
+ * Copyright (C) 2022 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_PHY_QMP
+#define _DT_BINDINGS_PHY_QMP
+
+/* QMP USB4-USB3-DP clocks */
+#define QMP_USB43DP_USB3_PIPE_CLK	0
+#define QMP_USB43DP_DP_LINK_CLK		1
+#define QMP_USB43DP_DP_VCO_DIV_CLK	2
+
+/* QMP USB4-USB3-DP PHYs */
+#define QMP_USB43DP_USB3_PHY		0
+#define QMP_USB43DP_DP_PHY		1
+
+#endif /* _DT_BINDINGS_PHY_QMP */
diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h
new file mode 100644
index 000000000000..5c5e4d800cac
--- /dev/null
+++ b/include/dt-bindings/phy/phy-qcom-qusb2.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_
+#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_
+
+/* PHY HSTX TRIM bit values (24mA to 15mA) */
+#define QUSB2_V2_HSTX_TRIM_24_0_MA		0x0
+#define QUSB2_V2_HSTX_TRIM_23_4_MA		0x1
+#define QUSB2_V2_HSTX_TRIM_22_8_MA		0x2
+#define QUSB2_V2_HSTX_TRIM_22_2_MA		0x3
+#define QUSB2_V2_HSTX_TRIM_21_6_MA		0x4
+#define QUSB2_V2_HSTX_TRIM_21_0_MA		0x5
+#define QUSB2_V2_HSTX_TRIM_20_4_MA		0x6
+#define QUSB2_V2_HSTX_TRIM_19_8_MA		0x7
+#define QUSB2_V2_HSTX_TRIM_19_2_MA		0x8
+#define QUSB2_V2_HSTX_TRIM_18_6_MA		0x9
+#define QUSB2_V2_HSTX_TRIM_18_0_MA		0xa
+#define QUSB2_V2_HSTX_TRIM_17_4_MA		0xb
+#define QUSB2_V2_HSTX_TRIM_16_8_MA		0xc
+#define QUSB2_V2_HSTX_TRIM_16_2_MA		0xd
+#define QUSB2_V2_HSTX_TRIM_15_6_MA		0xe
+#define QUSB2_V2_HSTX_TRIM_15_0_MA		0xf
+
+/* PHY PREEMPHASIS bit values */
+#define QUSB2_V2_PREEMPHASIS_NONE		0
+#define QUSB2_V2_PREEMPHASIS_5_PERCENT		1
+#define QUSB2_V2_PREEMPHASIS_10_PERCENT		2
+#define QUSB2_V2_PREEMPHASIS_15_PERCENT		3
+
+/* PHY PREEMPHASIS-WIDTH bit values */
+#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT	0
+#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT	1
+
+#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
new file mode 100644
index 000000000000..e5df5ce45a0f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the Qualcomm PMIC GPIO binding.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
+#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
+
+#define PMIC_GPIO_PULL_UP_30		0
+#define PMIC_GPIO_PULL_UP_1P5		1
+#define PMIC_GPIO_PULL_UP_31P5		2
+#define PMIC_GPIO_PULL_UP_1P5_30	3
+
+#define PMIC_GPIO_STRENGTH_NO		0
+#define PMIC_GPIO_STRENGTH_HIGH		1
+#define PMIC_GPIO_STRENGTH_MED		2
+#define PMIC_GPIO_STRENGTH_LOW		3
+
+/*
+ * Note: PM8018 GPIO3 and GPIO4 are supporting
+ * only S3 and L2 options (1.8V)
+ */
+#define PM8018_GPIO_L6			0
+#define PM8018_GPIO_L5			1
+#define PM8018_GPIO_S3			2
+#define PM8018_GPIO_L14			3
+#define PM8018_GPIO_L2			4
+#define PM8018_GPIO_L4			5
+#define PM8018_GPIO_VDD			6
+
+/*
+ * Note: PM8038 GPIO7 and GPIO8 are supporting
+ * only L11 and L4 options (1.8V)
+ */
+#define PM8038_GPIO_VPH			0
+#define PM8038_GPIO_BB			1
+#define PM8038_GPIO_L11			2
+#define PM8038_GPIO_L15			3
+#define PM8038_GPIO_L4			4
+#define PM8038_GPIO_L3			5
+#define PM8038_GPIO_L17			6
+
+#define PM8058_GPIO_VPH			0
+#define PM8058_GPIO_BB			1
+#define PM8058_GPIO_S3			2
+#define PM8058_GPIO_L3			3
+#define PM8058_GPIO_L7			4
+#define PM8058_GPIO_L6			5
+#define PM8058_GPIO_L5			6
+#define PM8058_GPIO_L2			7
+
+/*
+ * Note: PM8916 GPIO1 and GPIO2 are supporting
+ * only L2(1.15V) and L5(1.8V) options
+ */
+#define PM8916_GPIO_VPH			0
+#define PM8916_GPIO_L2			2
+#define PM8916_GPIO_L5			3
+
+#define PM8917_GPIO_VPH			0
+#define PM8917_GPIO_S4			2
+#define PM8917_GPIO_L15			3
+#define PM8917_GPIO_L4			4
+#define PM8917_GPIO_L3			5
+#define PM8917_GPIO_L17			6
+
+#define PM8921_GPIO_VPH			0
+#define PM8921_GPIO_BB			1
+#define PM8921_GPIO_S4			2
+#define PM8921_GPIO_L15			3
+#define PM8921_GPIO_L4			4
+#define PM8921_GPIO_L3			5
+#define PM8921_GPIO_L17			6
+
+/*
+ * Note: PM8941 gpios from 15 to 18 are supporting
+ * only S3 and L6 options (1.8V)
+ */
+#define PM8941_GPIO_VPH			0
+#define PM8941_GPIO_L1			1
+#define PM8941_GPIO_S3			2
+#define PM8941_GPIO_L6			3
+
+/*
+ * Note: PMA8084 gpios from 15 to 18 are supporting
+ * only S4 and L6 options (1.8V)
+ */
+#define PMA8084_GPIO_VPH		0
+#define PMA8084_GPIO_L1			1
+#define PMA8084_GPIO_S4			2
+#define PMA8084_GPIO_L6			3
+
+#define PM8994_GPIO_VPH			0
+#define PM8994_GPIO_S4			2
+#define PM8994_GPIO_L12			3
+
+/* To be used with "function" */
+#define PMIC_GPIO_FUNC_NORMAL		"normal"
+#define PMIC_GPIO_FUNC_PAIRED		"paired"
+#define PMIC_GPIO_FUNC_FUNC1		"func1"
+#define PMIC_GPIO_FUNC_FUNC2		"func2"
+#define PMIC_GPIO_FUNC_FUNC3		"func3"
+#define PMIC_GPIO_FUNC_FUNC4		"func4"
+#define PMIC_GPIO_FUNC_DTEST1		"dtest1"
+#define PMIC_GPIO_FUNC_DTEST2		"dtest2"
+#define PMIC_GPIO_FUNC_DTEST3		"dtest3"
+#define PMIC_GPIO_FUNC_DTEST4		"dtest4"
+
+#define PM8038_GPIO1_2_LPG_DRV		PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO3_5V_BOOST_EN	PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO4_SSBI_ALT_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO5_6_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO10_11_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO6_7_CLK		PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO9_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
+#define PM8038_GPIO6_12_KYPD_DRV	PMIC_GPIO_FUNC_FUNC2
+
+#define PM8058_GPIO7_8_MP3_CLK		PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO7_8_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC2
+#define PM8058_GPIO9_26_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO21_23_UART_TX	PMIC_GPIO_FUNC_FUNC2
+#define PM8058_GPIO24_26_LPG_DRV	PMIC_GPIO_FUNC_FUNC2
+#define PM8058_GPIO33_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO34_35_MP3_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO36_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO37_UPL_OUT		PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO37_UART_M_RX		PMIC_GPIO_FUNC_FUNC2
+#define PM8058_GPIO38_XO_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO38_39_CLK_32KHZ	PMIC_GPIO_FUNC_FUNC2
+#define PM8058_GPIO39_MP3_CLK		PMIC_GPIO_FUNC_FUNC1
+#define PM8058_GPIO40_EXT_BB_EN		PMIC_GPIO_FUNC_FUNC1
+
+#define PM8916_GPIO1_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO1_KEYP_DRV		PMIC_GPIO_FUNC_FUNC2
+#define PM8916_GPIO2_DIV_CLK		PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO2_SLEEP_CLK		PMIC_GPIO_FUNC_FUNC2
+#define PM8916_GPIO3_KEYP_DRV		PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO4_KEYP_DRV		PMIC_GPIO_FUNC_FUNC2
+
+#define PM8917_GPIO9_18_KEYP_DRV	PMIC_GPIO_FUNC_FUNC1
+#define PM8917_GPIO20_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
+#define PM8917_GPIO21_23_UART_TX	PMIC_GPIO_FUNC_FUNC2
+#define PM8917_GPIO25_26_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
+#define PM8917_GPIO37_38_XO_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PM8917_GPIO37_38_MP3_CLK	PMIC_GPIO_FUNC_FUNC2
+
+#define PM8941_GPIO9_14_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
+#define PM8941_GPIO15_18_DIV_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PM8941_GPIO15_18_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC2
+#define PM8941_GPIO23_26_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
+#define PM8941_GPIO23_26_LPG_DRV_HI	PMIC_GPIO_FUNC_FUNC2
+#define PM8941_GPIO31_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
+#define PM8941_GPIO33_36_LPG_DRV_3D	PMIC_GPIO_FUNC_FUNC1
+#define PM8941_GPIO33_36_LPG_DRV_HI	PMIC_GPIO_FUNC_FUNC2
+
+#define PMA8084_GPIO4_5_LPG_DRV		PMIC_GPIO_FUNC_FUNC1
+#define PMA8084_GPIO7_10_LPG_DRV	PMIC_GPIO_FUNC_FUNC1
+#define PMA8084_GPIO5_14_KEYP_DRV	PMIC_GPIO_FUNC_FUNC2
+#define PMA8084_GPIO19_21_KEYP_DRV	PMIC_GPIO_FUNC_FUNC2
+#define PMA8084_GPIO15_18_DIV_CLK	PMIC_GPIO_FUNC_FUNC1
+#define PMA8084_GPIO15_18_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC2
+#define PMA8084_GPIO22_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
+
+#endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
new file mode 100644
index 000000000000..7f4e2983a4c5
--- /dev/null
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
+#define _DT_BINDINGS_POWER_QCOM_RPMPD_H
+
+/* SA8775P Power Domain Indexes */
+#define SA8775P_CX	0
+#define SA8775P_CX_AO	1
+#define SA8775P_DDR	2
+#define SA8775P_EBI	3
+#define SA8775P_GFX	4
+#define SA8775P_LCX	5
+#define SA8775P_LMX	6
+#define SA8775P_MMCX	7
+#define SA8775P_MMCX_AO	8
+#define SA8775P_MSS	9
+#define SA8775P_MX	10
+#define SA8775P_MX_AO	11
+#define SA8775P_MXC	12
+#define SA8775P_MXC_AO	13
+#define SA8775P_NSP0	14
+#define SA8775P_NSP1	15
+#define SA8775P_XO	16
+
+/* SDM670 Power Domain Indexes */
+#define SDM670_MX	0
+#define SDM670_MX_AO	1
+#define SDM670_CX	2
+#define SDM670_CX_AO	3
+#define SDM670_LMX	4
+#define SDM670_LCX	5
+#define SDM670_GFX	6
+#define SDM670_MSS	7
+
+/* SDM845 Power Domain Indexes */
+#define SDM845_EBI	0
+#define SDM845_MX	1
+#define SDM845_MX_AO	2
+#define SDM845_CX	3
+#define SDM845_CX_AO	4
+#define SDM845_LMX	5
+#define SDM845_LCX	6
+#define SDM845_GFX	7
+#define SDM845_MSS	8
+
+/* SDX55 Power Domain Indexes */
+#define SDX55_MSS	0
+#define SDX55_MX	1
+#define SDX55_CX	2
+
+/* SDX65 Power Domain Indexes */
+#define SDX65_MSS	0
+#define SDX65_MX	1
+#define SDX65_MX_AO	2
+#define SDX65_CX	3
+#define SDX65_CX_AO	4
+#define SDX65_MXC	5
+
+/* SM6350 Power Domain Indexes */
+#define SM6350_CX	0
+#define SM6350_GFX	1
+#define SM6350_LCX	2
+#define SM6350_LMX	3
+#define SM6350_MSS	4
+#define SM6350_MX	5
+
+/* SM6350 Power Domain Indexes */
+#define SM6375_VDDCX		0
+#define SM6375_VDDCX_AO	1
+#define SM6375_VDDCX_VFL	2
+#define SM6375_VDDMX		3
+#define SM6375_VDDMX_AO	4
+#define SM6375_VDDMX_VFL	5
+#define SM6375_VDDGX		6
+#define SM6375_VDDGX_AO	7
+#define SM6375_VDD_LPI_CX	8
+#define SM6375_VDD_LPI_MX	9
+
+/* SM8150 Power Domain Indexes */
+#define SM8150_MSS	0
+#define SM8150_EBI	1
+#define SM8150_LMX	2
+#define SM8150_LCX	3
+#define SM8150_GFX	4
+#define SM8150_MX	5
+#define SM8150_MX_AO	6
+#define SM8150_CX	7
+#define SM8150_CX_AO	8
+#define SM8150_MMCX	9
+#define SM8150_MMCX_AO	10
+
+/* SA8155P is a special case, kept for backwards compatibility */
+#define SA8155P_CX	SM8150_CX
+#define SA8155P_CX_AO	SM8150_CX_AO
+#define SA8155P_EBI	SM8150_EBI
+#define SA8155P_GFX	SM8150_GFX
+#define SA8155P_MSS	SM8150_MSS
+#define SA8155P_MX	SM8150_MX
+#define SA8155P_MX_AO	SM8150_MX_AO
+
+/* SM8250 Power Domain Indexes */
+#define SM8250_CX	0
+#define SM8250_CX_AO	1
+#define SM8250_EBI	2
+#define SM8250_GFX	3
+#define SM8250_LCX	4
+#define SM8250_LMX	5
+#define SM8250_MMCX	6
+#define SM8250_MMCX_AO	7
+#define SM8250_MX	8
+#define SM8250_MX_AO	9
+
+/* SM8350 Power Domain Indexes */
+#define SM8350_CX	0
+#define SM8350_CX_AO	1
+#define SM8350_EBI	2
+#define SM8350_GFX	3
+#define SM8350_LCX	4
+#define SM8350_LMX	5
+#define SM8350_MMCX	6
+#define SM8350_MMCX_AO	7
+#define SM8350_MX	8
+#define SM8350_MX_AO	9
+#define SM8350_MXC	10
+#define SM8350_MXC_AO	11
+#define SM8350_MSS	12
+
+/* SM8450 Power Domain Indexes */
+#define SM8450_CX	0
+#define SM8450_CX_AO	1
+#define SM8450_EBI	2
+#define SM8450_GFX	3
+#define SM8450_LCX	4
+#define SM8450_LMX	5
+#define SM8450_MMCX	6
+#define SM8450_MMCX_AO	7
+#define SM8450_MX	8
+#define SM8450_MX_AO	9
+#define SM8450_MXC	10
+#define SM8450_MXC_AO	11
+#define SM8450_MSS	12
+
+/* SM8550 Power Domain Indexes */
+#define SM8550_CX	0
+#define SM8550_CX_AO	1
+#define SM8550_EBI	2
+#define SM8550_GFX	3
+#define SM8550_LCX	4
+#define SM8550_LMX	5
+#define SM8550_MMCX	6
+#define SM8550_MMCX_AO	7
+#define SM8550_MX	8
+#define SM8550_MX_AO	9
+#define SM8550_MXC	10
+#define SM8550_MXC_AO	11
+#define SM8550_MSS	12
+#define SM8550_NSP	13
+
+/* QDU1000/QRU1000 Power Domain Indexes */
+#define QDU1000_EBI	0
+#define QDU1000_MSS	1
+#define QDU1000_CX	2
+#define QDU1000_MX	3
+
+/* SC7180 Power Domain Indexes */
+#define SC7180_CX	0
+#define SC7180_CX_AO	1
+#define SC7180_GFX	2
+#define SC7180_MX	3
+#define SC7180_MX_AO	4
+#define SC7180_LMX	5
+#define SC7180_LCX	6
+#define SC7180_MSS	7
+
+/* SC7280 Power Domain Indexes */
+#define SC7280_CX	0
+#define SC7280_CX_AO	1
+#define SC7280_EBI	2
+#define SC7280_GFX	3
+#define SC7280_MX	4
+#define SC7280_MX_AO	5
+#define SC7280_LMX	6
+#define SC7280_LCX	7
+#define SC7280_MSS	8
+
+/* SC8180X Power Domain Indexes */
+#define SC8180X_CX	0
+#define SC8180X_CX_AO	1
+#define SC8180X_EBI	2
+#define SC8180X_GFX	3
+#define SC8180X_LCX	4
+#define SC8180X_LMX	5
+#define SC8180X_MMCX	6
+#define SC8180X_MMCX_AO	7
+#define SC8180X_MSS	8
+#define SC8180X_MX	9
+#define SC8180X_MX_AO	10
+
+/* SC8280XP Power Domain Indexes */
+#define SC8280XP_CX		0
+#define SC8280XP_CX_AO		1
+#define SC8280XP_DDR		2
+#define SC8280XP_EBI		3
+#define SC8280XP_GFX		4
+#define SC8280XP_LCX		5
+#define SC8280XP_LMX		6
+#define SC8280XP_MMCX		7
+#define SC8280XP_MMCX_AO	8
+#define SC8280XP_MSS		9
+#define SC8280XP_MX		10
+#define SC8280XP_MXC		12
+#define SC8280XP_MX_AO		11
+#define SC8280XP_NSP		13
+#define SC8280XP_QPHY		14
+#define SC8280XP_XO		15
+
+/* SDM845 Power Domain performance levels */
+#define RPMH_REGULATOR_LEVEL_RETENTION		16
+#define RPMH_REGULATOR_LEVEL_MIN_SVS		48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
+#define RPMH_REGULATOR_LEVEL_LOW_SVS		64
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1		80
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2		96
+#define RPMH_REGULATOR_LEVEL_SVS		128
+#define RPMH_REGULATOR_LEVEL_SVS_L0		144
+#define RPMH_REGULATOR_LEVEL_SVS_L1		192
+#define RPMH_REGULATOR_LEVEL_SVS_L2		224
+#define RPMH_REGULATOR_LEVEL_NOM		256
+#define RPMH_REGULATOR_LEVEL_NOM_L0		288
+#define RPMH_REGULATOR_LEVEL_NOM_L1		320
+#define RPMH_REGULATOR_LEVEL_NOM_L2		336
+#define RPMH_REGULATOR_LEVEL_TURBO		384
+#define RPMH_REGULATOR_LEVEL_TURBO_L0		400
+#define RPMH_REGULATOR_LEVEL_TURBO_L1		416
+#define RPMH_REGULATOR_LEVEL_TURBO_L2		432
+#define RPMH_REGULATOR_LEVEL_TURBO_L3		448
+#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
+#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
+
+/* MDM9607 Power Domains */
+#define MDM9607_VDDCX		0
+#define MDM9607_VDDCX_AO	1
+#define MDM9607_VDDCX_VFL	2
+#define MDM9607_VDDMX		3
+#define MDM9607_VDDMX_AO	4
+#define MDM9607_VDDMX_VFL	5
+
+/* MSM8226 Power Domain Indexes */
+#define MSM8226_VDDCX		0
+#define MSM8226_VDDCX_AO	1
+#define MSM8226_VDDCX_VFC	2
+
+/* MSM8939 Power Domains */
+#define MSM8939_VDDMDCX		0
+#define MSM8939_VDDMDCX_AO	1
+#define MSM8939_VDDMDCX_VFC	2
+#define MSM8939_VDDCX		3
+#define MSM8939_VDDCX_AO	4
+#define MSM8939_VDDCX_VFC	5
+#define MSM8939_VDDMX		6
+#define MSM8939_VDDMX_AO	7
+
+/* MSM8916 Power Domain Indexes */
+#define MSM8916_VDDCX		0
+#define MSM8916_VDDCX_AO	1
+#define MSM8916_VDDCX_VFC	2
+#define MSM8916_VDDMX		3
+#define MSM8916_VDDMX_AO	4
+
+/* MSM8909 Power Domain Indexes */
+#define MSM8909_VDDCX		MSM8916_VDDCX
+#define MSM8909_VDDCX_AO	MSM8916_VDDCX_AO
+#define MSM8909_VDDCX_VFC	MSM8916_VDDCX_VFC
+#define MSM8909_VDDMX		MSM8916_VDDMX
+#define MSM8909_VDDMX_AO	MSM8916_VDDMX_AO
+
+/* MSM8917 Power Domain Indexes */
+#define MSM8917_VDDCX		0
+#define MSM8917_VDDCX_AO	1
+#define MSM8917_VDDCX_VFL	2
+#define MSM8917_VDDMX		3
+#define MSM8917_VDDMX_AO	4
+
+/* MSM8937 Power Domain Indexes */
+#define MSM8937_VDDCX		MSM8917_VDDCX
+#define MSM8937_VDDCX_AO	MSM8917_VDDCX_AO
+#define MSM8937_VDDCX_VFL	MSM8917_VDDCX_VFL
+#define MSM8937_VDDMX		MSM8917_VDDMX
+#define MSM8937_VDDMX_AO	MSM8917_VDDMX_AO
+
+/* QM215 Power Domain Indexes */
+#define QM215_VDDCX		MSM8917_VDDCX
+#define QM215_VDDCX_AO		MSM8917_VDDCX_AO
+#define QM215_VDDCX_VFL		MSM8917_VDDCX_VFL
+#define QM215_VDDMX		MSM8917_VDDMX
+#define QM215_VDDMX_AO		MSM8917_VDDMX_AO
+
+/* MSM8953 Power Domain Indexes */
+#define MSM8953_VDDMD		0
+#define MSM8953_VDDMD_AO	1
+#define MSM8953_VDDCX		2
+#define MSM8953_VDDCX_AO	3
+#define MSM8953_VDDCX_VFL	4
+#define MSM8953_VDDMX		5
+#define MSM8953_VDDMX_AO	6
+
+/* MSM8976 Power Domain Indexes */
+#define MSM8976_VDDCX		0
+#define MSM8976_VDDCX_AO	1
+#define MSM8976_VDDCX_VFL	2
+#define MSM8976_VDDMX		3
+#define MSM8976_VDDMX_AO	4
+#define MSM8976_VDDMX_VFL	5
+
+/* MSM8994 Power Domain Indexes */
+#define MSM8994_VDDCX		0
+#define MSM8994_VDDCX_AO	1
+#define MSM8994_VDDCX_VFC	2
+#define MSM8994_VDDMX		3
+#define MSM8994_VDDMX_AO	4
+#define MSM8994_VDDGFX		5
+#define MSM8994_VDDGFX_VFC	6
+
+/* MSM8996 Power Domain Indexes */
+#define MSM8996_VDDCX		0
+#define MSM8996_VDDCX_AO	1
+#define MSM8996_VDDCX_VFC	2
+#define MSM8996_VDDMX		3
+#define MSM8996_VDDMX_AO	4
+#define MSM8996_VDDSSCX		5
+#define MSM8996_VDDSSCX_VFC	6
+
+/* MSM8998 Power Domain Indexes */
+#define MSM8998_VDDCX		0
+#define MSM8998_VDDCX_AO	1
+#define MSM8998_VDDCX_VFL	2
+#define MSM8998_VDDMX		3
+#define MSM8998_VDDMX_AO	4
+#define MSM8998_VDDMX_VFL	5
+#define MSM8998_SSCCX		6
+#define MSM8998_SSCCX_VFL	7
+#define MSM8998_SSCMX		8
+#define MSM8998_SSCMX_VFL	9
+
+/* QCS404 Power Domains */
+#define QCS404_VDDMX		0
+#define QCS404_VDDMX_AO		1
+#define QCS404_VDDMX_VFL	2
+#define QCS404_LPICX		3
+#define QCS404_LPICX_VFL	4
+#define QCS404_LPIMX		5
+#define QCS404_LPIMX_VFL	6
+
+/* SDM660 Power Domains */
+#define SDM660_VDDCX		0
+#define SDM660_VDDCX_AO		1
+#define SDM660_VDDCX_VFL	2
+#define SDM660_VDDMX		3
+#define SDM660_VDDMX_AO		4
+#define SDM660_VDDMX_VFL	5
+#define SDM660_SSCCX		6
+#define SDM660_SSCCX_VFL	7
+#define SDM660_SSCMX		8
+#define SDM660_SSCMX_VFL	9
+
+/* SM6115 Power Domains */
+#define SM6115_VDDCX		0
+#define SM6115_VDDCX_AO		1
+#define SM6115_VDDCX_VFL	2
+#define SM6115_VDDMX		3
+#define SM6115_VDDMX_AO		4
+#define SM6115_VDDMX_VFL	5
+#define SM6115_VDD_LPI_CX	6
+#define SM6115_VDD_LPI_MX	7
+
+/* SM6125 Power Domains */
+#define SM6125_VDDCX		0
+#define SM6125_VDDCX_AO		1
+#define SM6125_VDDCX_VFL	2
+#define SM6125_VDDMX		3
+#define SM6125_VDDMX_AO		4
+#define SM6125_VDDMX_VFL	5
+
+/* QCM2290 Power Domains */
+#define QCM2290_VDDCX		0
+#define QCM2290_VDDCX_AO	1
+#define QCM2290_VDDCX_VFL	2
+#define QCM2290_VDDMX		3
+#define QCM2290_VDDMX_AO	4
+#define QCM2290_VDDMX_VFL	5
+#define QCM2290_VDD_LPI_CX	6
+#define QCM2290_VDD_LPI_MX	7
+
+/* RPM SMD Power Domain performance levels */
+#define RPM_SMD_LEVEL_RETENTION       16
+#define RPM_SMD_LEVEL_RETENTION_PLUS  32
+#define RPM_SMD_LEVEL_MIN_SVS         48
+#define RPM_SMD_LEVEL_LOW_SVS         64
+#define RPM_SMD_LEVEL_SVS             128
+#define RPM_SMD_LEVEL_SVS_PLUS        192
+#define RPM_SMD_LEVEL_NOM             256
+#define RPM_SMD_LEVEL_NOM_PLUS        320
+#define RPM_SMD_LEVEL_TURBO           384
+#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
+#define RPM_SMD_LEVEL_TURBO_HIGH      448
+#define RPM_SMD_LEVEL_BINNING         512
+
+#endif
diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
new file mode 100644
index 000000000000..86713dcf9e02
--- /dev/null
+++ b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+#ifndef __QCOM_RPMH_REGULATOR_H
+#define __QCOM_RPMH_REGULATOR_H
+
+/*
+ * These mode constants may be used to specify modes for various RPMh regulator
+ * device tree properties (e.g. regulator-initial-mode).  Each type of regulator
+ * supports a subset of the possible modes.
+ *
+ * %RPMH_REGULATOR_MODE_RET:	Retention mode in which only an extremely small
+ *				load current is allowed.  This mode is supported
+ *				by LDO and SMPS type regulators.
+ * %RPMH_REGULATOR_MODE_LPM:	Low power mode in which a small load current is
+ *				allowed.  This mode corresponds to PFM for SMPS
+ *				and BOB type regulators.  This mode is supported
+ *				by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
+ *				regulators.
+ * %RPMH_REGULATOR_MODE_AUTO:	Auto mode in which the regulator hardware
+ *				automatically switches between LPM and HPM based
+ *				upon the real-time load current.  This mode is
+ *				supported by HFSMPS, BOB, and PMIC4 FTSMPS type
+ *				regulators.
+ * %RPMH_REGULATOR_MODE_HPM:	High power mode in which the full rated current
+ *				of the regulator is allowed.  This mode
+ *				corresponds to PWM for SMPS and BOB type
+ *				regulators.  This mode is supported by all types
+ *				of regulators.
+ */
+#define RPMH_REGULATOR_MODE_RET		0
+#define RPMH_REGULATOR_MODE_LPM		1
+#define RPMH_REGULATOR_MODE_AUTO	2
+#define RPMH_REGULATOR_MODE_HPM		3
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
new file mode 100644
index 000000000000..476c5fc873b6
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART	0
+#define AOSS_CC_CAMSS_RESTART	1
+#define AOSS_CC_VENUS_RESTART	2
+#define AOSS_CC_GPU_RESTART	3
+#define AOSS_CC_DISPSS_RESTART	4
+#define AOSS_CC_WCSS_RESTART	5
+#define AOSS_CC_LPASS_RESTART	6
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
new file mode 100644
index 000000000000..03a0c0eb8147
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
+#define _DT_BINDINGS_RESET_PDC_SDM_845_H
+
+#define PDC_APPS_SYNC_RESET	0
+#define PDC_SP_SYNC_RESET	1
+#define PDC_AUDIO_SYNC_RESET	2
+#define PDC_SENSORS_SYNC_RESET	3
+#define PDC_AOP_SYNC_RESET	4
+#define PDC_DEBUG_SYNC_RESET	5
+#define PDC_GPU_SYNC_RESET	6
+#define PDC_DISPLAY_SYNC_RESET	7
+#define PDC_COMPUTE_SYNC_RESET	8
+#define PDC_MODEM_SYNC_RESET	9
+#define PDC_WLAN_RF_SYNC_RESET	10
+#define PDC_WPSS_SYNC_RESET	11
+
+#endif
diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h
new file mode 100644
index 000000000000..006362400c0f
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,apr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_QCOM_APR_H
+#define __DT_BINDINGS_QCOM_APR_H
+
+/* Domain IDs */
+#define APR_DOMAIN_SIM		0x1
+#define APR_DOMAIN_PC		0x2
+#define APR_DOMAIN_MODEM	0x3
+#define APR_DOMAIN_ADSP		0x4
+#define APR_DOMAIN_APPS		0x5
+#define APR_DOMAIN_MAX		0x6
+
+/* ADSP service IDs */
+#define APR_SVC_ADSP_CORE	0x3
+#define APR_SVC_AFE		0x4
+#define APR_SVC_VSM		0x5
+#define APR_SVC_VPM		0x6
+#define APR_SVC_ASM		0x7
+#define APR_SVC_ADM		0x8
+#define APR_SVC_ADSP_MVM	0x09
+#define APR_SVC_ADSP_CVS	0x0A
+#define APR_SVC_ADSP_CVP	0x0B
+#define APR_SVC_USM		0x0C
+#define APR_SVC_LSM		0x0D
+#define APR_SVC_VIDC		0x16
+#define APR_SVC_MAX		0x17
+
+#endif /* __DT_BINDINGS_QCOM_APR_H */
diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h
new file mode 100644
index 000000000000..868f998ea998
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,rpmh-rsc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_QCOM_RPMH_RSC_H__
+#define __DT_QCOM_RPMH_RSC_H__
+
+#define SLEEP_TCS	0
+#define WAKE_TCS	1
+#define ACTIVE_TCS	2
+#define CONTROL_TCS	3
+
+#endif /* __DT_QCOM_RPMH_RSC_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
new file mode 100644
index 000000000000..9d5d89cfabcf
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,q6afe.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_Q6_AFE_H__
+#define __DT_BINDINGS_Q6_AFE_H__
+
+/* This file exists due to backward compatibility reasons, Please do not DELETE! */
+
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+
+#endif /* __DT_BINDINGS_Q6_AFE_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h
new file mode 100644
index 000000000000..f59d74f14395
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,q6asm.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_Q6_ASM_H__
+#define __DT_BINDINGS_Q6_ASM_H__
+
+#define	MSM_FRONTEND_DAI_MULTIMEDIA1	0
+#define	MSM_FRONTEND_DAI_MULTIMEDIA2	1
+#define	MSM_FRONTEND_DAI_MULTIMEDIA3	2
+#define	MSM_FRONTEND_DAI_MULTIMEDIA4	3
+#define	MSM_FRONTEND_DAI_MULTIMEDIA5	4
+#define	MSM_FRONTEND_DAI_MULTIMEDIA6	5
+#define	MSM_FRONTEND_DAI_MULTIMEDIA7	6
+#define	MSM_FRONTEND_DAI_MULTIMEDIA8	7
+#define	MSM_FRONTEND_DAI_MULTIMEDIA9	8
+#define	MSM_FRONTEND_DAI_MULTIMEDIA10	9
+#define	MSM_FRONTEND_DAI_MULTIMEDIA11	10
+#define	MSM_FRONTEND_DAI_MULTIMEDIA12	11
+#define	MSM_FRONTEND_DAI_MULTIMEDIA13	12
+#define	MSM_FRONTEND_DAI_MULTIMEDIA14	13
+#define	MSM_FRONTEND_DAI_MULTIMEDIA15	14
+#define	MSM_FRONTEND_DAI_MULTIMEDIA16	15
+
+#define Q6ASM_DAI_TX_RX	0
+#define Q6ASM_DAI_TX	1
+#define Q6ASM_DAI_RX	2
+
+#endif /* __DT_BINDINGS_Q6_ASM_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
new file mode 100644
index 000000000000..39f203256c4f
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
+#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
+
+/* LPASS Audio virtual ports IDs */
+#define HDMI_RX		1
+#define SLIMBUS_0_RX    2
+#define SLIMBUS_0_TX    3
+#define SLIMBUS_1_RX    4
+#define SLIMBUS_1_TX    5
+#define SLIMBUS_2_RX    6
+#define SLIMBUS_2_TX    7
+#define SLIMBUS_3_RX    8
+#define SLIMBUS_3_TX    9
+#define SLIMBUS_4_RX    10
+#define SLIMBUS_4_TX    11
+#define SLIMBUS_5_RX    12
+#define SLIMBUS_5_TX    13
+#define SLIMBUS_6_RX    14
+#define SLIMBUS_6_TX    15
+#define PRIMARY_MI2S_RX		16
+#define PRIMARY_MI2S_TX		17
+#define SECONDARY_MI2S_RX	18
+#define SECONDARY_MI2S_TX	19
+#define TERTIARY_MI2S_RX	20
+#define TERTIARY_MI2S_TX	21
+#define QUATERNARY_MI2S_RX	22
+#define QUATERNARY_MI2S_TX	23
+#define PRIMARY_TDM_RX_0	24
+#define PRIMARY_TDM_TX_0	25
+#define PRIMARY_TDM_RX_1	26
+#define PRIMARY_TDM_TX_1	27
+#define PRIMARY_TDM_RX_2	28
+#define PRIMARY_TDM_TX_2	29
+#define PRIMARY_TDM_RX_3	30
+#define PRIMARY_TDM_TX_3	31
+#define PRIMARY_TDM_RX_4	32
+#define PRIMARY_TDM_TX_4	33
+#define PRIMARY_TDM_RX_5	34
+#define PRIMARY_TDM_TX_5	35
+#define PRIMARY_TDM_RX_6	36
+#define PRIMARY_TDM_TX_6	37
+#define PRIMARY_TDM_RX_7	38
+#define PRIMARY_TDM_TX_7	39
+#define SECONDARY_TDM_RX_0	40
+#define SECONDARY_TDM_TX_0	41
+#define SECONDARY_TDM_RX_1	42
+#define SECONDARY_TDM_TX_1	43
+#define SECONDARY_TDM_RX_2	44
+#define SECONDARY_TDM_TX_2	45
+#define SECONDARY_TDM_RX_3	46
+#define SECONDARY_TDM_TX_3	47
+#define SECONDARY_TDM_RX_4	48
+#define SECONDARY_TDM_TX_4	49
+#define SECONDARY_TDM_RX_5	50
+#define SECONDARY_TDM_TX_5	51
+#define SECONDARY_TDM_RX_6	52
+#define SECONDARY_TDM_TX_6	53
+#define SECONDARY_TDM_RX_7	54
+#define SECONDARY_TDM_TX_7	55
+#define TERTIARY_TDM_RX_0	56
+#define TERTIARY_TDM_TX_0	57
+#define TERTIARY_TDM_RX_1	58
+#define TERTIARY_TDM_TX_1	59
+#define TERTIARY_TDM_RX_2	60
+#define TERTIARY_TDM_TX_2	61
+#define TERTIARY_TDM_RX_3	62
+#define TERTIARY_TDM_TX_3	63
+#define TERTIARY_TDM_RX_4	64
+#define TERTIARY_TDM_TX_4	65
+#define TERTIARY_TDM_RX_5	66
+#define TERTIARY_TDM_TX_5	67
+#define TERTIARY_TDM_RX_6	68
+#define TERTIARY_TDM_TX_6	69
+#define TERTIARY_TDM_RX_7	70
+#define TERTIARY_TDM_TX_7	71
+#define QUATERNARY_TDM_RX_0	72
+#define QUATERNARY_TDM_TX_0	73
+#define QUATERNARY_TDM_RX_1	74
+#define QUATERNARY_TDM_TX_1	75
+#define QUATERNARY_TDM_RX_2	76
+#define QUATERNARY_TDM_TX_2	77
+#define QUATERNARY_TDM_RX_3	78
+#define QUATERNARY_TDM_TX_3	79
+#define QUATERNARY_TDM_RX_4	80
+#define QUATERNARY_TDM_TX_4	81
+#define QUATERNARY_TDM_RX_5	82
+#define QUATERNARY_TDM_TX_5	83
+#define QUATERNARY_TDM_RX_6	84
+#define QUATERNARY_TDM_TX_6	85
+#define QUATERNARY_TDM_RX_7	86
+#define QUATERNARY_TDM_TX_7	87
+#define QUINARY_TDM_RX_0	88
+#define QUINARY_TDM_TX_0	89
+#define QUINARY_TDM_RX_1	90
+#define QUINARY_TDM_TX_1	91
+#define QUINARY_TDM_RX_2	92
+#define QUINARY_TDM_TX_2	93
+#define QUINARY_TDM_RX_3	94
+#define QUINARY_TDM_TX_3	95
+#define QUINARY_TDM_RX_4	96
+#define QUINARY_TDM_TX_4	97
+#define QUINARY_TDM_RX_5	98
+#define QUINARY_TDM_TX_5	99
+#define QUINARY_TDM_RX_6	100
+#define QUINARY_TDM_TX_6	101
+#define QUINARY_TDM_RX_7	102
+#define QUINARY_TDM_TX_7	103
+#define DISPLAY_PORT_RX		104
+#define WSA_CODEC_DMA_RX_0	105
+#define WSA_CODEC_DMA_TX_0	106
+#define WSA_CODEC_DMA_RX_1	107
+#define WSA_CODEC_DMA_TX_1	108
+#define WSA_CODEC_DMA_TX_2	109
+#define VA_CODEC_DMA_TX_0	110
+#define VA_CODEC_DMA_TX_1	111
+#define VA_CODEC_DMA_TX_2	112
+#define RX_CODEC_DMA_RX_0	113
+#define TX_CODEC_DMA_TX_0	114
+#define RX_CODEC_DMA_RX_1	115
+#define TX_CODEC_DMA_TX_1	116
+#define RX_CODEC_DMA_RX_2	117
+#define TX_CODEC_DMA_TX_2	118
+#define RX_CODEC_DMA_RX_3	119
+#define TX_CODEC_DMA_TX_3	120
+#define RX_CODEC_DMA_RX_4	121
+#define TX_CODEC_DMA_TX_4	122
+#define RX_CODEC_DMA_RX_5	123
+#define TX_CODEC_DMA_TX_5	124
+#define RX_CODEC_DMA_RX_6	125
+#define RX_CODEC_DMA_RX_7	126
+#define QUINARY_MI2S_RX		127
+#define QUINARY_MI2S_TX		128
+#define DISPLAY_PORT_RX_0	DISPLAY_PORT_RX
+#define DISPLAY_PORT_RX_1	129
+#define DISPLAY_PORT_RX_2	130
+#define DISPLAY_PORT_RX_3	131
+#define DISPLAY_PORT_RX_4	132
+#define DISPLAY_PORT_RX_5	133
+#define DISPLAY_PORT_RX_6	134
+#define DISPLAY_PORT_RX_7	135
+
+#define LPASS_CLK_ID_PRI_MI2S_IBIT	1
+#define LPASS_CLK_ID_PRI_MI2S_EBIT	2
+#define LPASS_CLK_ID_SEC_MI2S_IBIT	3
+#define LPASS_CLK_ID_SEC_MI2S_EBIT	4
+#define LPASS_CLK_ID_TER_MI2S_IBIT	5
+#define LPASS_CLK_ID_TER_MI2S_EBIT	6
+#define LPASS_CLK_ID_QUAD_MI2S_IBIT	7
+#define LPASS_CLK_ID_QUAD_MI2S_EBIT	8
+#define LPASS_CLK_ID_SPEAKER_I2S_IBIT	9
+#define LPASS_CLK_ID_SPEAKER_I2S_EBIT	10
+#define LPASS_CLK_ID_SPEAKER_I2S_OSR	11
+#define LPASS_CLK_ID_QUI_MI2S_IBIT	12
+#define LPASS_CLK_ID_QUI_MI2S_EBIT	13
+#define LPASS_CLK_ID_SEN_MI2S_IBIT	14
+#define LPASS_CLK_ID_SEN_MI2S_EBIT	15
+#define LPASS_CLK_ID_INT0_MI2S_IBIT	16
+#define LPASS_CLK_ID_INT1_MI2S_IBIT	17
+#define LPASS_CLK_ID_INT2_MI2S_IBIT	18
+#define LPASS_CLK_ID_INT3_MI2S_IBIT	19
+#define LPASS_CLK_ID_INT4_MI2S_IBIT	20
+#define LPASS_CLK_ID_INT5_MI2S_IBIT	21
+#define LPASS_CLK_ID_INT6_MI2S_IBIT	22
+#define LPASS_CLK_ID_QUI_MI2S_OSR	23
+#define LPASS_CLK_ID_PRI_PCM_IBIT	24
+#define LPASS_CLK_ID_PRI_PCM_EBIT	25
+#define LPASS_CLK_ID_SEC_PCM_IBIT	26
+#define LPASS_CLK_ID_SEC_PCM_EBIT	27
+#define LPASS_CLK_ID_TER_PCM_IBIT	28
+#define LPASS_CLK_ID_TER_PCM_EBIT	29
+#define LPASS_CLK_ID_QUAD_PCM_IBIT	30
+#define LPASS_CLK_ID_QUAD_PCM_EBIT	31
+#define LPASS_CLK_ID_QUIN_PCM_IBIT	32
+#define LPASS_CLK_ID_QUIN_PCM_EBIT	33
+#define LPASS_CLK_ID_QUI_PCM_OSR	34
+#define LPASS_CLK_ID_PRI_TDM_IBIT	35
+#define LPASS_CLK_ID_PRI_TDM_EBIT	36
+#define LPASS_CLK_ID_SEC_TDM_IBIT	37
+#define LPASS_CLK_ID_SEC_TDM_EBIT	38
+#define LPASS_CLK_ID_TER_TDM_IBIT	39
+#define LPASS_CLK_ID_TER_TDM_EBIT	40
+#define LPASS_CLK_ID_QUAD_TDM_IBIT	41
+#define LPASS_CLK_ID_QUAD_TDM_EBIT	42
+#define LPASS_CLK_ID_QUIN_TDM_IBIT	43
+#define LPASS_CLK_ID_QUIN_TDM_EBIT	44
+#define LPASS_CLK_ID_QUIN_TDM_OSR	45
+#define LPASS_CLK_ID_MCLK_1		46
+#define LPASS_CLK_ID_MCLK_2		47
+#define LPASS_CLK_ID_MCLK_3		48
+#define LPASS_CLK_ID_MCLK_4		49
+#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE	50
+#define LPASS_CLK_ID_INT_MCLK_0		51
+#define LPASS_CLK_ID_INT_MCLK_1		52
+#define LPASS_CLK_ID_MCLK_5		53
+#define LPASS_CLK_ID_WSA_CORE_MCLK	54
+#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK	55
+#define LPASS_CLK_ID_VA_CORE_MCLK	56
+#define LPASS_CLK_ID_TX_CORE_MCLK	57
+#define LPASS_CLK_ID_TX_CORE_NPL_MCLK	58
+#define LPASS_CLK_ID_RX_CORE_MCLK	59
+#define LPASS_CLK_ID_RX_CORE_NPL_MCLK	60
+#define LPASS_CLK_ID_VA_CORE_2X_MCLK	61
+/* Clock ID for MCLK for WSA2 core */
+#define LPASS_CLK_ID_WSA2_CORE_MCLK	62
+/* Clock ID for NPL MCLK for WSA2 core */
+#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK	63
+/* Clock ID for RX Core TX MCLK */
+#define LPASS_CLK_ID_RX_CORE_TX_MCLK	64
+/* Clock ID for RX CORE TX 2X MCLK */
+#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK	65
+/* Clock ID for WSA core TX MCLK */
+#define LPASS_CLK_ID_WSA_CORE_TX_MCLK	66
+/* Clock ID for WSA core TX 2X MCLK */
+#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK	67
+/* Clock ID for WSA2 core TX MCLK */
+#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK	68
+/* Clock ID for WSA2 core TX 2X MCLK */
+#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK	69
+/* Clock ID for RX CORE MCLK2 2X  MCLK */
+#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK	70
+
+#define LPASS_HW_AVTIMER_VOTE		101
+#define LPASS_HW_MACRO_VOTE		102
+#define LPASS_HW_DCODEC_VOTE		103
+
+#define Q6AFE_MAX_CLK_ID			104
+
+#define LPASS_CLK_ATTRIBUTE_INVALID		0x0
+#define LPASS_CLK_ATTRIBUTE_COUPLE_NO		0x1
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND	0x2
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR	0x3
+
+#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */

-- 
2.43.1

[PATCH v4 28/39] dts: sdm845: import supporting dtsi files

[Caleb Connolly]

Import the PM8998 and PMI8998 PMIC DTSI files from Linux as well
as the common audio codec in preperation for replacing board DTS files
with upstream.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/pm8998.dtsi         | 130 +++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/pmi8998.dtsi        |  98 +++++++++++++++++++++++++++++
 arch/arm/dts/sdm845-wcd9340.dtsi |  86 ++++++++++++++++++++++++++
 3 files changed, 314 insertions(+)

diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi
new file mode 100644
index 000000000000..3f82715392c6
--- /dev/null
+++ b/arch/arm/dts/pm8998.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* Copyright 2018 Google LLC. */
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	thermal-zones {
+		pm8998-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&pm8998_temp>;
+
+			trips {
+				pm8998_alert0: pm8998-alert0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				pm8998_crit: pm8998-crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pm8998_lsid0: pmic@0 {
+		compatible = "qcom,pm8998", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8998_pon: pon@800 {
+			compatible = "qcom,pm8998-pon";
+
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pm8998_pwrkey: pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+
+			pm8998_resin: resin {
+				compatible = "qcom,pm8941-resin";
+				interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				status = "disabled";
+			};
+		};
+
+		pm8998_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8998_coincell: charger@2800 {
+			compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell";
+			reg = <0x2800>;
+
+			status = "disabled";
+		};
+
+		pm8998_adc: adc@3100 {
+			compatible = "qcom,spmi-adc-rev2";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@6 {
+				reg = <ADC5_DIE_TEMP>;
+				label = "die_temp";
+			};
+		};
+
+		pm8998_adc_tm: adc-tm@3400 {
+			compatible = "qcom,spmi-adc-tm-hc";
+			reg = <0x3400>;
+			interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+			#thermal-sensor-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pm8998_gpios: gpio@c000 {
+			compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm8998_gpios 0 0 26>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pm8998_lsid1: pmic@1 {
+		compatible = "qcom,pm8998", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm/dts/pmi8998.dtsi b/arch/arm/dts/pmi8998.dtsi
new file mode 100644
index 000000000000..cd3f0790fd42
--- /dev/null
+++ b/arch/arm/dts/pmi8998.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pmi8998_lsid0: pmic@2 {
+		compatible = "qcom,pmi8998", "qcom,spmi-pmic";
+		reg = <0x2 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmi8998_charger: charger@1000 {
+			compatible = "qcom,pmi8998-charger";
+			reg = <0x1000>;
+
+			interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+				     <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+				     <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "usb-plugin",
+					  "bat-ov",
+					  "wdog-bark",
+					  "usbin-icl-change";
+
+			io-channels = <&pmi8998_rradc 3>,
+				      <&pmi8998_rradc 4>;
+			io-channel-names = "usbin_i", "usbin_v";
+
+			status = "disabled";
+		};
+
+		pmi8998_gpios: gpio@c000 {
+			compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pmi8998_gpios 0 0 14>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmi8998_rradc: adc@4500 {
+			compatible = "qcom,pmi8998-rradc";
+			reg = <0x4500>;
+			#io-channel-cells = <1>;
+		};
+	};
+
+	pmi8998_lsid1: pmic@3 {
+		compatible = "qcom,pmi8998", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		labibb {
+			compatible = "qcom,pmi8998-lab-ibb";
+
+			ibb: ibb {
+				interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "sc-err", "ocp";
+			};
+
+			lab: lab {
+				interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-names = "sc-err", "ocp";
+			};
+		};
+
+		pmi8998_lpg: pwm {
+			compatible = "qcom,pmi8998-lpg";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		pmi8998_flash: led-controller@d300 {
+			compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led";
+			reg = <0xd300>;
+			status = "disabled";
+		};
+
+		pmi8998_wled: leds@d800 {
+			compatible = "qcom,pmi8998-wled";
+			reg = <0xd800>, <0xd900>;
+			interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ovp", "short";
+			label = "backlight";
+
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/sdm845-wcd9340.dtsi b/arch/arm/dts/sdm845-wcd9340.dtsi
new file mode 100644
index 000000000000..c15d48860646
--- /dev/null
+++ b/arch/arm/dts/sdm845-wcd9340.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 SoC device tree source
+ *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+&slim {
+	status = "okay";
+
+	slim@1 {
+		reg = <1>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		wcd9340_ifd: ifd@0,0 {
+			compatible = "slim217,250";
+			reg = <0 0>;
+		};
+
+		wcd9340: codec@1,0 {
+			compatible = "slim217,250";
+			reg = <1 0>;
+			slim-ifc-dev = <&wcd9340_ifd>;
+
+			#sound-dai-cells = <1>;
+
+			interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			clock-names = "extclk";
+			clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+
+			#clock-cells = <0>;
+			clock-frequency = <9600000>;
+			clock-output-names = "mclk";
+
+			pinctrl-0 = <&wcd_intr_default>;
+			pinctrl-names = "default";
+
+			qcom,micbias1-microvolt = <1800000>;
+			qcom,micbias2-microvolt = <1800000>;
+			qcom,micbias3-microvolt = <1800000>;
+			qcom,micbias4-microvolt = <1800000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			wcdgpio: gpio-controller@42 {
+				compatible = "qcom,wcd9340-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42 0x2>;
+			};
+
+			swm: swm@c85 {
+				compatible = "qcom,soundwire-v1.3.0";
+				reg = <0xc85 0x40>;
+				interrupts-extended = <&wcd9340 20>;
+
+				qcom,dout-ports = <6>;
+				qcom,din-ports = <2>;
+				qcom,ports-sinterval-low = /bits/ 8  <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>;
+				qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>;
+				qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>;
+
+				#sound-dai-cells = <1>;
+				clocks = <&wcd9340>;
+				clock-names = "iface";
+				#address-cells = <2>;
+				#size-cells = <0>;
+			};
+		};
+	};
+};
+
+&tlmm {
+	wcd_intr_default: wcd-intr-default-state {
+		pins = "gpio54";
+		function = "gpio";
+
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+};

-- 
2.43.1

[PATCH v4 29/39] dts: sdm845: replace with upstream DTS

[Caleb Connolly]

Import sdm845.dtsi from upstream, as well as the upstream DTS files for
the db845c and Samsung starqltechn. Delete the old board files.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/Makefile                              |    4 +-
 arch/arm/dts/dragonboard845c-uboot.dtsi            |   26 -
 arch/arm/dts/dragonboard845c.dts                   |   48 -
 arch/arm/dts/sdm845-db845c.dts                     | 1190 ++++
 .../arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi |   16 +
 arch/arm/dts/sdm845-samsung-starqltechn.dts        |  460 ++
 arch/arm/dts/sdm845.dtsi                           | 5801 +++++++++++++++++++-
 arch/arm/dts/starqltechn-uboot.dtsi                |   27 -
 arch/arm/dts/starqltechn.dts                       |   68 -
 configs/qcom_defconfig                             |    2 +-
 10 files changed, 7386 insertions(+), 256 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 751035a577f6..3f4e49b3e445 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -633,8 +633,8 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
 	dragonboard820c.dtb \
-	dragonboard845c.dtb \
-	starqltechn.dtb \
+	sdm845-db845c.dtb \
+	sdm845-samsung-starqltechn.dtb \
 	qcs404-evb.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
deleted file mode 100644
index 775f45c0149f..000000000000
--- a/arch/arm/dts/dragonboard845c-uboot.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
- * (dragonboard845c) pins
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-/
-{
-	soc {
-		bootph-all;
-
-		serial@a84000 {
-			bootph-all;
-		};
-
-		clock-controller@100000 {
-			bootph-all;
-		};
-
-		pinctrl@3400000 {
-			bootph-all;
-		};
-	};
-};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
deleted file mode 100644
index 054f253eb32a..000000000000
--- a/arch/arm/dts/dragonboard845c.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm Robotics RB3 Development (dragonboard845c) board device
- * tree source
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-/dts-v1/;
-
-#include "sdm845.dtsi"
-
-/ {
-	model = "Thundercomm Dragonboard 845c";
-	compatible = "thundercomm,db845c", "qcom,sdm845";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		serial0 = &uart9;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0xfdfa0000>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	soc: soc {
-		serial@a84000 {
-			status = "okay";
-		};
-	};
-};
-
-&pm8998_resin {
-	status = "okay";
-};
-
-#include "dragonboard845c-uboot.dtsi"
diff --git a/arch/arm/dts/sdm845-db845c.dts b/arch/arm/dts/sdm845-db845c.dts
new file mode 100644
index 000000000000..c7eba6c491be
--- /dev/null
+++ b/arch/arm/dts/sdm845-db845c.dts
@@ -0,0 +1,1190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include "sdm845.dtsi"
+#include "sdm845-wcd9340.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+
+/ {
+	model = "Thundercomm Dragonboard 845c";
+	compatible = "thundercomm,db845c", "qcom,sdm845";
+	qcom,msm-id = <341 0x20001>;
+	qcom,board-id = <8 0>;
+
+	aliases {
+		serial0 = &uart9;
+		serial1 = &uart6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* Fixed crystal oscillator dedicated to MCP2517FD */
+	clk40M: can-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+
+	dc12v: dc12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "DC12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vol_up_pin_a>;
+
+		key-vol-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "green:user4";
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "panic-indicator";
+			default-state = "off";
+		};
+
+		led-1 {
+			label = "yellow:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_YELLOW>;
+			gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0tx";
+			default-state = "off";
+		};
+
+		led-2 {
+			label = "blue:bt";
+			function = LED_FUNCTION_BLUETOOTH;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "bluetooth-power";
+			default-state = "off";
+		};
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&lt9611_out>;
+			};
+		};
+	};
+
+	reserved-memory {
+		/* Cont splash region set up by the bootloader */
+		cont_splash_mem: framebuffer@9d400000 {
+			reg = <0x0 0x9d400000 0x0 0x2400000>;
+			no-map;
+		};
+	};
+
+	lt9611_1v8: lt9611-vdd18-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "LT9611_1V8";
+
+		vin-supply = <&vdc_5v>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	lt9611_3v3: lt9611-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "LT9611_3V3";
+
+		vin-supply = <&vdc_3v3>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		/*
+		 * TODO: make it possible to drive same GPIO from two clients
+		 * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+		 * enable-active-high;
+		 */
+	};
+
+	pcie0_1p05v: pcie-0-1p05v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "PCIE0_1.05V";
+
+		vin-supply = <&vbat>;
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+
+		/*
+		 * TODO: make it possible to drive same GPIO from two clients
+		 * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
+		 * enable-active-high;
+		 */
+	};
+
+	cam0_dvdd_1v2: cam0-dvdd-1v2-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM0_DVDD_1V2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		enable-active-high;
+		gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam0_dvdd_1v2_en_default>;
+		vin-supply = <&vbat>;
+	};
+
+	cam0_avdd_2v8: cam0-avdd-2v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM0_AVDD_2V8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		enable-active-high;
+		gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam0_avdd_2v8_en_default>;
+		vin-supply = <&vbat>;
+	};
+
+	/* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */
+	cam3_avdd_2v8: cam3-avdd-2v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM3_AVDD_2V8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		regulator-always-on;
+		vin-supply = <&vbat>;
+	};
+
+	pcie0_3p3v_dual: vldo-3v3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VLDO_3V3";
+
+		vin-supply = <&vbat>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie0_pwren_state>;
+	};
+
+	v5p0_hdmiout: v5p0-hdmiout-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "V5P0_HDMIOUT";
+
+		vin-supply = <&vdc_5v>;
+		regulator-min-microvolt = <500000>;
+		regulator-max-microvolt = <500000>;
+
+		/*
+		 * TODO: make it possible to drive same GPIO from two clients
+		 * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+		 * enable-active-high;
+		 */
+	};
+
+	vbat: vbat-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VBAT";
+
+		vin-supply = <&dc12v>;
+		regulator-min-microvolt = <4200000>;
+		regulator-max-microvolt = <4200000>;
+		regulator-always-on;
+	};
+
+	vbat_som: vbat-som-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VBAT_SOM";
+
+		vin-supply = <&dc12v>;
+		regulator-min-microvolt = <4200000>;
+		regulator-max-microvolt = <4200000>;
+		regulator-always-on;
+	};
+
+	vdc_3v3: vdc-3v3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VDC_3V3";
+		vin-supply = <&dc12v>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdc_5v: vdc-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VDC_5V";
+
+		vin-supply = <&dc12v>;
+		regulator-min-microvolt = <500000>;
+		regulator-max-microvolt = <500000>;
+		regulator-always-on;
+	};
+
+	vreg_s4a_1p8: vreg-s4a-1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_s4a_1p8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+
+		vin-supply = <&vbat_som>;
+	};
+};
+
+&adsp_pas {
+	status = "okay";
+
+	firmware-name = "qcom/sdm845/adsp.mbn";
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8998-rpmh-regulators";
+		qcom,pmic-id = "a";
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-s9-supply = <&vph_pwr>;
+		vdd-s10-supply = <&vph_pwr>;
+		vdd-s11-supply = <&vph_pwr>;
+		vdd-s12-supply = <&vph_pwr>;
+		vdd-s13-supply = <&vph_pwr>;
+		vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+		vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+		vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+		vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+		vdd-l6-supply = <&vph_pwr>;
+		vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+		vdd-l9-supply = <&vreg_bob>;
+		vdd-l10-l23-l25-supply = <&vreg_bob>;
+		vdd-l13-l19-l21-supply = <&vreg_bob>;
+		vdd-l16-l28-supply = <&vreg_bob>;
+		vdd-l18-l22-supply = <&vreg_bob>;
+		vdd-l20-l24-supply = <&vreg_bob>;
+		vdd-l26-supply = <&vreg_s3a_1p35>;
+		vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+		vreg_s3a_1p35: smps3 {
+			regulator-min-microvolt = <1352000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_s5a_2p04: smps5 {
+			regulator-min-microvolt = <1904000>;
+			regulator-max-microvolt = <2040000>;
+		};
+
+		vreg_s7a_1p025: smps7 {
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1028000>;
+		};
+
+		vreg_l1a_0p875: ldo1 {
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a_0p8: ldo5 {
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12a_1p8: ldo12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a_1p8: ldo7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13a_2p95: ldo13 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17a_1p3: ldo17 {
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l20a_2p95: ldo20 {
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2968000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l21a_2p95: ldo21 {
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2968000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l24a_3p075: ldo24 {
+			regulator-min-microvolt = <3088000>;
+			regulator-max-microvolt = <3088000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l25a_3p3: ldo25 {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l26a_1p2: ldo26 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_lvs1a_1p8: lvs1 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vreg_lvs2a_1p8: lvs2 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmi8998-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob-supply = <&vph_pwr>;
+
+		vreg_bob: bob {
+			regulator-min-microvolt = <3312000>;
+			regulator-max-microvolt = <3600000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+			regulator-allow-bypass;
+		};
+	};
+};
+
+&camss {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
+&cdsp_pas {
+	status = "okay";
+	firmware-name = "qcom/sdm845/cdsp.mbn";
+};
+
+&gcc {
+	protected-clocks = <GCC_QSPI_CORE_CLK>,
+			   <GCC_QSPI_CORE_CLK_SRC>,
+			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			   <GCC_LPASS_Q6_AXI_CLK>,
+			   <GCC_LPASS_SWAY_CLK>;
+};
+
+&gmu {
+	status = "okay";
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sdm845/a630_zap.mbn";
+	};
+};
+
+&i2c10 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	lt9611_codec: hdmi-bridge@3b {
+		compatible = "lontium,lt9611";
+		reg = <0x3b>;
+		#sound-dai-cells = <1>;
+
+		interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
+
+		reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&lt9611_1v8>;
+		vcc-supply = <&lt9611_3v3>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt9611_irq_pin>, <&dsi_sw_sel>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				lt9611_a: endpoint {
+					remote-endpoint = <&mdss_dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				lt9611_b: endpoint {
+					remote-endpoint = <&mdss_dsi1_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				lt9611_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&i2c11 {
+	/* On Low speed expansion */
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c14 {
+	/* On Low speed expansion */
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&mdss {
+	memory-region = <&cont_splash_mem>;
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	status = "okay";
+	vdda-supply = <&vreg_l26a_1p2>;
+
+	qcom,dual-dsi-mode;
+	qcom,master-dsi;
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&lt9611_a>;
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_phy {
+	status = "okay";
+	vdds-supply = <&vreg_l1a_0p875>;
+};
+
+&mdss_dsi1 {
+	vdda-supply = <&vreg_l26a_1p2>;
+
+	qcom,dual-dsi-mode;
+
+	/* DSI1 is slave, so use DSI0 clocks */
+	assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+	status = "okay";
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&lt9611_b>;
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&mdss_dsi1_phy {
+	vdds-supply = <&vreg_l1a_0p875>;
+	status = "okay";
+};
+
+&mss_pil {
+	status = "okay";
+	firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+	enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+
+	vddpe-3v3-supply = <&pcie0_3p3v_dual>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_default_state>;
+};
+
+&pcie0_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
+&pcie1 {
+	status = "okay";
+	perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_default_state>;
+};
+
+&pcie1_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
+&pm8998_gpios {
+	gpio-line-names =
+		"NC",
+		"NC",
+		"WLAN_SW_CTRL",
+		"NC",
+		"PM_GPIO5_BLUE_BT_LED",
+		"VOL_UP_N",
+		"NC",
+		"ADC_IN1",
+		"PM_GPIO9_YEL_WIFI_LED",
+		"CAM0_AVDD_EN",
+		"NC",
+		"CAM0_DVDD_EN",
+		"PM_GPIO13_GREEN_U4_LED",
+		"DIV_CLK2",
+		"NC",
+		"NC",
+		"NC",
+		"SMB_STAT",
+		"NC",
+		"NC",
+		"ADC_IN2",
+		"OPTION1",
+		"WCSS_PWR_REQ",
+		"PM845_GPIO24",
+		"OPTION2",
+		"PM845_SLB";
+
+	cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state {
+		pins = "gpio12";
+		function = "normal";
+
+		bias-pull-up;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+	};
+
+	cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state {
+		pins = "gpio10";
+		function = "normal";
+
+		bias-pull-up;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+	};
+
+	vol_up_pin_a: vol-up-active-state {
+		pins = "gpio6";
+		function = "normal";
+		input-enable;
+		bias-pull-up;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+	};
+};
+
+&pm8998_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+	status = "okay";
+};
+
+&pmi8998_lpg {
+	status = "okay";
+
+	qcom,power-source = <1>;
+
+	led@3 {
+		reg = <3>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_HEARTBEAT;
+		function-enumerator = <3>;
+
+		linux,default-trigger = "heartbeat";
+		default-state = "on";
+	};
+
+	led@4 {
+		reg = <4>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <2>;
+	};
+
+	led@5 {
+		reg = <5>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <1>;
+	};
+};
+
+/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
+&q6afedai {
+	dai@22 {
+		reg = <QUATERNARY_MI2S_RX>;
+		qcom,sd-lines = <0 1 2 3>;
+	};
+};
+
+&q6asmdai {
+	dai@0 {
+		reg = <0>;
+	};
+
+	dai@1 {
+		reg = <1>;
+	};
+
+	dai@2 {
+		reg = <2>;
+	};
+
+	dai@3 {
+		reg = <3>;
+		direction = <2>;
+		is-compress-dai;
+	};
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&sdhc_2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+
+	vmmc-supply = <&vreg_l21a_2p95>;
+	vqmmc-supply = <&vreg_l13a_2p95>;
+
+	bus-width = <4>;
+	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+	compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard";
+	pinctrl-0 = <&quat_mi2s_active
+			 &quat_mi2s_sd0_active
+			 &quat_mi2s_sd1_active
+			 &quat_mi2s_sd2_active
+			 &quat_mi2s_sd3_active>;
+	pinctrl-names = "default";
+	model = "DB845c";
+	audio-routing =
+		"RX_BIAS", "MCLK",
+		"AMIC1", "MIC BIAS1",
+		"AMIC2", "MIC BIAS2",
+		"DMIC0", "MIC BIAS1",
+		"DMIC1", "MIC BIAS1",
+		"DMIC2", "MIC BIAS3",
+		"DMIC3", "MIC BIAS3",
+		"SpkrLeft IN", "SPK1 OUT",
+		"SpkrRight IN", "SPK2 OUT",
+		"MM_DL1",  "MultiMedia1 Playback",
+		"MM_DL2",  "MultiMedia2 Playback",
+		"MM_DL4",  "MultiMedia4 Playback",
+		"MultiMedia3 Capture", "MM_UL3";
+
+	mm1-dai-link {
+		link-name = "MultiMedia1";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
+		};
+	};
+
+	mm2-dai-link {
+		link-name = "MultiMedia2";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
+		};
+	};
+
+	mm3-dai-link {
+		link-name = "MultiMedia3";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
+		};
+	};
+
+	mm4-dai-link {
+		link-name = "MultiMedia4";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA4>;
+		};
+	};
+
+	hdmi-dai-link {
+		link-name = "HDMI Playback";
+		cpu {
+			sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&lt9611_codec 0>;
+		};
+	};
+
+	slim-dai-link {
+		link-name = "SLIM Playback";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_0_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
+		};
+	};
+
+	slimcap-dai-link {
+		link-name = "SLIM Capture";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_0_TX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&wcd9340 1>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qup_spi0_default>;
+	cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+	can@0 {
+		compatible = "microchip,mcp2517fd";
+		reg = <0>;
+		clocks = <&clk40M>;
+		interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
+		spi-max-frequency = <10000000>;
+		vdd-supply = <&vdc_5v>;
+		xceiver-supply = <&vdc_5v>;
+	};
+};
+
+&spi2 {
+	/* On Low speed expansion */
+	status = "okay";
+};
+
+&tlmm {
+	cam0_default: cam0-default-state {
+		rst-pins {
+			pins = "gpio9";
+			function = "gpio";
+
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		mclk0-pins {
+			pins = "gpio13";
+			function = "cam_mclk";
+
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	cam3_default: cam3-default-state {
+		rst-pins {
+			function = "gpio";
+			pins = "gpio21";
+
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		mclk3-pins {
+			function = "cam_mclk";
+			pins = "gpio16";
+
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	dsi_sw_sel: dsi-sw-sel-state {
+		pins = "gpio120";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+
+	lt9611_irq_pin: lt9611-irq-state {
+		pins = "gpio84";
+		function = "gpio";
+		bias-disable;
+	};
+
+	pcie0_default_state: pcie0-default-state {
+		clkreq-pins {
+			pins = "gpio36";
+			function = "pci_e0";
+			bias-pull-up;
+		};
+
+		reset-n-pins {
+			pins = "gpio35";
+			function = "gpio";
+
+			drive-strength = <2>;
+			output-low;
+			bias-pull-down;
+		};
+
+		wake-n-pins {
+			pins = "gpio37";
+			function = "gpio";
+
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie0_pwren_state: pcie0-pwren-state {
+		pins = "gpio90";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie1_default_state: pcie1-default-state {
+		perst-n-pins {
+			pins = "gpio102";
+			function = "gpio";
+
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		clkreq-pins {
+			pins = "gpio103";
+			function = "pci_e1";
+			bias-pull-up;
+		};
+
+		wake-n-pins {
+			pins = "gpio11";
+			function = "gpio";
+
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		reset-n-pins {
+			pins = "gpio75";
+			function = "gpio";
+
+			drive-strength = <16>;
+			bias-pull-up;
+			output-high;
+		};
+	};
+
+	sdc2_default_state: sdc2-default-state {
+		clk-pins {
+			pins = "sdc2_clk";
+			bias-disable;
+
+			/*
+			 * It seems that mmc_test reports errors if drive
+			 * strength is not 16 on clk, cmd, and data pins.
+			 */
+			drive-strength = <16>;
+		};
+
+		cmd-pins {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data-pins {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+	};
+
+	sdc2_card_det_n: sd-card-det-n-state {
+		pins = "gpio126";
+		function = "gpio";
+		bias-pull-up;
+	};
+};
+
+&uart3 {
+	label = "LS-UART0";
+	pinctrl-0 = <&qup_uart3_4pin>;
+
+	status = "disabled";
+};
+
+&uart6 {
+	status = "okay";
+
+	pinctrl-0 = <&qup_uart6_4pin>;
+
+	bluetooth {
+		compatible = "qcom,wcn3990-bt";
+
+		vddio-supply = <&vreg_s4a_1p8>;
+		vddxo-supply = <&vreg_l7a_1p8>;
+		vddrf-supply = <&vreg_l17a_1p3>;
+		vddch0-supply = <&vreg_l25a_3p3>;
+		max-speed = <3200000>;
+	};
+};
+
+&uart9 {
+	label = "LS-UART1";
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+	status = "okay";
+
+	vdd-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+
+	qcom,imp-res-offset-value = <8>;
+	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+};
+
+&usb_1_qmpphy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l26a_1p2>;
+	vdda-pll-supply = <&vreg_l1a_0p875>;
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_2_hsphy {
+	status = "okay";
+
+	vdd-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+
+	qcom,imp-res-offset-value = <8>;
+	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
+};
+
+&usb_2_qmpphy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l26a_1p2>;
+	vdda-pll-supply = <&vreg_l1a_0p875>;
+};
+
+&ufs_mem_hc {
+	status = "okay";
+
+	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+
+	vcc-supply = <&vreg_l20a_2p95>;
+	vcc-max-microamp = <800000>;
+};
+
+&ufs_mem_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
+&venus {
+	status = "okay";
+};
+
+&wcd9340 {
+	reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+	vdd-buck-supply = <&vreg_s4a_1p8>;
+	vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+	vdd-tx-supply = <&vreg_s4a_1p8>;
+	vdd-rx-supply = <&vreg_s4a_1p8>;
+	vdd-io-supply = <&vreg_s4a_1p8>;
+
+	swm: swm@c85 {
+		left_spkr: speaker@0,1 {
+			compatible = "sdw10217201000";
+			reg = <0 1>;
+			powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
+			#thermal-sensor-cells = <0>;
+			sound-name-prefix = "SpkrLeft";
+			#sound-dai-cells = <0>;
+		};
+
+		right_spkr: speaker@0,2 {
+			compatible = "sdw10217201000";
+			powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
+			reg = <0 2>;
+			#thermal-sensor-cells = <0>;
+			sound-name-prefix = "SpkrRight";
+			#sound-dai-cells = <0>;
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
+	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+
+	qcom,snoc-host-cap-8bit-quirk;
+	qcom,ath10k-calibration-variant = "Thundercomm_DB845C";
+};
+
+/* PINCTRL - additions to nodes defined in sdm845.dtsi */
+&qup_spi2_default {
+	drive-strength = <16>;
+};
+
+&qup_i2c10_default {
+	drive-strength = <2>;
+	bias-disable;
+};
+
+&qup_uart9_rx {
+	drive-strength = <2>;
+	bias-pull-up;
+};
+
+&qup_uart9_tx {
+	drive-strength = <2>;
+	bias-disable;
+};
+
+/* PINCTRL - additions to nodes defined in sdm845.dtsi */
+&qup_spi0_default {
+	drive-strength = <6>;
+	bias-disable;
+};
diff --git a/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi
new file mode 100644
index 000000000000..c78bd6e92406
--- /dev/null
+++ b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+	chosen {
+		stdout-path = "serial0:921600n8";
+	};
+};
+
+&tlmm {
+	muic-i2c-n {
+		pins = "gpio33", "gpio34";
+		drive-strength = <0x2>;
+		function = "gpio";
+		bias-disable;
+	};
+};
diff --git a/arch/arm/dts/sdm845-samsung-starqltechn.dts b/arch/arm/dts/sdm845-samsung-starqltechn.dts
new file mode 100644
index 000000000000..d37a433130b9
--- /dev/null
+++ b/arch/arm/dts/sdm845-samsung-starqltechn.dts
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sdm845.dtsi"
+
+/ {
+	chassis-type = "handset";
+	model = "Samsung Galaxy S9 SM-G9600";
+	compatible = "samsung,starqltechn", "qcom,sdm845";
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		framebuffer: framebuffer@9d400000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000
+			width = <1440>;
+			height = <2960>;
+			stride = <(1440 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+	};
+
+	/*
+	 * Apparently RPMh does not provide support for PM8998 S4 because it
+	 * is always-on; model it as a fixed regulator.
+	 */
+	vreg_s4a_1p8: pm8998-smps4 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_s4a_1p8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+
+		vin-supply = <&vph_pwr>;
+	};
+
+	reserved-memory {
+		memory@9d400000 {
+			reg = <0x0 0x9d400000 0x0 0x02400000>;
+			no-map;
+		};
+
+		memory@a1300000 {
+			compatible = "ramoops";
+			reg = <0x0 0xa1300000 0x0 0x100000>;
+			record-size = <0x40000>;
+			console-size = <0x40000>;
+			ftrace-size = <0x40000>;
+			pmsg-size = <0x40000>;
+		};
+	};
+};
+
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8998-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-s9-supply = <&vph_pwr>;
+		vdd-s10-supply = <&vph_pwr>;
+		vdd-s11-supply = <&vph_pwr>;
+		vdd-s12-supply = <&vph_pwr>;
+		vdd-s13-supply = <&vph_pwr>;
+		vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+		vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+		vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+		vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+		vdd-l6-supply = <&vph_pwr>;
+		vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+		vdd-l26-supply = <&vreg_s3a_1p35>;
+		vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+		vreg_s2a_1p125: smps2 {
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1100000>;
+		};
+
+		vreg_s3a_1p35: smps3 {
+			regulator-min-microvolt = <1352000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_s5a_2p04: smps5 {
+			regulator-min-microvolt = <1904000>;
+			regulator-max-microvolt = <2040000>;
+		};
+
+		vreg_s7a_1p025: smps7 {
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1028000>;
+		};
+
+		vdd_qusb_hs0:
+		vdda_hp_pcie_core:
+		vdda_mipi_csi0_0p9:
+		vdda_mipi_csi1_0p9:
+		vdda_mipi_csi2_0p9:
+		vdda_mipi_dsi0_pll:
+		vdda_mipi_dsi1_pll:
+		vdda_qlink_lv:
+		vdda_qlink_lv_ck:
+		vdda_qrefs_0p875:
+		vdda_pcie_core:
+		vdda_pll_cc_ebi01:
+		vdda_pll_cc_ebi23:
+		vdda_sp_sensor:
+		vdda_ufs1_core:
+		vdda_ufs2_core:
+		vdda_usb1_ss_core:
+		vdda_usb2_ss_core:
+		vreg_l1a_0p875: ldo1 {
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vddpx_10:
+		vreg_l2a_1p2: ldo2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l3a_1p0: ldo3 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vdd_wcss_cx:
+		vdd_wcss_mx:
+		vdda_wcss_pll:
+		vreg_l5a_0p8: ldo5 {
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vddpx_13:
+		vreg_l6a_1p8: ldo6 {
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <1856000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a_1p8: ldo7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a_1p2: ldo8 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1248000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a_1p8: ldo9 {
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <2928000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10a_1p8: ldo10 {
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <2928000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11a_1p0: ldo11 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vdd_qfprom:
+		vdd_qfprom_sp:
+		vdda_apc1_cs_1p8:
+		vdda_gfx_cs_1p8:
+		vdda_qrefs_1p8:
+		vdda_qusb_hs0_1p8:
+		vddpx_11:
+		vreg_l12a_1p8: ldo12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vddpx_2:
+		vreg_l13a_2p95: ldo13 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14a_1p88: ldo14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15a_1p8: ldo15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16a_2p7: ldo16 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2704000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17a_1p3: ldo17 {
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l18a_2p7: ldo18 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l19a_3p0: ldo19 {
+			regulator-min-microvolt = <2856000>;
+			regulator-max-microvolt = <3104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l20a_2p95: ldo20 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l21a_2p95: ldo21 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l22a_2p85: ldo22 {
+			regulator-min-microvolt = <2864000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l23a_3p3: ldo23 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vdda_qusb_hs0_3p1:
+		vreg_l24a_3p075: ldo24 {
+			regulator-min-microvolt = <3088000>;
+			regulator-max-microvolt = <3088000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l25a_3p3: ldo25 {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vdda_hp_pcie_1p2:
+		vdda_hv_ebi0:
+		vdda_hv_ebi1:
+		vdda_hv_ebi2:
+		vdda_hv_ebi3:
+		vdda_mipi_csi_1p25:
+		vdda_mipi_dsi0_1p2:
+		vdda_mipi_dsi1_1p2:
+		vdda_pcie_1p2:
+		vdda_ufs1_1p2:
+		vdda_ufs2_1p2:
+		vdda_usb1_ss_1p2:
+		vdda_usb2_ss_1p2:
+		vreg_l26a_1p2: ldo26 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l28a_3p0: ldo28 {
+			regulator-min-microvolt = <2856000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_lvs1a_1p8: lvs1 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vreg_lvs2a_1p8: lvs2 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8005-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s3c_0p6: smps3 {
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <600000>;
+		};
+	};
+};
+
+&gcc {
+	protected-clocks = <GCC_QSPI_CORE_CLK>,
+				<GCC_QSPI_CORE_CLK_SRC>,
+				<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+				<GCC_LPASS_Q6_AXI_CLK>,
+				<GCC_LPASS_SWAY_CLK>;
+};
+
+&i2c10 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&uart9 {
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l20a_2p95>;
+	vcc-max-microamp = <600000>;
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vdda_ufs1_core>;
+	vdda-pll-supply = <&vdda_ufs1_1p2>;
+	status = "okay";
+};
+
+&sdhc_2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>;
+	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&vreg_l21a_2p95>;
+	vqmmc-supply = <&vddpx_2>;
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	/* Until we have Type C hooked up we'll force this as peripheral. */
+	dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vdda_usb1_ss_core>;
+	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
+	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
+
+	qcom,imp-res-offset-value = <8>;
+	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vdda_usb1_ss_1p2>;
+	vdda-pll-supply = <&vdda_usb1_ss_core>;
+	status = "okay";
+};
+
+&wifi {
+	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
+	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+	status = "okay";
+};
+
+&tlmm {
+	gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
+
+	sdc2_clk_state: sdc2-clk-state {
+		pins = "sdc2_clk";
+		bias-disable;
+
+		/*
+		 * It seems that mmc_test reports errors if drive
+		 * strength is not 16 on clk, cmd, and data pins.
+		 */
+		drive-strength = <16>;
+	};
+
+	sdc2_cmd_state: sdc2-cmd-state {
+		pins = "sdc2_cmd";
+		bias-pull-up;
+		drive-strength = <16>;
+	};
+
+	sdc2_data_state: sdc2-data-state {
+		pins = "sdc2_data";
+		bias-pull-up;
+		drive-strength = <16>;
+	};
+
+	sd_card_det_n_state: sd-card-det-n-state {
+		pins = "gpio126";
+		function = "gpio";
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 96c9749a52c0..bf5e6eb9d313 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -1,119 +1,5752 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Qualcomm SDM845 chip device tree source
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ * SDM845 SoC device tree source
  *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  */
 
-/dts-v1/;
-
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
-#include "skeleton64.dtsi"
+#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
+#include <dt-bindings/clock/qcom,lpass-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
+#include <dt-bindings/interconnect/qcom,sdm845.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
-	soc: soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0 0xffffffff>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		spi4 = &spi4;
+		spi5 = &spi5;
+		spi6 = &spi6;
+		spi7 = &spi7;
+		spi8 = &spi8;
+		spi9 = &spi9;
+		spi10 = &spi10;
+		spi11 = &spi11;
+		spi12 = &spi12;
+		spi13 = &spi13;
+		spi14 = &spi14;
+		spi15 = &spi15;
+	};
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+	};
+
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x0>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <611>;
+			dynamic-power-coefficient = <154>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x100>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <611>;
+			dynamic-power-coefficient = <154>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_100>;
+			L2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x200>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <611>;
+			dynamic-power-coefficient = <154>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_200>;
+			L2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x300>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <611>;
+			dynamic-power-coefficient = <154>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			#cooling-cells = <2>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_300>;
+			L2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x400>;
+			clocks = <&cpufreq_hw 1>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <442>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_400>;
+			L2_400: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x500>;
+			clocks = <&cpufreq_hw 1>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <442>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_500>;
+			L2_500: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x600>;
+			clocks = <&cpufreq_hw 1>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <442>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD6>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_600>;
+			L2_600: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo385";
+			reg = <0x0 0x700>;
+			clocks = <&cpufreq_hw 1>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <442>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
+					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_700>;
+			L2_700: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+
+				core4 {
+					cpu = <&CPU4>;
+				};
+
+				core5 {
+					cpu = <&CPU5>;
+				};
+
+				core6 {
+					cpu = <&CPU6>;
+				};
+
+				core7 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+
+		cpu_idle_states: idle-states {
+			entry-method = "psci";
+
+			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <350>;
+				exit-latency-us = <461>;
+				min-residency-us = <1890>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <264>;
+				exit-latency-us = <621>;
+				min-residency-us = <952>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x4100c244>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9987>;
+			};
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-sdm845", "qcom,scm";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	cpu0_opp_table: opp-table-cpu0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		cpu0_opp1: opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-peak-kBps = <800000 4800000>;
+		};
+
+		cpu0_opp2: opp-403200000 {
+			opp-hz = /bits/ 64 <403200000>;
+			opp-peak-kBps = <800000 4800000>;
+		};
+
+		cpu0_opp3: opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-peak-kBps = <800000 6451200>;
+		};
+
+		cpu0_opp4: opp-576000000 {
+			opp-hz = /bits/ 64 <576000000>;
+			opp-peak-kBps = <800000 6451200>;
+		};
+
+		cpu0_opp5: opp-652800000 {
+			opp-hz = /bits/ 64 <652800000>;
+			opp-peak-kBps = <800000 7680000>;
+		};
+
+		cpu0_opp6: opp-748800000 {
+			opp-hz = /bits/ 64 <748800000>;
+			opp-peak-kBps = <1804000 9216000>;
+		};
+
+		cpu0_opp7: opp-825600000 {
+			opp-hz = /bits/ 64 <825600000>;
+			opp-peak-kBps = <1804000 9216000>;
+		};
+
+		cpu0_opp8: opp-902400000 {
+			opp-hz = /bits/ 64 <902400000>;
+			opp-peak-kBps = <1804000 10444800>;
+		};
+
+		cpu0_opp9: opp-979200000 {
+			opp-hz = /bits/ 64 <979200000>;
+			opp-peak-kBps = <1804000 11980800>;
+		};
+
+		cpu0_opp10: opp-1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-peak-kBps = <1804000 11980800>;
+		};
+
+		cpu0_opp11: opp-1132800000 {
+			opp-hz = /bits/ 64 <1132800000>;
+			opp-peak-kBps = <2188000 13516800>;
+		};
+
+		cpu0_opp12: opp-1228800000 {
+			opp-hz = /bits/ 64 <1228800000>;
+			opp-peak-kBps = <2188000 15052800>;
+		};
+
+		cpu0_opp13: opp-1324800000 {
+			opp-hz = /bits/ 64 <1324800000>;
+			opp-peak-kBps = <2188000 16588800>;
+		};
+
+		cpu0_opp14: opp-1420800000 {
+			opp-hz = /bits/ 64 <1420800000>;
+			opp-peak-kBps = <3072000 18124800>;
+		};
+
+		cpu0_opp15: opp-1516800000 {
+			opp-hz = /bits/ 64 <1516800000>;
+			opp-peak-kBps = <3072000 19353600>;
+		};
+
+		cpu0_opp16: opp-1612800000 {
+			opp-hz = /bits/ 64 <1612800000>;
+			opp-peak-kBps = <4068000 19353600>;
+		};
+
+		cpu0_opp17: opp-1689600000 {
+			opp-hz = /bits/ 64 <1689600000>;
+			opp-peak-kBps = <4068000 20889600>;
+		};
+
+		cpu0_opp18: opp-1766400000 {
+			opp-hz = /bits/ 64 <1766400000>;
+			opp-peak-kBps = <4068000 22425600>;
+		};
+	};
+
+	cpu4_opp_table: opp-table-cpu4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		cpu4_opp1: opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-peak-kBps = <800000 4800000>;
+		};
+
+		cpu4_opp2: opp-403200000 {
+			opp-hz = /bits/ 64 <403200000>;
+			opp-peak-kBps = <800000 4800000>;
+		};
+
+		cpu4_opp3: opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-peak-kBps = <1804000 4800000>;
+		};
+
+		cpu4_opp4: opp-576000000 {
+			opp-hz = /bits/ 64 <576000000>;
+			opp-peak-kBps = <1804000 4800000>;
+		};
+
+		cpu4_opp5: opp-652800000 {
+			opp-hz = /bits/ 64 <652800000>;
+			opp-peak-kBps = <1804000 4800000>;
+		};
+
+		cpu4_opp6: opp-748800000 {
+			opp-hz = /bits/ 64 <748800000>;
+			opp-peak-kBps = <1804000 4800000>;
+		};
+
+		cpu4_opp7: opp-825600000 {
+			opp-hz = /bits/ 64 <825600000>;
+			opp-peak-kBps = <2188000 9216000>;
+		};
+
+		cpu4_opp8: opp-902400000 {
+			opp-hz = /bits/ 64 <902400000>;
+			opp-peak-kBps = <2188000 9216000>;
+		};
+
+		cpu4_opp9: opp-979200000 {
+			opp-hz = /bits/ 64 <979200000>;
+			opp-peak-kBps = <2188000 9216000>;
+		};
+
+		cpu4_opp10: opp-1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-peak-kBps = <3072000 9216000>;
+		};
+
+		cpu4_opp11: opp-1132800000 {
+			opp-hz = /bits/ 64 <1132800000>;
+			opp-peak-kBps = <3072000 11980800>;
+		};
+
+		cpu4_opp12: opp-1209600000 {
+			opp-hz = /bits/ 64 <1209600000>;
+			opp-peak-kBps = <4068000 11980800>;
+		};
+
+		cpu4_opp13: opp-1286400000 {
+			opp-hz = /bits/ 64 <1286400000>;
+			opp-peak-kBps = <4068000 11980800>;
+		};
+
+		cpu4_opp14: opp-1363200000 {
+			opp-hz = /bits/ 64 <1363200000>;
+			opp-peak-kBps = <4068000 15052800>;
+		};
+
+		cpu4_opp15: opp-1459200000 {
+			opp-hz = /bits/ 64 <1459200000>;
+			opp-peak-kBps = <4068000 15052800>;
+		};
+
+		cpu4_opp16: opp-1536000000 {
+			opp-hz = /bits/ 64 <1536000000>;
+			opp-peak-kBps = <5412000 15052800>;
+		};
+
+		cpu4_opp17: opp-1612800000 {
+			opp-hz = /bits/ 64 <1612800000>;
+			opp-peak-kBps = <5412000 15052800>;
+		};
+
+		cpu4_opp18: opp-1689600000 {
+			opp-hz = /bits/ 64 <1689600000>;
+			opp-peak-kBps = <5412000 19353600>;
+		};
+
+		cpu4_opp19: opp-1766400000 {
+			opp-hz = /bits/ 64 <1766400000>;
+			opp-peak-kBps = <6220000 19353600>;
+		};
+
+		cpu4_opp20: opp-1843200000 {
+			opp-hz = /bits/ 64 <1843200000>;
+			opp-peak-kBps = <6220000 19353600>;
+		};
+
+		cpu4_opp21: opp-1920000000 {
+			opp-hz = /bits/ 64 <1920000000>;
+			opp-peak-kBps = <7216000 19353600>;
+		};
+
+		cpu4_opp22: opp-1996800000 {
+			opp-hz = /bits/ 64 <1996800000>;
+			opp-peak-kBps = <7216000 20889600>;
+		};
+
+		cpu4_opp23: opp-2092800000 {
+			opp-hz = /bits/ 64 <2092800000>;
+			opp-peak-kBps = <7216000 20889600>;
+		};
+
+		cpu4_opp24: opp-2169600000 {
+			opp-hz = /bits/ 64 <2169600000>;
+			opp-peak-kBps = <7216000 20889600>;
+		};
+
+		cpu4_opp25: opp-2246400000 {
+			opp-hz = /bits/ 64 <2246400000>;
+			opp-peak-kBps = <7216000 20889600>;
+		};
+
+		cpu4_opp26: opp-2323200000 {
+			opp-hz = /bits/ 64 <2323200000>;
+			opp-peak-kBps = <7216000 20889600>;
+		};
+
+		cpu4_opp27: opp-2400000000 {
+			opp-hz = /bits/ 64 <2400000000>;
+			opp-peak-kBps = <7216000 22425600>;
+		};
+
+		cpu4_opp28: opp-2476800000 {
+			opp-hz = /bits/ 64 <2476800000>;
+			opp-peak-kBps = <7216000 22425600>;
+		};
+
+		cpu4_opp29: opp-2553600000 {
+			opp-hz = /bits/ 64 <2553600000>;
+			opp-peak-kBps = <7216000 22425600>;
+		};
+
+		cpu4_opp30: opp-2649600000 {
+			opp-hz = /bits/ 64 <2649600000>;
+			opp-peak-kBps = <7216000 22425600>;
+		};
+
+		cpu4_opp31: opp-2745600000 {
+			opp-hz = /bits/ 64 <2745600000>;
+			opp-peak-kBps = <7216000 25497600>;
+		};
+
+		cpu4_opp32: opp-2803200000 {
+			opp-hz = /bits/ 64 <2803200000>;
+			opp-peak-kBps = <7216000 25497600>;
+		};
+	};
+
+	dsi_opp_table: opp-table-dsi {
+		compatible = "operating-points-v2";
+
+		opp-19200000 {
+			opp-hz = /bits/ 64 <19200000>;
+			required-opps = <&rpmhpd_opp_min_svs>;
+		};
+
+		opp-180000000 {
+			opp-hz = /bits/ 64 <180000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+
+		opp-328580000 {
+			opp-hz = /bits/ 64 <328580000>;
+			required-opps = <&rpmhpd_opp_svs_l1>;
+		};
+
+		opp-358000000 {
+			opp-hz = /bits/ 64 <358000000>;
+			required-opps = <&rpmhpd_opp_nom>;
+		};
+	};
+
+	qspi_opp_table: opp-table-qspi {
+		compatible = "operating-points-v2";
+
+		opp-19200000 {
+			opp-hz = /bits/ 64 <19200000>;
+			required-opps = <&rpmhpd_opp_min_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-150000000 {
+			opp-hz = /bits/ 64 <150000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			required-opps = <&rpmhpd_opp_nom>;
+		};
+	};
+
+	qup_opp_table: opp-table-qup {
+		compatible = "operating-points-v2";
+
+		opp-50000000 {
+			opp-hz = /bits/ 64 <50000000>;
+			required-opps = <&rpmhpd_opp_min_svs>;
+		};
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+
+		opp-128000000 {
+			opp-hz = /bits/ 64 <128000000>;
+			required-opps = <&rpmhpd_opp_nom>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci: psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+		};
+
+		CPU_PD4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0>;
+		};
+
+		CPU_PD5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0>;
+		};
+
+		CPU_PD6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0>;
+		};
+
+		CPU_PD7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0>;
+		};
+
+		CLUSTER_PD: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_SLEEP_0>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp-mem@85700000 {
+			reg = <0 0x85700000 0 0x600000>;
+			no-map;
+		};
+
+		xbl_mem: xbl-mem@85e00000 {
+			reg = <0 0x85e00000 0 0x100000>;
+			no-map;
+		};
+
+		aop_mem: aop-mem@85fc0000 {
+			reg = <0 0x85fc0000 0 0x20000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x85fe0000 0 0x20000>;
+			no-map;
+		};
+
+		smem@86000000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86000000 0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		tz_mem: tz@86200000 {
+			reg = <0 0x86200000 0 0x2d00000>;
+			no-map;
+		};
+
+		rmtfs_mem: rmtfs@88f00000 {
+			compatible = "qcom,rmtfs-mem";
+			reg = <0 0x88f00000 0 0x200000>;
+			no-map;
+
+			qcom,client-id = <1>;
+			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+		};
+
+		qseecom_mem: qseecom@8ab00000 {
+			reg = <0 0x8ab00000 0 0x1400000>;
+			no-map;
+		};
+
+		camera_mem: camera-mem@8bf00000 {
+			reg = <0 0x8bf00000 0 0x500000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@8c400000 {
+			reg = <0 0x8c400000 0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@8c410000 {
+			reg = <0 0x8c410000 0 0x5000>;
+			no-map;
+		};
+
+		gpu_mem: gpu@8c415000 {
+			reg = <0 0x8c415000 0 0x2000>;
+			no-map;
+		};
+
+		adsp_mem: adsp@8c500000 {
+			reg = <0 0x8c500000 0 0x1a00000>;
+			no-map;
+		};
+
+		wlan_msa_mem: wlan-msa@8df00000 {
+			reg = <0 0x8df00000 0 0x100000>;
+			no-map;
+		};
+
+		mpss_region: mpss@8e000000 {
+			reg = <0 0x8e000000 0 0x7800000>;
+			no-map;
+		};
+
+		venus_mem: venus@95800000 {
+			reg = <0 0x95800000 0 0x500000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@95d00000 {
+			reg = <0 0x95d00000 0 0x800000>;
+			no-map;
+		};
+
+		mba_region: mba@96500000 {
+			reg = <0 0x96500000 0 0x200000>;
+			no-map;
+		};
+
+		slpi_mem: slpi@96700000 {
+			reg = <0 0x96700000 0 0x1400000>;
+			no-map;
+		};
+
+		spss_mem: spss@97b00000 {
+			reg = <0 0x97b00000 0 0x100000>;
+			no-map;
+		};
+
+		mdata_mem: mpss-metadata {
+			alloc-ranges = <0 0xa0000000 0 0x20000000>;
+			size = <0 0x4000>;
+			no-map;
+		};
+
+		fastrpc_mem: fastrpc {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+			reusable;
+		};
+	};
+
+	adsp_pas: remoteproc-adsp {
+		compatible = "qcom,sdm845-adsp-pas";
+
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		memory-region = <&adsp_mem>;
+
+		qcom,qmp = <&aoss_qmp>;
+
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+			label = "lpass";
+			qcom,remote-pid = <2>;
+			mboxes = <&apss_shared 8>;
+
+			apr {
+				compatible = "qcom,apr-v2";
+				qcom,glink-channels = "apr_audio_svc";
+				qcom,domain = <APR_DOMAIN_ADSP>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,intents = <512 20>;
+
+				service@3 {
+					reg = <APR_SVC_ADSP_CORE>;
+					compatible = "qcom,q6core";
+					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+				};
+
+				q6afe: service@4 {
+					compatible = "qcom,q6afe";
+					reg = <APR_SVC_AFE>;
+					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+					q6afedai: dais {
+						compatible = "qcom,q6afe-dais";
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#sound-dai-cells = <1>;
+					};
+				};
+
+				q6asm: service@7 {
+					compatible = "qcom,q6asm";
+					reg = <APR_SVC_ASM>;
+					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+					q6asmdai: dais {
+						compatible = "qcom,q6asm-dais";
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#sound-dai-cells = <1>;
+						iommus = <&apps_smmu 0x1821 0x0>;
+					};
+				};
+
+				q6adm: service@8 {
+					compatible = "qcom,q6adm";
+					reg = <APR_SVC_ADM>;
+					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+					q6routing: routing {
+						compatible = "qcom,q6adm-routing";
+						#sound-dai-cells = <0>;
+					};
+				};
+			};
+
+			fastrpc {
+				compatible = "qcom,fastrpc";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				label = "adsp";
+				qcom,non-secure-domain;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				compute-cb@3 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <3>;
+					iommus = <&apps_smmu 0x1823 0x0>;
+				};
+
+				compute-cb@4 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <4>;
+					iommus = <&apps_smmu 0x1824 0x0>;
+				};
+			};
+		};
+	};
+
+	cdsp_pas: remoteproc-cdsp {
+		compatible = "qcom,sdm845-cdsp-pas";
+
+		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		memory-region = <&cdsp_mem>;
+
+		qcom,qmp = <&aoss_qmp>;
+
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+			label = "turing";
+			qcom,remote-pid = <5>;
+			mboxes = <&apss_shared 4>;
+			fastrpc {
+				compatible = "qcom,fastrpc";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				label = "cdsp";
+				qcom,non-secure-domain;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				compute-cb@1 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <1>;
+					iommus = <&apps_smmu 0x1401 0x30>;
+				};
+
+				compute-cb@2 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <2>;
+					iommus = <&apps_smmu 0x1402 0x30>;
+				};
+
+				compute-cb@3 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <3>;
+					iommus = <&apps_smmu 0x1403 0x30>;
+				};
+
+				compute-cb@4 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <4>;
+					iommus = <&apps_smmu 0x1404 0x30>;
+				};
+
+				compute-cb@5 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <5>;
+					iommus = <&apps_smmu 0x1405 0x30>;
+				};
+
+				compute-cb@6 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <6>;
+					iommus = <&apps_smmu 0x1406 0x30>;
+				};
+
+				compute-cb@7 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <7>;
+					iommus = <&apps_smmu 0x1407 0x30>;
+				};
+
+				compute-cb@8 {
+					compatible = "qcom,fastrpc-compute-cb";
+					reg = <8>;
+					iommus = <&apps_smmu 0x1408 0x30>;
+				};
+			};
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+
+		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 6>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-lpass {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-mpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apss_shared 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		ipa_smp2p_out: ipa-ap-to-modem {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		ipa_smp2p_in: ipa-modem-to-ap {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-slpi {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apss_shared 26>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		slpi_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		slpi_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
 		compatible = "simple-bus";
 
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sdm845";
-			reg = <0x100000 0x1f0000>;
+			reg = <0 0x00100000 0 0x1f0000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>;
+			clock-names = "bi_tcxo",
+				      "bi_tcxo_ao",
+				      "sleep_clk",
+				      "pcie_0_pipe_clk",
+				      "pcie_1_pipe_clk";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd SDM845_CX>;
+		};
+
+		qfprom@784000 {
+			compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
+			reg = <0 0x00784000 0 0x8ff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qusb2p_hstx_trim: hstx-trim-primary@1eb {
+				reg = <0x1eb 0x1>;
+				bits = <1 4>;
+			};
+
+			qusb2s_hstx_trim: hstx-trim-secondary@1eb {
+				reg = <0x1eb 0x2>;
+				bits = <6 4>;
+			};
+		};
+
+		rng: rng@793000 {
+			compatible = "qcom,prng-ee";
+			reg = <0 0x00793000 0 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		gpi_dma0: dma-controller@800000 {
+			#dma-cells = <3>;
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00800000 0 0x60000>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x0016 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x008c0000 0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
+			interconnect-names = "qup-core";
+			status = "disabled";
+
+			i2c0: i2c@880000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi0: spi@880000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart0: serial@880000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c1: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi1: spi@884000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart1: serial@884000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c2: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00888000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c2_default>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi2: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00888000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi2_default>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart2: serial@888000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00888000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart2_default>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c3: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi3: spi@88c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart3: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c4: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00890000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c4_default>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi4: spi@890000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00890000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi4_default>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart4: serial@890000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00890000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart4_default>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c5: i2c@894000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi5: spi@894000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart5: serial@894000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c6: i2c@898000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00898000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c6_default>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi6: spi@898000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00898000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi6_default>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart6: serial@898000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00898000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart6_default>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c7: i2c@89c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0089c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c7_default>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+
+			spi7: spi@89c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0089c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi7_default>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart7: serial@89c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0089c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart7_default>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			#dma-cells = <3>;
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00a00000 0 0x60000>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x06d6 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x00ac0000 0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x6c3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
+			interconnect-names = "qup-core";
+			status = "disabled";
+
+			i2c8: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c8_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi8: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi8_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart8: serial@a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart8_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c9: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c9_default>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi9: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi9_default>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart9: serial@a84000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart9_default>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c10: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c10_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi10: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi10_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart10: serial@a88000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart10_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c11: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c11_default>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi11: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi11_default>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart11: serial@a8c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart11_default>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c12: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c12_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi12: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi12_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart12: serial@a90000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart12_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c13: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c13_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi13: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi13_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart13: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart13_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c14: i2c@a98000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c14_default>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			spi14: spi@a98000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi14_default>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart14: serial@a98000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart14_default>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c15: i2c@a9c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c15_default>;
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+			};
+
+			spi15: spi@a9c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi15_default>;
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				status = "disabled";
+			};
+
+			uart15: serial@a9c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart15_default>;
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM845_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+		};
+
+		llcc: system-cache-controller@1100000 {
+			compatible = "qcom,sdm845-llcc";
+			reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
+			      <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
+			      <0 0x01300000 0 0x50000>;
+			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+				    "llcc3_base", "llcc_broadcast_base";
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		dma@10a2000 {
+			compatible = "qcom,sdm845-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+			      <0x0 0x010ae000 0x0 0x2000>;
+		};
+
+		pmu@114a000 {
+			compatible = "qcom,sdm845-llcc-bwmon";
+			reg = <0 0x0114a000 0 0x1000>;
+			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/*
+				 * The interconnect path bandwidth taken from
+				 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
+				 * interconnect.  This also matches the
+				 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
+				 * bus width: 4 bytes) from msm-4.9 downstream
+				 * kernel.
+				 */
+				opp-0 {
+					opp-peak-kBps = <800000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <1804000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <3072000>;
+				};
+				opp-3 {
+					opp-peak-kBps = <5412000>;
+				};
+				opp-4 {
+					opp-peak-kBps = <7216000>;
+				};
+			};
+		};
+
+		pmu@1436400 {
+			compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x01436400 0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/*
+				 * The interconnect path bandwidth taken from
+				 * cpu4_opp_table bandwidth for OSM L3
+				 * interconnect.  This also matches the OSM L3
+				 * from bandwidth table of qcom,cpu4-l3lat-mon
+				 * (qcom,core-dev-table, bus width: 16 bytes)
+				 * from msm-4.9 downstream kernel.
+				 */
+				opp-0 {
+					opp-peak-kBps = <4800000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <9216000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <15052800>;
+				};
+				opp-3 {
+					opp-peak-kBps = <20889600>;
+				};
+				opp-4 {
+					opp-peak-kBps = <25497600>;
+				};
+			};
+		};
+
+		pcie0: pci@1c00000 {
+			compatible = "qcom,pcie-sdm845";
+			reg = <0 0x01c00000 0 0x2000>,
+			      <0 0x60000000 0 0xf1d>,
+			      <0 0x60000f20 0 0xa8>,
+			      <0 0x60100000 0 0x100000>,
+			      <0 0x01c07000 0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "config", "mhi";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+				 <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+			clock-names = "pipe",
+				      "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "tbu";
+
+			iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
+				    <0x100 &apps_smmu 0x1c11 0x1>,
+				    <0x200 &apps_smmu 0x1c12 0x1>,
+				    <0x300 &apps_smmu 0x1c13 0x1>,
+				    <0x400 &apps_smmu 0x1c14 0x1>,
+				    <0x500 &apps_smmu 0x1c15 0x1>,
+				    <0x600 &apps_smmu 0x1c16 0x1>,
+				    <0x700 &apps_smmu 0x1c17 0x1>,
+				    <0x800 &apps_smmu 0x1c18 0x1>,
+				    <0x900 &apps_smmu 0x1c19 0x1>,
+				    <0xa00 &apps_smmu 0x1c1a 0x1>,
+				    <0xb00 &apps_smmu 0x1c1b 0x1>,
+				    <0xc00 &apps_smmu 0x1c1c 0x1>,
+				    <0xd00 &apps_smmu 0x1c1d 0x1>,
+				    <0xe00 &apps_smmu 0x1c1e 0x1>,
+				    <0xf00 &apps_smmu 0x1c1f 0x1>;
+
+			resets = <&gcc GCC_PCIE_0_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+		};
+
+		pcie0_phy: phy@1c06000 {
+			compatible = "qcom,sdm845-qmp-pcie-phy";
+			reg = <0 0x01c06000 0 0x1000>;
+			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
+				 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+				 <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "refgen",
+				      "pipe";
+
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			status = "disabled";
+		};
+
+		pcie1: pci@1c08000 {
+			compatible = "qcom,pcie-sdm845";
+			reg = <0 0x01c08000 0 0x2000>,
+			      <0 0x40000000 0 0xf1d>,
+			      <0 0x40000f20 0 0xa8>,
+			      <0 0x40100000 0 0x100000>,
+			      <0 0x01c0c000 0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "config", "mhi";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+				 <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_CLKREF_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+			clock-names = "pipe",
+				      "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ref",
+				      "tbu";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+				    <0x100 &apps_smmu 0x1c01 0x1>,
+				    <0x200 &apps_smmu 0x1c02 0x1>,
+				    <0x300 &apps_smmu 0x1c03 0x1>,
+				    <0x400 &apps_smmu 0x1c04 0x1>,
+				    <0x500 &apps_smmu 0x1c05 0x1>,
+				    <0x600 &apps_smmu 0x1c06 0x1>,
+				    <0x700 &apps_smmu 0x1c07 0x1>,
+				    <0x800 &apps_smmu 0x1c08 0x1>,
+				    <0x900 &apps_smmu 0x1c09 0x1>,
+				    <0xa00 &apps_smmu 0x1c0a 0x1>,
+				    <0xb00 &apps_smmu 0x1c0b 0x1>,
+				    <0xc00 &apps_smmu 0x1c0c 0x1>,
+				    <0xd00 &apps_smmu 0x1c0d 0x1>,
+				    <0xe00 &apps_smmu 0x1c0e 0x1>,
+				    <0xf00 &apps_smmu 0x1c0f 0x1>;
+
+			resets = <&gcc GCC_PCIE_1_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc PCIE_1_GDSC>;
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@1c0a000 {
+			compatible = "qcom,sdm845-qhp-pcie-phy";
+			reg = <0 0x01c0a000 0 0x2000>;
+			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_CLKREF_CLK>,
+				 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+				 <&gcc GCC_PCIE_1_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "refgen",
+				      "pipe";
+
+			clock-output-names = "pcie_1_pipe_clk";
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			status = "disabled";
+		};
+
+		mem_noc: interconnect@1380000 {
+			compatible = "qcom,sdm845-mem-noc";
+			reg = <0 0x01380000 0 0x27200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		dc_noc: interconnect@14e0000 {
+			compatible = "qcom,sdm845-dc-noc";
+			reg = <0 0x014e0000 0 0x400>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		config_noc: interconnect@1500000 {
+			compatible = "qcom,sdm845-config-noc";
+			reg = <0 0x01500000 0 0x5080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1620000 {
+			compatible = "qcom,sdm845-system-noc";
+			reg = <0 0x01620000 0 0x18080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sdm845-aggre1-noc";
+			reg = <0 0x016e0000 0 0x15080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sdm845-aggre2-noc";
+			reg = <0 0x01700000 0 0x1f300>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sdm845-mmss-noc";
+			reg = <0 0x01740000 0 0x1c100>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		ufs_mem_hc: ufshc@1d84000 {
+			compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0 0x01d84000 0 0x2500>,
+			      <0 0x01d90000 0 0x8000>;
+			reg-names = "std", "ice";
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufs_mem_phy_lanes>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			power-domains = <&gcc UFS_PHY_GDSC>;
+			#reset-cells = <1>;
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			iommus = <&apps_smmu 0x100 0xf>;
+
+			clock-names =
+				"core_clk",
+				"bus_aggr_clk",
+				"iface_clk",
+				"core_clk_unipro",
+				"ref_clk",
+				"tx_lane0_sync_clk",
+				"rx_lane0_sync_clk",
+				"rx_lane1_sync_clk",
+				"ice_core_clk";
+			clocks =
+				<&gcc GCC_UFS_PHY_AXI_CLK>,
+				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				<&gcc GCC_UFS_PHY_AHB_CLK>,
+				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				<&rpmhcc RPMH_CXO_CLK>,
+				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+				<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			freq-table-hz =
+				<50000000 200000000>,
+				<0 0>,
+				<0 0>,
+				<37500000 150000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<75000000 300000000>;
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
+					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
+			interconnect-names = "ufs-ddr", "cpu-ufs";
+
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,sdm845-qmp-ufs-phy";
+			reg = <0 0x01d87000 0 0x18c>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			clock-names = "ref",
+				      "ref_aux";
+			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+			status = "disabled";
+
+			ufs_mem_phy_lanes: phy@1d87400 {
+				reg = <0 0x01d87400 0 0x108>,
+				      <0 0x01d87600 0 0x1e0>,
+				      <0 0x01d87c00 0 0x1dc>,
+				      <0 0x01d87800 0 0x108>,
+				      <0 0x01d87a00 0 0x1e0>;
+				#phy-cells = <0>;
+			};
+		};
+
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0 0x01dc4000 0 0x24000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rpmhcc RPMH_CE_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			iommus = <&apps_smmu 0x704 0x1>,
+				 <&apps_smmu 0x706 0x1>,
+				 <&apps_smmu 0x714 0x1>,
+				 <&apps_smmu 0x716 0x1>;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,crypto-v5.4";
+			reg = <0 0x01dfa000 0 0x6000>;
+			clocks = <&gcc GCC_CE1_AHB_CLK>,
+				 <&gcc GCC_CE1_AXI_CLK>,
+				 <&rpmhcc RPMH_CE_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 6>, <&cryptobam 7>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x704 0x1>,
+				 <&apps_smmu 0x706 0x1>,
+				 <&apps_smmu 0x714 0x1>,
+				 <&apps_smmu 0x716 0x1>;
+		};
+
+		ipa: ipa@1e40000 {
+			compatible = "qcom,sdm845-ipa";
+
+			iommus = <&apps_smmu 0x720 0x0>,
+				 <&apps_smmu 0x722 0x0>;
+			reg = <0 0x01e40000 0 0x7000>,
+			      <0 0x01e47000 0 0x2000>,
+			      <0 0x01e04000 0 0x2c000>;
+			reg-names = "ipa-reg",
+				    "ipa-shared",
+				    "gsi";
+
+			interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ipa",
+					  "gsi",
+					  "ipa-clock-query",
+					  "ipa-setup-ready";
+
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+			clock-names = "core";
+
+			interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
+					<&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
+					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
+			interconnect-names = "memory",
+					     "imem",
+					     "config";
+
+			qcom,smem-states = <&ipa_smp2p_out 0>,
+					   <&ipa_smp2p_out 1>;
+			qcom,smem-state-names = "ipa-clock-enabled-valid",
+						"ipa-clock-enabled";
+
+			status = "disabled";
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0 0x01f40000 0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr_regs_1: syscon@1f60000 {
+			compatible = "qcom,sdm845-tcsr", "syscon";
+			reg = <0 0x01f60000 0 0x20000>;
+		};
+
+		tlmm: pinctrl@3400000 {
+			compatible = "qcom,sdm845-pinctrl";
+			reg = <0 0x03400000 0 0xc00000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 151>;
+			wakeup-parent = <&pdc_intc>;
+
+			cci0_default: cci0-default-state {
+				/* SDA, SCL */
+				pins = "gpio17", "gpio18";
+				function = "cci_i2c";
+
+				bias-pull-up;
+				drive-strength = <2>; /* 2 mA */
+			};
+
+			cci0_sleep: cci0-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio17", "gpio18";
+				function = "cci_i2c";
+
+				drive-strength = <2>; /* 2 mA */
+				bias-pull-down;
+			};
+
+			cci1_default: cci1-default-state {
+				/* SDA, SCL */
+				pins = "gpio19", "gpio20";
+				function = "cci_i2c";
+
+				bias-pull-up;
+				drive-strength = <2>; /* 2 mA */
+			};
+
+			cci1_sleep: cci1-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio19", "gpio20";
+				function = "cci_i2c";
+
+				drive-strength = <2>; /* 2 mA */
+				bias-pull-down;
+			};
+
+			qspi_clk: qspi-clk-state {
+				pins = "gpio95";
+				function = "qspi_clk";
+			};
+
+			qspi_cs0: qspi-cs0-state {
+				pins = "gpio90";
+				function = "qspi_cs";
+			};
+
+			qspi_cs1: qspi-cs1-state {
+				pins = "gpio89";
+				function = "qspi_cs";
+			};
+
+			qspi_data0: qspi-data0-state {
+				pins = "gpio91";
+				function = "qspi_data";
+			};
+
+			qspi_data1: qspi-data1-state {
+				pins = "gpio92";
+				function = "qspi_data";
+			};
+
+			qspi_data23: qspi-data23-state {
+				pins = "gpio93", "gpio94";
+				function = "qspi_data";
+			};
+
+			qup_i2c0_default: qup-i2c0-default-state {
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+			};
+
+			qup_i2c1_default: qup-i2c1-default-state {
+				pins = "gpio17", "gpio18";
+				function = "qup1";
+			};
+
+			qup_i2c2_default: qup-i2c2-default-state {
+				pins = "gpio27", "gpio28";
+				function = "qup2";
+			};
+
+			qup_i2c3_default: qup-i2c3-default-state {
+				pins = "gpio41", "gpio42";
+				function = "qup3";
+			};
+
+			qup_i2c4_default: qup-i2c4-default-state {
+				pins = "gpio89", "gpio90";
+				function = "qup4";
+			};
+
+			qup_i2c5_default: qup-i2c5-default-state {
+				pins = "gpio85", "gpio86";
+				function = "qup5";
+			};
+
+			qup_i2c6_default: qup-i2c6-default-state {
+				pins = "gpio45", "gpio46";
+				function = "qup6";
+			};
+
+			qup_i2c7_default: qup-i2c7-default-state {
+				pins = "gpio93", "gpio94";
+				function = "qup7";
+			};
+
+			qup_i2c8_default: qup-i2c8-default-state {
+				pins = "gpio65", "gpio66";
+				function = "qup8";
+			};
+
+			qup_i2c9_default: qup-i2c9-default-state {
+				pins = "gpio6", "gpio7";
+				function = "qup9";
+			};
+
+			qup_i2c10_default: qup-i2c10-default-state {
+				pins = "gpio55", "gpio56";
+				function = "qup10";
+			};
+
+			qup_i2c11_default: qup-i2c11-default-state {
+				pins = "gpio31", "gpio32";
+				function = "qup11";
+			};
+
+			qup_i2c12_default: qup-i2c12-default-state {
+				pins = "gpio49", "gpio50";
+				function = "qup12";
+			};
+
+			qup_i2c13_default: qup-i2c13-default-state {
+				pins = "gpio105", "gpio106";
+				function = "qup13";
+			};
+
+			qup_i2c14_default: qup-i2c14-default-state {
+				pins = "gpio33", "gpio34";
+				function = "qup14";
+			};
+
+			qup_i2c15_default: qup-i2c15-default-state {
+				pins = "gpio81", "gpio82";
+				function = "qup15";
+			};
+
+			qup_spi0_default: qup-spi0-default-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "qup0";
+			};
+
+			qup_spi1_default: qup-spi1-default-state {
+				pins = "gpio17", "gpio18", "gpio19", "gpio20";
+				function = "qup1";
+			};
+
+			qup_spi2_default: qup-spi2-default-state {
+				pins = "gpio27", "gpio28", "gpio29", "gpio30";
+				function = "qup2";
+			};
+
+			qup_spi3_default: qup-spi3-default-state {
+				pins = "gpio41", "gpio42", "gpio43", "gpio44";
+				function = "qup3";
+			};
+
+			qup_spi4_default: qup-spi4-default-state {
+				pins = "gpio89", "gpio90", "gpio91", "gpio92";
+				function = "qup4";
+			};
+
+			qup_spi5_default: qup-spi5-default-state {
+				pins = "gpio85", "gpio86", "gpio87", "gpio88";
+				function = "qup5";
+			};
+
+			qup_spi6_default: qup-spi6-default-state {
+				pins = "gpio45", "gpio46", "gpio47", "gpio48";
+				function = "qup6";
+			};
+
+			qup_spi7_default: qup-spi7-default-state {
+				pins = "gpio93", "gpio94", "gpio95", "gpio96";
+				function = "qup7";
+			};
+
+			qup_spi8_default: qup-spi8-default-state {
+				pins = "gpio65", "gpio66", "gpio67", "gpio68";
+				function = "qup8";
+			};
+
+			qup_spi9_default: qup-spi9-default-state {
+				pins = "gpio6", "gpio7", "gpio4", "gpio5";
+				function = "qup9";
+			};
+
+			qup_spi10_default: qup-spi10-default-state {
+				pins = "gpio55", "gpio56", "gpio53", "gpio54";
+				function = "qup10";
+			};
+
+			qup_spi11_default: qup-spi11-default-state {
+				pins = "gpio31", "gpio32", "gpio33", "gpio34";
+				function = "qup11";
+			};
+
+			qup_spi12_default: qup-spi12-default-state {
+				pins = "gpio49", "gpio50", "gpio51", "gpio52";
+				function = "qup12";
+			};
+
+			qup_spi13_default: qup-spi13-default-state {
+				pins = "gpio105", "gpio106", "gpio107", "gpio108";
+				function = "qup13";
+			};
+
+			qup_spi14_default: qup-spi14-default-state {
+				pins = "gpio33", "gpio34", "gpio31", "gpio32";
+				function = "qup14";
+			};
+
+			qup_spi15_default: qup-spi15-default-state {
+				pins = "gpio81", "gpio82", "gpio83", "gpio84";
+				function = "qup15";
+			};
+
+			qup_uart0_default: qup-uart0-default-state {
+				qup_uart0_tx: tx-pins {
+					pins = "gpio2";
+					function = "qup0";
+				};
+
+				qup_uart0_rx: rx-pins {
+					pins = "gpio3";
+					function = "qup0";
+				};
+			};
+
+			qup_uart1_default: qup-uart1-default-state {
+				qup_uart1_tx: tx-pins {
+					pins = "gpio19";
+					function = "qup1";
+				};
+
+				qup_uart1_rx: rx-pins {
+					pins = "gpio20";
+					function = "qup1";
+				};
+			};
+
+			qup_uart2_default: qup-uart2-default-state {
+				qup_uart2_tx: tx-pins {
+					pins = "gpio29";
+					function = "qup2";
+				};
+
+				qup_uart2_rx: rx-pins {
+					pins = "gpio30";
+					function = "qup2";
+				};
+			};
+
+			qup_uart3_default: qup-uart3-default-state {
+				qup_uart3_tx: tx-pins {
+					pins = "gpio43";
+					function = "qup3";
+				};
+
+				qup_uart3_rx: rx-pins {
+					pins = "gpio44";
+					function = "qup3";
+				};
+			};
+
+			qup_uart3_4pin: qup-uart3-4pin-state {
+				qup_uart3_4pin_cts: cts-pins {
+					pins = "gpio41";
+					function = "qup3";
+				};
+
+				qup_uart3_4pin_rts_tx: rts-tx-pins {
+					pins = "gpio42", "gpio43";
+					function = "qup3";
+				};
+
+				qup_uart3_4pin_rx: rx-pins {
+					pins = "gpio44";
+					function = "qup3";
+				};
+			};
+
+			qup_uart4_default: qup-uart4-default-state {
+				qup_uart4_tx: tx-pins {
+					pins = "gpio91";
+					function = "qup4";
+				};
+
+				qup_uart4_rx: rx-pins {
+					pins = "gpio92";
+					function = "qup4";
+				};
+			};
+
+			qup_uart5_default: qup-uart5-default-state {
+				qup_uart5_tx: tx-pins {
+					pins = "gpio87";
+					function = "qup5";
+				};
+
+				qup_uart5_rx: rx-pins {
+					pins = "gpio88";
+					function = "qup5";
+				};
+			};
+
+			qup_uart6_default: qup-uart6-default-state {
+				qup_uart6_tx: tx-pins {
+					pins = "gpio47";
+					function = "qup6";
+				};
+
+				qup_uart6_rx: rx-pins {
+					pins = "gpio48";
+					function = "qup6";
+				};
+			};
+
+			qup_uart6_4pin: qup-uart6-4pin-state {
+				qup_uart6_4pin_cts: cts-pins {
+					pins = "gpio45";
+					function = "qup6";
+					bias-pull-down;
+				};
+
+				qup_uart6_4pin_rts_tx: rts-tx-pins {
+					pins = "gpio46", "gpio47";
+					function = "qup6";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				qup_uart6_4pin_rx: rx-pins {
+					pins = "gpio48";
+					function = "qup6";
+					bias-pull-up;
+				};
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				qup_uart7_tx: tx-pins {
+					pins = "gpio95";
+					function = "qup7";
+				};
+
+				qup_uart7_rx: rx-pins {
+					pins = "gpio96";
+					function = "qup7";
+				};
+			};
+
+			qup_uart8_default: qup-uart8-default-state {
+				qup_uart8_tx: tx-pins {
+					pins = "gpio67";
+					function = "qup8";
+				};
+
+				qup_uart8_rx: rx-pins {
+					pins = "gpio68";
+					function = "qup8";
+				};
+			};
+
+			qup_uart9_default: qup-uart9-default-state {
+				qup_uart9_tx: tx-pins {
+					pins = "gpio4";
+					function = "qup9";
+				};
+
+				qup_uart9_rx: rx-pins {
+					pins = "gpio5";
+					function = "qup9";
+				};
+			};
+
+			qup_uart10_default: qup-uart10-default-state {
+				qup_uart10_tx: tx-pins {
+					pins = "gpio53";
+					function = "qup10";
+				};
+
+				qup_uart10_rx: rx-pins {
+					pins = "gpio54";
+					function = "qup10";
+				};
+			};
+
+			qup_uart11_default: qup-uart11-default-state {
+				qup_uart11_tx: tx-pins {
+					pins = "gpio33";
+					function = "qup11";
+				};
+
+				qup_uart11_rx: rx-pins {
+					pins = "gpio34";
+					function = "qup11";
+				};
+			};
+
+			qup_uart12_default: qup-uart12-default-state {
+				qup_uart12_tx: tx-pins {
+					pins = "gpio51";
+					function = "qup0";
+				};
+
+				qup_uart12_rx: rx-pins {
+					pins = "gpio52";
+					function = "qup0";
+				};
+			};
+
+			qup_uart13_default: qup-uart13-default-state {
+				qup_uart13_tx: tx-pins {
+					pins = "gpio107";
+					function = "qup13";
+				};
+
+				qup_uart13_rx: rx-pins {
+					pins = "gpio108";
+					function = "qup13";
+				};
+			};
+
+			qup_uart14_default: qup-uart14-default-state {
+				qup_uart14_tx: tx-pins {
+					pins = "gpio31";
+					function = "qup14";
+				};
+
+				qup_uart14_rx: rx-pins {
+					pins = "gpio32";
+					function = "qup14";
+				};
+			};
+
+			qup_uart15_default: qup-uart15-default-state {
+				qup_uart15_tx: tx-pins {
+					pins = "gpio83";
+					function = "qup15";
+				};
+
+				qup_uart15_rx: rx-pins {
+					pins = "gpio84";
+					function = "qup15";
+				};
+			};
+
+			quat_mi2s_sleep: quat-mi2s-sleep-state {
+				pins = "gpio58", "gpio59";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			quat_mi2s_active: quat-mi2s-active-state {
+				pins = "gpio58", "gpio59";
+				function = "qua_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+
+			quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
+				pins = "gpio60";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
+				pins = "gpio60";
+				function = "qua_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
+				pins = "gpio61";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
+				pins = "gpio61";
+				function = "qua_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
+				pins = "gpio62";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
+				pins = "gpio62";
+				function = "qua_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
+				pins = "gpio63";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
+				pins = "gpio63";
+				function = "qua_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		};
+
+		mss_pil: remoteproc@4080000 {
+			compatible = "qcom,sdm845-mss-pil";
+			reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
+			reg-names = "qdsp6", "rmb";
+
+			interrupts-extended =
+				<&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack",
+					  "shutdown-ack";
+
+			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+				 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
+				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
+				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
+				 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
+				 <&gcc GCC_PRNG_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "bus", "mem", "gpll0_mss",
+				      "snoc_axi", "mnoc_axi", "prng", "xo";
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&modem_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+				 <&pdc_reset PDC_MODEM_SYNC_RESET>;
+			reset-names = "mss_restart", "pdc_reset";
+
+			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
+
+			power-domains = <&rpmhpd SDM845_CX>,
+					<&rpmhpd SDM845_MX>,
+					<&rpmhpd SDM845_MSS>;
+			power-domain-names = "cx", "mx", "mss";
+
+			status = "disabled";
+
+			mba {
+				memory-region = <&mba_region>;
+			};
+
+			mpss {
+				memory-region = <&mpss_region>;
+			};
+
+			metadata {
+				memory-region = <&mdata_mem>;
+			};
+
+			glink-edge {
+				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+				label = "modem";
+				qcom,remote-pid = <1>;
+				mboxes = <&apss_shared 12>;
+			};
+		};
+
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,sdm845-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk_src",
+				      "gcc_gpu_gpll0_div_clk_src";
+		};
+
+		slpi_pas: remoteproc@5c00000 {
+			compatible = "qcom,sdm845-slpi-pas";
+			reg = <0 0x5c00000 0 0x4000>;
+
+			interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
+						<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+						<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+						<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+						<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+						"handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			qcom,qmp = <&aoss_qmp>;
+
+			power-domains = <&rpmhpd SDM845_CX>,
+					<&rpmhpd SDM845_MX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&slpi_mem>;
+
+			qcom,smem-states = <&slpi_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+				label = "dsps";
+				qcom,remote-pid = <3>;
+				mboxes = <&apss_shared 24>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "sdsp";
+					qcom,non-secure-domain;
+					qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
+						      QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
+					memory-region = <&fastrpc_mem>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@0 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <0>;
+					};
+				};
+			};
+		};
+
+		stm@6002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0 0x06002000 0 0x1000>,
+			      <0 0x16280000 0 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint =
+						  <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@6041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06041000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in0>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6043000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06043000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel2_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in2>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@5 {
+					reg = <5>;
+					funnel2_in5: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06045000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					merge_funnel_out: endpoint {
+						remote-endpoint = <&etf_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					merge_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&funnel0_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					merge_funnel_in2: endpoint {
+						remote-endpoint =
+						  <&funnel2_out>;
+					};
+				};
+			};
+		};
+
+		replicator@6046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0 0x06046000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					replicator_out: endpoint {
+						remote-endpoint = <&etr_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					replicator_in: endpoint {
+						remote-endpoint = <&etf_out>;
+					};
+				};
+			};
+		};
+
+		etf@6047000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06047000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etf_out: endpoint {
+						remote-endpoint =
+						  <&replicator_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+					etf_in: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		etr@6048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06048000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr_in: endpoint {
+						remote-endpoint =
+						  <&replicator_out>;
+					};
+				};
+			};
+		};
+
+		etm@7040000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07040000 0 0x1000>;
+
+			cpu = <&CPU0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		etm@7140000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07140000 0 0x1000>;
+
+			cpu = <&CPU1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		etm@7240000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07240000 0 0x1000>;
+
+			cpu = <&CPU2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in2>;
+					};
+				};
+			};
+		};
+
+		etm@7340000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07340000 0 0x1000>;
+
+			cpu = <&CPU3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in3>;
+					};
+				};
+			};
+		};
+
+		etm@7440000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07440000 0 0x1000>;
+
+			cpu = <&CPU4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		etm@7540000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07540000 0 0x1000>;
+
+			cpu = <&CPU5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in5>;
+					};
+				};
+			};
+		};
+
+		etm@7640000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07640000 0 0x1000>;
+
+			cpu = <&CPU6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		etm@7740000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07740000 0 0x1000>;
+
+			cpu = <&CPU7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,coresight-loses-context-with-cpu;
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@7800000 { /* APSS Funnel */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07800000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_funnel_out: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					apss_funnel_in2: endpoint {
+						remote-endpoint =
+						  <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+					apss_funnel_in3: endpoint {
+						remote-endpoint =
+						  <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					apss_funnel_in4: endpoint {
+						remote-endpoint =
+						  <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+					apss_funnel_in5: endpoint {
+						remote-endpoint =
+						  <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+					apss_funnel_in6: endpoint {
+						remote-endpoint =
+						  <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					apss_funnel_in7: endpoint {
+						remote-endpoint =
+						  <&etm7_out>;
+					};
+				};
+			};
+		};
+
+		funnel@7810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07810000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&funnel2_in5>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					apss_merge_funnel_in: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_out>;
+					};
+				};
+			};
+		};
+
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08804000 0 0x1000>;
+
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0xa0 0xf>;
+			power-domains = <&rpmhpd SDM845_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-9600000 {
+					opp-hz = /bits/ 64 <9600000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-201500000 {
+					opp-hz = /bits/ 64 <201500000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
+		qspi: spi@88df000 {
+			compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
+			reg = <0 0x088df000 0 0x600>;
+			iommus = <&apps_smmu 0x160 0x0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+				 <&gcc GCC_QSPI_CORE_CLK>;
+			clock-names = "iface", "core";
+			power-domains = <&rpmhpd SDM845_CX>;
+			operating-points-v2 = <&qspi_opp_table>;
+			status = "disabled";
+		};
+
+		slim: slim-ngd@171c0000 {
+			compatible = "qcom,slim-ngd-v2.1.0";
+			reg = <0 0x171c0000 0 0x2c000>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+
+			dmas = <&slimbam 3>, <&slimbam 4>;
+			dma-names = "rx", "tx";
+
+			iommus = <&apps_smmu 0x1806 0x0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		lmh_cluster1: lmh@17d70800 {
+			compatible = "qcom,sdm845-lmh";
+			reg = <0 0x17d70800 0 0x400>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			cpus = <&CPU4>;
+			qcom,lmh-temp-arm-millicelsius = <65000>;
+			qcom,lmh-temp-low-millicelsius = <94500>;
+			qcom,lmh-temp-high-millicelsius = <95000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		lmh_cluster0: lmh@17d78800 {
+			compatible = "qcom,sdm845-lmh";
+			reg = <0 0x17d78800 0 0x400>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			cpus = <&CPU0>;
+			qcom,lmh-temp-arm-millicelsius = <65000>;
+			qcom,lmh-temp-low-millicelsius = <94500>;
+			qcom,lmh-temp-high-millicelsius = <95000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		usb_1_hsphy: phy@88e2000 {
+			compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
+			reg = <0 0x088e2000 0 0x400>;
+			status = "disabled";
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			nvmem-cells = <&qusb2p_hstx_trim>;
+		};
+
+		usb_2_hsphy: phy@88e3000 {
+			compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
+			reg = <0 0x088e3000 0 0x400>;
+			status = "disabled";
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+			nvmem-cells = <&qusb2s_hstx_trim>;
+		};
+
+		usb_1_qmpphy: phy@88e8000 {
+			compatible = "qcom,sdm845-qmp-usb3-dp-phy";
+			reg = <0 0x088e8000 0 0x3000>;
+			status = "disabled";
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "com_aux",
+				      "usb3_pipe",
+				      "cfg_ahb";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+		};
+
+		usb_2_qmpphy: phy@88eb000 {
+			compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+			reg = <0 0x088eb000 0 0x18c>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+				 <&gcc GCC_USB3_PHY_SEC_BCR>;
+			reset-names = "phy", "common";
+
+			usb_2_ssphy: phy@88eb200 {
+				reg = <0 0x088eb200 0 0x128>,
+				      <0 0x088eb400 0 0x1fc>,
+				      <0 0x088eb800 0 0x218>,
+				      <0 0x088eb600 0 0x70>;
+				#clock-cells = <0>;
+				#phy-cells = <0>;
+				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "usb3_uni_phy_pipe_clk_src";
+			};
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
+			reg = <0 0x0a6f8800 0 0x400>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			dma-ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <150000000>;
+
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq", "ss_phy_irq",
+					  "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
+					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a600000 0 0xcd00>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x740 0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usb_2: usb@a8f8800 {
+			compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
+			reg = <0 0x0a8f8800 0 0x400>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			dma-ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <150000000>;
+
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq", "ss_phy_irq",
+					  "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+			power-domains = <&gcc USB30_SEC_GDSC>;
+
+			resets = <&gcc GCC_USB30_SEC_BCR>;
+
+			interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
+					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			usb_2_dwc3: usb@a800000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a800000 0 0xcd00>;
+				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x760 0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		venus: video-codec@aa00000 {
+			compatible = "qcom,sdm845-venus-v2";
+			reg = <0 0x0aa00000 0 0xff000>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&videocc VENUS_GDSC>,
+					<&videocc VCODEC0_GDSC>,
+					<&videocc VCODEC1_GDSC>,
+					<&rpmhpd SDM845_CX>;
+			power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
+			operating-points-v2 = <&venus_opp_table>;
+			clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+				 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+				 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+				 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+				 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
+				 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
+				 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
+			clock-names = "core", "iface", "bus",
+				      "vcodec0_core", "vcodec0_bus",
+				      "vcodec1_core", "vcodec1_bus";
+			iommus = <&apps_smmu 0x10a0 0x8>,
+				 <&apps_smmu 0x10b0 0x0>;
+			memory-region = <&venus_mem>;
+			interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
+					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
+			interconnect-names = "video-mem", "cpu-cfg";
+
+			status = "disabled";
+
+			video-core0 {
+				compatible = "venus-decoder";
+			};
+
+			video-core1 {
+				compatible = "venus-encoder";
+			};
+
+			venus_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-320000000 {
+					opp-hz = /bits/ 64 <320000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-380000000 {
+					opp-hz = /bits/ 64 <380000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-444000000 {
+					opp-hz = /bits/ 64 <444000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+
+				opp-533000097 {
+					opp-hz = /bits/ 64 <533000097>;
+					required-opps = <&rpmhpd_opp_turbo>;
+				};
+			};
+		};
+
+		videocc: clock-controller@ab00000 {
+			compatible = "qcom,sdm845-videocc";
+			reg = <0 0x0ab00000 0 0x10000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		camss: camss@acb3000 {
+			compatible = "qcom,sdm845-camss";
+
+			reg = <0 0x0acb3000 0 0x1000>,
+				<0 0x0acba000 0 0x1000>,
+				<0 0x0acc8000 0 0x1000>,
+				<0 0x0ac65000 0 0x1000>,
+				<0 0x0ac66000 0 0x1000>,
+				<0 0x0ac67000 0 0x1000>,
+				<0 0x0ac68000 0 0x1000>,
+				<0 0x0acaf000 0 0x4000>,
+				<0 0x0acb6000 0 0x4000>,
+				<0 0x0acc4000 0 0x4000>;
+			reg-names = "csid0",
+				"csid1",
+				"csid2",
+				"csiphy0",
+				"csiphy1",
+				"csiphy2",
+				"csiphy3",
+				"vfe0",
+				"vfe1",
+				"vfe_lite";
+
+			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "csid0",
+				"csid1",
+				"csid2",
+				"csiphy0",
+				"csiphy1",
+				"csiphy2",
+				"csiphy3",
+				"vfe0",
+				"vfe1",
+				"vfe_lite";
+
+			power-domains = <&clock_camcc IFE_0_GDSC>,
+				<&clock_camcc IFE_1_GDSC>,
+				<&clock_camcc TITAN_TOP_GDSC>;
+
+			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+				<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY0_CLK>,
+				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY1_CLK>,
+				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY2_CLK>,
+				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY3_CLK>,
+				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+				<&gcc GCC_CAMERA_AHB_CLK>,
+				<&gcc GCC_CAMERA_AXI_CLK>,
+				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_LITE_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
+			clock-names = "camnoc_axi",
+				"cpas_ahb",
+				"cphy_rx_src",
+				"csi0",
+				"csi0_src",
+				"csi1",
+				"csi1_src",
+				"csi2",
+				"csi2_src",
+				"csiphy0",
+				"csiphy0_timer",
+				"csiphy0_timer_src",
+				"csiphy1",
+				"csiphy1_timer",
+				"csiphy1_timer_src",
+				"csiphy2",
+				"csiphy2_timer",
+				"csiphy2_timer_src",
+				"csiphy3",
+				"csiphy3_timer",
+				"csiphy3_timer_src",
+				"gcc_camera_ahb",
+				"gcc_camera_axi",
+				"slow_ahb_src",
+				"soc_ahb",
+				"vfe0_axi",
+				"vfe0",
+				"vfe0_cphy_rx",
+				"vfe0_src",
+				"vfe1_axi",
+				"vfe1",
+				"vfe1_cphy_rx",
+				"vfe1_src",
+				"vfe_lite",
+				"vfe_lite_cphy_rx",
+				"vfe_lite_src";
+
+			iommus = <&apps_smmu 0x0808 0x0>,
+				 <&apps_smmu 0x0810 0x8>,
+				 <&apps_smmu 0x0c08 0x0>,
+				 <&apps_smmu 0x0c10 0x8>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+
+				port@2 {
+					reg = <2>;
+				};
+
+				port@3 {
+					reg = <3>;
+				};
+			};
+		};
+
+		cci: cci@ac4a000 {
+			compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			reg = <0 0x0ac4a000 0 0x4000>;
+			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
+				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK_SRC>;
+			clock-names = "camnoc_axi",
+				"soc_ahb",
+				"slow_ahb_src",
+				"cpas_ahb",
+				"cci",
+				"cci_src";
+
+			assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK>;
+			assigned-clock-rates = <80000000>, <37500000>;
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&cci0_default &cci1_default>;
+			pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+			status = "disabled";
+
+			cci_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		clock_camcc: clock-controller@ad00000 {
+			compatible = "qcom,sdm845-camcc";
+			reg = <0 0x0ad00000 0 0x10000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+		};
+
+		mdss: display-subsystem@ae00000 {
+			compatible = "qcom,sdm845-mdss";
+			reg = <0 0x0ae00000 0 0x1000>;
+			reg-names = "mdss";
+
+			power-domains = <&dispcc MDSS_GDSC>;
+
+			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			clock-names = "iface", "core";
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
+					<&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
+			interconnect-names = "mdp0-mem", "mdp1-mem";
+
+			iommus = <&apps_smmu 0x880 0x8>,
+			         <&apps_smmu 0xc80 0x8>;
+
+			status = "disabled";
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			mdss_mdp: display-controller@ae01000 {
+				compatible = "qcom,sdm845-dpu";
+				reg = <0 0x0ae01000 0 0x8f000>,
+				      <0 0x0aeb0000 0 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&gcc GCC_DISP_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+				operating-points-v2 = <&mdp_opp_table>;
+				power-domains = <&rpmhpd SDM845_CX>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&dp_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&mdss_dsi1_in>;
+						};
+					};
+				};
+
+				mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-19200000 {
+						opp-hz = /bits/ 64 <19200000>;
+						required-opps = <&rpmhpd_opp_min_svs>;
+					};
+
+					opp-171428571 {
+						opp-hz = /bits/ 64 <171428571>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-344000000 {
+						opp-hz = /bits/ 64 <344000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-430000000 {
+						opp-hz = /bits/ 64 <430000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss_dp: displayport-controller@ae90000 {
+				status = "disabled";
+				compatible = "qcom,sdm845-dp";
+
+				reg = <0 0x0ae90000 0 0x200>,
+				      <0 0x0ae90200 0 0x200>,
+				      <0 0x0ae90400 0 0x600>,
+				      <0 0x0ae90a00 0 0x600>,
+				      <0 0x0ae91000 0 0x600>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <12>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+					 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+					 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+				clock-names = "core_iface", "core_aux", "ctrl_link",
+					      "ctrl_link_iface", "stream_pixel";
+				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp_opp_table>;
+				power-domains = <&rpmhpd SDM845_CX>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					port@0 {
+						reg = <0>;
+						dp_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dp_out: endpoint { };
+					};
+				};
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-162000000 {
+						opp-hz = /bits/ 64 <162000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@ae94000 {
+				compatible = "qcom,sdm845-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae94000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SDM845_CX>;
+
+				phys = <&mdss_dsi0_phy>;
+
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@ae94400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0 0x0ae94400 0 0x200>,
+				      <0 0x0ae94600 0 0x280>,
+				      <0 0x0ae94a00 0 0x1e0>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+
+			mdss_dsi1: dsi@ae96000 {
+				compatible = "qcom,sdm845-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae96000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SDM845_CX>;
+
+				phys = <&mdss_dsi1_phy>;
+
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi1_phy: phy@ae96400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0 0x0ae96400 0 0x200>,
+				      <0 0x0ae96600 0 0x280>,
+				      <0 0x0ae96a00 0 0x10e>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+		};
+
+		gpu: gpu@5000000 {
+			compatible = "qcom,adreno-630.2", "qcom,adreno";
+
+			reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+			/*
+			 * Look ma, no clocks! The GPU clocks and power are
+			 * controlled entirely by the GMU
+			 */
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
+			interconnect-names = "gfx-mem";
+
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-710000000 {
+					opp-hz = /bits/ 64 <710000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <7216000>;
+				};
+
+				opp-675000000 {
+					opp-hz = /bits/ 64 <675000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <7216000>;
+				};
+
+				opp-596000000 {
+					opp-hz = /bits/ 64 <596000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <6220000>;
+				};
+
+				opp-520000000 {
+					opp-hz = /bits/ 64 <520000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <6220000>;
+				};
+
+				opp-414000000 {
+					opp-hz = /bits/ 64 <414000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <4068000>;
+				};
+
+				opp-342000000 {
+					opp-hz = /bits/ 64 <342000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <2724000>;
+				};
+
+				opp-257000000 {
+					opp-hz = /bits/ 64 <257000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <1648000>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0 0x05040000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			         <&gcc GCC_GPU_CFG_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+			reg = <0 0x0506a000 0 0x30000>,
+			      <0 0x0b280000 0 0x10000>,
+			      <0 0x0b480000 0 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			         <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx", "gx";
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			status = "disabled";
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,sdm845-dispcc";
+			reg = <0 0x0af00000 0 0x10000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+				 <&mdss_dsi0_phy 0>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi1_phy 0>,
+				 <&mdss_dsi1_phy 1>,
+				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+			clock-names = "bi_tcxo",
+				      "gcc_disp_gpll0_clk_src",
+				      "gcc_disp_gpll0_div_clk_src",
+				      "dsi0_phy_pll_out_byteclk",
+				      "dsi0_phy_pll_out_dsiclk",
+				      "dsi1_phy_pll_out_byteclk",
+				      "dsi1_phy_pll_out_dsiclk",
+				      "dp_link_clk_divsel_ten",
+				      "dp_vco_divided_clk_src_mux";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 		};
 
-		tlmm: pinctrl@3400000 {
-			compatible = "qcom,sdm845-pinctrl";
-			reg = <0x3400000 0xc00000>;
-			gpio-count = <150>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&tlmm 0 0 150>;
+		pdc_intc: interrupt-controller@b220000 {
+			compatible = "qcom,sdm845-pdc", "qcom,pdc";
+			reg = <0 0x0b220000 0 0x30000>;
+			qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
 
-			/* DEBUG UART */
-			qup_uart9: qup-uart9-default {
-				pins = "GPIO_4", "GPIO_5";
-				function = "qup9";
+		pdc_reset: reset-controller@b2e0000 {
+			compatible = "qcom,sdm845-pdc-global";
+			reg = <0 0x0b2e0000 0 0x20000>;
+			#reset-cells = <1>;
+		};
+
+		tsens0: thermal-sensor@c263000 {
+			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
+			reg = <0 0x0c263000 0 0x1ff>, /* TM */
+			      <0 0x0c222000 0 0x1ff>; /* SROT */
+			#qcom,sensors = <13>;
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens1: thermal-sensor@c265000 {
+			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
+			reg = <0 0x0c265000 0 0x1ff>, /* TM */
+			      <0 0x0c223000 0 0x1ff>; /* SROT */
+			#qcom,sensors = <8>;
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		aoss_reset: reset-controller@c2a0000 {
+			compatible = "qcom,sdm845-aoss-cc";
+			reg = <0 0x0c2a0000 0 0x31000>;
+			#reset-cells = <1>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0 0x0c300000 0 0x400>;
+			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&apss_shared 0>;
+
+			#clock-cells = <0>;
+
+			cx_cdev: cx {
+				#cooling-cells = <2>;
+			};
+
+			ebi_cdev: ebi {
+				#cooling-cells = <2>;
 			};
 		};
 
-		qupv3_id_1: geniqup@ac0000 {
-			compatible = "qcom,geni-se-qup";
-			reg = <0x00ac0000 0x6000>;
+		sram@c3f0000 {
+			compatible = "qcom,sdm845-rpmh-stats";
+			reg = <0 0x0c3f0000 0 0x400>;
+		};
+
+		spmi_bus: spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0 0x0c440000 0 0x1100>,
+			      <0 0x0c600000 0 0x2000000>,
+			      <0 0x0e600000 0 0x100000>,
+			      <0 0x0e700000 0 0xa0000>,
+			      <0 0x0c40a000 0 0x26000>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		sram@146bf000 {
+			compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
+			reg = <0 0x146bf000 0 0x1000>;
+
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
 
-			uart9: serial@a84000 {
-				compatible = "qcom,geni-debug-uart";
-				reg = <0xa84000 0x4000>;
-				clock-names = "se";
-				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&qup_uart9>;
+			ranges = <0 0 0x146bf000 0x1000>;
+
+			pil-reloc@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
 			};
 		};
 
-		spmi@c440000 {
-			compatible = "qcom,spmi-pmic-arb";
-			reg = <0xc440000 0x1100>,
-			      <0xc600000 0x2000000>,
-			      <0xe600000 0x100000>;
-			reg-names = "core", "chnls", "obsrvr";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
+			reg = <0 0x15000000 0 0x80000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+		};
 
-			qcom,revid@100 {
-				compatible = "qcom,qpnp-revid";
-				reg = <0x100 0x100>;
+		lpasscc: clock-controller@17014000 {
+			compatible = "qcom,sdm845-lpasscc";
+			reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
+			reg-names = "cc", "qdsp6ss";
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		gladiator_noc: interconnect@17900000 {
+			compatible = "qcom,sdm845-gladiator-noc";
+			reg = <0 0x17900000 0 0xd080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		watchdog@17980000 {
+			compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
+			reg = <0 0x17980000 0 0x1000>;
+			clocks = <&sleep_clk>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		apss_shared: mailbox@17990000 {
+			compatible = "qcom,sdm845-apss-shared";
+			reg = <0 0x17990000 0 0x1000>;
+			#mbox-cells = <1>;
+		};
+
+		apps_rsc: rsc@179c0000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x179c0000 0 0x10000>,
+			      <0 0x179d0000 0 0x10000>,
+			      <0 0x179e0000 0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS  2>,
+					  <SLEEP_TCS   3>,
+					  <WAKE_TCS    3>,
+					  <CONTROL_TCS 1>;
+			power-domains = <&CLUSTER_PD>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
 			};
 
-			pmic0: pm8998@0 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x0 0x1>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
-
-				pm8998_pon: pon@800 {
-					compatible = "qcom,pm8998-pon";
-
-					reg = <0x800 0x100>;
-					mode-bootloader = <0x2>;
-					mode-recovery = <0x1>;
-
-					pm8998_pwrkey: pwrkey {
-						compatible = "qcom,pm8941-pwrkey";
-						debounce = <15625>;
-						bias-pull-up;
-					};
-
-					pm8998_resin: resin {
-						compatible = "qcom,pm8941-resin";
-						debounce = <15625>;
-						bias-pull-up;
-						status = "disabled";
-					};
-				};
-
-				pm8998_gpios: pm8998_gpios@c000 {
-					compatible = "qcom,pm8998-gpio";
-					reg = <0xc000 0x1a00>;
-					gpio-controller;
-					gpio-ranges = <&pm8998_gpios 0 0 26>;
-					#gpio-cells = <2>;
-				};
+			rpmhcc: clock-controller {
+				compatible = "qcom,sdm845-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
 			};
 
-			pmic1: pm8998@1 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x1 0x0>;
-				#address-cells = <0x2>;
-				#size-cells = <0x0>;
+			rpmhpd: power-controller {
+				compatible = "qcom,sdm845-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs: opp3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp10 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0 0x17a00000 0 0x10000>,     /* GICD */
+			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			msi-controller@17a40000 {
+				compatible = "arm,gic-v3-its";
+				msi-controller;
+				#msi-cells = <1>;
+				reg = <0 0x17a40000 0 0x20000>;
+				status = "disabled";
+			};
+		};
+
+		slimbam: dma-controller@17184000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			qcom,controlled-remotely;
+			reg = <0 0x17184000 0 0x2a000>;
+			num-channels = <31>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,num-ees = <2>;
+			iommus = <&apps_smmu 0x1806 0x0>;
+		};
+
+		timer@17c90000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0 0x20000000>;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0x17c90000 0 0x1000>;
+
+			frame@17ca0000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17ca0000 0x1000>,
+				      <0x17cb0000 0x1000>;
+			};
+
+			frame@17cc0000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17cc0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17cd0000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17cd0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17ce0000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17ce0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17cf0000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17cf0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17d00000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17d00000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17d10000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17d10000 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		osm_l3: interconnect@17d41000 {
+			compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
+			reg = <0 0x17d41000 0 0x1400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
+		cpufreq_hw: cpufreq@17d43000 {
+			compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
+			reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
+			reg-names = "freq-domain0", "freq-domain1";
+
+			interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
+		wifi: wifi@18800000 {
+			compatible = "qcom,wcn3990-wifi";
+			status = "disabled";
+			reg = <0 0x18800000 0 0x800000>;
+			reg-names = "membase";
+			memory-region = <&wlan_msa_mem>;
+			clock-names = "cxo_ref_clk_pin";
+			clocks = <&rpmhcc RPMH_RF_CLK2>;
+			interrupts =
+				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
+			iommus = <&apps_smmu 0x0040 0x1>;
+		};
+	};
+
+	sound: sound {
+	};
+
+	thermal-zones {
+		cpu0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu4-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				cpu4_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu4_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu4_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu5-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				cpu5_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu5_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu5_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu6-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				cpu6_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu6_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu6_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu7-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				cpu7_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu7_alert1: trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu7_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		aoss0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				aoss0_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cluster0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				cluster0_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cluster0_crit: cluster0_crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cluster1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 6>;
+
+			trips {
+				cluster1_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cluster1_crit: cluster1_crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-top-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				gpu1_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		gpu-bottom-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 12>;
+
+			trips {
+				gpu2_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		aoss1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 0>;
+
+			trips {
+				aoss1_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-modem-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 1>;
+
+			trips {
+				q6_modem_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		mem-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 2>;
+
+			trips {
+				mem_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		wlan-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 3>;
+
+			trips {
+				wlan_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-hvx-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 4>;
+
+			trips {
+				q6_hvx_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		camera-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 5>;
+
+			trips {
+				camera_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		video-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 6>;
+
+			trips {
+				video_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		modem-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 7>;
+
+			trips {
+				modem_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
 			};
 		};
 	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+	};
 };
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi
deleted file mode 100644
index 55c6d18412ba..000000000000
--- a/arch/arm/dts/starqltechn-uboot.dtsi
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- *
- */
-
-/
-{
-	framebuffer@9D400000 {
-		bootph-all;
-	};
-	soc {
-		bootph-all;
-		serial@a84000 {
-			bootph-all;
-		};
-		clock-controller@100000 {
-			bootph-all;
-		};
-		pinctrl@3400000 {
-			bootph-all;
-		};
-	};
-};
-
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
deleted file mode 100644
index 0842e19adb60..000000000000
--- a/arch/arm/dts/starqltechn.dts
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Samsung S9 SM-G9600 (starqltechn) board device tree source
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- *
- */
-
-/dts-v1/;
-
-#include "sdm845.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Samsung S9 (SM-G9600)";
-	compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	chosen {
-		stdout-path = "serial0:921600n8";
-	};
-
-	aliases {
-		serial0 = &uart9;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0xfe1bffff>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	framebuffer: framebuffer@9D400000 {
-		compatible = "simple-framebuffer";
-		reg = <0 0x9D400000 0 (2960 * 1440 * 4)>;//2400000
-		width = <1440>;
-		height = <2960>;
-		stride = <(1440 * 4)>;
-		format = "a8r8g8b8";
-	};
-
-	soc: soc {
-		serial@a84000 {
-			status = "okay";
-		};
-	};
-};
-
-&pm8998_resin {
-	status = "okay";
-};
-
-&tlmm {
-	muic_i2c: muic-i2c-n {
-		pins = "GPIO_33", "GPIO_34";
-		drive-strength = <0x2>;
-		function = "gpio";
-		bias-disable;
-	};
-};
-
-#include "starqltechn-uboot.dtsi"
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index a84f5aee444e..222db6448aba 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
+CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c"
 CONFIG_SYS_LOAD_ADDR=0x0
 CONFIG_BUTTON_CMD=y
 CONFIG_FIT=y

-- 
2.43.1

[PATCH v4 30/39] dt-bindings: import headers for MSM8916

[Caleb Connolly]

Import the dt-bindings headers in preparation for switching to upstream
DTS for MSM8916.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 include/dt-bindings/arm/coresight-cti-dt.h      |  37 +++++
 include/dt-bindings/clock/qcom,rpmcc.h          | 174 ++++++++++++++++++++++++
 include/dt-bindings/interconnect/qcom,msm8916.h | 100 ++++++++++++++
 include/dt-bindings/pinctrl/qcom,pmic-mpp.h     | 106 +++++++++++++++
 include/dt-bindings/reset/qcom,gcc-msm8916.h    | 100 ++++++++++++++
 include/dt-bindings/sound/apq8016-lpass.h       |   9 ++
 include/dt-bindings/sound/qcom,lpass.h          |  46 +++++++
 7 files changed, 572 insertions(+)

diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h
new file mode 100644
index 000000000000..61e7bdf8ea6e
--- /dev/null
+++ b/include/dt-bindings/arm/coresight-cti-dt.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the defined trigger signal
+ * types on CoreSight CTI.
+ */
+
+#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
+#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
+
+#define GEN_IO		0
+#define GEN_INTREQ	1
+#define GEN_INTACK	2
+#define GEN_HALTREQ	3
+#define GEN_RESTARTREQ	4
+#define PE_EDBGREQ	5
+#define PE_DBGRESTART	6
+#define PE_CTIIRQ	7
+#define PE_PMUIRQ	8
+#define PE_DBGTRIGGER	9
+#define ETM_EXTOUT	10
+#define ETM_EXTIN	11
+#define SNK_FULL	12
+#define SNK_ACQCOMP	13
+#define SNK_FLUSHCOMP	14
+#define SNK_FLUSHIN	15
+#define SNK_TRIGIN	16
+#define STM_ASYNCOUT	17
+#define STM_TOUT_SPTE	18
+#define STM_TOUT_SW	19
+#define STM_TOUT_HETE	20
+#define STM_HWEVENT	21
+#define ELA_TSTART	22
+#define ELA_TSTOP	23
+#define ELA_DBGREQ	24
+#define CTI_TRIG_MAX	25
+
+#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
new file mode 100644
index 000000000000..46309c9953b2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2015 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
+#define _DT_BINDINGS_CLK_MSM_RPMCC_H
+
+/* RPM clocks */
+#define RPM_PXO_CLK				0
+#define RPM_PXO_A_CLK				1
+#define RPM_CXO_CLK				2
+#define RPM_CXO_A_CLK				3
+#define RPM_APPS_FABRIC_CLK			4
+#define RPM_APPS_FABRIC_A_CLK			5
+#define RPM_CFPB_CLK				6
+#define RPM_CFPB_A_CLK				7
+#define RPM_QDSS_CLK				8
+#define RPM_QDSS_A_CLK				9
+#define RPM_DAYTONA_FABRIC_CLK			10
+#define RPM_DAYTONA_FABRIC_A_CLK		11
+#define RPM_EBI1_CLK				12
+#define RPM_EBI1_A_CLK				13
+#define RPM_MM_FABRIC_CLK			14
+#define RPM_MM_FABRIC_A_CLK			15
+#define RPM_MMFPB_CLK				16
+#define RPM_MMFPB_A_CLK				17
+#define RPM_SYS_FABRIC_CLK			18
+#define RPM_SYS_FABRIC_A_CLK			19
+#define RPM_SFPB_CLK				20
+#define RPM_SFPB_A_CLK				21
+#define RPM_SMI_CLK				22
+#define RPM_SMI_A_CLK				23
+#define RPM_PLL4_CLK				24
+#define RPM_XO_D0				25
+#define RPM_XO_D1				26
+#define RPM_XO_A0				27
+#define RPM_XO_A1				28
+#define RPM_XO_A2				29
+#define RPM_NSS_FABRIC_0_CLK			30
+#define RPM_NSS_FABRIC_0_A_CLK			31
+#define RPM_NSS_FABRIC_1_CLK			32
+#define RPM_NSS_FABRIC_1_A_CLK			33
+
+/* SMD RPM clocks */
+#define RPM_SMD_XO_CLK_SRC				0
+#define RPM_SMD_XO_A_CLK_SRC			1
+#define RPM_SMD_PCNOC_CLK				2
+#define RPM_SMD_PCNOC_A_CLK				3
+#define RPM_SMD_SNOC_CLK				4
+#define RPM_SMD_SNOC_A_CLK				5
+#define RPM_SMD_BIMC_CLK				6
+#define RPM_SMD_BIMC_A_CLK				7
+#define RPM_SMD_QDSS_CLK				8
+#define RPM_SMD_QDSS_A_CLK				9
+#define RPM_SMD_BB_CLK1				10
+#define RPM_SMD_BB_CLK1_A				11
+#define RPM_SMD_BB_CLK2				12
+#define RPM_SMD_BB_CLK2_A				13
+#define RPM_SMD_RF_CLK1				14
+#define RPM_SMD_RF_CLK1_A				15
+#define RPM_SMD_RF_CLK2				16
+#define RPM_SMD_RF_CLK2_A				17
+#define RPM_SMD_BB_CLK1_PIN				18
+#define RPM_SMD_BB_CLK1_A_PIN			19
+#define RPM_SMD_BB_CLK2_PIN				20
+#define RPM_SMD_BB_CLK2_A_PIN			21
+#define RPM_SMD_RF_CLK1_PIN				22
+#define RPM_SMD_RF_CLK1_A_PIN			23
+#define RPM_SMD_RF_CLK2_PIN				24
+#define RPM_SMD_RF_CLK2_A_PIN			25
+#define RPM_SMD_PNOC_CLK			26
+#define RPM_SMD_PNOC_A_CLK			27
+#define RPM_SMD_CNOC_CLK			28
+#define RPM_SMD_CNOC_A_CLK			29
+#define RPM_SMD_MMSSNOC_AHB_CLK			30
+#define RPM_SMD_MMSSNOC_AHB_A_CLK		31
+#define RPM_SMD_GFX3D_CLK_SRC			32
+#define RPM_SMD_GFX3D_A_CLK_SRC			33
+#define RPM_SMD_OCMEMGX_CLK			34
+#define RPM_SMD_OCMEMGX_A_CLK			35
+#define RPM_SMD_CXO_D0				36
+#define RPM_SMD_CXO_D0_A			37
+#define RPM_SMD_CXO_D1				38
+#define RPM_SMD_CXO_D1_A			39
+#define RPM_SMD_CXO_A0				40
+#define RPM_SMD_CXO_A0_A			41
+#define RPM_SMD_CXO_A1				42
+#define RPM_SMD_CXO_A1_A			43
+#define RPM_SMD_CXO_A2				44
+#define RPM_SMD_CXO_A2_A			45
+#define RPM_SMD_DIV_CLK1			46
+#define RPM_SMD_DIV_A_CLK1			47
+#define RPM_SMD_DIV_CLK2			48
+#define RPM_SMD_DIV_A_CLK2			49
+#define RPM_SMD_DIFF_CLK			50
+#define RPM_SMD_DIFF_A_CLK			51
+#define RPM_SMD_CXO_D0_PIN			52
+#define RPM_SMD_CXO_D0_A_PIN			53
+#define RPM_SMD_CXO_D1_PIN			54
+#define RPM_SMD_CXO_D1_A_PIN			55
+#define RPM_SMD_CXO_A0_PIN			56
+#define RPM_SMD_CXO_A0_A_PIN			57
+#define RPM_SMD_CXO_A1_PIN			58
+#define RPM_SMD_CXO_A1_A_PIN			59
+#define RPM_SMD_CXO_A2_PIN			60
+#define RPM_SMD_CXO_A2_A_PIN			61
+#define RPM_SMD_AGGR1_NOC_CLK			62
+#define RPM_SMD_AGGR1_NOC_A_CLK			63
+#define RPM_SMD_AGGR2_NOC_CLK			64
+#define RPM_SMD_AGGR2_NOC_A_CLK			65
+#define RPM_SMD_MMAXI_CLK			66
+#define RPM_SMD_MMAXI_A_CLK			67
+#define RPM_SMD_IPA_CLK				68
+#define RPM_SMD_IPA_A_CLK			69
+#define RPM_SMD_CE1_CLK				70
+#define RPM_SMD_CE1_A_CLK			71
+#define RPM_SMD_DIV_CLK3			72
+#define RPM_SMD_DIV_A_CLK3			73
+#define RPM_SMD_LN_BB_CLK			74
+#define RPM_SMD_LN_BB_A_CLK			75
+#define RPM_SMD_BIMC_GPU_CLK			76
+#define RPM_SMD_BIMC_GPU_A_CLK			77
+#define RPM_SMD_QPIC_CLK			78
+#define RPM_SMD_QPIC_CLK_A			79
+#define RPM_SMD_LN_BB_CLK1			80
+#define RPM_SMD_LN_BB_CLK1_A			81
+#define RPM_SMD_LN_BB_CLK2			82
+#define RPM_SMD_LN_BB_CLK2_A			83
+#define RPM_SMD_LN_BB_CLK3_PIN			84
+#define RPM_SMD_LN_BB_CLK3_A_PIN		85
+#define RPM_SMD_RF_CLK3				86
+#define RPM_SMD_RF_CLK3_A			87
+#define RPM_SMD_RF_CLK3_PIN			88
+#define RPM_SMD_RF_CLK3_A_PIN			89
+#define RPM_SMD_MMSSNOC_AXI_CLK			90
+#define RPM_SMD_MMSSNOC_AXI_CLK_A		91
+#define RPM_SMD_CNOC_PERIPH_CLK			92
+#define RPM_SMD_CNOC_PERIPH_A_CLK		93
+#define RPM_SMD_LN_BB_CLK3			94
+#define RPM_SMD_LN_BB_CLK3_A			95
+#define RPM_SMD_LN_BB_CLK1_PIN			96
+#define RPM_SMD_LN_BB_CLK1_A_PIN		97
+#define RPM_SMD_LN_BB_CLK2_PIN			98
+#define RPM_SMD_LN_BB_CLK2_A_PIN		99
+#define RPM_SMD_SYSMMNOC_CLK			100
+#define RPM_SMD_SYSMMNOC_A_CLK			101
+#define RPM_SMD_CE2_CLK				102
+#define RPM_SMD_CE2_A_CLK			103
+#define RPM_SMD_CE3_CLK				104
+#define RPM_SMD_CE3_A_CLK			105
+#define RPM_SMD_QUP_CLK				106
+#define RPM_SMD_QUP_A_CLK			107
+#define RPM_SMD_MMRT_CLK			108
+#define RPM_SMD_MMRT_A_CLK			109
+#define RPM_SMD_MMNRT_CLK			110
+#define RPM_SMD_MMNRT_A_CLK			111
+#define RPM_SMD_SNOC_PERIPH_CLK			112
+#define RPM_SMD_SNOC_PERIPH_A_CLK		113
+#define RPM_SMD_SNOC_LPASS_CLK			114
+#define RPM_SMD_SNOC_LPASS_A_CLK		115
+#define RPM_SMD_HWKM_CLK			116
+#define RPM_SMD_HWKM_A_CLK			117
+#define RPM_SMD_PKA_CLK				118
+#define RPM_SMD_PKA_A_CLK			119
+#define RPM_SMD_CPUSS_GNOC_CLK			120
+#define RPM_SMD_CPUSS_GNOC_A_CLK		121
+#define RPM_SMD_MSS_CFG_AHB_CLK		122
+#define RPM_SMD_MSS_CFG_AHB_A_CLK		123
+#define RPM_SMD_BIMC_FREQ_LOG			124
+#define RPM_SMD_LN_BB_CLK_PIN			125
+#define RPM_SMD_LN_BB_A_CLK_PIN			126
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h
new file mode 100644
index 000000000000..359a75feb198
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8916.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm interconnect IDs
+ *
+ * Copyright (c) 2019, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
+
+#define BIMC_SNOC_SLV			0
+#define MASTER_JPEG			1
+#define MASTER_MDP_PORT0		2
+#define MASTER_QDSS_BAM			3
+#define MASTER_QDSS_ETR			4
+#define MASTER_SNOC_CFG			5
+#define MASTER_VFE			6
+#define MASTER_VIDEO_P0			7
+#define SNOC_MM_INT_0			8
+#define SNOC_MM_INT_1			9
+#define SNOC_MM_INT_2			10
+#define SNOC_MM_INT_BIMC		11
+#define PCNOC_SNOC_SLV			12
+#define SLAVE_APSS			13
+#define SLAVE_CATS_128			14
+#define SLAVE_OCMEM_64			15
+#define SLAVE_IMEM			16
+#define SLAVE_QDSS_STM			17
+#define SLAVE_SRVC_SNOC			18
+#define SNOC_BIMC_0_MAS			19
+#define SNOC_BIMC_1_MAS			20
+#define SNOC_INT_0			21
+#define SNOC_INT_1			22
+#define SNOC_INT_BIMC			23
+#define SNOC_PCNOC_MAS			24
+#define SNOC_QDSS_INT			25
+
+#define BIMC_SNOC_MAS			0
+#define MASTER_AMPSS_M0			1
+#define MASTER_GRAPHICS_3D		2
+#define MASTER_TCU0			3
+#define MASTER_TCU1			4
+#define SLAVE_AMPSS_L2			5
+#define SLAVE_EBI_CH0			6
+#define SNOC_BIMC_0_SLV			7
+#define SNOC_BIMC_1_SLV			8
+
+#define MASTER_BLSP_1			0
+#define MASTER_DEHR			1
+#define MASTER_LPASS			2
+#define MASTER_CRYPTO_CORE0		3
+#define MASTER_SDCC_1			4
+#define MASTER_SDCC_2			5
+#define MASTER_SPDM			6
+#define MASTER_USB_HS			7
+#define PCNOC_INT_0			8
+#define PCNOC_INT_1			9
+#define PCNOC_MAS_0			10
+#define PCNOC_MAS_1			11
+#define PCNOC_SLV_0			12
+#define PCNOC_SLV_1			13
+#define PCNOC_SLV_2			14
+#define PCNOC_SLV_3			15
+#define PCNOC_SLV_4			16
+#define PCNOC_SLV_8			17
+#define PCNOC_SLV_9			18
+#define PCNOC_SNOC_MAS			19
+#define SLAVE_BIMC_CFG			20
+#define SLAVE_BLSP_1			21
+#define SLAVE_BOOT_ROM			22
+#define SLAVE_CAMERA_CFG		23
+#define SLAVE_CLK_CTL			24
+#define SLAVE_CRYPTO_0_CFG		25
+#define SLAVE_DEHR_CFG			26
+#define SLAVE_DISPLAY_CFG		27
+#define SLAVE_GRAPHICS_3D_CFG		28
+#define SLAVE_IMEM_CFG			29
+#define SLAVE_LPASS			30
+#define SLAVE_MPM			31
+#define SLAVE_MSG_RAM			32
+#define SLAVE_MSS			33
+#define SLAVE_PDM			34
+#define SLAVE_PMIC_ARB			35
+#define SLAVE_PCNOC_CFG			36
+#define SLAVE_PRNG			37
+#define SLAVE_QDSS_CFG			38
+#define SLAVE_RBCPR_CFG			39
+#define SLAVE_SDCC_1			40
+#define SLAVE_SDCC_2			41
+#define SLAVE_SECURITY			42
+#define SLAVE_SNOC_CFG			43
+#define SLAVE_SPDM			44
+#define SLAVE_TCSR			45
+#define SLAVE_TLMM			46
+#define SLAVE_USB_HS			47
+#define SLAVE_VENUS_CFG			48
+#define SNOC_PCNOC_SLV			49
+
+#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
new file mode 100644
index 000000000000..32e66ee7e830
--- /dev/null
+++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the Qualcomm PMIC's
+ * Multi-Purpose Pin binding.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
+#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
+
+/* power-source */
+
+/* Digital Input/Output: level [PM8058] */
+#define PM8058_MPP_VPH			0
+#define PM8058_MPP_S3			1
+#define PM8058_MPP_L2			2
+#define PM8058_MPP_L3			3
+
+/* Digital Input/Output: level [PM8901] */
+#define PM8901_MPP_MSMIO		0
+#define PM8901_MPP_DIG			1
+#define PM8901_MPP_L5			2
+#define PM8901_MPP_S4			3
+#define PM8901_MPP_VPH			4
+
+/* Digital Input/Output: level [PM8921] */
+#define PM8921_MPP_S4			1
+#define PM8921_MPP_L15			3
+#define PM8921_MPP_L17			4
+#define PM8921_MPP_VPH			7
+
+/* Digital Input/Output: level [PM8821] */
+#define PM8821_MPP_1P8			0
+#define PM8821_MPP_VPH			7
+
+/* Digital Input/Output: level [PM8018] */
+#define PM8018_MPP_L4			0
+#define PM8018_MPP_L14			1
+#define PM8018_MPP_S3			2
+#define PM8018_MPP_L6			3
+#define PM8018_MPP_L2			4
+#define PM8018_MPP_L5			5
+#define PM8018_MPP_VPH			7
+
+/* Digital Input/Output: level [PM8038] */
+#define PM8038_MPP_L20			0
+#define PM8038_MPP_L11			1
+#define PM8038_MPP_L5			2
+#define PM8038_MPP_L15			3
+#define PM8038_MPP_L17			4
+#define PM8038_MPP_VPH			7
+
+#define PM8841_MPP_VPH			0
+#define PM8841_MPP_S3			2
+
+#define PM8916_MPP_VPH			0
+#define PM8916_MPP_L2			2
+#define PM8916_MPP_L5			3
+
+#define PM8941_MPP_VPH			0
+#define PM8941_MPP_L1			1
+#define PM8941_MPP_S3			2
+#define PM8941_MPP_L6			3
+
+#define PMA8084_MPP_VPH			0
+#define PMA8084_MPP_L1			1
+#define PMA8084_MPP_S4			2
+#define PMA8084_MPP_L6			3
+
+#define PM8994_MPP_VPH			0
+/* Only supported for MPP_05-MPP_08 */
+#define PM8994_MPP_L19			1
+#define PM8994_MPP_S4			2
+#define PM8994_MPP_L12			3
+
+/*
+ * Analog Input - Set the source for analog input.
+ * To be used with "qcom,amux-route" property
+ */
+#define PMIC_MPP_AMUX_ROUTE_CH5		0
+#define PMIC_MPP_AMUX_ROUTE_CH6		1
+#define PMIC_MPP_AMUX_ROUTE_CH7		2
+#define PMIC_MPP_AMUX_ROUTE_CH8		3
+#define PMIC_MPP_AMUX_ROUTE_ABUS1	4
+#define PMIC_MPP_AMUX_ROUTE_ABUS2	5
+#define PMIC_MPP_AMUX_ROUTE_ABUS3	6
+#define PMIC_MPP_AMUX_ROUTE_ABUS4	7
+
+/* Analog Output: level */
+#define PMIC_MPP_AOUT_LVL_1V25		0
+#define PMIC_MPP_AOUT_LVL_1V25_2	1
+#define PMIC_MPP_AOUT_LVL_0V625		2
+#define PMIC_MPP_AOUT_LVL_0V3125	3
+#define PMIC_MPP_AOUT_LVL_MPP		4
+#define PMIC_MPP_AOUT_LVL_ABUS1		5
+#define PMIC_MPP_AOUT_LVL_ABUS2		6
+#define PMIC_MPP_AOUT_LVL_ABUS3		7
+
+/* To be used with "function" */
+#define PMIC_MPP_FUNC_NORMAL		"normal"
+#define PMIC_MPP_FUNC_PAIRED		"paired"
+#define PMIC_MPP_FUNC_DTEST1		"dtest1"
+#define PMIC_MPP_FUNC_DTEST2		"dtest2"
+#define PMIC_MPP_FUNC_DTEST3		"dtest3"
+#define PMIC_MPP_FUNC_DTEST4		"dtest4"
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..1f9be10872df
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2015 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
+
+#define GCC_BLSP1_BCR			0
+#define GCC_BLSP1_QUP1_BCR		1
+#define GCC_BLSP1_UART1_BCR		2
+#define GCC_BLSP1_QUP2_BCR		3
+#define GCC_BLSP1_UART2_BCR		4
+#define GCC_BLSP1_QUP3_BCR		5
+#define GCC_BLSP1_QUP4_BCR		6
+#define GCC_BLSP1_QUP5_BCR		7
+#define GCC_BLSP1_QUP6_BCR		8
+#define GCC_IMEM_BCR			9
+#define GCC_SMMU_BCR			10
+#define GCC_APSS_TCU_BCR		11
+#define GCC_SMMU_XPU_BCR		12
+#define GCC_PCNOC_TBU_BCR		13
+#define GCC_PRNG_BCR			14
+#define GCC_BOOT_ROM_BCR		15
+#define GCC_CRYPTO_BCR			16
+#define GCC_SEC_CTRL_BCR		17
+#define GCC_AUDIO_CORE_BCR		18
+#define GCC_ULT_AUDIO_BCR		19
+#define GCC_DEHR_BCR			20
+#define GCC_SYSTEM_NOC_BCR		21
+#define GCC_PCNOC_BCR			22
+#define GCC_TCSR_BCR			23
+#define GCC_QDSS_BCR			24
+#define GCC_DCD_BCR			25
+#define GCC_MSG_RAM_BCR			26
+#define GCC_MPM_BCR			27
+#define GCC_SPMI_BCR			28
+#define GCC_SPDM_BCR			29
+#define GCC_MM_SPDM_BCR			30
+#define GCC_BIMC_BCR			31
+#define GCC_RBCPR_BCR			32
+#define GCC_TLMM_BCR			33
+#define GCC_USB_HS_BCR			34
+#define GCC_USB2A_PHY_BCR		35
+#define GCC_SDCC1_BCR			36
+#define GCC_SDCC2_BCR			37
+#define GCC_PDM_BCR			38
+#define GCC_SNOC_BUS_TIMEOUT0_BCR	39
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR	40
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR	41
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR	42
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR	43
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR	44
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR	45
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR	46
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR	47
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR	48
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR	49
+#define GCC_MMSS_BCR			50
+#define GCC_VENUS0_BCR			51
+#define GCC_MDSS_BCR			52
+#define GCC_CAMSS_PHY0_BCR		53
+#define GCC_CAMSS_CSI0_BCR		54
+#define GCC_CAMSS_CSI0PHY_BCR		55
+#define GCC_CAMSS_CSI0RDI_BCR		56
+#define GCC_CAMSS_CSI0PIX_BCR		57
+#define GCC_CAMSS_PHY1_BCR		58
+#define GCC_CAMSS_CSI1_BCR		59
+#define GCC_CAMSS_CSI1PHY_BCR		60
+#define GCC_CAMSS_CSI1RDI_BCR		61
+#define GCC_CAMSS_CSI1PIX_BCR		62
+#define GCC_CAMSS_ISPIF_BCR		63
+#define GCC_CAMSS_CCI_BCR		64
+#define GCC_CAMSS_MCLK0_BCR		65
+#define GCC_CAMSS_MCLK1_BCR		66
+#define GCC_CAMSS_GP0_BCR		67
+#define GCC_CAMSS_GP1_BCR		68
+#define GCC_CAMSS_TOP_BCR		69
+#define GCC_CAMSS_MICRO_BCR		70
+#define GCC_CAMSS_JPEG_BCR		71
+#define GCC_CAMSS_VFE_BCR		72
+#define GCC_CAMSS_CSI_VFE0_BCR		73
+#define GCC_OXILI_BCR			74
+#define GCC_GMEM_BCR			75
+#define GCC_CAMSS_AHB_BCR		76
+#define GCC_MDP_TBU_BCR			77
+#define GCC_GFX_TBU_BCR			78
+#define GCC_GFX_TCU_BCR			79
+#define GCC_MSS_TBU_AXI_BCR		80
+#define GCC_MSS_TBU_GSS_AXI_BCR		81
+#define GCC_MSS_TBU_Q6_AXI_BCR		82
+#define GCC_GTCU_AHB_BCR		83
+#define GCC_SMMU_CFG_BCR		84
+#define GCC_VFE_TBU_BCR			85
+#define GCC_VENUS_TBU_BCR		86
+#define GCC_JPEG_TBU_BCR		87
+#define GCC_PRONTO_TBU_BCR		88
+#define GCC_SMMU_CATS_BCR		89
+
+#endif
diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h
new file mode 100644
index 000000000000..dc605c4bc224
--- /dev/null
+++ b/include/dt-bindings/sound/apq8016-lpass.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_APQ8016_LPASS_H
+#define __DT_APQ8016_LPASS_H
+
+#include <dt-bindings/sound/qcom,lpass.h>
+
+/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */
+
+#endif /* __DT_APQ8016_LPASS_H */
diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h
new file mode 100644
index 000000000000..a9404c3b8884
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,lpass.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_QCOM_LPASS_H
+#define __DT_QCOM_LPASS_H
+
+#define MI2S_PRIMARY	0
+#define MI2S_SECONDARY	1
+#define MI2S_TERTIARY	2
+#define MI2S_QUATERNARY	3
+#define MI2S_QUINARY	4
+
+#define LPASS_DP_RX	5
+
+#define LPASS_CDC_DMA_RX0 6
+#define LPASS_CDC_DMA_RX1 7
+#define LPASS_CDC_DMA_RX2 8
+#define LPASS_CDC_DMA_RX3 9
+#define LPASS_CDC_DMA_RX4 10
+#define LPASS_CDC_DMA_RX5 11
+#define LPASS_CDC_DMA_RX6 12
+#define LPASS_CDC_DMA_RX7 13
+#define LPASS_CDC_DMA_RX8 14
+#define LPASS_CDC_DMA_RX9 15
+
+#define LPASS_CDC_DMA_TX0 16
+#define LPASS_CDC_DMA_TX1 17
+#define LPASS_CDC_DMA_TX2 18
+#define LPASS_CDC_DMA_TX3 19
+#define LPASS_CDC_DMA_TX4 20
+#define LPASS_CDC_DMA_TX5 21
+#define LPASS_CDC_DMA_TX6 22
+#define LPASS_CDC_DMA_TX7 23
+#define LPASS_CDC_DMA_TX8 24
+
+#define LPASS_CDC_DMA_VA_TX0 25
+#define LPASS_CDC_DMA_VA_TX1 26
+#define LPASS_CDC_DMA_VA_TX2 27
+#define LPASS_CDC_DMA_VA_TX3 28
+#define LPASS_CDC_DMA_VA_TX4 29
+#define LPASS_CDC_DMA_VA_TX5 30
+#define LPASS_CDC_DMA_VA_TX6 31
+#define LPASS_CDC_DMA_VA_TX7 32
+#define LPASS_CDC_DMA_VA_TX8 33
+
+#define LPASS_MCLK0	0
+
+#endif /* __DT_QCOM_LPASS_H */

-- 
2.43.1

[PATCH v4 31/39] dts: msm8916: import PMIC dtsi files

[Caleb Connolly]

Import the supporting pm8916.dtsi and msm8916-pm8916.dtsi files from
upstream in preparation for switching boards over.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/msm8916-pm8916.dtsi | 157 ++++++++++++++++++++++++++++++++++
 arch/arm/dts/pm8916.dtsi         | 178 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 335 insertions(+)

diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi
new file mode 100644
index 000000000000..b1a7eafbee31
--- /dev/null
+++ b/arch/arm/dts/msm8916-pm8916.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
+ * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
+ * Many regulators have a fixed purpose in the original reference design and
+ * were rarely re-used for different purposes. Devices that deviate from the
+ * typical reference design should not make use of this include and instead add
+ * the necessary properties in the board-specific device tree.
+ */
+
+#include "msm8916.dtsi"
+#include "pm8916.dtsi"
+
+&camss {
+	vdda-supply = <&pm8916_l2>;
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&pm8916_l2>;
+	vddio-supply = <&pm8916_l6>;
+};
+
+&mdss_dsi0_phy {
+	vddio-supply = <&pm8916_l6>;
+};
+
+&mpss {
+	pll-supply = <&pm8916_l7>;
+};
+
+&pm8916_codec {
+	vdd-cdc-io-supply = <&pm8916_l5>;
+	vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
+	vdd-micbias-supply = <&pm8916_l13>;
+};
+
+&sdhc_1 {
+	vmmc-supply = <&pm8916_l8>;
+	vqmmc-supply = <&pm8916_l5>;
+};
+
+&sdhc_2 {
+	vmmc-supply = <&pm8916_l11>;
+	vqmmc-supply = <&pm8916_l12>;
+};
+
+&usb_hs_phy {
+	v1p8-supply = <&pm8916_l7>;
+	v3p3-supply = <&pm8916_l13>;
+};
+
+&wcnss {
+	vddpx-supply = <&pm8916_l7>;
+};
+
+&wcnss_iris {
+	vddxo-supply = <&pm8916_l7>;
+	vddrfa-supply = <&pm8916_s3>;
+	vddpa-supply = <&pm8916_l9>;
+	vdddig-supply = <&pm8916_l5>;
+};
+
+&rpm_requests {
+	pm8916_rpm_regulators: regulators {
+		compatible = "qcom,rpm-pm8916-regulators";
+		vdd_l1_l2_l3-supply = <&pm8916_s3>;
+		vdd_l4_l5_l6-supply = <&pm8916_s4>;
+		vdd_l7-supply = <&pm8916_s4>;
+
+		/* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
+
+		pm8916_s3: s3 {
+			regulator-min-microvolt = <1250000>;
+			regulator-max-microvolt = <1350000>;
+			regulator-always-on; /* Needed for L2 */
+		};
+
+		pm8916_s4: s4 {
+			regulator-min-microvolt = <1850000>;
+			regulator-max-microvolt = <2150000>;
+			regulator-always-on; /* Needed for L5/L7 */
+		};
+
+		/*
+		 * Some of the regulators are unused or managed by another
+		 * processor (e.g. the modem). We should still define nodes for
+		 * them to ensure the vote from the application processor can be
+		 * dropped in case the regulators are already on during boot.
+		 *
+		 * The labels for these nodes are omitted on purpose because
+		 * boards should configure a proper voltage before using them.
+		 */
+		l1 {};
+
+		pm8916_l2: l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-always-on; /* Needed for LPDDR RAM */
+		};
+
+		/* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
+
+		l4 {};
+
+		pm8916_l5: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on; /* Needed for most digital I/O */
+		};
+
+		pm8916_l6: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8916_l7: l7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on; /* Needed for CPU PLL */
+		};
+
+		pm8916_l8: l8 {
+			regulator-min-microvolt = <2900000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8916_l9: l9 {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		l10 {};
+
+		pm8916_l11: l11 {
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+			regulator-system-load = <200000>;
+		};
+
+		pm8916_l12: l12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2950000>;
+		};
+
+		pm8916_l13: l13 {
+			regulator-min-microvolt = <3075000>;
+			regulator-max-microvolt = <3075000>;
+		};
+
+		l14 {};
+		l15 {};
+		l16 {};
+		l17 {};
+		l18 {};
+	};
+};
diff --git a/arch/arm/dts/pm8916.dtsi b/arch/arm/dts/pm8916.dtsi
new file mode 100644
index 000000000000..f4de86787743
--- /dev/null
+++ b/arch/arm/dts/pm8916.dtsi
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	pm8916_0: pmic@0 {
+		compatible = "qcom,pm8916", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon@800 {
+			compatible = "qcom,pm8916-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+
+			pm8916_resin: resin {
+				compatible = "qcom,pm8941-resin";
+				interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				status = "disabled";
+			};
+
+			watchdog {
+				compatible = "qcom,pm8916-wdt";
+				interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
+				timeout-sec = <60>;
+			};
+		};
+
+		pm8916_usbin: usb-detect@1300 {
+			compatible = "qcom,pm8941-misc";
+			reg = <0x1300>;
+			interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "usb_vbus";
+			status = "disabled";
+		};
+
+		pm8916_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8916_vadc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <VADC_USBIN>;
+				qcom,pre-scaling = <1 10>;
+			};
+			channel@7 {
+				reg = <VADC_VSYS>;
+				qcom,pre-scaling = <1 3>;
+			};
+			channel@8 {
+				reg = <VADC_DIE_TEMP>;
+			};
+			channel@9 {
+				reg = <VADC_REF_625MV>;
+			};
+			channel@a {
+				reg = <VADC_REF_1250MV>;
+			};
+			channel@e {
+				reg = <VADC_GND_REF>;
+			};
+			channel@f {
+				reg = <VADC_VDD_VADC>;
+			};
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pm8916_mpps: mpps@a000 {
+			compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pm8916_mpps 0 0 4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8916_gpios: gpio@c000 {
+			compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm8916_gpios 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8916_1: pmic@1 {
+		compatible = "qcom,pm8916", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8916_pwm: pwm {
+			compatible = "qcom,pm8916-pwm";
+
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		pm8916_vib: vibrator@c000 {
+			compatible = "qcom,pm8916-vib";
+			reg = <0xc000>;
+			status = "disabled";
+		};
+
+		pm8916_codec: audio-codec@f000 {
+			compatible = "qcom,pm8916-wcd-analog-codec";
+			reg = <0xf000>;
+			interrupt-parent = <&spmi_bus>;
+			interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+				     <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+				     <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+			interrupt-names = "cdc_spk_cnp_int",
+					  "cdc_spk_clip_int",
+					  "cdc_spk_ocp_int",
+					  "mbhc_ins_rem_det1",
+					  "mbhc_but_rel_det",
+					  "mbhc_but_press_det",
+					  "mbhc_ins_rem_det",
+					  "mbhc_switch_int",
+					  "cdc_ear_ocp_int",
+					  "cdc_hphr_ocp_int",
+					  "cdc_hphl_ocp_det",
+					  "cdc_ear_cnp_int",
+					  "cdc_hphr_cnp_int",
+					  "cdc_hphl_cnp_int";
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+	};
+};

-- 
2.43.1

[PATCH v4 32/39] dts: msm8916: replace with upstream DTS

[Caleb Connolly]

Drop the U-Boot specific dragonboard410c.dts in favour of the upstream
msm8916-sbc.dts. No additional changes are needed to this DTS for U-Boot
support.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/Makefile                   |    2 +-
 arch/arm/dts/apq8016-sbc-u-boot.dtsi    |   20 +
 arch/arm/dts/apq8016-sbc.dts            |  729 +++++++++
 arch/arm/dts/dragonboard410c-uboot.dtsi |   44 -
 arch/arm/dts/dragonboard410c.dts        |  221 ---
 arch/arm/dts/msm8916.dtsi               | 2702 +++++++++++++++++++++++++++++++
 configs/dragonboard410c_defconfig       |    2 +-
 7 files changed, 3453 insertions(+), 267 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3f4e49b3e445..9ba1a94da5d0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,7 +631,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
 
 dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 
-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
 	dragonboard820c.dtb \
 	sdm845-db845c.dtb \
 	sdm845-samsung-starqltechn.dtb \
diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
new file mode 100644
index 000000000000..585d54d29623
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+	/* When running as a first-stage bootloader this isn't filled in automatically */
+	memory@80000000 {
+		reg = <0 0x80000000 0 0x3da00000>;
+	};
+};
+
+/*
+ * When running as a first-stage bootloader, we need to re-configure the UART pins
+ * because SBL de-initialises them. Indicate that the UART pins should be configured
+ * during all boot stages.
+ */
+&blsp_uart2_default {
+	bootph-all;
+};
diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-sbc.dts
new file mode 100644
index 000000000000..9ffad7d1f2b6
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc.dts
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
+	compatible = "qcom,apq8016-sbc", "qcom,apq8016";
+
+	aliases {
+		mmc0 = &sdhc_1; /* eMMC */
+		mmc1 = &sdhc_2; /* SD card */
+		serial0 = &blsp_uart2;
+		serial1 = &blsp_uart1;
+		usid0 = &pm8916_0;
+		i2c0 = &blsp_i2c2;
+		i2c1 = &blsp_i2c6;
+		i2c3 = &blsp_i2c4;
+		spi0 = &blsp_spi5;
+		spi1 = &blsp_spi3;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	reserved-memory {
+		ramoops@bff00000 {
+			compatible = "ramoops";
+			reg = <0x0 0xbff00000 0x0 0x100000>;
+
+			record-size = <0x20000>;
+			console-size = <0x20000>;
+			ftrace-size = <0x20000>;
+		};
+	};
+
+	usb2513 {
+		compatible = "smsc,usb3503";
+		reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
+		initial-mode = <1>;
+	};
+
+	usb_id: usb-id {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_id_default>;
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7533_out>;
+			};
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&msm_key_volp_n_default>;
+
+		button {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&tlmm_leds>,
+			    <&pm8916_gpios_leds>,
+			    <&pm8916_mpps_leds>;
+
+		compatible = "gpio-leds";
+
+		led@1 {
+			label = "apq8016-sbc:green:user1";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "apq8016-sbc:green:user2";
+			function = LED_FUNCTION_DISK_ACTIVITY;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "apq8016-sbc:green:user3";
+			function = LED_FUNCTION_DISK_ACTIVITY;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc1";
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "apq8016-sbc:green:user4";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "none";
+			panic-indicator;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "apq8016-sbc:yellow:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_YELLOW>;
+			gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0tx";
+			default-state = "off";
+		};
+
+		led@6 {
+			label = "apq8016-sbc:blue:bt";
+			function = LED_FUNCTION_BLUETOOTH;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "bluetooth-power";
+			default-state = "off";
+		};
+	};
+};
+
+&blsp_i2c2 {
+	/* On Low speed expansion: LS-I2C0 */
+	status = "okay";
+};
+
+&blsp_i2c4 {
+	/* On High speed expansion: HS-I2C2 */
+	status = "okay";
+
+	adv_bridge: bridge@39 {
+		status = "okay";
+
+		compatible = "adi,adv7533";
+		reg = <0x39>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+
+		adi,dsi-lanes = <4>;
+		clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+		clock-names = "cec";
+
+		pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+
+		avdd-supply = <&pm8916_l6>;
+		a2vdd-supply = <&pm8916_l6>;
+		dvdd-supply = <&pm8916_l6>;
+		pvdd-supply = <&pm8916_l6>;
+		v1p2-supply = <&pm8916_l6>;
+		v3p3-supply = <&pm8916_l17>;
+
+		pinctrl-names = "default","sleep";
+		pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
+		pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
+		#sound-dai-cells = <1>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7533_in: endpoint {
+					remote-endpoint = <&mdss_dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7533_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&blsp_i2c6 {
+	/* On Low speed expansion: LS-I2C1 */
+	status = "okay";
+};
+
+&blsp_spi3 {
+	/* On High speed expansion: HS-SPI1 */
+	status = "okay";
+};
+
+&blsp_spi5 {
+	/* On Low speed expansion: LS-SPI0 */
+	status = "okay";
+};
+
+&blsp_uart1 {
+	status = "okay";
+	label = "LS-UART0";
+};
+
+&blsp_uart2 {
+	status = "okay";
+	label = "LS-UART1";
+};
+
+&camss {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&lpass {
+	status = "okay";
+};
+
+&lpass_codec {
+	status = "okay";
+};
+
+&mba_mem {
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0_out {
+	data-lanes = <0 1 2 3>;
+	remote-endpoint = <&adv7533_in>;
+};
+
+&mpss {
+	status = "okay";
+
+	firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn";
+};
+
+&mpss_mem {
+	status = "okay";
+	reg = <0x0 0x86800000 0x0 0x2b00000>;
+};
+
+&pm8916_codec {
+	status = "okay";
+	qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+	qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+};
+
+&pm8916_resin {
+	status = "okay";
+	linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pm8916_rpm_regulators {
+	/*
+	 * The 96Boards specification expects a 1.8V power rail on the low-speed
+	 * expansion connector that is able to provide at least 0.18W / 100 mA.
+	 * L15/L16 are connected in parallel to provide 55 mA each. A minimum load
+	 * must be specified to ensure the regulators are not put in LPM where they
+	 * would only provide 5 mA.
+	 */
+	pm8916_l15: l15 {
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-system-load = <50000>;
+		regulator-allow-set-load;
+		regulator-always-on;
+	};
+	pm8916_l16: l16 {
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-system-load = <50000>;
+		regulator-allow-set-load;
+		regulator-always-on;
+	};
+
+	pm8916_l17: l17 {
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&sdhc_1 {
+	status = "okay";
+};
+
+&sdhc_2 {
+	status = "okay";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+
+	cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+	status = "okay";
+
+	pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
+	pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
+	pinctrl-names = "default", "sleep";
+	model = "DB410c";
+	audio-routing =
+		"AMIC2", "MIC BIAS Internal2",
+		"AMIC3", "MIC BIAS External1";
+
+	quaternary-dai-link {
+		link-name = "ADV7533";
+		cpu {
+			sound-dai = <&lpass MI2S_QUATERNARY>;
+		};
+		codec {
+			sound-dai = <&adv_bridge 0>;
+		};
+	};
+
+	primary-dai-link {
+		link-name = "WCD";
+		cpu {
+			sound-dai = <&lpass MI2S_PRIMARY>;
+		};
+		codec {
+			sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
+		};
+	};
+
+	tertiary-dai-link {
+		link-name = "WCD-Capture";
+		cpu {
+			sound-dai = <&lpass MI2S_TERTIARY>;
+		};
+		codec {
+			sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
+		};
+	};
+};
+
+&usb {
+	status = "okay";
+	extcon = <&usb_id>, <&usb_id>;
+
+	pinctrl-names = "default", "device";
+	pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
+	pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
+};
+
+&usb_hs_phy {
+	extcon = <&usb_id>;
+};
+
+&venus {
+	status = "okay";
+};
+
+&venus_mem {
+	status = "okay";
+};
+
+&wcnss {
+	status = "okay";
+	firmware-name = "qcom/apq8016/wcnss.mbn";
+};
+
+&wcnss_ctrl {
+	firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
+};
+
+&wcnss_iris {
+	compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+	status = "okay";
+};
+
+/* Enable CoreSight */
+&cti0 { status = "okay"; };
+&cti1 { status = "okay"; };
+&cti12 { status = "okay"; };
+&cti13 { status = "okay"; };
+&cti14 { status = "okay"; };
+&cti15 { status = "okay"; };
+&debug0 { status = "okay"; };
+&debug1 { status = "okay"; };
+&debug2 { status = "okay"; };
+&debug3 { status = "okay"; };
+&etf { status = "okay"; };
+&etm0 { status = "okay"; };
+&etm1 { status = "okay"; };
+&etm2 { status = "okay"; };
+&etm3 { status = "okay"; };
+&etr { status = "okay"; };
+&funnel0 { status = "okay"; };
+&funnel1 { status = "okay"; };
+&replicator { status = "okay"; };
+&stm { status = "okay"; };
+&tpiu { status = "okay"; };
+
+/*
+ * 2mA drive strength is not enough when connecting multiple
+ * I2C devices with different pull up resistors.
+ */
+&blsp_i2c2_default {
+	drive-strength = <16>;
+};
+
+&blsp_i2c4_default {
+	drive-strength = <16>;
+};
+
+&blsp_i2c6_default {
+	drive-strength = <16>;
+};
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ *         NC = not connected (pin out but not routed from the chip to
+ *              anything the board)
+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ *         LSEC = Low Speed External Connector
+ *         HSEC = High Speed External Connector
+ *
+ * Line names are taken from the schematic "DragonBoard410c"
+ * dated monday, august 31, 2015. Page 5 in particular.
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
+&tlmm {
+	gpio-line-names =
+		"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
+		"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
+		"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
+		"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
+		"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
+		"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
+		"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
+		"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
+		"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
+		"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
+		"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
+		"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
+		"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
+		"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
+		"[I2C3_SDA]", /* HSEC pin 38 */
+		"[I2C3_SCL]", /* HSEC pin 36 */
+		"[SPI0_MOSI]", /* LSEC pin 14 */
+		"[SPI0_MISO]", /* LSEC pin 10 */
+		"[SPI0_CS_N]", /* LSEC pin 12 */
+		"[SPI0_CLK]", /* LSEC pin 8 */
+		"HDMI_HPD_N", /* GPIO 20 */
+		"USR_LED_1_CTRL",
+		"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
+		"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
+		"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
+		"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
+		"[CSI0_MCLK]", /* HSEC pin 15 */
+		"[CSI1_MCLK]", /* HSEC pin 17 */
+		"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
+		"[I2C2_SDA]", /* HSEC pin 34 */
+		"[I2C2_SCL]", /* HSEC pin 32 */
+		"DSI2HDMI_INT_N",
+		"DSI_SW_SEL_APQ",
+		"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
+		"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
+		"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
+		"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
+		"FORCED_USB_BOOT",
+		"SD_CARD_DET_N",
+		"[WCSS_BT_SSBI]",
+		"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
+		"[WCSS_WLAN_DATA_1]",
+		"[WCSS_WLAN_DATA_0]",
+		"[WCSS_WLAN_SET]",
+		"[WCSS_WLAN_CLK]",
+		"[WCSS_FM_SSBI]",
+		"[WCSS_FM_SDI]",
+		"[WCSS_BT_DAT_CTL]",
+		"[WCSS_BT_DAT_STB]",
+		"NC",
+		"NC", /* GPIO 50 */
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC", /* GPIO 60 */
+		"NC",
+		"NC",
+		"[CDC_PDM0_CLK]",
+		"[CDC_PDM0_SYNC]",
+		"[CDC_PDM0_TX0]",
+		"[CDC_PDM0_RX0]",
+		"[CDC_PDM0_RX1]",
+		"[CDC_PDM0_RX2]",
+		"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
+		"NC", /* GPIO 70 */
+		"NC",
+		"NC",
+		"NC",
+		"NC", /* GPIO 74 */
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"BOOT_CONFIG_0", /* GPIO 80 */
+		"BOOT_CONFIG_1",
+		"BOOT_CONFIG_2",
+		"BOOT_CONFIG_3",
+		"NC",
+		"NC",
+		"BOOT_CONFIG_5",
+		"NC",
+		"NC",
+		"NC",
+		"NC", /* GPIO 90 */
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC", /* GPIO 100 */
+		"NC",
+		"NC",
+		"NC",
+		"SSBI_GPS",
+		"NC",
+		"NC",
+		"KEY_VOLP_N",
+		"NC",
+		"NC",
+		"[LS_EXP_MI2S_WS]", /* GPIO 110 */
+		"NC",
+		"NC",
+		"[LS_EXP_MI2S_SCK]",
+		"[LS_EXP_MI2S_DATA0]",
+		"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
+		"NC",
+		"[DSI2HDMI_MI2S_WS]",
+		"[DSI2HDMI_MI2S_SCK]",
+		"[DSI2HDMI_MI2S_DATA0]",
+		"USR_LED_2_CTRL", /* GPIO 120 */
+		"SB_HS_ID";
+
+	sdc2_cd_default: sdc2-cd-default-state {
+		pins = "gpio38";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tlmm_leds: tlmm-leds-state {
+		pins = "gpio21", "gpio120";
+		function = "gpio";
+
+		output-low;
+	};
+
+	usb_id_default: usb-id-default-state {
+		pins = "gpio121";
+		function = "gpio";
+
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	adv7533_int_active: adv533-int-active-state {
+		pins = "gpio31";
+		function = "gpio";
+
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	adv7533_int_suspend: adv7533-int-suspend-state {
+		pins = "gpio31";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	adv7533_switch_active: adv7533-switch-active-state {
+		pins = "gpio32";
+		function = "gpio";
+
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	adv7533_switch_suspend: adv7533-switch-suspend-state {
+		pins = "gpio32";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	msm_key_volp_n_default: msm-key-volp-n-default-state {
+		pins = "gpio107";
+		function = "gpio";
+
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+};
+
+&pm8916_gpios {
+	gpio-line-names =
+		"USR_LED_3_CTRL",
+		"USR_LED_4_CTRL",
+		"USB_HUB_RESET_N_PM",
+		"USB_SW_SEL_PM";
+
+	usb_hub_reset_pm: usb-hub-reset-pm-state {
+		pins = "gpio3";
+		function = PMIC_GPIO_FUNC_NORMAL;
+
+		input-disable;
+		output-high;
+	};
+
+	usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {
+		pins = "gpio3";
+		function = PMIC_GPIO_FUNC_NORMAL;
+
+		output-low;
+	};
+
+	usb_sw_sel_pm: usb-sw-sel-pm-state {
+		pins = "gpio4";
+		function = PMIC_GPIO_FUNC_NORMAL;
+
+		power-source = <PM8916_GPIO_VPH>;
+		input-disable;
+		output-high;
+	};
+
+	usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {
+		pins = "gpio4";
+		function = PMIC_GPIO_FUNC_NORMAL;
+
+		power-source = <PM8916_GPIO_VPH>;
+		input-disable;
+		output-low;
+	};
+
+	pm8916_gpios_leds: pm8916-gpios-leds-state {
+		pins = "gpio1", "gpio2";
+		function = PMIC_GPIO_FUNC_NORMAL;
+
+		output-low;
+	};
+};
+
+&pm8916_mpps {
+	gpio-line-names =
+		"VDD_PX_BIAS",
+		"WLAN_LED_CTRL",
+		"BT_LED_CTRL",
+		"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ls_exp_gpio_f>;
+
+	ls_exp_gpio_f: pm8916-mpp4-state {
+		pins = "mpp4";
+		function = "digital";
+
+		output-low;
+		power-source = <PM8916_MPP_L5>;	/* 1.8V */
+	};
+
+	pm8916_mpps_leds: pm8916-mpps-state {
+		pins = "mpp2", "mpp3";
+		function = "digital";
+
+		output-low;
+	};
+};
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi
deleted file mode 100644
index cec64bf80f99..000000000000
--- a/arch/arm/dts/dragonboard410c-uboot.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot addition to handle Dragonboard 410c pins
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-
-/ {
-
-	smem {
-		bootph-all;
-	};
-
-	soc {
-		bootph-all;
-
-		pinctrl@1000000 {
-			bootph-all;
-
-			uart {
-				bootph-all;
-			};
-		};
-
-		qcom,gcc@1800000 {
-			bootph-all;
-		};
-
-		serial@78b0000 {
-			bootph-all;
-		};
-	};
-};
-
-
-&pm8916_gpios {
-	usb_hub_reset_pm {
-		gpios = <&pm8916_gpios 2 0>;
-	};
-
-	usb_sw_sel_pm {
-		gpios = <&pm8916_gpios 3 0>;
-	};
-};
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
deleted file mode 100644
index 453642b25705..000000000000
--- a/arch/arm/dts/dragonboard410c.dts
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8016 based Dragonboard 410C board device tree source
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-
-/dts-v1/;
-
-#include "skeleton64.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Qualcomm Technologies, Inc. Dragonboard 410c";
-	compatible = "qcom,apq8016-sbc", "qcom,apq8016";
-	qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
-	qcom,board-id = <0x10018 0x0>;
-	#address-cells = <0x2>;
-	#size-cells = <0x2>;
-
-	aliases {
-		usb0 = "/soc/ehci@78d9000";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x3da00000>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		smem_mem: smem_region@86300000 {
-			reg = <0x0 0x86300000 0x0 0x100000>;
-			no-map;
-		};
-	};
-
-	chosen {
-		stdout-path = "/soc/serial@78b0000";
-	};
-
-	smem {
-		compatible = "qcom,smem";
-		memory-region = <&smem_mem>;
-		qcom,rpm-msg-ram = <&rpm_msg_ram>;
-	};
-
-	soc {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		ranges = <0x0 0x0 0x0 0xffffffff>;
-		compatible = "simple-bus";
-
-		rpm_msg_ram: memory@60000 {
-			compatible = "qcom,rpm-msg-ram";
-			reg = <0x60000 0x8000>;
-		};
-
-		soc_gpios: pinctrl@1000000 {
-			compatible = "qcom,msm8916-pinctrl";
-			reg = <0x1000000 0x400000>;
-			gpio-controller;
-			gpio-count = <122>;
-			gpio-bank-name="soc";
-			#gpio-cells = <2>;
-
-			blsp1_uart: uart {
-				function = "blsp1_uart";
-				pins = "GPIO_4", "GPIO_5";
-				drive-strength = <8>;
-				bias-disable;
-			};
-		};
-		clkc: qcom,gcc@1800000 {
-			compatible = "qcom,gcc-msm8916";
-			reg = <0x1800000 0x80000>;
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			#clock-cells = <0x1>;
-		};
-
-		serial@78b0000 {
-			compatible = "qcom,msm-uartdm-v1.4";
-			reg = <0x78b0000 0x200>;
-			clocks = <&clkc 4>;
-			clock-names = "core";
-			pinctrl-names = "uart";
-			pinctrl-0 = <&blsp1_uart>;
-		};
-
-		ehci@78d9000 {
-			compatible = "qcom,ci-hdrc";
-			reg = <0x78d9000 0x400>;
-			phys = <&ehci_phy>;
-
-			ulpi {
-				usb_hs_phy: phy {
-					compatible = "qcom,usb-hs-phy-msm8916",
-						     "qcom,usb-hs-phy";
-					#phy-cells = <0>;
-					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
-					clock-names = "ref", "sleep";
-					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
-					reset-names = "phy", "por";
-					qcom,init-seq = /bits/ 8 <0x0 0x44>,
-								 <0x1 0x6b>,
-								 <0x2 0x24>,
-								 <0x3 0x13>;
-				};
-			};
-		};
-
-		sdhci@07824000 {
-			compatible = "qcom,sdhci-msm-v4";
-			reg = <0x7824900 0x11c 0x7824000 0x800>;
-			bus-width = <0x8>;
-			index = <0x0>;
-			non-removable;
-			clock = <&clkc 0>;
-			clock-frequency = <100000000>;
-		};
-
-		sdhci@07864000 {
-			compatible = "qcom,sdhci-msm-v4";
-			reg = <0x7864900 0x11c 0x7864000 0x800>;
-			index = <0x1>;
-			bus-width = <0x4>;
-			clock = <&clkc 1>;
-			clock-frequency = <200000000>;
-			cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
-		};
-
-		wcnss {
-			bt {
-				compatible="qcom,wcnss-bt";
-			};
-
-			wifi {
-				compatible="qcom,wcnss-wlan";
-			};
-		};
-
-		spmi_bus: spmi@200f000 {
-			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x0200f000 0x001000>,
-			      <0x02400000 0x400000>,
-			      <0x02c00000 0x400000>,
-			      <0x03800000 0x200000>,
-			      <0x0200a000 0x002100>;
-			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			pmic0: pm8916@0 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x0 0x1>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
-
-				pon@800 {
-					compatible = "qcom,pm8916-pon";
-					reg = <0x800 0x100>;
-					mode-bootloader = <0x2>;
-					mode-recovery = <0x1>;
-
-					pwrkey {
-						compatible = "qcom,pm8941-pwrkey";
-						debounce = <15625>;
-						bias-pull-up;
-					};
-
-					pm8916_resin: resin {
-						compatible = "qcom,pm8941-resin";
-						debounce = <15625>;
-						bias-pull-up;
-					};
-				};
-
-				pm8916_gpios: pm8916_gpios@c000 {
-					compatible = "qcom,pm8916-gpio";
-					reg = <0xc000 0x400>;
-					gpio-controller;
-					gpio-ranges = <&pm8916_gpios 0 0 4>;
-					#gpio-cells = <2>;
-				};
-			};
-
-			pmic1: pm8916@1 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x1 0x1>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		user1 {
-			label = "green:user1";
-			gpios = <&soc_gpios 21 0>;
-		};
-
-		user2 {
-			label = "green:user2";
-			gpios = <&soc_gpios 120 0>;
-		};
-
-		user3 {
-			label = "green:user3";
-			gpios = <&pm8916_gpios 0 0>;
-		};
-
-		user4 {
-			label = "green:user4";
-			gpios = <&pm8916_gpios 1 0>;
-		};
-	};
-};
-
-#include "dragonboard410c-uboot.dtsi"
diff --git a/arch/arm/dts/msm8916.dtsi b/arch/arm/dts/msm8916.dtsi
new file mode 100644
index 000000000000..4f799b536a92
--- /dev/null
+++ b/arch/arm/dts/msm8916.dtsi
@@ -0,0 +1,2702 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/arm/coresight-cti-dt.h>
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interconnect/qcom,msm8916.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz-apps@86000000 {
+			reg = <0x0 0x86000000 0x0 0x300000>;
+			no-map;
+		};
+
+		smem@86300000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86300000 0x0 0x100000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		};
+
+		hypervisor@86400000 {
+			reg = <0x0 0x86400000 0x0 0x100000>;
+			no-map;
+		};
+
+		tz@86500000 {
+			reg = <0x0 0x86500000 0x0 0x180000>;
+			no-map;
+		};
+
+		reserved@86680000 {
+			reg = <0x0 0x86680000 0x0 0x80000>;
+			no-map;
+		};
+
+		rmtfs@86700000 {
+			compatible = "qcom,rmtfs-mem";
+			reg = <0x0 0x86700000 0x0 0xe0000>;
+			no-map;
+
+			qcom,client-id = <1>;
+		};
+
+		rfsa@867e0000 {
+			reg = <0x0 0x867e0000 0x0 0x20000>;
+			no-map;
+		};
+
+		mpss_mem: mpss@86800000 {
+			/*
+			 * The memory region for the mpss firmware is generally
+			 * relocatable and could be allocated dynamically.
+			 * However, many firmware versions tend to fail when
+			 * loaded to some special addresses, so it is hard to
+			 * define reliable alloc-ranges.
+			 *
+			 * alignment = <0x0 0x400000>;
+			 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			 */
+			reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
+			no-map;
+			status = "disabled";
+		};
+
+		wcnss_mem: wcnss {
+			size = <0x0 0x600000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		venus_mem: venus {
+			size = <0x0 0x500000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		mba_mem: mba {
+			size = <0x0 0x100000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			qcom,acc = <&cpu0_acc>;
+			qcom,saw = <&cpu0_saw>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			qcom,acc = <&cpu1_acc>;
+			qcom,saw = <&cpu1_saw>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			qcom,acc = <&cpu2_acc>;
+			qcom,saw = <&cpu2_saw>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			qcom,acc = <&cpu3_acc>;
+			qcom,saw = <&cpu3_saw>;
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x40000002>;
+				entry-latency-us = <130>;
+				exit-latency-us = <150>;
+				min-residency-us = <2000>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+
+			CLUSTER_RET: cluster-retention {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000012>;
+				entry-latency-us = <500>;
+				exit-latency-us = <500>;
+				min-residency-us = <2000>;
+			};
+
+			CLUSTER_PWRDN: cluster-gdhs {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000032>;
+				entry-latency-us = <2000>;
+				exit-latency-us = <2000>;
+				min-residency-us = <6000>;
+			};
+		};
+	};
+
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+		};
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+		};
+		opp-998400000 {
+			opp-hz = /bits/ 64 <998400000>;
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-msm8916", "qcom,scm";
+			clocks = <&gcc GCC_CRYPTO_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "core", "bus", "iface";
+			#reset-cells = <1>;
+
+			qcom,dload-mode = <&tcsr 0x6100>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_SLEEP_0>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_SLEEP_0>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_SLEEP_0>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_SLEEP_0>;
+		};
+
+		CLUSTER_PD: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
+		};
+	};
+
+	rpm: remoteproc {
+		compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
+
+		smd-edge {
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,ipc = <&apcs 8 0>;
+			qcom,smd-edge = <15>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-msm8916";
+				qcom,smd-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
+					#clock-cells = <1>;
+					clocks = <&xo_board>;
+					clock-names = "xo";
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,msm8916-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp_ret: opp1 {
+							opp-level = <1>;
+						};
+						rpmpd_opp_svs_krait: opp2 {
+							opp-level = <2>;
+						};
+						rpmpd_opp_svs_soc: opp3 {
+							opp-level = <3>;
+						};
+						rpmpd_opp_nom: opp4 {
+							opp-level = <4>;
+						};
+						rpmpd_opp_turbo: opp5 {
+							opp-level = <5>;
+						};
+						rpmpd_opp_super_turbo: opp6 {
+							opp-level = <6>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	smp2p-hexagon {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		hexagon_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		hexagon_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcnss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <451>, <431>;
+
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 18>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <4>;
+
+		wcnss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcnss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,ipc-1 = <&apcs 8 13>;
+		qcom,ipc-3 = <&apcs 8 19>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		hexagon_smsm: hexagon@1 {
+			reg = <1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@6 {
+			reg = <6>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		rng@22000 {
+			compatible = "qcom,prng";
+			reg = <0x00022000 0x200>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		restart@4ab000 {
+			compatible = "qcom,pshold";
+			reg = <0x004ab000 0x4>;
+		};
+
+		qfprom: qfprom@5c000 {
+			compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
+			reg = <0x0005c000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			tsens_base1: base1@d0 {
+				reg = <0xd0 0x1>;
+				bits = <0 7>;
+			};
+
+			tsens_s0_p1: s0-p1@d0 {
+				reg = <0xd0 0x2>;
+				bits = <7 5>;
+			};
+
+			tsens_s0_p2: s0-p2@d1 {
+				reg = <0xd1 0x2>;
+				bits = <4 5>;
+			};
+
+			tsens_s1_p1: s1-p1@d2 {
+				reg = <0xd2 0x1>;
+				bits = <1 5>;
+			};
+			tsens_s1_p2: s1-p2@d2 {
+				reg = <0xd2 0x2>;
+				bits = <6 5>;
+			};
+			tsens_s2_p1: s2-p1@d3 {
+				reg = <0xd3 0x1>;
+				bits = <3 5>;
+			};
+
+			tsens_s2_p2: s2-p2@d4 {
+				reg = <0xd4 0x1>;
+				bits = <0 5>;
+			};
+
+			// no tsens with hw_id 3
+
+			tsens_s4_p1: s4-p1@d4 {
+				reg = <0xd4 0x2>;
+				bits = <5 5>;
+			};
+
+			tsens_s4_p2: s4-p2@d5 {
+				reg = <0xd5 0x1>;
+				bits = <2 5>;
+			};
+
+			tsens_s5_p1: s5-p1@d5 {
+				reg = <0xd5 0x2>;
+				bits = <7 5>;
+			};
+
+			tsens_s5_p2: s5-p2@d6 {
+				reg = <0xd6 0x2>;
+				bits = <4 5>;
+			};
+
+			tsens_base2: base2@d7 {
+				reg = <0xd7 0x1>;
+				bits = <1 7>;
+			};
+
+			tsens_mode: mode@ef {
+				reg = <0xef 0x1>;
+				bits = <5 3>;
+			};
+		};
+
+		rpm_msg_ram: sram@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x8000>;
+		};
+
+		sram@290000 {
+			compatible = "qcom,msm8916-rpm-stats";
+			reg = <0x00290000 0x10000>;
+		};
+
+		bimc: interconnect@400000 {
+			compatible = "qcom,msm8916-bimc";
+			reg = <0x00400000 0x62000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
+		};
+
+		tsens: thermal-sensor@4a9000 {
+			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
+			reg = <0x004a9000 0x1000>, /* TM */
+			      <0x004a8000 0x1000>; /* SROT */
+
+			// no hw_id 3
+			nvmem-cells = <&tsens_mode>,
+				      <&tsens_base1>, <&tsens_base2>,
+				      <&tsens_s0_p1>, <&tsens_s0_p2>,
+				      <&tsens_s1_p1>, <&tsens_s1_p2>,
+				      <&tsens_s2_p1>, <&tsens_s2_p2>,
+				      <&tsens_s4_p1>, <&tsens_s4_p2>,
+				      <&tsens_s5_p1>, <&tsens_s5_p2>;
+			nvmem-cell-names = "mode",
+					   "base1", "base2",
+					   "s0_p1", "s0_p2",
+					   "s1_p1", "s1_p2",
+					   "s2_p1", "s2_p2",
+					   "s4_p1", "s4_p2",
+					   "s5_p1", "s5_p2";
+			#qcom,sensors = <5>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow";
+			#thermal-sensor-cells = <1>;
+		};
+
+		pcnoc: interconnect@500000 {
+			compatible = "qcom,msm8916-pcnoc";
+			reg = <0x00500000 0x11000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
+				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
+		};
+
+		snoc: interconnect@580000 {
+			compatible = "qcom,msm8916-snoc";
+			reg = <0x00580000 0x14000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
+		};
+
+		stm: stm@802000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x00802000 0x1000>,
+			      <0x09280000 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		/* System CTIs */
+		/* CTI 0 - TMC connections */
+		cti0: cti@810000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x00810000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			status = "disabled";
+		};
+
+		/* CTI 1 - TPIU connections */
+		cti1: cti@811000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x00811000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			status = "disabled";
+		};
+
+		/* CTIs 2-11 - no information - not instantiated */
+
+		tpiu: tpiu@820000 {
+			compatible = "arm,coresight-tpiu", "arm,primecell";
+			reg = <0x00820000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			in-ports {
+				port {
+					tpiu_in: endpoint {
+						remote-endpoint = <&replicator_out1>;
+					};
+				};
+			};
+		};
+
+		funnel0: funnel@821000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x00821000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/*
+				 * Not described input ports:
+				 * 0 - connected to Resource and Power Manger CPU ETM
+				 * 1 - not-connected
+				 * 2 - connected to Modem CPU ETM
+				 * 3 - not-connected
+				 * 5 - not-connected
+				 * 6 - connected trought funnel to Wireless CPU ETM
+				 * 7 - connected to STM component
+				 */
+
+				port@4 {
+					reg = <4>;
+					funnel0_in4: endpoint {
+						remote-endpoint = <&funnel1_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint = <&etf_in>;
+					};
+				};
+			};
+		};
+
+		replicator: replicator@824000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x00824000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					replicator_out0: endpoint {
+						remote-endpoint = <&etr_in>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					replicator_out1: endpoint {
+						remote-endpoint = <&tpiu_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					replicator_in: endpoint {
+						remote-endpoint = <&etf_out>;
+					};
+				};
+			};
+		};
+
+		etf: etf@825000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x00825000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			in-ports {
+				port {
+					etf_in: endpoint {
+						remote-endpoint = <&funnel0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf_out: endpoint {
+						remote-endpoint = <&replicator_in>;
+					};
+				};
+			};
+		};
+
+		etr: etr@826000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x00826000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			in-ports {
+				port {
+					etr_in: endpoint {
+						remote-endpoint = <&replicator_out0>;
+					};
+				};
+			};
+		};
+
+		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x00841000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					funnel1_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					funnel1_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+				port@2 {
+					reg = <2>;
+					funnel1_in2: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+				port@3 {
+					reg = <3>;
+					funnel1_in3: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint = <&funnel0_in4>;
+					};
+				};
+			};
+		};
+
+		debug0: debug@850000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x00850000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU0>;
+			status = "disabled";
+		};
+
+		debug1: debug@852000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x00852000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU1>;
+			status = "disabled";
+		};
+
+		debug2: debug@854000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x00854000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU2>;
+			status = "disabled";
+		};
+
+		debug3: debug@856000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x00856000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU3>;
+			status = "disabled";
+		};
+
+		/* Core CTIs; CTIs 12-15 */
+		/* CTI - CPU-0 */
+		cti12: cti@858000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x00858000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU0>;
+			arm,cs-dev-assoc = <&etm0>;
+
+			status = "disabled";
+		};
+
+		/* CTI - CPU-1 */
+		cti13: cti@859000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x00859000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU1>;
+			arm,cs-dev-assoc = <&etm1>;
+
+			status = "disabled";
+		};
+
+		/* CTI - CPU-2 */
+		cti14: cti@85a000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x0085a000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU2>;
+			arm,cs-dev-assoc = <&etm2>;
+
+			status = "disabled";
+		};
+
+		/* CTI - CPU-3 */
+		cti15: cti@85b000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x0085b000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU3>;
+			arm,cs-dev-assoc = <&etm3>;
+
+			status = "disabled";
+		};
+
+		etm0: etm@85c000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x0085c000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+			arm,coresight-loses-context-with-cpu;
+
+			cpu = <&CPU0>;
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint = <&funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		etm1: etm@85d000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x0085d000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+			arm,coresight-loses-context-with-cpu;
+
+			cpu = <&CPU1>;
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint = <&funnel1_in1>;
+					};
+				};
+			};
+		};
+
+		etm2: etm@85e000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x0085e000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+			arm,coresight-loses-context-with-cpu;
+
+			cpu = <&CPU2>;
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint = <&funnel1_in2>;
+					};
+				};
+			};
+		};
+
+		etm3: etm@85f000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x0085f000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+			arm,coresight-loses-context-with-cpu;
+
+			cpu = <&CPU3>;
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint = <&funnel1_in3>;
+					};
+				};
+			};
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,msm8916-pinctrl";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 122>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp_i2c1_default: blsp-i2c1-default-state {
+				pins = "gpio2", "gpio3";
+				function = "blsp_i2c1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c1_sleep: blsp-i2c1-sleep-state {
+				pins = "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c2_default: blsp-i2c2-default-state {
+				pins = "gpio6", "gpio7";
+				function = "blsp_i2c2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c2_sleep: blsp-i2c2-sleep-state {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c3_default: blsp-i2c3-default-state {
+				pins = "gpio10", "gpio11";
+				function = "blsp_i2c3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c3_sleep: blsp-i2c3-sleep-state {
+				pins = "gpio10", "gpio11";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c4_default: blsp-i2c4-default-state {
+				pins = "gpio14", "gpio15";
+				function = "blsp_i2c4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c4_sleep: blsp-i2c4-sleep-state {
+				pins = "gpio14", "gpio15";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c5_default: blsp-i2c5-default-state {
+				pins = "gpio18", "gpio19";
+				function = "blsp_i2c5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c5_sleep: blsp-i2c5-sleep-state {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c6_default: blsp-i2c6-default-state {
+				pins = "gpio22", "gpio23";
+				function = "blsp_i2c6";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_i2c6_sleep: blsp-i2c6-sleep-state {
+				pins = "gpio22", "gpio23";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp_spi1_default: blsp-spi1-default-state {
+				spi-pins {
+					pins = "gpio0", "gpio1", "gpio3";
+					function = "blsp_spi1";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio2";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi1_sleep: blsp-spi1-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_spi2_default: blsp-spi2-default-state {
+				spi-pins {
+					pins = "gpio4", "gpio5", "gpio7";
+					function = "blsp_spi2";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio6";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi2_sleep: blsp-spi2-sleep-state {
+				pins = "gpio4", "gpio5", "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_spi3_default: blsp-spi3-default-state {
+				spi-pins {
+					pins = "gpio8", "gpio9", "gpio11";
+					function = "blsp_spi3";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio10";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi3_sleep: blsp-spi3-sleep-state {
+				pins = "gpio8", "gpio9", "gpio10", "gpio11";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_spi4_default: blsp-spi4-default-state {
+				spi-pins {
+					pins = "gpio12", "gpio13", "gpio15";
+					function = "blsp_spi4";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio14";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi4_sleep: blsp-spi4-sleep-state {
+				pins = "gpio12", "gpio13", "gpio14", "gpio15";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_spi5_default: blsp-spi5-default-state {
+				spi-pins {
+					pins = "gpio16", "gpio17", "gpio19";
+					function = "blsp_spi5";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio18";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi5_sleep: blsp-spi5-sleep-state {
+				pins = "gpio16", "gpio17", "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_spi6_default: blsp-spi6-default-state {
+				spi-pins {
+					pins = "gpio20", "gpio21", "gpio23";
+					function = "blsp_spi6";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				cs-pins {
+					pins = "gpio22";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp_spi6_sleep: blsp-spi6-sleep-state {
+				pins = "gpio20", "gpio21", "gpio22", "gpio23";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_uart1_default: blsp-uart1-default-state {
+				/* TX, RX, CTS_N, RTS_N */
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "blsp_uart1";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp_uart1_sleep: blsp-uart1-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp_uart2_default: blsp-uart2-default-state {
+				pins = "gpio4", "gpio5";
+				function = "blsp_uart2";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp_uart2_sleep: blsp-uart2-sleep-state {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			camera_front_default: camera-front-default-state {
+				pwdn-pins {
+					pins = "gpio33";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+				rst-pins {
+					pins = "gpio28";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+				mclk1-pins {
+					pins = "gpio27";
+					function = "cam_mclk1";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			camera_rear_default: camera-rear-default-state {
+				pwdn-pins {
+					pins = "gpio34";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+				rst-pins {
+					pins = "gpio35";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+				mclk0-pins {
+					pins = "gpio26";
+					function = "cam_mclk0";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			cci0_default: cci0-default-state {
+				pins = "gpio29", "gpio30";
+				function = "cci_i2c";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			cdc_dmic_default: cdc-dmic-default-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "dmic0_clk";
+					drive-strength = <8>;
+				};
+				data-pins {
+					pins = "gpio1";
+					function = "dmic0_data";
+					drive-strength = <8>;
+				};
+			};
+
+			cdc_dmic_sleep: cdc-dmic-sleep-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "dmic0_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+				data-pins {
+					pins = "gpio1";
+					function = "dmic0_data";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			cdc_pdm_default: cdc-pdm-default-state {
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+				function = "cdc_pdm0";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			cdc_pdm_sleep: cdc-pdm-sleep-state {
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+				function = "cdc_pdm0";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			pri_mi2s_default: mi2s-pri-default-state {
+				pins = "gpio113", "gpio114", "gpio115", "gpio116";
+				function = "pri_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			pri_mi2s_sleep: mi2s-pri-sleep-state {
+				pins = "gpio113", "gpio114", "gpio115", "gpio116";
+				function = "pri_mi2s";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
+				pins = "gpio116";
+				function = "pri_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
+				pins = "gpio116";
+				function = "pri_mi2s";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			pri_mi2s_ws_default: mi2s-pri-ws-default-state {
+				pins = "gpio110";
+				function = "pri_mi2s_ws";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
+				pins = "gpio110";
+				function = "pri_mi2s_ws";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			sec_mi2s_default: mi2s-sec-default-state {
+				pins = "gpio112", "gpio117", "gpio118", "gpio119";
+				function = "sec_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+			sec_mi2s_sleep: mi2s-sec-sleep-state {
+				pins = "gpio112", "gpio117", "gpio118", "gpio119";
+				function = "sec_mi2s";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			sdc1_default: sdc1-default-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc1_sleep: sdc1-sleep-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+
+			wcss_wlan_default: wcss-wlan-default-state {
+				pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+				function = "wcss_wlan";
+				drive-strength = <6>;
+				bias-pull-up;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-msm8916";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x01800000 0x80000>;
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi0_phy 0>,
+				 <0>,
+				 <0>,
+				 <0>;
+			clock-names = "xo",
+				      "sleep_clk",
+				      "dsi0pll",
+				      "dsi0pllbyte",
+				      "ext_mclk",
+				      "ext_pri_i2s",
+				      "ext_sec_i2s";
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x01905000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8916", "syscon";
+			reg = <0x01937000 0x30000>;
+		};
+
+		mdss: display-subsystem@1a00000 {
+			status = "disabled";
+			compatible = "qcom,mdss";
+			reg = <0x01a00000 0x1000>,
+			      <0x01ac8000 0x3000>;
+			reg-names = "mdss_phys", "vbif_phys";
+
+			power-domains = <&gcc MDSS_GDSC>;
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>;
+			clock-names = "iface",
+				      "bus",
+				      "vsync";
+
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdss_mdp: display-controller@1a01000 {
+				compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
+				reg = <0x01a01000 0x89000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_VSYNC_CLK>;
+				clock-names = "iface",
+					      "bus",
+					      "core",
+					      "vsync";
+
+				iommus = <&apps_iommu 4>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_mdp_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@1a98000 {
+				compatible = "qcom,msm8916-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0x01a98000 0x25c>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
+						  <&gcc PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>,
+							 <&mdss_dsi0_phy 1>;
+
+				clocks = <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_BYTE0_CLK>,
+					 <&gcc GCC_MDSS_PCLK0_CLK>,
+					 <&gcc GCC_MDSS_ESC0_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core";
+				phys = <&mdss_dsi0_phy>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&mdss_mdp_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@1a98300 {
+				compatible = "qcom,dsi-phy-28nm-lp";
+				reg = <0x01a98300 0xd4>,
+				      <0x01a98500 0x280>,
+				      <0x01a98780 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
+			};
+		};
+
+		camss: camss@1b0ac00 {
+			compatible = "qcom,msm8916-camss";
+			reg = <0x01b0ac00 0x200>,
+				<0x01b00030 0x4>,
+				<0x01b0b000 0x200>,
+				<0x01b00038 0x4>,
+				<0x01b08000 0x100>,
+				<0x01b08400 0x100>,
+				<0x01b0a000 0x500>,
+				<0x01b00020 0x10>,
+				<0x01b10000 0x1000>;
+			reg-names = "csiphy0",
+				"csiphy0_clk_mux",
+				"csiphy1",
+				"csiphy1_clk_mux",
+				"csid0",
+				"csid1",
+				"ispif",
+				"csi_clk_mux",
+				"vfe0";
+			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "csiphy0",
+				"csiphy1",
+				"csid0",
+				"csid1",
+				"ispif",
+				"vfe0";
+			power-domains = <&gcc VFE_GDSC>;
+			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+				<&gcc GCC_CAMSS_CSI0_CLK>,
+				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
+				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
+				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
+				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+				<&gcc GCC_CAMSS_CSI1_CLK>,
+				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
+				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
+				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
+				<&gcc GCC_CAMSS_AHB_CLK>,
+				<&gcc GCC_CAMSS_VFE0_CLK>,
+				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
+				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
+			clock-names = "top_ahb",
+				"ispif_ahb",
+				"csiphy0_timer",
+				"csiphy1_timer",
+				"csi0_ahb",
+				"csi0",
+				"csi0_phy",
+				"csi0_pix",
+				"csi0_rdi",
+				"csi1_ahb",
+				"csi1",
+				"csi1_phy",
+				"csi1_pix",
+				"csi1_rdi",
+				"ahb",
+				"vfe0",
+				"csi_vfe0",
+				"vfe_ahb",
+				"vfe_axi";
+			iommus = <&apps_iommu 3>;
+			status = "disabled";
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		cci: cci@1b0c000 {
+			compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x01b0c000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
+				<&gcc GCC_CAMSS_CCI_CLK>,
+				<&gcc GCC_CAMSS_AHB_CLK>;
+			clock-names = "camss_top_ahb", "cci_ahb",
+					  "cci", "camss_ahb";
+			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+					  <&gcc GCC_CAMSS_CCI_CLK>;
+			assigned-clock-rates = <80000000>, <19200000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&cci0_default>;
+			status = "disabled";
+
+			cci_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		gpu: gpu@1c00000 {
+			compatible = "qcom,adreno-306.0", "qcom,adreno";
+			reg = <0x01c00000 0x20000>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names =
+			    "core",
+			    "iface",
+			    "mem",
+			    "mem_iface",
+			    "alt_mem_iface",
+			    "gfx3d";
+			clocks =
+			    <&gcc GCC_OXILI_GFX3D_CLK>,
+			    <&gcc GCC_OXILI_AHB_CLK>,
+			    <&gcc GCC_OXILI_GMEM_CLK>,
+			    <&gcc GCC_BIMC_GFX_CLK>,
+			    <&gcc GCC_BIMC_GPU_CLK>,
+			    <&gcc GFX3D_CLK_SRC>;
+			power-domains = <&gcc OXILI_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+				};
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+				};
+			};
+		};
+
+		venus: video-codec@1d00000 {
+			compatible = "qcom,msm8916-venus";
+			reg = <0x01d00000 0xff000>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&gcc VENUS_GDSC>;
+			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+				 <&gcc GCC_VENUS0_AHB_CLK>,
+				 <&gcc GCC_VENUS0_AXI_CLK>;
+			clock-names = "core", "iface", "bus";
+			iommus = <&apps_iommu 5>;
+			memory-region = <&venus_mem>;
+			status = "disabled";
+
+			video-decoder {
+				compatible = "venus-decoder";
+			};
+
+			video-encoder {
+				compatible = "venus-encoder";
+			};
+		};
+
+		apps_iommu: iommu@1ef0000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01e20000 0x20000>;
+			reg = <0x01ef0000 0x3000>;
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_APSS_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <17>;
+
+			/* VFE */
+			iommu-ctx@3000 {
+				compatible = "qcom,msm-iommu-v1-sec";
+				reg = <0x3000 0x1000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* MDP_0 */
+			iommu-ctx@4000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x4000 0x1000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* VENUS_NS */
+			iommu-ctx@5000 {
+				compatible = "qcom,msm-iommu-v1-sec";
+				reg = <0x5000 0x1000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu_iommu: iommu@1f08000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01f08000 0x10000>;
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_GFX_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <18>;
+
+			/* GFX3D_USER */
+			iommu-ctx@1000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x1000 0x1000>;
+				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* GFX3D_PRIV */
+			iommu-ctx@2000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x2000 0x1000>;
+				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x400000>,
+			      <0x02c00000 0x400000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		bam_dmux_dma: dma-controller@4044000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x04044000 0x19000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+
+			num-channels = <6>;
+			qcom,num-ees = <1>;
+			qcom,powered-remotely;
+
+			status = "disabled";
+		};
+
+		mpss: remoteproc@4080000 {
+			compatible = "qcom,msm8916-mss-pil";
+			reg = <0x04080000 0x100>,
+			      <0x04020000 0x040>;
+
+			reg-names = "qdsp6", "rmb";
+
+			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			power-domains = <&rpmpd MSM8916_VDDCX>,
+					<&rpmpd MSM8916_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "bus", "mem", "xo";
+
+			qcom,smem-states = <&hexagon_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			resets = <&scm 0>;
+			reset-names = "mss_restart";
+
+			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
+
+			status = "disabled";
+
+			mba {
+				memory-region = <&mba_mem>;
+			};
+
+			mpss {
+				memory-region = <&mpss_mem>;
+			};
+
+			bam_dmux: bam-dmux {
+				compatible = "qcom,bam-dmux";
+
+				interrupt-parent = <&hexagon_smsm>;
+				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
+				interrupt-names = "pc", "pc-ack";
+
+				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+				qcom,smem-state-names = "pc", "pc-ack";
+
+				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			smd-edge {
+				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+				qcom,smd-edge = <0>;
+				qcom,ipc = <&apcs 8 12>;
+				qcom,remote-pid = <1>;
+
+				label = "hexagon";
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,smd-channels = "fastrpcsmd-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+					};
+				};
+			};
+		};
+
+		sound: sound@7702000 {
+			status = "disabled";
+			compatible = "qcom,apq8016-sbc-sndcard";
+			reg = <0x07702000 0x4>, <0x07702004 0x4>;
+			reg-names = "mic-iomux", "spkr-iomux";
+		};
+
+		lpass: audio-controller@7708000 {
+			status = "disabled";
+			compatible = "qcom,apq8016-lpass-cpu";
+
+			/*
+			 * Note: Unlike the name would suggest, the SEC_I2S_CLK
+			 * is actually only used by Tertiary MI2S while
+			 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
+			 */
+			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
+				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
+
+			clock-names = "ahbix-clk",
+					"mi2s-bit-clk0",
+					"mi2s-bit-clk1",
+					"mi2s-bit-clk2",
+					"mi2s-bit-clk3",
+					"pcnoc-mport-clk",
+					"pcnoc-sway-clk";
+			#sound-dai-cells = <1>;
+
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "lpass-irq-lpaif";
+			reg = <0x07708000 0x10000>;
+			reg-names = "lpass-lpaif";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		lpass_codec: audio-codec@771c000 {
+			compatible = "qcom,msm8916-wcd-digital-codec";
+			reg = <0x0771c000 0x400>;
+			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
+			clock-names = "ahbix-clk", "mclk";
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		sdhc_1: mmc@7824900 {
+			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
+			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc1_default>;
+			pinctrl-1 = <&sdc1_sleep>;
+			pinctrl-names = "default", "sleep";
+			mmc-ddr-1_8v;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		sdhc_2: mmc@7864900 {
+			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
+			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc2_default>;
+			pinctrl-1 = <&sdc2_sleep>;
+			pinctrl-names = "default", "sleep";
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		blsp_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x23000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		blsp_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_uart1_default>;
+			pinctrl-1 = <&blsp_uart1_sleep>;
+			status = "disabled";
+		};
+
+		blsp_uart2: serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b0000 0x200>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_uart2_default>;
+			pinctrl-1 = <&blsp_uart2_sleep>;
+			status = "disabled";
+		};
+
+		blsp_i2c1: i2c@78b5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b5000 0x500>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c1_default>;
+			pinctrl-1 = <&blsp_i2c1_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi1: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b5000 0x500>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi1_default>;
+			pinctrl-1 = <&blsp_spi1_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b6000 0x500>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c2_default>;
+			pinctrl-1 = <&blsp_i2c2_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi2: spi@78b6000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b6000 0x500>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi2_default>;
+			pinctrl-1 = <&blsp_spi2_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c3: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b7000 0x500>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c3_default>;
+			pinctrl-1 = <&blsp_i2c3_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi3: spi@78b7000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b7000 0x500>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi3_default>;
+			pinctrl-1 = <&blsp_spi3_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c4: i2c@78b8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b8000 0x500>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c4_default>;
+			pinctrl-1 = <&blsp_i2c4_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi4: spi@78b8000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b8000 0x500>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi4_default>;
+			pinctrl-1 = <&blsp_spi4_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c5: i2c@78b9000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b9000 0x500>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c5_default>;
+			pinctrl-1 = <&blsp_i2c5_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi5: spi@78b9000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b9000 0x500>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi5_default>;
+			pinctrl-1 = <&blsp_spi5_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c6: i2c@78ba000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078ba000 0x500>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_i2c6_default>;
+			pinctrl-1 = <&blsp_i2c6_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_spi6: spi@78ba000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078ba000 0x500>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp_spi6_default>;
+			pinctrl-1 = <&blsp_spi6_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		usb: usb@78d9000 {
+			compatible = "qcom,ci-hdrc";
+			reg = <0x078d9000 0x200>,
+			      <0x078d9200 0x200>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			clock-names = "iface", "core";
+			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <80000000>;
+			resets = <&gcc GCC_USB_HS_BCR>;
+			reset-names = "core";
+			phy_type = "ulpi";
+			dr_mode = "otg";
+			hnp-disable;
+			srp-disable;
+			adp-disable;
+			ahb-burst-config = <0>;
+			phy-names = "usb-phy";
+			phys = <&usb_hs_phy>;
+			status = "disabled";
+			#reset-cells = <1>;
+
+			ulpi {
+				usb_hs_phy: phy {
+					compatible = "qcom,usb-hs-phy-msm8916",
+						     "qcom,usb-hs-phy";
+					#phy-cells = <0>;
+					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+					clock-names = "ref", "sleep";
+					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
+					reset-names = "phy", "por";
+					qcom,init-seq = /bits/ 8 <0x0 0x44>,
+								 <0x1 0x6b>,
+								 <0x2 0x24>,
+								 <0x3 0x13>;
+				};
+			};
+		};
+
+		wcnss: remoteproc@a204000 {
+			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
+			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
+			reg-names = "ccu", "dxe", "pmu";
+
+			memory-region = <&wcnss_mem>;
+
+			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+			power-domains = <&rpmpd MSM8916_VDDCX>,
+					<&rpmpd MSM8916_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			qcom,smem-states = <&wcnss_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&wcss_wlan_default>;
+
+			status = "disabled";
+
+			wcnss_iris: iris {
+				/* Separate chip, compatible is board-specific */
+				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+				clock-names = "xo";
+			};
+
+			smd-edge {
+				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+				qcom,ipc = <&apcs 8 17>;
+				qcom,smd-edge = <6>;
+				qcom,remote-pid = <4>;
+
+				label = "pronto";
+
+				wcnss_ctrl: wcnss {
+					compatible = "qcom,wcnss";
+					qcom,smd-channels = "WCNSS_CTRL";
+
+					qcom,mmio = <&wcnss>;
+
+					wcnss_bt: bluetooth {
+						compatible = "qcom,wcnss-bt";
+					};
+
+					wcnss_wifi: wifi {
+						compatible = "qcom,wcnss-wlan";
+
+						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+						interrupt-names = "tx", "rx";
+
+						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
+			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
+			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		apcs: mailbox@b011000 {
+			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
+			reg = <0x0b011000 0x1000>;
+			#mbox-cells = <1>;
+			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
+			clock-names = "pll", "aux";
+			#clock-cells = <0>;
+		};
+
+		a53pll: clock@b016000 {
+			compatible = "qcom,msm8916-a53pll";
+			reg = <0x0b016000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+		};
+
+		timer@b020000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b020000 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@b021000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b021000 0x1000>,
+				      <0x0b022000 0x1000>;
+			};
+
+			frame@b023000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b023000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b024000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b024000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b025000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b025000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b026000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b026000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b027000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b027000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b028000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b028000 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		cpu0_acc: power-manager@b088000 {
+			compatible = "qcom,msm8916-acc";
+			reg = <0x0b088000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu0_saw: power-manager@b089000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+			reg = <0x0b089000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu1_acc: power-manager@b098000 {
+			compatible = "qcom,msm8916-acc";
+			reg = <0x0b098000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu1_saw: power-manager@b099000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+			reg = <0x0b099000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu2_acc: power-manager@b0a8000 {
+			compatible = "qcom,msm8916-acc";
+			reg = <0x0b0a8000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu2_saw: power-manager@b0a9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+			reg = <0x0b0a9000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu3_acc: power-manager@b0b8000 {
+			compatible = "qcom,msm8916-acc";
+			reg = <0x0b0b8000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+
+		cpu3_saw: power-manager@b0b9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+			reg = <0x0b0b9000 0x1000>;
+			status = "reserved"; /* Controlled by PSCI firmware */
+		};
+	};
+
+	thermal-zones {
+		cpu0-1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 5>;
+
+			trips {
+				cpu0_1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu0_1_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_1_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu2-3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 4>;
+
+			trips {
+				cpu2_3_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu2_3_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_3_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 2>;
+
+			trips {
+				gpu_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				gpu_crit: gpu-crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 1>;
+
+			trips {
+				cam_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		modem-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 0>;
+
+			trips {
+				modem_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index efdee8a40fa3..0481ceeb6c65 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
-CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
 CONFIG_SYS_LOAD_ADDR=0x80080000

-- 
2.43.1

[PATCH v4 33/39] dt-bindings: import headers for MSM8996

[Caleb Connolly]

Import dt-binding headers for MSM8996/APQ8096 from Linux.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 include/dt-bindings/clock/qcom,gcc-msm8996.h       | 362 +++++++++++++++++++++
 include/dt-bindings/clock/qcom,mmcc-msm8996.h      | 295 +++++++++++++++++
 .../dt-bindings/interconnect/qcom,msm8996-cbf.h    |  12 +
 include/dt-bindings/interconnect/qcom,msm8996.h    | 163 ++++++++++
 include/dt-bindings/sound/qcom,wcd9335.h           |  15 +
 5 files changed, 847 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 000000000000..ddfd6fd73081
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
+
+#define GPLL0_EARLY						0
+#define GPLL0							1
+#define GPLL1_EARLY						2
+#define GPLL1							3
+#define GPLL2_EARLY						4
+#define GPLL2							5
+#define GPLL3_EARLY						6
+#define GPLL3							7
+#define GPLL4_EARLY						8
+#define GPLL4							9
+#define SYSTEM_NOC_CLK_SRC					10
+/* U-Boot: KConfig check in CI erroneously picks this up, it's unused
+ * anyway so comment it out for now
+ */
+//#define CONFIG _NOC_CLK_SRC					11
+#define PERIPH_NOC_CLK_SRC					12
+#define MMSS_BIMC_GFX_CLK_SRC					13
+#define USB30_MASTER_CLK_SRC					14
+#define USB30_MOCK_UTMI_CLK_SRC					15
+#define USB3_PHY_AUX_CLK_SRC					16
+#define USB20_MASTER_CLK_SRC					17
+#define USB20_MOCK_UTMI_CLK_SRC					18
+#define SDCC1_APPS_CLK_SRC					19
+#define SDCC1_ICE_CORE_CLK_SRC					20
+#define SDCC2_APPS_CLK_SRC					21
+#define SDCC3_APPS_CLK_SRC					22
+#define SDCC4_APPS_CLK_SRC					23
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
+#define BLSP1_UART1_APPS_CLK_SRC				26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
+#define BLSP1_UART2_APPS_CLK_SRC				29
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
+#define BLSP1_UART3_APPS_CLK_SRC				32
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
+#define BLSP1_UART4_APPS_CLK_SRC				35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
+#define BLSP1_UART5_APPS_CLK_SRC				38
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
+#define BLSP1_UART6_APPS_CLK_SRC				41
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
+#define BLSP2_UART1_APPS_CLK_SRC				44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
+#define BLSP2_UART2_APPS_CLK_SRC				47
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
+#define BLSP2_UART3_APPS_CLK_SRC				50
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
+#define BLSP2_UART4_APPS_CLK_SRC				53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
+#define BLSP2_UART5_APPS_CLK_SRC				56
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
+#define BLSP2_UART6_APPS_CLK_SRC				59
+#define PDM2_CLK_SRC						60
+#define TSIF_REF_CLK_SRC					61
+#define CE1_CLK_SRC						62
+#define GCC_SLEEP_CLK_SRC					63
+#define BIMC_CLK_SRC						64
+#define HMSS_AHB_CLK_SRC					65
+#define BIMC_HMSS_AXI_CLK_SRC					66
+#define HMSS_RBCPR_CLK_SRC					67
+#define HMSS_GPLL0_CLK_SRC					68
+#define GP1_CLK_SRC						69
+#define GP2_CLK_SRC						70
+#define GP3_CLK_SRC						71
+#define PCIE_AUX_CLK_SRC					72
+#define UFS_AXI_CLK_SRC						73
+#define UFS_ICE_CORE_CLK_SRC					74
+#define QSPI_SER_CLK_SRC					75
+#define GCC_SYS_NOC_AXI_CLK					76
+#define GCC_SYS_NOC_HMSS_AHB_CLK				77
+#define GCC_SNOC_CNOC_AHB_CLK					78
+#define GCC_SNOC_PNOC_AHB_CLK					79
+#define GCC_SYS_NOC_AT_CLK					80
+#define GCC_SYS_NOC_USB3_AXI_CLK				81
+#define GCC_SYS_NOC_UFS_AXI_CLK					82
+#define GCC_CFG_NOC_AHB_CLK					83
+#define GCC_PERIPH_NOC_AHB_CLK					84
+#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
+#define GCC_TIC_CLK						86
+#define GCC_IMEM_AXI_CLK					87
+#define GCC_MMSS_SYS_NOC_AXI_CLK				88
+#define GCC_MMSS_NOC_CFG_AHB_CLK				89
+#define GCC_MMSS_BIMC_GFX_CLK					90
+#define GCC_USB30_MASTER_CLK					91
+#define GCC_USB30_SLEEP_CLK					92
+#define GCC_USB30_MOCK_UTMI_CLK					93
+#define GCC_USB3_PHY_AUX_CLK					94
+#define GCC_USB3_PHY_PIPE_CLK					95
+#define GCC_USB20_MASTER_CLK					96
+#define GCC_USB20_SLEEP_CLK					97
+#define GCC_USB20_MOCK_UTMI_CLK					98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
+#define GCC_SDCC1_APPS_CLK					100
+#define GCC_SDCC1_AHB_CLK					101
+#define GCC_SDCC1_ICE_CORE_CLK					102
+#define GCC_SDCC2_APPS_CLK					103
+#define GCC_SDCC2_AHB_CLK					104
+#define GCC_SDCC3_APPS_CLK					105
+#define GCC_SDCC3_AHB_CLK					106
+#define GCC_SDCC4_APPS_CLK					107
+#define GCC_SDCC4_AHB_CLK					108
+#define GCC_BLSP1_AHB_CLK					109
+#define GCC_BLSP1_SLEEP_CLK					110
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
+#define GCC_BLSP1_UART1_APPS_CLK				113
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
+#define GCC_BLSP1_UART2_APPS_CLK				116
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
+#define GCC_BLSP1_UART3_APPS_CLK				119
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
+#define GCC_BLSP1_UART4_APPS_CLK				122
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
+#define GCC_BLSP1_UART5_APPS_CLK				125
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
+#define GCC_BLSP1_UART6_APPS_CLK				128
+#define GCC_BLSP2_AHB_CLK					129
+#define GCC_BLSP2_SLEEP_CLK					130
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
+#define GCC_BLSP2_UART1_APPS_CLK				133
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
+#define GCC_BLSP2_UART2_APPS_CLK				136
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
+#define GCC_BLSP2_UART3_APPS_CLK				139
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
+#define GCC_BLSP2_UART4_APPS_CLK				142
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
+#define GCC_BLSP2_UART5_APPS_CLK				145
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
+#define GCC_BLSP2_UART6_APPS_CLK				148
+#define GCC_PDM_AHB_CLK						149
+#define GCC_PDM_XO4_CLK						150
+#define GCC_PDM2_CLK						151
+#define GCC_PRNG_AHB_CLK					152
+#define GCC_TSIF_AHB_CLK					153
+#define GCC_TSIF_REF_CLK					154
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
+#define GCC_TCSR_AHB_CLK					156
+#define GCC_BOOT_ROM_AHB_CLK					157
+#define GCC_MSG_RAM_AHB_CLK					158
+#define GCC_TLMM_AHB_CLK					159
+#define GCC_TLMM_CLK						160
+#define GCC_MPM_AHB_CLK						161
+#define GCC_SPMI_SER_CLK					162
+#define GCC_SPMI_CNOC_AHB_CLK					163
+#define GCC_CE1_CLK						164
+#define GCC_CE1_AXI_CLK						165
+#define GCC_CE1_AHB_CLK						166
+#define GCC_BIMC_HMSS_AXI_CLK					167
+#define GCC_BIMC_GFX_CLK					168
+#define GCC_HMSS_AHB_CLK					169
+#define GCC_HMSS_SLV_AXI_CLK					170
+#define GCC_HMSS_MSTR_AXI_CLK					171
+#define GCC_HMSS_RBCPR_CLK					172
+#define GCC_GP1_CLK						173
+#define GCC_GP2_CLK						174
+#define GCC_GP3_CLK						175
+#define GCC_PCIE_0_SLV_AXI_CLK					176
+#define GCC_PCIE_0_MSTR_AXI_CLK					177
+#define GCC_PCIE_0_CFG_AHB_CLK					178
+#define GCC_PCIE_0_AUX_CLK					179
+#define GCC_PCIE_0_PIPE_CLK					180
+#define GCC_PCIE_1_SLV_AXI_CLK					181
+#define GCC_PCIE_1_MSTR_AXI_CLK					182
+#define GCC_PCIE_1_CFG_AHB_CLK					183
+#define GCC_PCIE_1_AUX_CLK					184
+#define GCC_PCIE_1_PIPE_CLK					185
+#define GCC_PCIE_2_SLV_AXI_CLK					186
+#define GCC_PCIE_2_MSTR_AXI_CLK					187
+#define GCC_PCIE_2_CFG_AHB_CLK					188
+#define GCC_PCIE_2_AUX_CLK					189
+#define GCC_PCIE_2_PIPE_CLK					190
+#define GCC_PCIE_PHY_CFG_AHB_CLK				191
+#define GCC_PCIE_PHY_AUX_CLK					192
+#define GCC_UFS_AXI_CLK						193
+#define GCC_UFS_AHB_CLK						194
+#define GCC_UFS_TX_CFG_CLK					195
+#define GCC_UFS_RX_CFG_CLK					196
+#define GCC_UFS_TX_SYMBOL_0_CLK					197
+#define GCC_UFS_RX_SYMBOL_0_CLK					198
+#define GCC_UFS_RX_SYMBOL_1_CLK					199
+#define GCC_UFS_UNIPRO_CORE_CLK					200
+#define GCC_UFS_ICE_CORE_CLK					201
+#define GCC_UFS_SYS_CLK_CORE_CLK				202
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
+#define GCC_AGGRE0_SNOC_AXI_CLK					204
+#define GCC_AGGRE0_CNOC_AHB_CLK					205
+#define GCC_SMMU_AGGRE0_AXI_CLK					206
+#define GCC_SMMU_AGGRE0_AHB_CLK					207
+#define GCC_AGGRE1_PNOC_AHB_CLK					208
+#define GCC_AGGRE2_UFS_AXI_CLK					209
+#define GCC_AGGRE2_USB3_AXI_CLK					210
+#define GCC_QSPI_AHB_CLK					211
+#define GCC_QSPI_SER_CLK					212
+#define GCC_USB3_CLKREF_CLK					213
+#define GCC_HDMI_CLKREF_CLK					214
+#define GCC_UFS_CLKREF_CLK					215
+#define GCC_PCIE_CLKREF_CLK					216
+#define GCC_RX2_USB2_CLKREF_CLK					217
+#define GCC_RX1_USB2_CLKREF_CLK					218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			220
+#define GCC_EDP_CLKREF_CLK					221
+#define GCC_MSS_CFG_AHB_CLK					222
+#define GCC_MSS_Q6_BIMC_AXI_CLK					223
+#define GCC_MSS_SNOC_AXI_CLK					224
+#define GCC_MSS_MNOC_BIMC_AXI_CLK				225
+#define GCC_DCC_AHB_CLK						226
+#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				227
+#define GCC_MMSS_GPLL0_DIV_CLK					228
+#define GCC_MSS_GPLL0_DIV_CLK					229
+
+#define GCC_SYSTEM_NOC_BCR					0
+#define GCC_CONFIG_NOC_BCR					1
+#define GCC_PERIPH_NOC_BCR					2
+#define GCC_IMEM_BCR						3
+#define GCC_MMSS_BCR						4
+#define GCC_PIMEM_BCR						5
+#define GCC_QDSS_BCR						6
+#define GCC_USB_30_BCR						7
+#define GCC_USB_20_BCR						8
+#define GCC_QUSB2PHY_PRIM_BCR					9
+#define GCC_QUSB2PHY_SEC_BCR					10
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				11
+#define GCC_SDCC1_BCR						12
+#define GCC_SDCC2_BCR						13
+#define GCC_SDCC3_BCR						14
+#define GCC_SDCC4_BCR						15
+#define GCC_BLSP1_BCR						16
+#define GCC_BLSP1_QUP1_BCR					17
+#define GCC_BLSP1_UART1_BCR					18
+#define GCC_BLSP1_QUP2_BCR					19
+#define GCC_BLSP1_UART2_BCR					20
+#define GCC_BLSP1_QUP3_BCR					21
+#define GCC_BLSP1_UART3_BCR					22
+#define GCC_BLSP1_QUP4_BCR					23
+#define GCC_BLSP1_UART4_BCR					24
+#define GCC_BLSP1_QUP5_BCR					25
+#define GCC_BLSP1_UART5_BCR					26
+#define GCC_BLSP1_QUP6_BCR					27
+#define GCC_BLSP1_UART6_BCR					28
+#define GCC_BLSP2_BCR						29
+#define GCC_BLSP2_QUP1_BCR					30
+#define GCC_BLSP2_UART1_BCR					31
+#define GCC_BLSP2_QUP2_BCR					32
+#define GCC_BLSP2_UART2_BCR					33
+#define GCC_BLSP2_QUP3_BCR					34
+#define GCC_BLSP2_UART3_BCR					35
+#define GCC_BLSP2_QUP4_BCR					36
+#define GCC_BLSP2_UART4_BCR					37
+#define GCC_BLSP2_QUP5_BCR					38
+#define GCC_BLSP2_UART5_BCR					39
+#define GCC_BLSP2_QUP6_BCR					40
+#define GCC_BLSP2_UART6_BCR					41
+#define GCC_PDM_BCR						42
+#define GCC_PRNG_BCR						43
+#define GCC_TSIF_BCR						44
+#define GCC_TCSR_BCR						45
+#define GCC_BOOT_ROM_BCR					46
+#define GCC_MSG_RAM_BCR						47
+#define GCC_TLMM_BCR						48
+#define GCC_MPM_BCR						49
+#define GCC_SEC_CTRL_BCR					50
+#define GCC_SPMI_BCR						51
+#define GCC_SPDM_BCR						52
+#define GCC_CE1_BCR						53
+#define GCC_BIMC_BCR						54
+#define GCC_SNOC_BUS_TIMEOUT0_BCR				55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR				56
+#define GCC_SNOC_BUS_TIMEOUT1_BCR				57
+#define GCC_SNOC_BUS_TIMEOUT3_BCR				58
+#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR				60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR				61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR				62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR				63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR				64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR				65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR				66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR				67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR				68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR				69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR				70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR				71
+#define GCC_CNOC_BUS_TIMEOUT7_BCR				72
+#define GCC_CNOC_BUS_TIMEOUT8_BCR				73
+#define GCC_CNOC_BUS_TIMEOUT9_BCR				74
+#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				75
+#define GCC_APB2JTAG_BCR					76
+#define GCC_RBCPR_CX_BCR					77
+#define GCC_RBCPR_MX_BCR					78
+#define GCC_PCIE_0_BCR						79
+#define GCC_PCIE_0_PHY_BCR					80
+#define GCC_PCIE_1_BCR						81
+#define GCC_PCIE_1_PHY_BCR					82
+#define GCC_PCIE_2_BCR						83
+#define GCC_PCIE_2_PHY_BCR					84
+#define GCC_PCIE_PHY_BCR					85
+#define GCC_DCD_BCR						86
+#define GCC_OBT_ODT_BCR						87
+#define GCC_UFS_BCR						88
+#define GCC_SSC_BCR						89
+#define GCC_VS_BCR						90
+#define GCC_AGGRE0_NOC_BCR					91
+#define GCC_AGGRE1_NOC_BCR					92
+#define GCC_AGGRE2_NOC_BCR					93
+#define GCC_DCC_BCR						94
+#define GCC_IPA_BCR						95
+#define GCC_QSPI_BCR						96
+#define GCC_SKL_BCR						97
+#define GCC_MSMPU_BCR						98
+#define GCC_MSS_Q6_BCR						99
+#define GCC_QREFS_VBG_CAL_BCR					100
+#define GCC_PCIE_PHY_COM_BCR					101
+#define GCC_PCIE_PHY_COM_NOCSR_BCR				102
+#define GCC_USB3_PHY_BCR					103
+#define GCC_USB3PHY_PHY_BCR					104
+#define GCC_MSS_RESTART						105
+
+
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC			0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC	2
+#define HLOS1_VOTE_LPASS_CORE_GDSC	3
+#define USB30_GDSC			4
+#define PCIE0_GDSC			5
+#define PCIE1_GDSC			6
+#define PCIE2_GDSC			7
+#define UFS_GDSC			8
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
new file mode 100644
index 000000000000..d51f9ac70566
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -0,0 +1,295 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+
+#define MMPLL0_EARLY					0
+#define MMPLL0_PLL					1
+#define MMPLL1_EARLY					2
+#define MMPLL1_PLL					3
+#define MMPLL2_EARLY					4
+#define MMPLL2_PLL					5
+#define MMPLL3_EARLY					6
+#define MMPLL3_PLL					7
+#define MMPLL4_EARLY					8
+#define MMPLL4_PLL					9
+#define MMPLL5_EARLY					10
+#define MMPLL5_PLL					11
+#define MMPLL8_EARLY					12
+#define MMPLL8_PLL					13
+#define MMPLL9_EARLY					14
+#define MMPLL9_PLL					15
+#define AHB_CLK_SRC					16
+#define AXI_CLK_SRC					17
+#define MAXI_CLK_SRC					18
+#define DSA_CORE_CLK_SRC				19
+#define GFX3D_CLK_SRC					20
+#define RBBMTIMER_CLK_SRC				21
+#define ISENSE_CLK_SRC					22
+#define RBCPR_CLK_SRC					23
+#define VIDEO_CORE_CLK_SRC				24
+#define VIDEO_SUBCORE0_CLK_SRC				25
+#define VIDEO_SUBCORE1_CLK_SRC				26
+#define PCLK0_CLK_SRC					27
+#define PCLK1_CLK_SRC					28
+#define MDP_CLK_SRC					29
+#define EXTPCLK_CLK_SRC					30
+#define VSYNC_CLK_SRC					31
+#define HDMI_CLK_SRC					32
+#define BYTE0_CLK_SRC					33
+#define BYTE1_CLK_SRC					34
+#define ESC0_CLK_SRC					35
+#define ESC1_CLK_SRC					36
+#define CAMSS_GP0_CLK_SRC				37
+#define CAMSS_GP1_CLK_SRC				38
+#define MCLK0_CLK_SRC					39
+#define MCLK1_CLK_SRC					40
+#define MCLK2_CLK_SRC					41
+#define MCLK3_CLK_SRC					42
+#define CCI_CLK_SRC					43
+#define CSI0PHYTIMER_CLK_SRC				44
+#define CSI1PHYTIMER_CLK_SRC				45
+#define CSI2PHYTIMER_CLK_SRC				46
+#define CSIPHY0_3P_CLK_SRC				47
+#define CSIPHY1_3P_CLK_SRC				48
+#define CSIPHY2_3P_CLK_SRC				49
+#define JPEG0_CLK_SRC					50
+#define JPEG2_CLK_SRC					51
+#define JPEG_DMA_CLK_SRC				52
+#define VFE0_CLK_SRC					53
+#define VFE1_CLK_SRC					54
+#define CPP_CLK_SRC					55
+#define CSI0_CLK_SRC					56
+#define CSI1_CLK_SRC					57
+#define CSI2_CLK_SRC					58
+#define CSI3_CLK_SRC					59
+#define FD_CORE_CLK_SRC					60
+#define MMSS_CXO_CLK					61
+#define MMSS_SLEEPCLK_CLK				62
+#define MMSS_MMAGIC_AHB_CLK				63
+#define MMSS_MMAGIC_CFG_AHB_CLK				64
+#define MMSS_MISC_AHB_CLK				65
+#define MMSS_MISC_CXO_CLK				66
+#define MMSS_BTO_AHB_CLK				67
+#define MMSS_MMAGIC_AXI_CLK				68
+#define MMSS_S0_AXI_CLK					69
+#define MMSS_MMAGIC_MAXI_CLK				70
+#define DSA_CORE_CLK					71
+#define DSA_NOC_CFG_AHB_CLK				72
+#define MMAGIC_CAMSS_AXI_CLK				73
+#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK			74
+#define THROTTLE_CAMSS_CXO_CLK				75
+#define THROTTLE_CAMSS_AHB_CLK				76
+#define THROTTLE_CAMSS_AXI_CLK				77
+#define SMMU_VFE_AHB_CLK				78
+#define SMMU_VFE_AXI_CLK				79
+#define SMMU_CPP_AHB_CLK				80
+#define SMMU_CPP_AXI_CLK				81
+#define SMMU_JPEG_AHB_CLK				82
+#define SMMU_JPEG_AXI_CLK				83
+#define MMAGIC_MDSS_AXI_CLK				84
+#define MMAGIC_MDSS_NOC_CFG_AHB_CLK			85
+#define THROTTLE_MDSS_CXO_CLK				86
+#define THROTTLE_MDSS_AHB_CLK				87
+#define THROTTLE_MDSS_AXI_CLK				88
+#define SMMU_ROT_AHB_CLK				89
+#define SMMU_ROT_AXI_CLK				90
+#define SMMU_MDP_AHB_CLK				91
+#define SMMU_MDP_AXI_CLK				92
+#define MMAGIC_VIDEO_AXI_CLK				93
+#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK			94
+#define THROTTLE_VIDEO_CXO_CLK				95
+#define THROTTLE_VIDEO_AHB_CLK				96
+#define THROTTLE_VIDEO_AXI_CLK				97
+#define SMMU_VIDEO_AHB_CLK				98
+#define SMMU_VIDEO_AXI_CLK				99
+#define MMAGIC_BIMC_AXI_CLK				100
+#define MMAGIC_BIMC_NOC_CFG_AHB_CLK			101
+#define GPU_GX_GFX3D_CLK				102
+#define GPU_GX_RBBMTIMER_CLK				103
+#define GPU_AHB_CLK					104
+#define GPU_AON_ISENSE_CLK				105
+#define VMEM_MAXI_CLK					106
+#define VMEM_AHB_CLK					107
+#define MMSS_RBCPR_CLK					108
+#define MMSS_RBCPR_AHB_CLK				109
+#define VIDEO_CORE_CLK					110
+#define VIDEO_AXI_CLK					111
+#define VIDEO_MAXI_CLK					112
+#define VIDEO_AHB_CLK					113
+#define VIDEO_SUBCORE0_CLK				114
+#define VIDEO_SUBCORE1_CLK				115
+#define MDSS_AHB_CLK					116
+#define MDSS_HDMI_AHB_CLK				117
+#define MDSS_AXI_CLK					118
+#define MDSS_PCLK0_CLK					119
+#define MDSS_PCLK1_CLK					120
+#define MDSS_MDP_CLK					121
+#define MDSS_EXTPCLK_CLK				122
+#define MDSS_VSYNC_CLK					123
+#define MDSS_HDMI_CLK					124
+#define MDSS_BYTE0_CLK					125
+#define MDSS_BYTE1_CLK					126
+#define MDSS_ESC0_CLK					127
+#define MDSS_ESC1_CLK					128
+#define CAMSS_TOP_AHB_CLK				129
+#define CAMSS_AHB_CLK					130
+#define CAMSS_MICRO_AHB_CLK				131
+#define CAMSS_GP0_CLK					132
+#define CAMSS_GP1_CLK					133
+#define CAMSS_MCLK0_CLK					134
+#define CAMSS_MCLK1_CLK					135
+#define CAMSS_MCLK2_CLK					136
+#define CAMSS_MCLK3_CLK					137
+#define CAMSS_CCI_CLK					138
+#define CAMSS_CCI_AHB_CLK				139
+#define CAMSS_CSI0PHYTIMER_CLK				140
+#define CAMSS_CSI1PHYTIMER_CLK				141
+#define CAMSS_CSI2PHYTIMER_CLK				142
+#define CAMSS_CSIPHY0_3P_CLK				143
+#define CAMSS_CSIPHY1_3P_CLK				144
+#define CAMSS_CSIPHY2_3P_CLK				145
+#define CAMSS_JPEG0_CLK					146
+#define CAMSS_JPEG2_CLK					147
+#define CAMSS_JPEG_DMA_CLK				148
+#define CAMSS_JPEG_AHB_CLK				149
+#define CAMSS_JPEG_AXI_CLK				150
+#define CAMSS_VFE_AHB_CLK				151
+#define CAMSS_VFE_AXI_CLK				152
+#define CAMSS_VFE0_CLK					153
+#define CAMSS_VFE0_STREAM_CLK				154
+#define CAMSS_VFE0_AHB_CLK				155
+#define CAMSS_VFE1_CLK					156
+#define CAMSS_VFE1_STREAM_CLK				157
+#define CAMSS_VFE1_AHB_CLK				158
+#define CAMSS_CSI_VFE0_CLK				159
+#define CAMSS_CSI_VFE1_CLK				160
+#define CAMSS_CPP_VBIF_AHB_CLK				161
+#define CAMSS_CPP_AXI_CLK				162
+#define CAMSS_CPP_CLK					163
+#define CAMSS_CPP_AHB_CLK				164
+#define CAMSS_CSI0_CLK					165
+#define CAMSS_CSI0_AHB_CLK				166
+#define CAMSS_CSI0PHY_CLK				167
+#define CAMSS_CSI0RDI_CLK				168
+#define CAMSS_CSI0PIX_CLK				169
+#define CAMSS_CSI1_CLK					170
+#define CAMSS_CSI1_AHB_CLK				171
+#define CAMSS_CSI1PHY_CLK				172
+#define CAMSS_CSI1RDI_CLK				173
+#define CAMSS_CSI1PIX_CLK				174
+#define CAMSS_CSI2_CLK					175
+#define CAMSS_CSI2_AHB_CLK				176
+#define CAMSS_CSI2PHY_CLK				177
+#define CAMSS_CSI2RDI_CLK				178
+#define CAMSS_CSI2PIX_CLK				179
+#define CAMSS_CSI3_CLK					180
+#define CAMSS_CSI3_AHB_CLK				181
+#define CAMSS_CSI3PHY_CLK				182
+#define CAMSS_CSI3RDI_CLK				183
+#define CAMSS_CSI3PIX_CLK				184
+#define CAMSS_ISPIF_AHB_CLK				185
+#define FD_CORE_CLK					186
+#define FD_CORE_UAR_CLK					187
+#define FD_AHB_CLK					188
+#define MMSS_SPDM_CSI0_CLK				189
+#define MMSS_SPDM_JPEG_DMA_CLK				190
+#define MMSS_SPDM_CPP_CLK				191
+#define MMSS_SPDM_PCLK0_CLK				192
+#define MMSS_SPDM_AHB_CLK				193
+#define MMSS_SPDM_GFX3D_CLK				194
+#define MMSS_SPDM_PCLK1_CLK				195
+#define MMSS_SPDM_JPEG2_CLK				196
+#define MMSS_SPDM_DEBUG_CLK				197
+#define MMSS_SPDM_VFE1_CLK				198
+#define MMSS_SPDM_VFE0_CLK				199
+#define MMSS_SPDM_VIDEO_CORE_CLK			200
+#define MMSS_SPDM_AXI_CLK				201
+#define MMSS_SPDM_MDP_CLK				202
+#define MMSS_SPDM_JPEG0_CLK				203
+#define MMSS_SPDM_RM_AXI_CLK				204
+#define MMSS_SPDM_RM_MAXI_CLK				205
+
+#define MMAGICAHB_BCR					0
+#define MMAGIC_CFG_BCR					1
+#define MISC_BCR					2
+#define BTO_BCR						3
+#define MMAGICAXI_BCR					4
+#define MMAGICMAXI_BCR					5
+#define DSA_BCR						6
+#define MMAGIC_CAMSS_BCR				7
+#define THROTTLE_CAMSS_BCR				8
+#define SMMU_VFE_BCR					9
+#define SMMU_CPP_BCR					10
+#define SMMU_JPEG_BCR					11
+#define MMAGIC_MDSS_BCR					12
+#define THROTTLE_MDSS_BCR				13
+#define SMMU_ROT_BCR					14
+#define SMMU_MDP_BCR					15
+#define MMAGIC_VIDEO_BCR				16
+#define THROTTLE_VIDEO_BCR				17
+#define SMMU_VIDEO_BCR					18
+#define MMAGIC_BIMC_BCR					19
+#define GPU_GX_BCR					20
+#define GPU_BCR						21
+#define GPU_AON_BCR					22
+#define VMEM_BCR					23
+#define MMSS_RBCPR_BCR					24
+#define VIDEO_BCR					25
+#define MDSS_BCR					26
+#define CAMSS_TOP_BCR					27
+#define CAMSS_AHB_BCR					28
+#define CAMSS_MICRO_BCR					29
+#define CAMSS_CCI_BCR					30
+#define CAMSS_PHY0_BCR					31
+#define CAMSS_PHY1_BCR					32
+#define CAMSS_PHY2_BCR					33
+#define CAMSS_CSIPHY0_3P_BCR				34
+#define CAMSS_CSIPHY1_3P_BCR				35
+#define CAMSS_CSIPHY2_3P_BCR				36
+#define CAMSS_JPEG_BCR					37
+#define CAMSS_VFE_BCR					38
+#define CAMSS_VFE0_BCR					39
+#define CAMSS_VFE1_BCR					40
+#define CAMSS_CSI_VFE0_BCR				41
+#define CAMSS_CSI_VFE1_BCR				42
+#define CAMSS_CPP_TOP_BCR				43
+#define CAMSS_CPP_BCR					44
+#define CAMSS_CSI0_BCR					45
+#define CAMSS_CSI0RDI_BCR				46
+#define CAMSS_CSI0PIX_BCR				47
+#define CAMSS_CSI1_BCR					48
+#define CAMSS_CSI1RDI_BCR				49
+#define CAMSS_CSI1PIX_BCR				50
+#define CAMSS_CSI2_BCR					51
+#define CAMSS_CSI2RDI_BCR				52
+#define CAMSS_CSI2PIX_BCR				53
+#define CAMSS_CSI3_BCR					54
+#define CAMSS_CSI3RDI_BCR				55
+#define CAMSS_CSI3PIX_BCR				56
+#define CAMSS_ISPIF_BCR					57
+#define FD_BCR						58
+#define MMSS_SPDM_RM_BCR				59
+
+/* Indexes for GDSCs */
+#define MMAGIC_VIDEO_GDSC	0
+#define MMAGIC_MDSS_GDSC	1
+#define MMAGIC_CAMSS_GDSC	2
+#define GPU_GDSC		3
+#define VENUS_GDSC		4
+#define VENUS_CORE0_GDSC	5
+#define VENUS_CORE1_GDSC	6
+#define CAMSS_GDSC		7
+#define VFE0_GDSC		8
+#define VFE1_GDSC		9
+#define JPEG_GDSC		10
+#define CPP_GDSC		11
+#define FD_GDSC			12
+#define MDSS_GDSC		13
+#define GPU_GX_GDSC		14
+#define MMAGIC_BIMC_GDSC	15
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
new file mode 100644
index 000000000000..aac5e69f6bd5
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
+
+#define MASTER_CBF_M4M		0
+#define SLAVE_CBF_M4M		1
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h
new file mode 100644
index 000000000000..a0b7c0ec7bed
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8996.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
+/*
+ * Qualcomm MSM8996 interconnect IDs
+ *
+ * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
+
+/* A0NOC */
+#define MASTER_PCIE_0			0
+#define MASTER_PCIE_1			1
+#define MASTER_PCIE_2			2
+
+/* A1NOC */
+#define MASTER_CNOC_A1NOC		0
+#define MASTER_CRYPTO_CORE0		1
+#define MASTER_PNOC_A1NOC		2
+
+/* A2NOC */
+#define MASTER_USB3			0
+#define MASTER_IPA			1
+#define MASTER_UFS			2
+
+/* BIMC */
+#define MASTER_AMPSS_M0			0
+#define MASTER_GRAPHICS_3D		1
+#define MASTER_MNOC_BIMC		2
+#define MASTER_SNOC_BIMC		3
+#define SLAVE_EBI_CH0			4
+#define SLAVE_HMSS_L3			5
+#define SLAVE_BIMC_SNOC_0		6
+#define SLAVE_BIMC_SNOC_1		7
+
+/* CNOC */
+#define MASTER_SNOC_CNOC		0
+#define MASTER_QDSS_DAP			1
+#define SLAVE_CNOC_A1NOC		2
+#define SLAVE_CLK_CTL			3
+#define SLAVE_TCSR			4
+#define SLAVE_TLMM			5
+#define SLAVE_CRYPTO_0_CFG		6
+#define SLAVE_MPM			7
+#define SLAVE_PIMEM_CFG			8
+#define SLAVE_IMEM_CFG			9
+#define SLAVE_MESSAGE_RAM		10
+#define SLAVE_BIMC_CFG			11
+#define SLAVE_PMIC_ARB			12
+#define SLAVE_PRNG			13
+#define SLAVE_DCC_CFG			14
+#define SLAVE_RBCPR_MX			15
+#define SLAVE_QDSS_CFG			16
+#define SLAVE_RBCPR_CX			17
+#define SLAVE_QDSS_RBCPR_APU		18
+#define SLAVE_CNOC_MNOC_CFG		19
+#define SLAVE_SNOC_CFG			20
+#define SLAVE_SNOC_MPU_CFG		21
+#define SLAVE_EBI1_PHY_CFG		22
+#define SLAVE_A0NOC_CFG			23
+#define SLAVE_PCIE_1_CFG		24
+#define SLAVE_PCIE_2_CFG		25
+#define SLAVE_PCIE_0_CFG		26
+#define SLAVE_PCIE20_AHB2PHY		27
+#define SLAVE_A0NOC_MPU_CFG		28
+#define SLAVE_UFS_CFG			29
+#define SLAVE_A1NOC_CFG			30
+#define SLAVE_A1NOC_MPU_CFG		31
+#define SLAVE_A2NOC_CFG			32
+#define SLAVE_A2NOC_MPU_CFG		33
+#define SLAVE_SSC_CFG			34
+#define SLAVE_A0NOC_SMMU_CFG		35
+#define SLAVE_A1NOC_SMMU_CFG		36
+#define SLAVE_A2NOC_SMMU_CFG		37
+#define SLAVE_LPASS_SMMU_CFG		38
+#define SLAVE_CNOC_MNOC_MMSS_CFG	39
+
+/* MNOC */
+#define MASTER_CNOC_MNOC_CFG		0
+#define MASTER_CPP			1
+#define MASTER_JPEG			2
+#define MASTER_MDP_PORT0		3
+#define MASTER_MDP_PORT1		4
+#define MASTER_ROTATOR			5
+#define MASTER_VIDEO_P0			6
+#define MASTER_VFE			7
+#define MASTER_SNOC_VMEM		8
+#define MASTER_VIDEO_P0_OCMEM		9
+#define MASTER_CNOC_MNOC_MMSS_CFG	10
+#define SLAVE_MNOC_BIMC			11
+#define SLAVE_VMEM			12
+#define SLAVE_SERVICE_MNOC		13
+#define SLAVE_MMAGIC_CFG		14
+#define SLAVE_CPR_CFG			15
+#define SLAVE_MISC_CFG			16
+#define SLAVE_VENUS_THROTTLE_CFG	17
+#define SLAVE_VENUS_CFG			18
+#define SLAVE_VMEM_CFG			19
+#define SLAVE_DSA_CFG			20
+#define SLAVE_MMSS_CLK_CFG		21
+#define SLAVE_DSA_MPU_CFG		22
+#define SLAVE_MNOC_MPU_CFG		23
+#define SLAVE_DISPLAY_CFG		24
+#define SLAVE_DISPLAY_THROTTLE_CFG	25
+#define SLAVE_CAMERA_CFG		26
+#define SLAVE_CAMERA_THROTTLE_CFG	27
+#define SLAVE_GRAPHICS_3D_CFG		28
+#define SLAVE_SMMU_MDP_CFG		29
+#define SLAVE_SMMU_ROT_CFG		30
+#define SLAVE_SMMU_VENUS_CFG		31
+#define SLAVE_SMMU_CPP_CFG		32
+#define SLAVE_SMMU_JPEG_CFG		33
+#define SLAVE_SMMU_VFE_CFG		34
+
+/* PNOC */
+#define MASTER_SNOC_PNOC		0
+#define MASTER_SDCC_1			1
+#define MASTER_SDCC_2			2
+#define MASTER_SDCC_4			3
+#define MASTER_USB_HS			4
+#define MASTER_BLSP_1			5
+#define MASTER_BLSP_2			6
+#define MASTER_TSIF			7
+#define SLAVE_PNOC_A1NOC		8
+#define SLAVE_USB_HS			9
+#define SLAVE_SDCC_2			10
+#define SLAVE_SDCC_4			11
+#define SLAVE_TSIF			12
+#define SLAVE_BLSP_2			13
+#define SLAVE_SDCC_1			14
+#define SLAVE_BLSP_1			15
+#define SLAVE_PDM			16
+#define SLAVE_AHB2PHY			17
+
+/* SNOC */
+#define MASTER_HMSS			0
+#define MASTER_QDSS_BAM			1
+#define MASTER_SNOC_CFG			2
+#define MASTER_BIMC_SNOC_0		3
+#define MASTER_BIMC_SNOC_1		4
+#define MASTER_A0NOC_SNOC		5
+#define MASTER_A1NOC_SNOC		6
+#define MASTER_A2NOC_SNOC		7
+#define MASTER_QDSS_ETR			8
+#define SLAVE_A0NOC_SNOC		9
+#define SLAVE_A1NOC_SNOC		10
+#define SLAVE_A2NOC_SNOC		11
+#define SLAVE_HMSS			12
+#define SLAVE_LPASS			13
+#define SLAVE_USB3			14
+#define SLAVE_SNOC_BIMC			15
+#define SLAVE_SNOC_CNOC			16
+#define SLAVE_IMEM			17
+#define SLAVE_PIMEM			18
+#define SLAVE_SNOC_VMEM			19
+#define SLAVE_SNOC_PNOC			20
+#define SLAVE_QDSS_STM			21
+#define SLAVE_PCIE_0			22
+#define SLAVE_PCIE_1			23
+#define SLAVE_PCIE_2			24
+#define SLAVE_SERVICE_SNOC		25
+
+#endif
diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h
new file mode 100644
index 000000000000..f5e9f1db091e
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,wcd9335.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_SOUND_QCOM_WCD9335_H
+#define __DT_SOUND_QCOM_WCD9335_H
+
+#define AIF1_PB                 0
+#define AIF1_CAP                1
+#define AIF2_PB                 2
+#define AIF2_CAP                3
+#define AIF3_PB                 4
+#define AIF3_CAP                5
+#define AIF4_PB                 6
+#define NUM_CODEC_DAIS          7
+
+#endif

-- 
2.43.1

[PATCH v4 34/39] dts: msm8996: import PMIC dtsi files

[Caleb Connolly]

Import PM8994 and PMI8994 DTSI files in preparation for switching
MSM8996 boards to upstream DTS.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/pm8994.dtsi  | 152 ++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/pmi8994.dtsi |  65 ++++++++++++++++++++
 2 files changed, 217 insertions(+)

diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi
new file mode 100644
index 000000000000..d44a95caf04a
--- /dev/null
+++ b/arch/arm/dts/pm8994.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pm8994-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&pm8994_temp>;
+
+			trips {
+				pm8994_alert0: pm8994-alert0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				pm8994_crit: pm8994-crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+
+	pmic@0 {
+		compatible = "qcom,pm8994", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pm8994_pon: pon@800 {
+			compatible = "qcom,pm8916-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+
+			pm8994_resin: resin {
+				compatible = "qcom,pm8941-resin";
+				interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				status = "disabled";
+			};
+		};
+
+		pm8994_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8994_vadc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@7 {
+				reg = <VADC_VSYS>;
+				qcom,pre-scaling = <1 3>;
+				label = "vph_pwr";
+			};
+			channel@8 {
+				reg = <VADC_DIE_TEMP>;
+				label = "die_temp";
+			};
+			channel@9 {
+				reg = <VADC_REF_625MV>;
+				label = "ref_625mv";
+			};
+			channel@a {
+				reg = <VADC_REF_1250MV>;
+				label = "ref_1250mv";
+			};
+			channel@e {
+				reg = <VADC_GND_REF>;
+			};
+			channel@f {
+				reg = <VADC_VDD_VADC>;
+			};
+		};
+
+		pm8994_gpios: gpio@c000 {
+			compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm8994_gpios 0 0 22>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8994_mpps: mpps@a000 {
+			compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pm8994_mpps 0 0 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pmic@1 {
+		compatible = "qcom,pm8994", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8994_lpg: pwm {
+			compatible = "qcom,pm8994-lpg";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		pm8994_spmi_regulators: regulators {
+			compatible = "qcom,pm8994-regulators";
+		};
+	};
+};
diff --git a/arch/arm/dts/pmi8994.dtsi b/arch/arm/dts/pmi8994.dtsi
new file mode 100644
index 000000000000..36d6a1fb553a
--- /dev/null
+++ b/arch/arm/dts/pmi8994.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	pmic@2 {
+		compatible = "qcom,pmi8994", "qcom,spmi-pmic";
+		reg = <0x2 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmi8994_gpios: gpio@c000 {
+			compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pmi8994_gpios 0 0 10>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmi8994_mpps: mpps@a000 {
+			compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			gpio-ranges = <&pmi8994_mpps 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pmic@3 {
+		compatible = "qcom,pmi8994", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmi8994_lpg: pwm {
+			compatible = "qcom,pmi8994-lpg";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		pmi8994_spmi_regulators: regulators {
+			compatible = "qcom,pmi8994-regulators";
+		};
+
+		pmi8994_wled: wled@d800 {
+			compatible = "qcom,pmi8994-wled";
+			reg = <0xd800>, <0xd900>;
+			interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ovp", "short";
+			qcom,cabc;
+			qcom,external-pfet;
+			status = "disabled";
+		};
+	};
+};

-- 
2.43.1

[PATCH v4 35/39] dts: dragonboard820c: use correct bindings for clocks

[Caleb Connolly]

Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be
compatible with upstream.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/dragonboard820c.dts | 5 +++--
 drivers/clk/qcom/clock-apq8096.c | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 86b7f83d36d6..282c37e28f42 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/clock/qcom,gcc-msm8996.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. DB820c";
@@ -78,7 +79,7 @@
 		blsp2_uart2: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
-			clocks = <&gcc 4>;
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
 			clock-names = "core";
 			pinctrl-names = "uart";
 			pinctrl-0 = <&blsp8_uart>;
@@ -89,7 +90,7 @@
 			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 			index = <0x0>;
 			bus-width = <4>;
-			clock = <&gcc 0>;
+			clock = <&gcc GCC_SDCC1_APPS_CLK>;
 			clock-frequency = <200000000>;
 		 };
 
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index 1e6fdb5cd42d..a4731613c5e0 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -13,6 +13,7 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-msm8996.h>
 
 #include "clock-qcom.h"
 
@@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case 0: /* SDC1 */
+	case GCC_SDCC1_APPS_CLK: /* SDC1 */
 		return clk_init_sdc(priv, rate);
 		break;
-	case 4: /*UART2*/
+	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
 		return clk_init_uart(priv);
 	default:
 		return 0;

-- 
2.43.1

[PATCH v4 36/39] dts: msm8996: replace with upstream DTS

[Caleb Connolly]

Drop the U-Boot specific dragonboard820c.dts file in favour of the
upstream apq8096-db820c.dts and an additional -u-boot.dtsi with the
U-Boot specific additions.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/Makefile                   |    2 +-
 arch/arm/dts/apq8096-db820c-u-boot.dtsi |   14 +
 arch/arm/dts/apq8096-db820c.dts         | 1137 +++++++++
 arch/arm/dts/dragonboard820c-uboot.dtsi |   32 -
 arch/arm/dts/dragonboard820c.dts        |  153 --
 arch/arm/dts/msm8996.dtsi               | 3884 +++++++++++++++++++++++++++++++
 configs/dragonboard820c_defconfig       |    2 +-
 7 files changed, 5037 insertions(+), 187 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9ba1a94da5d0..54aaf022c2eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -632,7 +632,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
 dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
-	dragonboard820c.dtb \
+	apq8096-db820c.dtb \
 	sdm845-db845c.dtb \
 	sdm845-samsung-starqltechn.dtb \
 	qcs404-evb.dtb
diff --git a/arch/arm/dts/apq8096-db820c-u-boot.dtsi b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
new file mode 100644
index 000000000000..be61ea262b90
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+	/* Ensure that the fdtfile variable is generated properly */
+	compatible = "qcom,apq8096-db820c", "qcom,apq8096";
+};
+
+&sdhc2 {
+	status = "okay";
+	clock-frequency = <100000000>;
+};
diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts
new file mode 100644
index 000000000000..e8148b3d6c50
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include <dt-bindings/sound/qcom,wcd9335.h>
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ *         NC      = not connected (pin out but not routed from the chip to
+ *                   anything the board)
+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ *         LSEC    = Low Speed External Connector
+ *         P HSEC  = Primary High Speed External Connector
+ *         S HSEC  = Secondary High Speed External Connector
+ *         J14     = Camera Connector
+ *         TP      = Test Points
+ *
+ * Line names are taken from the schematic "DragonBoard 820c",
+ * drawing no: LM25-P2751-1
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
+/ {
+	model = "Qualcomm Technologies, Inc. DB820c";
+	compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
+
+	aliases {
+		serial0 = &blsp2_uart2;
+		serial1 = &blsp2_uart3;
+		serial2 = &blsp1_uart2;
+		i2c0 = &blsp1_i2c3;
+		i2c1 = &blsp2_i2c1;
+		i2c2 = &blsp2_i2c1;
+		spi0 = &blsp1_spi1;
+		spi1 = &blsp2_spi6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	div1_mclk: divclk1 {
+		compatible = "gpio-gate-clock";
+		pinctrl-0 = <&audio_mclk>;
+		pinctrl-names = "default";
+		clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+		#clock-cells = <0>;
+		enable-gpios = <&pm8994_gpios 15 0>;
+	};
+
+	divclk4: divclk4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "divclk4";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&divclk4_pin_a>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&volume_up_gpio>;
+
+		button {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	usb2_id: usb2-id {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb2_vbus_det_gpio>;
+	};
+
+	usb3_id: usb3-id {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_vbus_det_gpio>;
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+	};
+
+	wlan_en: wlan-en-1-8v {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wlan_en_gpios>;
+		compatible = "regulator-fixed";
+		regulator-name = "wlan-en-regulator";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8994_gpios 8 0>;
+
+		/* WLAN card specific delay */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+};
+
+&blsp1_i2c3 {
+	/* On Low speed expansion: LS-I2C0 */
+	status = "okay";
+};
+
+&blsp1_spi1 {
+	/* On Low speed expansion */
+	status = "okay";
+};
+
+&blsp1_uart2 {
+	label = "BT-UART";
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,qca6174-bt";
+
+		/* bt_disable_n gpio */
+		enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+
+		clocks = <&divclk4>;
+	};
+};
+
+&adsp_pil {
+	status = "okay";
+	firmware-name = "qcom/apq8096/adsp.mbn";
+};
+
+&blsp2_i2c1 {
+	/* On High speed expansion: HS-I2C2 */
+	status = "okay";
+};
+
+&blsp2_i2c1 {
+	/* On Low speed expansion: LS-I2C1 */
+	status = "okay";
+};
+
+&blsp2_spi6 {
+	/* On High speed expansion */
+	status = "okay";
+};
+
+&blsp2_uart2 {
+	label = "LS-UART1";
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&blsp2_uart2_2pins_default>;
+	pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
+};
+
+&blsp2_uart3 {
+	label = "LS-UART0";
+	status = "disabled";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&blsp2_uart3_4pins_default>;
+	pinctrl-1 = <&blsp2_uart3_4pins_sleep>;
+};
+
+&camss {
+	vdda-supply = <&vreg_l2a_1p25>;
+};
+
+&gpu {
+	status = "okay";
+};
+
+&hsusb_phy1 {
+	status = "okay";
+
+	vdd-supply = <&vreg_l28a_0p925>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+};
+
+&hsusb_phy2 {
+	status = "okay";
+
+	vdd-supply = <&vreg_l28a_0p925>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+};
+
+&mdp {
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_hdmi {
+	status = "okay";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+	pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+	core-vdda-supply = <&vreg_l12a_1p8>;
+	core-vcc-supply = <&vreg_s4a_1p8>;
+};
+
+&mdss_hdmi_phy {
+	status = "okay";
+
+	vddio-supply = <&vreg_l12a_1p8>;
+	vcca-supply = <&vreg_l28a_0p925>;
+	#phy-cells = <0>;
+};
+
+&mmcc {
+	vdd-gfx-supply = <&vdd_gfx>;
+};
+
+&mss_pil {
+	status = "okay";
+	pll-supply = <&vreg_l12a_1p8>;
+	firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn";
+};
+
+&pm8994_resin {
+	status = "okay";
+	linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&tlmm {
+	gpio-line-names =
+		"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
+		"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
+		"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
+		"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
+		"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
+		"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
+		"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
+		"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
+		"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
+		"TP93", /* GPIO_9 */
+		"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
+		"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
+		"NC", /* GPIO_12 */
+		"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
+		"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
+		"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
+		"TP99", /* GPIO_16 */
+		"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
+		"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
+		"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
+		"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
+		"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
+		"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
+		"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
+		"GPIO-D", /* GPIO_24, LSEC pin 26 */
+		"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
+		"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
+		"BLSP6_I2C_SDA", /* GPIO_27 */
+		"BLSP6_I2C_SCL", /* GPIO_28 */
+		"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
+		"GPIO30", /* GPIO_30, S HSEC pin 4 */
+		"HDMI_CEC", /* GPIO_31 */
+		"HDMI_DDC_CLOCK", /* GPIO_32 */
+		"HDMI_DDC_DATA", /* GPIO_33 */
+		"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
+		"PCIE0_RST_N", /* GPIO_35 */
+		"PCIE0_CLKREQ_N", /* GPIO_36 */
+		"PCIE0_WAKE", /* GPIO_37 */
+		"SD_CARD_DET_N", /* GPIO_38 */
+		"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
+		"W_DISABLE_N", /* GPIO_40 */
+		"[BLSP9_UART_TX]", /* GPIO_41 */
+		"[BLSP9_UART_RX]", /* GPIO_42 */
+		"[BLSP2_UART_CTS_N]", /* GPIO_43 */
+		"[BLSP2_UART_RFR_N]", /* GPIO_44 */
+		"[BLSP3_UART_TX]", /* GPIO_45 */
+		"[BLSP3_UART_RX]", /* GPIO_46 */
+		"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
+		"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
+		"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
+		"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
+		"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
+		"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
+		"[CODEC_INT1_N]", /* GPIO_53 */
+		"[CODEC_INT2_N]", /* GPIO_54 */
+		"[BLSP7_I2C_SDA]", /* GPIO_55 */
+		"[BLSP7_I2C_SCL]", /* GPIO_56 */
+		"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
+		"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
+		"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
+		"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
+		"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
+		"GPIO-E", /* GPIO_62, LSEC pin 27 */
+		"TP87", /* GPIO_63 */
+		"[CODEC_RST_N]", /* GPIO_64 */
+		"[PCM1_CLK]", /* GPIO_65 */
+		"[PCM1_SYNC]", /* GPIO_66 */
+		"[PCM1_DIN]", /* GPIO_67 */
+		"[PCM1_DOUT]", /* GPIO_68 */
+		"AUDIO_REF_CLK", /* GPIO_69 */
+		"SLIMBUS_CLK", /* GPIO_70 */
+		"SLIMBUS_DATA0", /* GPIO_71 */
+		"SLIMBUS_DATA1", /* GPIO_72 */
+		"NC", /* GPIO_73 */
+		"NC", /* GPIO_74 */
+		"NC", /* GPIO_75 */
+		"NC", /* GPIO_76 */
+		"TP94", /* GPIO_77 */
+		"NC", /* GPIO_78 */
+		"TP95", /* GPIO_79 */
+		"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
+		"TP88", /* GPIO_81 */
+		"TP89", /* GPIO_82 */
+		"TP90", /* GPIO_83 */
+		"TP91", /* GPIO_84 */
+		"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
+		"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
+		"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
+		"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
+		"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
+		"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
+		"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
+		"NC", /* GPIO_92 */
+		"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
+		"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
+		"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
+		"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
+		"NC", /* GPIO_97 */
+		"CAM1_STANDBY_N", /* GPIO_98 */
+		"NC", /* GPIO_99 */
+		"NC", /* GPIO_100 */
+		"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
+		"BOOT_CONFIG1", /* GPIO_102 */
+		"USB_HUB_RESET", /* GPIO_103 */
+		"CAM1_RST_N", /* GPIO_104 */
+		"NC", /* GPIO_105 */
+		"NC", /* GPIO_106 */
+		"NC", /* GPIO_107 */
+		"NC", /* GPIO_108 */
+		"NC", /* GPIO_109 */
+		"NC", /* GPIO_110 */
+		"NC", /* GPIO_111 */
+		"NC", /* GPIO_112 */
+		"PMI8994_BUA", /* GPIO_113 */
+		"PCIE2_RST_N", /* GPIO_114 */
+		"PCIE2_CLKREQ_N", /* GPIO_115 */
+		"PCIE2_WAKE", /* GPIO_116 */
+		"SSC_IRQ_0", /* GPIO_117 */
+		"SSC_IRQ_1", /* GPIO_118 */
+		"SSC_IRQ_2", /* GPIO_119 */
+		"NC", /* GPIO_120 */
+		"GPIO121", /* GPIO_121, S HSEC pin 2 */
+		"NC", /* GPIO_122 */
+		"SSC_IRQ_6", /* GPIO_123 */
+		"SSC_IRQ_7", /* GPIO_124 */
+		"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
+		"BOOT_CONFIG5", /* GPIO_126 */
+		"NC", /* GPIO_127 */
+		"NC", /* GPIO_128 */
+		"BOOT_CONFIG7", /* GPIO_129 */
+		"PCIE1_RST_N", /* GPIO_130 */
+		"PCIE1_CLKREQ_N", /* GPIO_131 */
+		"PCIE1_WAKE", /* GPIO_132 */
+		"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
+		"NC", /* GPIO_134 */
+		"NC", /* GPIO_135 */
+		"BOOT_CONFIG8", /* GPIO_136 */
+		"NC", /* GPIO_137 */
+		"NC", /* GPIO_138 */
+		"GPS_SSBI2", /* GPIO_139 */
+		"GPS_SSBI1", /* GPIO_140 */
+		"NC", /* GPIO_141 */
+		"NC", /* GPIO_142 */
+		"NC", /* GPIO_143 */
+		"BOOT_CONFIG6", /* GPIO_144 */
+		"NC", /* GPIO_145 */
+		"NC", /* GPIO_146 */
+		"NC", /* GPIO_147 */
+		"NC", /* GPIO_148 */
+		"NC"; /* GPIO_149 */
+
+	sdc2_cd_on: sdc2-cd-on-state {
+		pins = "gpio38";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <16>;
+	};
+
+	sdc2_cd_off: sdc2-cd-off-state {
+		pins = "gpio38";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <2>;
+	};
+
+	hdmi_hpd_active: hdmi-hpd-active-state {
+		pins = "gpio34";
+		function = "hdmi_hot";
+		bias-pull-down;
+		drive-strength = <16>;
+	};
+
+	hdmi_hpd_suspend: hdmi-hpd-suspend-state {
+		pins = "gpio34";
+		function = "hdmi_hot";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	hdmi_ddc_active: hdmi-ddc-active-state {
+		pins = "gpio32", "gpio33";
+		function = "hdmi_ddc";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	hdmi_ddc_suspend: hdmi-ddc-suspend-state {
+		pins = "gpio32", "gpio33";
+		function = "hdmi_ddc";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+	vddpe-3v3-supply = <&wlan_en>;
+	vdda-supply = <&vreg_l28a_0p925>;
+};
+
+&pcie1 {
+	status = "okay";
+	perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+	vdda-supply = <&vreg_l28a_0p925>;
+};
+
+&pcie2 {
+	status = "okay";
+	perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+	vdda-supply = <&vreg_l28a_0p925>;
+};
+
+&pcie_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l28a_0p925>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+};
+
+&pm8994_gpios {
+	gpio-line-names =
+		"NC",
+		"KEY_VOLP_N",
+		"NC",
+		"BL1_PWM",
+		"GPIO-F", /* BL0_PWM, LSEC pin 28 */
+		"BL1_EN",
+		"NC",
+		"WLAN_EN",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"DIVCLK1",
+		"DIVCLK2",
+		"DIVCLK3",
+		"DIVCLK4",
+		"BT_EN",
+		"PMIC_SLB",
+		"PMIC_BUA",
+		"USB_VBUS_DET";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
+
+	ls_exp_gpio_f: pm8994-gpio5-state {
+		pinconf {
+			pins = "gpio5";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+		};
+	};
+
+	bt_en_gpios: bt-en-pios-state {
+		pinconf {
+			pins = "gpio19";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+			bias-pull-down;
+		};
+	};
+
+	wlan_en_gpios: wlan-en-gpios-state {
+		pinconf {
+			pins = "gpio8";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+			bias-pull-down;
+		};
+	};
+
+	audio_mclk: clk-div1-state {
+		pinconf {
+			pins = "gpio15";
+			function = "func1";
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+		};
+	};
+
+	volume_up_gpio: pm8996-gpio2-state {
+		pinconf {
+			pins = "gpio2";
+			function = "normal";
+			input-enable;
+			drive-push-pull;
+			bias-pull-up;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+		};
+	};
+
+	divclk4_pin_a: divclk4-state {
+		pinconf {
+			pins = "gpio18";
+			function = PMIC_GPIO_FUNC_FUNC2;
+
+			bias-disable;
+			power-source = <PM8994_GPIO_S4>;
+		};
+	};
+
+	usb3_vbus_det_gpio: pm8996-gpio22-state {
+		pinconf {
+			pins = "gpio22";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+		};
+	};
+};
+
+&pm8994_mpps {
+	gpio-line-names =
+		"VDDPX_BIAS",
+		"WIFI_LED",
+		"NC",
+		"BT_LED",
+		"PM_MPP05",
+		"PM_MPP06",
+		"PM_MPP07",
+		"NC";
+};
+
+&pm8994_spmi_regulators {
+	qcom,saw-reg = <&saw3>;
+	vdd_s11-supply = <&vph_pwr>;
+
+	s9 {
+		qcom,saw-slave;
+	};
+	s10 {
+		qcom,saw-slave;
+	};
+	s11 {
+		qcom,saw-leader;
+		regulator-name = "VDD_APCC";
+		regulator-always-on;
+		regulator-min-microvolt = <980000>;
+		regulator-max-microvolt = <980000>;
+	};
+};
+
+&pmi8994_gpios {
+	gpio-line-names =
+		"NC",
+		"SPKR_AMP_EN1",
+		"SPKR_AMP_EN2",
+		"TP61",
+		"NC",
+		"USB2_VBUS_DET",
+		"NC",
+		"NC",
+		"NC",
+		"NC";
+
+	usb2_vbus_det_gpio: pmi8996-gpio6-state {
+		pinconf {
+			pins = "gpio6";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; /* 1.8V */
+		};
+	};
+};
+
+&pmi8994_lpg {
+	qcom,power-source = <1>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmi8994_mpp2_userled4>;
+
+	qcom,dtest = <0 0>,
+		     <0 0>,
+		     <0 0>,
+		     <4 1>;
+
+	status = "okay";
+
+	led@1 {
+		reg = <1>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_HEARTBEAT;
+		function-enumerator = <1>;
+
+		linux,default-trigger = "heartbeat";
+		default-state = "on";
+	};
+
+	led@2 {
+		reg = <2>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_HEARTBEAT;
+		function-enumerator = <0>;
+	};
+
+	led@3 {
+		reg = <3>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_HEARTBEAT;
+		function-enumerator = <2>;
+	};
+
+	led@4 {
+		reg = <4>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_HEARTBEAT;
+		function-enumerator = <3>;
+	};
+};
+
+&pmi8994_mpps {
+	pmi8994_mpp2_userled4: mpp2-userled4-state {
+		pins = "mpp2";
+		function = "sink";
+
+		output-low;
+		qcom,dtest = <4>;
+	};
+};
+
+&pmi8994_spmi_regulators {
+	vdd_s2-supply = <&vph_pwr>;
+
+	vdd_gfx: s2 {
+		regulator-name = "VDD_GFX";
+		regulator-min-microvolt = <980000>;
+		regulator-max-microvolt = <980000>;
+	};
+};
+
+&rpm_requests {
+	regulators-0 {
+		compatible = "qcom,rpm-pm8994-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_s6-supply = <&vph_pwr>;
+		vdd_s7-supply = <&vph_pwr>;
+		vdd_s8-supply = <&vph_pwr>;
+		vdd_s9-supply = <&vph_pwr>;
+		vdd_s10-supply = <&vph_pwr>;
+		vdd_s11-supply = <&vph_pwr>;
+		vdd_s12-supply = <&vph_pwr>;
+		vdd_l1-supply = <&vreg_s1b_1p025>;
+		vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
+		vdd_l3_l11-supply = <&vreg_s3a_1p3>;
+		vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
+		vdd_l5_l7-supply = <&vreg_s5a_2p15>;
+		vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
+		vdd_l8_l16_l30-supply = <&vph_pwr>;
+		vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
+		vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
+		vdd_l14_l15-supply = <&vreg_s5a_2p15>;
+		vdd_l17_l29-supply = <&vph_pwr_bbyp>;
+		vdd_l20_l21-supply = <&vph_pwr_bbyp>;
+		vdd_l25-supply = <&vreg_s3a_1p3>;
+		vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
+
+		vreg_s3a_1p3: s3 {
+			regulator-name = "vreg_s3a_1p3";
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1300000>;
+		};
+
+		/**
+		 * 1.8v required on LS expansion
+		 * for mezzanine boards
+		 */
+		vreg_s4a_1p8: s4 {
+			regulator-name = "vreg_s4a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+		vreg_s5a_2p15: s5 {
+			regulator-name = "vreg_s5a_2p15";
+			regulator-min-microvolt = <2150000>;
+			regulator-max-microvolt = <2150000>;
+		};
+		vreg_s7a_1p0: s7 {
+			regulator-name = "vreg_s7a_1p0";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+		};
+
+		vreg_l1a_1p0: l1 {
+			regulator-name = "vreg_l1a_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+		vreg_l2a_1p25: l2 {
+			regulator-name = "vreg_l2a_1p25";
+			regulator-min-microvolt = <1250000>;
+			regulator-max-microvolt = <1250000>;
+		};
+		vreg_l3a_0p875: l3 {
+			regulator-name = "vreg_l3a_0p875";
+			regulator-min-microvolt = <850000>;
+			regulator-max-microvolt = <850000>;
+		};
+		vreg_l4a_1p225: l4 {
+			regulator-name = "vreg_l4a_1p225";
+			regulator-min-microvolt = <1225000>;
+			regulator-max-microvolt = <1225000>;
+		};
+		vreg_l6a_1p2: l6 {
+			regulator-name = "vreg_l6a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+		vreg_l8a_1p8: l8 {
+			regulator-name = "vreg_l8a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l9a_1p8: l9 {
+			regulator-name = "vreg_l9a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l10a_1p8: l10 {
+			regulator-name = "vreg_l10a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l11a_1p15: l11 {
+			regulator-name = "vreg_l11a_1p15";
+			regulator-min-microvolt = <1150000>;
+			regulator-max-microvolt = <1150000>;
+		};
+		vreg_l12a_1p8: l12 {
+			regulator-name = "vreg_l12a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l13a_2p95: l13 {
+			regulator-name = "vreg_l13a_2p95";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2950000>;
+		};
+		vreg_l14a_1p8: l14 {
+			regulator-name = "vreg_l14a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l15a_1p8: l15 {
+			regulator-name = "vreg_l15a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l16a_2p7: l16 {
+			regulator-name = "vreg_l16a_2p7";
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2700000>;
+		};
+		vreg_l17a_2p8: l17 {
+			regulator-name = "vreg_l17a_2p8";
+			regulator-min-microvolt = <2500000>;
+			regulator-max-microvolt = <2500000>;
+		};
+		vreg_l18a_2p85: l18 {
+			regulator-name = "vreg_l18a_2p85";
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2900000>;
+		};
+		vreg_l19a_2p8: l19 {
+			regulator-name = "vreg_l19a_2p8";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+		};
+		vreg_l20a_2p95: l20 {
+			regulator-name = "vreg_l20a_2p95";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+		};
+		vreg_l21a_2p95: l21 {
+			regulator-name = "vreg_l21a_2p95";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+			regulator-system-load = <200000>;
+		};
+		vreg_l22a_3p0: l22 {
+			regulator-name = "vreg_l22a_3p0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+		vreg_l23a_2p8: l23 {
+			regulator-name = "vreg_l23a_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+		};
+		vreg_l24a_3p075: l24 {
+			regulator-name = "vreg_l24a_3p075";
+			regulator-min-microvolt = <3075000>;
+			regulator-max-microvolt = <3075000>;
+		};
+		vreg_l25a_1p2: l25 {
+			regulator-name = "vreg_l25a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-allow-set-load;
+		};
+		vreg_l26a_0p8: l27 {
+			regulator-name = "vreg_l26a_0p8";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+		vreg_l28a_0p925: l28 {
+			regulator-name = "vreg_l28a_0p925";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <925000>;
+			regulator-allow-set-load;
+		};
+		vreg_l29a_2p8: l29 {
+			regulator-name = "vreg_l29a_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+		};
+		vreg_l30a_1p8: l30 {
+			regulator-name = "vreg_l30a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+		vreg_l32a_1p8: l32 {
+			regulator-name = "vreg_l32a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vreg_lvs1a_1p8: lvs1 {
+			regulator-name = "vreg_lvs1a_1p8";
+		};
+
+		vreg_lvs2a_1p8: lvs2 {
+			regulator-name = "vreg_lvs2a_1p8";
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,rpm-pmi8994-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_bst_byp-supply = <&vph_pwr>;
+
+		vph_pwr_bbyp: boost-bypass {
+			regulator-name = "vph_pwr_bbyp";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		vreg_s1b_1p025: s1 {
+			regulator-name = "vreg_s1b_1p025";
+			regulator-min-microvolt = <1025000>;
+			regulator-max-microvolt = <1025000>;
+		};
+	};
+};
+
+&sdhc2 {
+	/* External SD card */
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>;
+	cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&vreg_l21a_2p95>;
+	vqmmc-supply = <&vreg_l13a_2p95>;
+	status = "okay";
+};
+
+&q6asmdai {
+	dai@0 {
+		reg = <0>;
+	};
+
+	dai@1 {
+		reg = <1>;
+	};
+
+	dai@2 {
+		reg = <2>;
+	};
+};
+
+&slim_msm {
+	status = "okay";
+
+	slim@1 {
+		reg = <1>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		tasha_ifd: tas-ifd@0,0 {
+			compatible = "slim217,1a0";
+			reg = <0 0>;
+		};
+
+		wcd9335: codec@1,0 {
+			compatible = "slim217,1a0";
+			reg = <1 0>;
+
+			clock-names = "mclk", "slimbus";
+			clocks = <&div1_mclk>,
+				 <&rpmcc RPM_SMD_BB_CLK1>;
+			interrupt-parent = <&tlmm>;
+			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
+				     <53 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr1", "intr2";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
+			pinctrl-names = "default";
+
+			reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+			slim-ifc-dev = <&tasha_ifd>;
+
+			#sound-dai-cells = <1>;
+
+			vdd-buck-supply = <&vreg_s4a_1p8>;
+			vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+			vdd-tx-supply = <&vreg_s4a_1p8>;
+			vdd-rx-supply = <&vreg_s4a_1p8>;
+			vdd-io-supply = <&vreg_s4a_1p8>;
+		};
+	};
+};
+
+&sound {
+	compatible = "qcom,apq8096-sndcard";
+	model = "DB820c";
+	audio-routing = "RX_BIAS", "MCLK",
+		"MM_DL1",  "MultiMedia1 Playback",
+		"MM_DL2",  "MultiMedia2 Playback",
+		"MultiMedia3 Capture", "MM_UL3";
+
+	mm1-dai-link {
+		link-name = "MultiMedia1";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
+		};
+	};
+
+	mm2-dai-link {
+		link-name = "MultiMedia2";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
+		};
+	};
+
+	mm3-dai-link {
+		link-name = "MultiMedia3";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
+		};
+	};
+
+	hdmi-dai-link {
+		link-name = "HDMI";
+		cpu {
+			sound-dai = <&q6afedai HDMI_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&mdss_hdmi 0>;
+		};
+	};
+
+	slim-dai-link {
+		link-name = "SLIM Playback";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_6_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&wcd9335 AIF4_PB>;
+		};
+	};
+
+	slimcap-dai-link {
+		link-name = "SLIM Capture";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_0_TX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&wcd9335 AIF1_CAP>;
+		};
+	};
+};
+
+&ufsphy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l28a_0p925>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+};
+
+&ufshc {
+	status = "okay";
+
+	vcc-supply = <&vreg_l20a_2p95>;
+	vccq-supply = <&vreg_l25a_1p2>;
+	vccq2-supply = <&vreg_s4a_1p8>;
+	vdd-hba-supply = <&vreg_l25a_1p2>;
+
+	vcc-max-microamp = <600000>;
+	vccq-max-microamp = <450000>;
+	vccq2-max-microamp = <450000>;
+};
+
+&usb2 {
+	status = "okay";
+	extcon = <&usb2_id>;
+};
+
+&usb2_dwc3 {
+	extcon = <&usb2_id>;
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
+
+&usb3 {
+	status = "okay";
+	extcon = <&usb3_id>;
+};
+
+&usb3_dwc3 {
+	extcon = <&usb3_id>;
+	dr_mode = "otg";
+};
+
+&usb3phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l28a_0p925>;
+	vdda-pll-supply = <&vreg_l12a_1p8>;
+};
+
+&venus {
+	status = "okay";
+};
diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
deleted file mode 100644
index d93c7c1fbdee..000000000000
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot addition to handle Dragonboard 820c pins
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-
-/ {
-	smem {
-		bootph-all;
-	};
-
-	soc {
-		bootph-all;
-
-		pinctrl@1010000 {
-			bootph-all;
-
-			uart {
-				bootph-all;
-			};
-		};
-
-		clock-controller@300000 {
-			bootph-all;
-		};
-
-		serial@75b0000 {
-			bootph-all;
-		};
-	};
-};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
deleted file mode 100644
index 282c37e28f42..000000000000
--- a/arch/arm/dts/dragonboard820c.dts
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8096 based Dragonboard 820C board device tree source
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-
-/dts-v1/;
-
-#include "skeleton64.dtsi"
-#include <dt-bindings/clock/qcom,gcc-msm8996.h>
-
-/ {
-	model = "Qualcomm Technologies, Inc. DB820c";
-	compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &blsp2_uart2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0xc0000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		smem_mem: smem_region@86300000 {
-			reg = <0x0 0x86300000 0x0 0x200000>;
-			no-map;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	smem {
-		compatible = "qcom,smem";
-		memory-region = <&smem_mem>;
-	};
-
-	soc: soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0 0xffffffff>;
-		compatible = "simple-bus";
-
-		gcc: clock-controller@300000 {
-			compatible = "qcom,gcc-msm8996";
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#power-domain-cells = <1>;
-			reg = <0x300000 0x90000>;
-		};
-
-		pinctrl: pinctrl@1010000 {
-			compatible = "qcom,msm8996-pinctrl";
-			reg = <0x1010000 0x400000>;
-
-			blsp8_uart: uart {
-				function = "blsp_uart8";
-				pins = "GPIO_4", "GPIO_5";
-				drive-strength = <8>;
-				bias-disable;
-			};
-		};
-
-		blsp2_uart2: serial@75b0000 {
-			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-			reg = <0x75b0000 0x1000>;
-			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
-			clock-names = "core";
-			pinctrl-names = "uart";
-			pinctrl-0 = <&blsp8_uart>;
-		};
-
-		sdhc2: sdhci@74a4900 {
-			compatible = "qcom,sdhci-msm-v4";
-			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
-			index = <0x0>;
-			bus-width = <4>;
-			clock = <&gcc GCC_SDCC1_APPS_CLK>;
-			clock-frequency = <200000000>;
-		 };
-
-		spmi_bus: spmi@400f000 {
-			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x0400f000 0x1000>,
-			      <0x04400000 0x800000>,
-			      <0x04c00000 0x800000>,
-			      <0x05800000 0x200000>,
-			      <0x0400a000 0x002100>;
-			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-
-			pmic0: pm8994@0 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x0 0x1>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
-
-				pm8994_pon: pon@800 {
-					compatible = "qcom,pm8916-pon";
-					reg = <0x800 0x100>;
-					mode-bootloader = <0x2>;
-					mode-recovery = <0x1>;
-
-					pwrkey {
-						compatible = "qcom,pm8941-pwrkey";
-						debounce = <15625>;
-						bias-pull-up;
-					};
-
-					pm8994_resin: resin {
-						compatible = "qcom,pm8941-resin";
-						debounce = <15625>;
-						bias-pull-up;
-					};
-				};
-
-				pm8994_gpios: pm8994_gpios@c000 {
-					compatible = "qcom,pm8994-gpio";
-					reg = <0xc000 0x400>;
-					gpio-controller;
-					gpio-ranges = <&pm8994_gpios 0 0 22>;
-					#gpio-cells = <2>;
-				};
-			};
-
-			pmic1: pm8994@1 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x1 0x1>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
-			};
-		};
-	};
-
-};
-
-#include "dragonboard820c-uboot.dtsi"
diff --git a/arch/arm/dts/msm8996.dtsi b/arch/arm/dts/msm8996.dtsi
new file mode 100644
index 000000000000..6ba9da9e6a8b
--- /dev/null
+++ b/arch/arm/dts/msm8996.dtsi
@@ -0,0 +1,3884 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8996.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interconnect/qcom,msm8996.h>
+#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			clocks = <&kryocc 0>;
+			interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
+			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			clocks = <&kryocc 0>;
+			interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
+			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			clocks = <&kryocc 1>;
+			interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
+			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		CPU3: cpu@101 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			clocks = <&kryocc 1>;
+			interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
+			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
+			next-level-cache = <&L2_1>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+
+				core1 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <130>;
+				exit-latency-us = <80>;
+				min-residency-us = <300>;
+			};
+		};
+	};
+
+	cluster0_opp: opp-table-cluster0 {
+		compatible = "operating-points-v2-kryo-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+		opp-shared;
+
+		/* Nominal fmax for now */
+		opp-307200000 {
+			opp-hz = /bits/ 64 <307200000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-422400000 {
+			opp-hz = /bits/ 64 <422400000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-556800000 {
+			opp-hz = /bits/ 64 <556800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-652800000 {
+			opp-hz = /bits/ 64 <652800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <384000>;
+		};
+		opp-729600000 {
+			opp-hz = /bits/ 64 <729600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <460800>;
+		};
+		opp-844800000 {
+			opp-hz = /bits/ 64 <844800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <537600>;
+		};
+		opp-960000000 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <672000>;
+		};
+		opp-1036800000 {
+			opp-hz = /bits/ 64 <1036800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <672000>;
+		};
+		opp-1113600000 {
+			opp-hz = /bits/ 64 <1113600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <825600>;
+		};
+		opp-1190400000 {
+			opp-hz = /bits/ 64 <1190400000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <825600>;
+		};
+		opp-1228800000 {
+			opp-hz = /bits/ 64 <1228800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <902400>;
+		};
+		opp-1324800000 {
+			opp-hz = /bits/ 64 <1324800000>;
+			opp-supported-hw = <0xd>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1056000>;
+		};
+		opp-1363200000 {
+			opp-hz = /bits/ 64 <1363200000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1132800>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			opp-supported-hw = <0xd>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1132800>;
+		};
+		opp-1478400000 {
+			opp-hz = /bits/ 64 <1478400000>;
+			opp-supported-hw = <0x9>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1190400>;
+		};
+		opp-1497600000 {
+			opp-hz = /bits/ 64 <1497600000>;
+			opp-supported-hw = <0x04>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1305600>;
+		};
+		opp-1593600000 {
+			opp-hz = /bits/ 64 <1593600000>;
+			opp-supported-hw = <0x9>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1382400>;
+		};
+	};
+
+	cluster1_opp: opp-table-cluster1 {
+		compatible = "operating-points-v2-kryo-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+		opp-shared;
+
+		/* Nominal fmax for now */
+		opp-307200000 {
+			opp-hz = /bits/ 64 <307200000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-403200000 {
+			opp-hz = /bits/ 64 <403200000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-556800000 {
+			opp-hz = /bits/ 64 <556800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-652800000 {
+			opp-hz = /bits/ 64 <652800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-729600000 {
+			opp-hz = /bits/ 64 <729600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <307200>;
+		};
+		opp-806400000 {
+			opp-hz = /bits/ 64 <806400000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <384000>;
+		};
+		opp-883200000 {
+			opp-hz = /bits/ 64 <883200000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <460800>;
+		};
+		opp-940800000 {
+			opp-hz = /bits/ 64 <940800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <537600>;
+		};
+		opp-1036800000 {
+			opp-hz = /bits/ 64 <1036800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <595200>;
+		};
+		opp-1113600000 {
+			opp-hz = /bits/ 64 <1113600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <672000>;
+		};
+		opp-1190400000 {
+			opp-hz = /bits/ 64 <1190400000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <672000>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <748800>;
+		};
+		opp-1324800000 {
+			opp-hz = /bits/ 64 <1324800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <825600>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <902400>;
+		};
+		opp-1478400000 {
+			opp-hz = /bits/ 64 <1478400000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <979200>;
+		};
+		opp-1555200000 {
+			opp-hz = /bits/ 64 <1555200000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1056000>;
+		};
+		opp-1632000000 {
+			opp-hz = /bits/ 64 <1632000000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1190400>;
+		};
+		opp-1708800000 {
+			opp-hz = /bits/ 64 <1708800000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1228800>;
+		};
+		opp-1785600000 {
+			opp-hz = /bits/ 64 <1785600000>;
+			opp-supported-hw = <0xf>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1305600>;
+		};
+		opp-1804800000 {
+			opp-hz = /bits/ 64 <1804800000>;
+			opp-supported-hw = <0xe>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1305600>;
+		};
+		opp-1824000000 {
+			opp-hz = /bits/ 64 <1824000000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1382400>;
+		};
+		opp-1900800000 {
+			opp-hz = /bits/ 64 <1900800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1305600>;
+		};
+		opp-1920000000 {
+			opp-hz = /bits/ 64 <1920000000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1459200>;
+		};
+		opp-1996800000 {
+			opp-hz = /bits/ 64 <1996800000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1593600>;
+		};
+		opp-2073600000 {
+			opp-hz = /bits/ 64 <2073600000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1593600>;
+		};
+		opp-2150400000 {
+			opp-hz = /bits/ 64 <2150400000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <200000>;
+			opp-peak-kBps = <1593600>;
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-msm8996", "qcom,scm";
+			qcom,dload-mode = <&tcsr_2 0x13000>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	rpm: remoteproc {
+		compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
+
+		glink-edge {
+			compatible = "qcom,glink-rpm";
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+			mboxes = <&apcs_glb 0>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-msm8996";
+				qcom,glink-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
+					#clock-cells = <1>;
+					clocks = <&xo_board>;
+					clock-names = "xo";
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,msm8996-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp1: opp1 {
+							opp-level = <1>;
+						};
+
+						rpmpd_opp2: opp2 {
+							opp-level = <2>;
+						};
+
+						rpmpd_opp3: opp3 {
+							opp-level = <3>;
+						};
+
+						rpmpd_opp4: opp4 {
+							opp-level = <4>;
+						};
+
+						rpmpd_opp5: opp5 {
+							opp-level = <5>;
+						};
+
+						rpmpd_opp6: opp6 {
+							opp-level = <6>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: memory@85800000 {
+			reg = <0x0 0x85800000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_mem: memory@85e00000 {
+			reg = <0x0 0x85e00000 0x0 0x200000>;
+			no-map;
+		};
+
+		smem_mem: smem-mem@86000000 {
+			reg = <0x0 0x86000000 0x0 0x200000>;
+			no-map;
+		};
+
+		tz_mem: memory@86200000 {
+			reg = <0x0 0x86200000 0x0 0x2600000>;
+			no-map;
+		};
+
+		rmtfs_mem: rmtfs {
+			compatible = "qcom,rmtfs-mem";
+
+			size = <0x0 0x200000>;
+			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+			no-map;
+
+			qcom,client-id = <1>;
+			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+		};
+
+		mpss_mem: mpss@88800000 {
+			reg = <0x0 0x88800000 0x0 0x6200000>;
+			no-map;
+		};
+
+		adsp_mem: adsp@8ea00000 {
+			reg = <0x0 0x8ea00000 0x0 0x1b00000>;
+			no-map;
+		};
+
+		slpi_mem: slpi@90500000 {
+			reg = <0x0 0x90500000 0x0 0xa00000>;
+			no-map;
+		};
+
+		gpu_mem: gpu@90f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x90f00000 0x0 0x100000>;
+			no-map;
+		};
+
+		venus_mem: venus@91000000 {
+			reg = <0x0 0x91000000 0x0 0x500000>;
+			no-map;
+		};
+
+		mba_mem: mba@91500000 {
+			reg = <0x0 0x91500000 0x0 0x200000>;
+			no-map;
+		};
+
+		mdata_mem: mpss-metadata {
+			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
+			size = <0x0 0x4000>;
+			no-map;
+		};
+	};
+
+	smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs_glb 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-mpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs_glb 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		mpss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		mpss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-slpi {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+
+		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs_glb 26>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		slpi_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		slpi_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		pcie_phy: phy-wrapper@34000 {
+			compatible = "qcom,msm8996-qmp-pcie-phy";
+			reg = <0x00034000 0x488>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00034000 0x4000>;
+
+			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+				<&gcc GCC_PCIE_CLKREF_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_PCIE_PHY_BCR>,
+				<&gcc GCC_PCIE_PHY_COM_BCR>,
+				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+			reset-names = "phy", "common", "cfg";
+
+			status = "disabled";
+
+			pciephy_0: phy@1000 {
+				reg = <0x1000 0x130>,
+				      <0x1200 0x200>,
+				      <0x1400 0x1dc>;
+
+				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+				clock-names = "pipe0";
+				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+				reset-names = "lane0";
+
+				#clock-cells = <0>;
+				clock-output-names = "pcie_0_pipe_clk_src";
+
+				#phy-cells = <0>;
+			};
+
+			pciephy_1: phy@2000 {
+				reg = <0x2000 0x130>,
+				      <0x2200 0x200>,
+				      <0x2400 0x1dc>;
+
+				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+				clock-names = "pipe1";
+				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+				reset-names = "lane1";
+
+				#clock-cells = <0>;
+				clock-output-names = "pcie_1_pipe_clk_src";
+
+				#phy-cells = <0>;
+			};
+
+			pciephy_2: phy@3000 {
+				reg = <0x3000 0x130>,
+				      <0x3200 0x200>,
+				      <0x3400 0x1dc>;
+
+				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+				clock-names = "pipe2";
+				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+				reset-names = "lane2";
+
+				#clock-cells = <0>;
+				clock-output-names = "pcie_2_pipe_clk_src";
+
+				#phy-cells = <0>;
+			};
+		};
+
+		rpm_msg_ram: sram@68000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00068000 0x6000>;
+		};
+
+		qfprom@74000 {
+			compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
+			reg = <0x00074000 0x8ff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qusb2p_hstx_trim: hstx_trim@24e {
+				reg = <0x24e 0x2>;
+				bits = <5 4>;
+			};
+
+			qusb2s_hstx_trim: hstx_trim@24f {
+				reg = <0x24f 0x1>;
+				bits = <1 4>;
+			};
+
+			speedbin_efuse: speedbin@133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
+		};
+
+		rng: rng@83000 {
+			compatible = "qcom,prng-ee";
+			reg = <0x00083000 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		gcc: clock-controller@300000 {
+			compatible = "qcom,gcc-msm8996";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x00300000 0x90000>;
+
+			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+				 <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&sleep_clk>,
+				 <&pciephy_0>,
+				 <&pciephy_1>,
+				 <&pciephy_2>,
+				 <&ssusb_phy_0>,
+				 <&ufsphy_lane 0>,
+				 <&ufsphy_lane 1>,
+				 <&ufsphy_lane 2>;
+			clock-names = "cxo",
+				      "cxo2",
+				      "sleep_clk",
+				      "pcie_0_pipe_clk_src",
+				      "pcie_1_pipe_clk_src",
+				      "pcie_2_pipe_clk_src",
+				      "usb3_phy_pipe_clk_src",
+				      "ufs_rx_symbol_0_clk_src",
+				      "ufs_rx_symbol_1_clk_src",
+				      "ufs_tx_symbol_0_clk_src";
+		};
+
+		bimc: interconnect@408000 {
+			compatible = "qcom,msm8996-bimc";
+			reg = <0x00408000 0x5a000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
+		};
+
+		tsens0: thermal-sensor@4a9000 {
+			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
+			reg = <0x004a9000 0x1000>, /* TM */
+			      <0x004a8000 0x1000>; /* SROT */
+			#qcom,sensors = <13>;
+			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens1: thermal-sensor@4ad000 {
+			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
+			reg = <0x004ad000 0x1000>, /* TM */
+			      <0x004ac000 0x1000>; /* SROT */
+			#qcom,sensors = <8>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		cryptobam: dma-controller@644000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x00644000 0x24000>;
+			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_CE1_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+		};
+
+		crypto: crypto@67a000 {
+			compatible = "qcom,crypto-v5.4";
+			reg = <0x0067a000 0x6000>;
+			clocks = <&gcc GCC_CE1_AHB_CLK>,
+				 <&gcc GCC_CE1_AXI_CLK>,
+				 <&gcc GCC_CE1_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 6>, <&cryptobam 7>;
+			dma-names = "rx", "tx";
+		};
+
+		cnoc: interconnect@500000 {
+			compatible = "qcom,msm8996-cnoc";
+			reg = <0x00500000 0x1000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+				 <&rpmcc RPM_SMD_CNOC_A_CLK>;
+		};
+
+		snoc: interconnect@524000 {
+			compatible = "qcom,msm8996-snoc";
+			reg = <0x00524000 0x1c000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
+		};
+
+		a0noc: interconnect@543000 {
+			compatible = "qcom,msm8996-a0noc";
+			reg = <0x00543000 0x6000>;
+			#interconnect-cells = <1>;
+			clock-names = "aggre0_snoc_axi",
+				      "aggre0_cnoc_ahb",
+				      "aggre0_noc_mpu_cfg";
+			clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
+				 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
+				 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
+			power-domains = <&gcc AGGRE0_NOC_GDSC>;
+		};
+
+		a1noc: interconnect@562000 {
+			compatible = "qcom,msm8996-a1noc";
+			reg = <0x00562000 0x5000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
+				 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
+		};
+
+		a2noc: interconnect@583000 {
+			compatible = "qcom,msm8996-a2noc";
+			reg = <0x00583000 0x7000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
+			clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
+				 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
+				 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+				 <&gcc GCC_UFS_AXI_CLK>;
+		};
+
+		mnoc: interconnect@5a4000 {
+			compatible = "qcom,msm8996-mnoc";
+			reg = <0x005a4000 0x1c000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a", "iface";
+			clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
+				 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
+				 <&mmcc AHB_CLK_SRC>;
+		};
+
+		pnoc: interconnect@5c0000 {
+			compatible = "qcom,msm8996-pnoc";
+			reg = <0x005c0000 0x3000>;
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
+				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
+		};
+
+		tcsr_mutex: hwlock@740000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x00740000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr_1: syscon@760000 {
+			compatible = "qcom,tcsr-msm8996", "syscon";
+			reg = <0x00760000 0x20000>;
+		};
+
+		tcsr_2: syscon@7a0000 {
+			compatible = "qcom,tcsr-msm8996", "syscon";
+			reg = <0x007a0000 0x18000>;
+		};
+
+		mmcc: clock-controller@8c0000 {
+			compatible = "qcom,mmcc-msm8996";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x008c0000 0x40000>;
+			clocks = <&xo_board>,
+				 <&gcc GPLL0>,
+				 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi0_phy 0>,
+				 <&mdss_dsi1_phy 1>,
+				 <&mdss_dsi1_phy 0>,
+				 <&mdss_hdmi_phy>;
+			clock-names = "xo",
+				      "gpll0",
+				      "gcc_mmss_noc_cfg_ahb_clk",
+				      "dsi0pll",
+				      "dsi0pllbyte",
+				      "dsi1pll",
+				      "dsi1pllbyte",
+				      "hdmipll";
+			assigned-clocks = <&mmcc MMPLL9_PLL>,
+					  <&mmcc MMPLL1_PLL>,
+					  <&mmcc MMPLL3_PLL>,
+					  <&mmcc MMPLL4_PLL>,
+					  <&mmcc MMPLL5_PLL>;
+			assigned-clock-rates = <624000000>,
+					       <810000000>,
+					       <980000000>,
+					       <960000000>,
+					       <825000000>;
+		};
+
+		mdss: display-subsystem@900000 {
+			compatible = "qcom,mdss";
+
+			reg = <0x00900000 0x1000>,
+			      <0x009b0000 0x1040>,
+			      <0x009b8000 0x1040>;
+			reg-names = "mdss_phys",
+				    "vbif_phys",
+				    "vbif_nrt_phys";
+
+			power-domains = <&mmcc MDSS_GDSC>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			clocks = <&mmcc MDSS_AHB_CLK>,
+				 <&mmcc MDSS_MDP_CLK>;
+			clock-names = "iface", "core";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			status = "disabled";
+
+			mdp: display-controller@901000 {
+				compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
+				reg = <0x00901000 0x90000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc SMMU_MDP_AXI_CLK>,
+					 <&mmcc MDSS_VSYNC_CLK>;
+				clock-names = "iface",
+					      "bus",
+					      "core",
+					      "iommu",
+					      "vsync";
+
+				iommus = <&mdp_smmu 0>;
+
+				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <300000000>,
+					 <19200000>;
+
+				interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
+						<&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
+						<&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
+				interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdp5_intf3_out: endpoint {
+							remote-endpoint = <&mdss_hdmi_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdp5_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+						mdp5_intf2_out: endpoint {
+							remote-endpoint = <&mdss_dsi1_in>;
+						};
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@994000 {
+				compatible = "qcom,msm8996-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0x00994000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_BYTE0_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MMSS_MISC_AHB_CLK>,
+					 <&mmcc MDSS_PCLK0_CLK>,
+					 <&mmcc MDSS_ESC0_CLK>;
+				clock-names = "mdp_core",
+					      "byte",
+					      "iface",
+					      "bus",
+					      "core_mmss",
+					      "pixel",
+					      "core";
+				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+				phys = <&mdss_dsi0_phy>;
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&mdp5_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@994400 {
+				compatible = "qcom,dsi-phy-14nm";
+				reg = <0x00994400 0x100>,
+				      <0x00994500 0x300>,
+				      <0x00994800 0x188>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+				clock-names = "iface", "ref";
+				status = "disabled";
+			};
+
+			mdss_dsi1: dsi@996000 {
+				compatible = "qcom,msm8996-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0x00996000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_BYTE1_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MMSS_MISC_AHB_CLK>,
+					 <&mmcc MDSS_PCLK1_CLK>,
+					 <&mmcc MDSS_ESC1_CLK>;
+				clock-names = "mdp_core",
+					      "byte",
+					      "iface",
+					      "bus",
+					      "core_mmss",
+					      "pixel",
+					      "core";
+				assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
+				phys = <&mdss_dsi1_phy>;
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi1_in: endpoint {
+							remote-endpoint = <&mdp5_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi1_phy: phy@996400 {
+				compatible = "qcom,dsi-phy-14nm";
+				reg = <0x00996400 0x100>,
+				      <0x00996500 0x300>,
+				      <0x00996800 0x188>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+				clock-names = "iface", "ref";
+				status = "disabled";
+			};
+
+			mdss_hdmi: hdmi-tx@9a0000 {
+				compatible = "qcom,hdmi-tx-8996";
+				reg = <0x009a0000 0x50c>,
+				      <0x00070000 0x6158>,
+				      <0x009e0000 0xfff>;
+				reg-names = "core_physical",
+					    "qfprom_physical",
+					    "hdcp_physical";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <8>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_HDMI_CLK>,
+					 <&mmcc MDSS_HDMI_AHB_CLK>,
+					 <&mmcc MDSS_EXTPCLK_CLK>;
+				clock-names =
+					"mdp_core",
+					"iface",
+					"core",
+					"alt_iface",
+					"extp";
+
+				phys = <&mdss_hdmi_phy>;
+				#sound-dai-cells = <1>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_hdmi_in: endpoint {
+							remote-endpoint = <&mdp5_intf3_out>;
+						};
+					};
+				};
+			};
+
+			mdss_hdmi_phy: phy@9a0600 {
+				#phy-cells = <0>;
+				compatible = "qcom,hdmi-phy-8996";
+				reg = <0x009a0600 0x1c4>,
+				      <0x009a0a00 0x124>,
+				      <0x009a0c00 0x124>,
+				      <0x009a0e00 0x124>,
+				      <0x009a1000 0x124>,
+				      <0x009a1200 0x0c8>;
+				reg-names = "hdmi_pll",
+					    "hdmi_tx_l0",
+					    "hdmi_tx_l1",
+					    "hdmi_tx_l2",
+					    "hdmi_tx_l3",
+					    "hdmi_phy";
+
+				clocks = <&mmcc MDSS_AHB_CLK>,
+					 <&gcc GCC_HDMI_CLKREF_CLK>,
+					 <&xo_board>;
+				clock-names = "iface",
+					      "ref",
+					      "xo";
+
+				#clock-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpu: gpu@b00000 {
+			compatible = "qcom,adreno-530.2", "qcom,adreno";
+
+			reg = <0x00b00000 0x3f000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&mmcc GPU_GX_RBBMTIMER_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+			clock-names = "core",
+				"iface",
+				"rbbmtimer",
+				"mem",
+				"mem_iface";
+
+			interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
+			interconnect-names = "gfx-mem";
+
+			power-domains = <&mmcc GPU_GX_GDSC>;
+			iommus = <&adreno_smmu 0>;
+
+			nvmem-cells = <&speedbin_efuse>;
+			nvmem-cell-names = "speed_bin";
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			status = "disabled";
+
+			#cooling-cells = <2>;
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/*
+				 * 624Mhz is only available on speed bins 0 and 3.
+				 * 560Mhz is only available on speed bins 0, 2 and 3.
+				 * All the rest are available on all bins of the hardware.
+				 */
+				opp-624000000 {
+					opp-hz = /bits/ 64 <624000000>;
+					opp-supported-hw = <0x09>;
+				};
+				opp-560000000 {
+					opp-hz = /bits/ 64 <560000000>;
+					opp-supported-hw = <0x0d>;
+				};
+				opp-510000000 {
+					opp-hz = /bits/ 64 <510000000>;
+					opp-supported-hw = <0xff>;
+				};
+				opp-401800000 {
+					opp-hz = /bits/ 64 <401800000>;
+					opp-supported-hw = <0xff>;
+				};
+				opp-315000000 {
+					opp-hz = /bits/ 64 <315000000>;
+					opp-supported-hw = <0xff>;
+				};
+				opp-214000000 {
+					opp-hz = /bits/ 64 <214000000>;
+					opp-supported-hw = <0xff>;
+				};
+				opp-133000000 {
+					opp-hz = /bits/ 64 <133000000>;
+					opp-supported-hw = <0xff>;
+				};
+			};
+
+			zap-shader {
+				memory-region = <&gpu_mem>;
+			};
+		};
+
+		tlmm: pinctrl@1010000 {
+			compatible = "qcom,msm8996-pinctrl";
+			reg = <0x01010000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 150>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp1_spi1_default: blsp1-spi1-default-state {
+				spi-pins {
+					pins = "gpio0", "gpio1", "gpio3";
+					function = "blsp_spi1";
+					drive-strength = <12>;
+					bias-disable;
+				};
+
+				cs-pins {
+					pins = "gpio2";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp1_spi1_sleep: blsp1-spi1-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
+				pins = "gpio4", "gpio5";
+				function = "blsp_uart8";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c2_default: blsp2-i2c2-state {
+				pins = "gpio6", "gpio7";
+				function = "blsp_i2c8";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c6_default: blsp1-i2c6-state {
+				pins = "gpio27", "gpio28";
+				function = "blsp_i2c6";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
+				pins = "gpio27", "gpio28";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			cci0_default: cci0-default-state {
+				pins = "gpio17", "gpio18";
+				function = "cci_i2c";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			camera0_state_on:
+			camera_rear_default: camera-rear-default-state {
+				camera0_mclk: mclk0-pins {
+					pins = "gpio13";
+					function = "cam_mclk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				camera0_rst: rst-pins {
+					pins = "gpio25";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				camera0_pwdn: pwdn-pins {
+					pins = "gpio26";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			cci1_default: cci1-default-state {
+				pins = "gpio19", "gpio20";
+				function = "cci_i2c";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			camera1_state_on:
+			camera_board_default: camera-board-default-state {
+				mclk1-pins {
+					pins = "gpio14";
+					function = "cam_mclk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				pwdn-pins {
+					pins = "gpio98";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				rst-pins {
+					pins = "gpio104";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			camera2_state_on:
+			camera_front_default: camera-front-default-state {
+				camera2_mclk: mclk2-pins {
+					pins = "gpio15";
+					function = "cam_mclk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				camera2_rst: rst-pins {
+					pins = "gpio23";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				pwdn-pins {
+					pins = "gpio133";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			pcie0_state_on: pcie0-state-on-state {
+				perst-pins {
+					pins = "gpio35";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio36";
+					function = "pci_e0";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio37";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			pcie0_state_off: pcie0-state-off-state {
+				perst-pins {
+					pins = "gpio35";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio36";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				wake-pins {
+					pins = "gpio37";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp1_uart2_default: blsp1-uart2-default-state {
+				pins = "gpio41", "gpio42", "gpio43", "gpio44";
+				function = "blsp_uart2";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp1_uart2_sleep: blsp1-uart2-sleep-state {
+				pins = "gpio41", "gpio42", "gpio43", "gpio44";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_default: blsp1-i2c3-default-state {
+				pins = "gpio47", "gpio48";
+				function = "blsp_i2c3";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
+				pins = "gpio47", "gpio48";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
+				pins = "gpio49", "gpio50", "gpio51", "gpio52";
+				function = "blsp_uart9";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
+				pins = "gpio49", "gpio50", "gpio51", "gpio52";
+				function = "blsp_uart9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c3_default: blsp2-i2c3-state-state {
+				pins = "gpio51", "gpio52";
+				function = "blsp_i2c9";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
+				pins = "gpio51", "gpio52";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			wcd_intr_default: wcd-intr-default-state {
+				pins = "gpio54";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp2_i2c1_default: blsp2-i2c1-state {
+				pins = "gpio55", "gpio56";
+				function = "blsp_i2c7";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
+				pins = "gpio55", "gpio56";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c5_default: blsp2-i2c5-state {
+				pins = "gpio60", "gpio61";
+				function = "blsp_i2c11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			/* Sleep state for BLSP2_I2C5 is missing.. */
+
+			cdc_reset_active: cdc-reset-active-state {
+				pins = "gpio64";
+				function = "gpio";
+				drive-strength = <16>;
+				bias-pull-down;
+				output-high;
+			};
+
+			cdc_reset_sleep: cdc-reset-sleep-state {
+				pins = "gpio64";
+				function = "gpio";
+				drive-strength = <16>;
+				bias-disable;
+				output-low;
+			};
+
+			blsp2_spi6_default: blsp2-spi6-default-state {
+				spi-pins {
+					pins = "gpio85", "gpio86", "gpio88";
+					function = "blsp_spi12";
+					drive-strength = <12>;
+					bias-disable;
+				};
+
+				cs-pins {
+					pins = "gpio87";
+					function = "gpio";
+					drive-strength = <16>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			blsp2_spi6_sleep: blsp2-spi6-sleep-state {
+				pins = "gpio85", "gpio86", "gpio87", "gpio88";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			blsp2_i2c6_default: blsp2-i2c6-state {
+				pins = "gpio87", "gpio88";
+				function = "blsp_i2c12";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
+				pins = "gpio87", "gpio88";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			pcie1_state_on: pcie1-on-state {
+				perst-pins {
+					pins = "gpio130";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio131";
+					function = "pci_e1";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio132";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			pcie1_state_off: pcie1-off-state {
+				/* Perst is missing? */
+				clkreq-pins {
+					pins = "gpio131";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				wake-pins {
+					pins = "gpio132";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			pcie2_state_on: pcie2-on-state {
+				perst-pins {
+					pins = "gpio114";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio115";
+					function = "pci_e2";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio116";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			pcie2_state_off: pcie2-off-state {
+				/* Perst is missing? */
+				clkreq-pins {
+					pins = "gpio115";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				wake-pins {
+					pins = "gpio116";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			sdc1_state_on: sdc1-on-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_state_off: sdc1-off-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc2_state_on: sdc2-on-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_state_off: sdc2-off-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+		};
+
+		sram@290000 {
+			compatible = "qcom,rpm-stats";
+			reg = <0x00290000 0x10000>;
+		};
+
+		spmi_bus: spmi@400f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0400f000 0x1000>,
+			      <0x04400000 0x800000>,
+			      <0x04c00000 0x800000>,
+			      <0x05800000 0x200000>,
+			      <0x0400a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		bus@0 {
+			power-domains = <&gcc AGGRE0_NOC_GDSC>;
+			compatible = "simple-pm-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0xffffffff>;
+
+			pcie0: pcie@600000 {
+				compatible = "qcom,pcie-msm8996";
+				status = "disabled";
+				power-domains = <&gcc PCIE0_GDSC>;
+				bus-range = <0x00 0xff>;
+				num-lanes = <1>;
+
+				reg = <0x00600000 0x2000>,
+				      <0x0c000000 0xf1d>,
+				      <0x0c000f20 0xa8>,
+				      <0x0c100000 0x100000>;
+				reg-names = "parf", "dbi", "elbi","config";
+
+				phys = <&pciephy_0>;
+				phy-names = "pciephy";
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
+					 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+
+				device_type = "pci";
+
+				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "msi";
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0x7>;
+				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+				pinctrl-names = "default", "sleep";
+				pinctrl-0 = <&pcie0_state_on>;
+				pinctrl-1 = <&pcie0_state_off>;
+
+				linux,pci-domain = <0>;
+
+				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+					<&gcc GCC_PCIE_0_AUX_CLK>,
+					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+
+				clock-names = "pipe",
+						"aux",
+						"cfg",
+						"bus_master",
+						"bus_slave";
+			};
+
+			pcie1: pcie@608000 {
+				compatible = "qcom,pcie-msm8996";
+				power-domains = <&gcc PCIE1_GDSC>;
+				bus-range = <0x00 0xff>;
+				num-lanes = <1>;
+
+				status = "disabled";
+
+				reg = <0x00608000 0x2000>,
+				      <0x0d000000 0xf1d>,
+				      <0x0d000f20 0xa8>,
+				      <0x0d100000 0x100000>;
+
+				reg-names = "parf", "dbi", "elbi","config";
+
+				phys = <&pciephy_1>;
+				phy-names = "pciephy";
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
+					 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
+
+				device_type = "pci";
+
+				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "msi";
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0x7>;
+				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+				pinctrl-names = "default", "sleep";
+				pinctrl-0 = <&pcie1_state_on>;
+				pinctrl-1 = <&pcie1_state_off>;
+
+				linux,pci-domain = <1>;
+
+				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+					<&gcc GCC_PCIE_1_AUX_CLK>,
+					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
+
+				clock-names = "pipe",
+						"aux",
+						"cfg",
+						"bus_master",
+						"bus_slave";
+			};
+
+			pcie2: pcie@610000 {
+				compatible = "qcom,pcie-msm8996";
+				power-domains = <&gcc PCIE2_GDSC>;
+				bus-range = <0x00 0xff>;
+				num-lanes = <1>;
+				status = "disabled";
+				reg = <0x00610000 0x2000>,
+				      <0x0e000000 0xf1d>,
+				      <0x0e000f20 0xa8>,
+				      <0x0e100000 0x100000>;
+
+				reg-names = "parf", "dbi", "elbi","config";
+
+				phys = <&pciephy_2>;
+				phy-names = "pciephy";
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
+					 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+
+				device_type = "pci";
+
+				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "msi";
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0x7>;
+				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+				pinctrl-names = "default", "sleep";
+				pinctrl-0 = <&pcie2_state_on>;
+				pinctrl-1 = <&pcie2_state_off>;
+
+				linux,pci-domain = <2>;
+				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+					<&gcc GCC_PCIE_2_AUX_CLK>,
+					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
+
+				clock-names = "pipe",
+						"aux",
+						"cfg",
+						"bus_master",
+						"bus_slave";
+			};
+		};
+
+		ufshc: ufshc@624000 {
+			compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0x00624000 0x2500>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+			phys = <&ufsphy_lane>;
+			phy-names = "ufsphy";
+
+			power-domains = <&gcc UFS_GDSC>;
+
+			clock-names =
+				"core_clk_src",
+				"core_clk",
+				"bus_clk",
+				"bus_aggr_clk",
+				"iface_clk",
+				"core_clk_unipro_src",
+				"core_clk_unipro",
+				"core_clk_ice",
+				"ref_clk",
+				"tx_lane0_sync_clk",
+				"rx_lane0_sync_clk";
+			clocks =
+				<&gcc UFS_AXI_CLK_SRC>,
+				<&gcc GCC_UFS_AXI_CLK>,
+				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
+				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+				<&gcc GCC_UFS_AHB_CLK>,
+				<&gcc UFS_ICE_CORE_CLK_SRC>,
+				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
+				<&gcc GCC_UFS_ICE_CORE_CLK>,
+				<&rpmcc RPM_SMD_LN_BB_CLK>,
+				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+			freq-table-hz =
+				<100000000 200000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<150000000 300000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>;
+
+			interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
+					<&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
+			interconnect-names = "ufs-ddr", "cpu-ufs";
+
+			lanes-per-direction = <1>;
+			#reset-cells = <1>;
+			status = "disabled";
+		};
+
+		ufsphy: phy@627000 {
+			compatible = "qcom,msm8996-qmp-ufs-phy";
+			reg = <0x00627000 0x1c4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
+			clock-names = "ref";
+
+			resets = <&ufshc 0>;
+			reset-names = "ufsphy";
+			status = "disabled";
+
+			ufsphy_lane: phy@627400 {
+				reg = <0x627400 0x12c>,
+				      <0x627600 0x200>,
+				      <0x627c00 0x1b4>;
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+			};
+		};
+
+		camss: camss@a34000 {
+			compatible = "qcom,msm8996-camss";
+			reg = <0x00a34000 0x1000>,
+			      <0x00a00030 0x4>,
+			      <0x00a35000 0x1000>,
+			      <0x00a00038 0x4>,
+			      <0x00a36000 0x1000>,
+			      <0x00a00040 0x4>,
+			      <0x00a30000 0x100>,
+			      <0x00a30400 0x100>,
+			      <0x00a30800 0x100>,
+			      <0x00a30c00 0x100>,
+			      <0x00a31000 0x500>,
+			      <0x00a00020 0x10>,
+			      <0x00a10000 0x1000>,
+			      <0x00a14000 0x1000>;
+			reg-names = "csiphy0",
+				"csiphy0_clk_mux",
+				"csiphy1",
+				"csiphy1_clk_mux",
+				"csiphy2",
+				"csiphy2_clk_mux",
+				"csid0",
+				"csid1",
+				"csid2",
+				"csid3",
+				"ispif",
+				"csi_clk_mux",
+				"vfe0",
+				"vfe1";
+			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "csiphy0",
+				"csiphy1",
+				"csiphy2",
+				"csid0",
+				"csid1",
+				"csid2",
+				"csid3",
+				"ispif",
+				"vfe0",
+				"vfe1";
+			power-domains = <&mmcc VFE0_GDSC>,
+					<&mmcc VFE1_GDSC>;
+			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+				<&mmcc CAMSS_ISPIF_AHB_CLK>,
+				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+				<&mmcc CAMSS_CSI0_AHB_CLK>,
+				<&mmcc CAMSS_CSI0_CLK>,
+				<&mmcc CAMSS_CSI0PHY_CLK>,
+				<&mmcc CAMSS_CSI0PIX_CLK>,
+				<&mmcc CAMSS_CSI0RDI_CLK>,
+				<&mmcc CAMSS_CSI1_AHB_CLK>,
+				<&mmcc CAMSS_CSI1_CLK>,
+				<&mmcc CAMSS_CSI1PHY_CLK>,
+				<&mmcc CAMSS_CSI1PIX_CLK>,
+				<&mmcc CAMSS_CSI1RDI_CLK>,
+				<&mmcc CAMSS_CSI2_AHB_CLK>,
+				<&mmcc CAMSS_CSI2_CLK>,
+				<&mmcc CAMSS_CSI2PHY_CLK>,
+				<&mmcc CAMSS_CSI2PIX_CLK>,
+				<&mmcc CAMSS_CSI2RDI_CLK>,
+				<&mmcc CAMSS_CSI3_AHB_CLK>,
+				<&mmcc CAMSS_CSI3_CLK>,
+				<&mmcc CAMSS_CSI3PHY_CLK>,
+				<&mmcc CAMSS_CSI3PIX_CLK>,
+				<&mmcc CAMSS_CSI3RDI_CLK>,
+				<&mmcc CAMSS_AHB_CLK>,
+				<&mmcc CAMSS_VFE0_CLK>,
+				<&mmcc CAMSS_CSI_VFE0_CLK>,
+				<&mmcc CAMSS_VFE0_AHB_CLK>,
+				<&mmcc CAMSS_VFE0_STREAM_CLK>,
+				<&mmcc CAMSS_VFE1_CLK>,
+				<&mmcc CAMSS_CSI_VFE1_CLK>,
+				<&mmcc CAMSS_VFE1_AHB_CLK>,
+				<&mmcc CAMSS_VFE1_STREAM_CLK>,
+				<&mmcc CAMSS_VFE_AHB_CLK>,
+				<&mmcc CAMSS_VFE_AXI_CLK>;
+			clock-names = "top_ahb",
+				"ispif_ahb",
+				"csiphy0_timer",
+				"csiphy1_timer",
+				"csiphy2_timer",
+				"csi0_ahb",
+				"csi0",
+				"csi0_phy",
+				"csi0_pix",
+				"csi0_rdi",
+				"csi1_ahb",
+				"csi1",
+				"csi1_phy",
+				"csi1_pix",
+				"csi1_rdi",
+				"csi2_ahb",
+				"csi2",
+				"csi2_phy",
+				"csi2_pix",
+				"csi2_rdi",
+				"csi3_ahb",
+				"csi3",
+				"csi3_phy",
+				"csi3_pix",
+				"csi3_rdi",
+				"ahb",
+				"vfe0",
+				"csi_vfe0",
+				"vfe0_ahb",
+				"vfe0_stream",
+				"vfe1",
+				"csi_vfe1",
+				"vfe1_ahb",
+				"vfe1_stream",
+				"vfe_ahb",
+				"vfe_axi";
+			iommus = <&vfe_smmu 0>,
+				 <&vfe_smmu 1>,
+				 <&vfe_smmu 2>,
+				 <&vfe_smmu 3>;
+			status = "disabled";
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		cci: cci@a0c000 {
+			compatible = "qcom,msm8996-cci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa0c000 0x1000>;
+			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&mmcc CAMSS_GDSC>;
+			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+				 <&mmcc CAMSS_CCI_AHB_CLK>,
+				 <&mmcc CAMSS_CCI_CLK>,
+				 <&mmcc CAMSS_AHB_CLK>;
+			clock-names = "camss_top_ahb",
+				      "cci_ahb",
+				      "cci",
+				      "camss_ahb";
+			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
+					  <&mmcc CAMSS_CCI_CLK>;
+			assigned-clock-rates = <80000000>, <37500000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&cci0_default &cci1_default>;
+			status = "disabled";
+
+			cci_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		adreno_smmu: iommu@b40000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0x00b40000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+
+			clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+				 <&mmcc GPU_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&mmcc GPU_GDSC>;
+		};
+
+		venus: video-codec@c00000 {
+			compatible = "qcom,msm8996-venus";
+			reg = <0x00c00000 0xff000>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mmcc VENUS_GDSC>;
+			clocks = <&mmcc VIDEO_CORE_CLK>,
+				 <&mmcc VIDEO_AHB_CLK>,
+				 <&mmcc VIDEO_AXI_CLK>,
+				 <&mmcc VIDEO_MAXI_CLK>;
+			clock-names = "core", "iface", "bus", "mbus";
+			interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
+					<&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
+			interconnect-names = "video-mem", "cpu-cfg";
+			iommus = <&venus_smmu 0x00>,
+				 <&venus_smmu 0x01>,
+				 <&venus_smmu 0x0a>,
+				 <&venus_smmu 0x07>,
+				 <&venus_smmu 0x0e>,
+				 <&venus_smmu 0x0f>,
+				 <&venus_smmu 0x08>,
+				 <&venus_smmu 0x09>,
+				 <&venus_smmu 0x0b>,
+				 <&venus_smmu 0x0c>,
+				 <&venus_smmu 0x0d>,
+				 <&venus_smmu 0x10>,
+				 <&venus_smmu 0x11>,
+				 <&venus_smmu 0x21>,
+				 <&venus_smmu 0x28>,
+				 <&venus_smmu 0x29>,
+				 <&venus_smmu 0x2b>,
+				 <&venus_smmu 0x2c>,
+				 <&venus_smmu 0x2d>,
+				 <&venus_smmu 0x31>;
+			memory-region = <&venus_mem>;
+			status = "disabled";
+
+			video-decoder {
+				compatible = "venus-decoder";
+				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+				clock-names = "core";
+				power-domains = <&mmcc VENUS_CORE0_GDSC>;
+			};
+
+			video-encoder {
+				compatible = "venus-encoder";
+				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+				clock-names = "core";
+				power-domains = <&mmcc VENUS_CORE1_GDSC>;
+			};
+		};
+
+		mdp_smmu: iommu@d00000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0x00d00000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+				 <&mmcc SMMU_MDP_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&mmcc MDSS_GDSC>;
+		};
+
+		venus_smmu: iommu@d40000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0x00d40000 0x20000>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
+			clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+				 <&mmcc SMMU_VIDEO_AHB_CLK>;
+			clock-names = "bus", "iface";
+			#iommu-cells = <1>;
+			status = "okay";
+		};
+
+		vfe_smmu: iommu@da0000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0x00da0000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
+			clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+				 <&mmcc SMMU_VFE_AHB_CLK>;
+			clock-names = "bus", "iface";
+			#iommu-cells = <1>;
+		};
+
+		lpass_q6_smmu: iommu@1600000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0x01600000 0x20000>;
+			#iommu-cells = <1>;
+			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+				 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+			clock-names = "bus", "iface";
+		};
+
+		slpi_pil: remoteproc@1c00000 {
+			compatible = "qcom,msm8996-slpi-pil";
+			reg = <0x01c00000 0x4000>;
+
+			interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
+					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&xo_board>,
+				 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
+			clock-names = "xo", "aggre2";
+
+			memory-region = <&slpi_mem>;
+
+			qcom,smem-states = <&slpi_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			power-domains = <&rpmpd MSM8996_VDDSSCX>;
+			power-domain-names = "ssc_cx";
+
+			status = "disabled";
+
+			smd-edge {
+				interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
+
+				label = "dsps";
+				mboxes = <&apcs_glb 25>;
+				qcom,smd-edge = <3>;
+				qcom,remote-pid = <3>;
+			};
+		};
+
+		mss_pil: remoteproc@2080000 {
+			compatible = "qcom,msm8996-mss-pil";
+			reg = <0x2080000 0x100>,
+			      <0x2180000 0x020>;
+			reg-names = "qdsp6", "rmb";
+
+			interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
+					      <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+					      <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack",
+					  "shutdown-ack";
+
+			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
+				 <&xo_board>,
+				 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
+				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
+				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+				 <&rpmcc RPM_SMD_PCNOC_CLK>,
+				 <&rpmcc RPM_SMD_QDSS_CLK>;
+			clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
+				      "snoc_axi", "mnoc_axi", "pnoc", "qdss";
+
+			resets = <&gcc GCC_MSS_RESTART>;
+			reset-names = "mss_restart";
+
+			power-domains = <&rpmpd MSM8996_VDDCX>,
+					<&rpmpd MSM8996_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			qcom,smem-states = <&mpss_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
+
+			status = "disabled";
+
+			mba {
+				memory-region = <&mba_mem>;
+			};
+
+			mpss {
+				memory-region = <&mpss_mem>;
+			};
+
+			metadata {
+				memory-region = <&mdata_mem>;
+			};
+
+			smd-edge {
+				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+
+				label = "mpss";
+				mboxes = <&apcs_glb 12>;
+				qcom,smd-edge = <0>;
+				qcom,remote-pid = <1>;
+			};
+		};
+
+		stm@3002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x3002000 0x1000>,
+			      <0x8280000 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint =
+						  <&funnel0_in>;
+					};
+				};
+			};
+		};
+
+		tpiu@3020000 {
+			compatible = "arm,coresight-tpiu", "arm,primecell";
+			reg = <0x3020000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				port {
+					tpiu_in: endpoint {
+						remote-endpoint =
+						  <&replicator_out1>;
+					};
+				};
+			};
+		};
+
+		funnel@3021000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3021000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel0_in: endpoint {
+						remote-endpoint =
+						  <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@3022000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3022000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+					funnel1_in: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@3023000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3023000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+
+			out-ports {
+				port {
+					funnel2_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in2>;
+					};
+				};
+			};
+		};
+
+		funnel@3025000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3025000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					merge_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					merge_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&funnel1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					merge_funnel_in2: endpoint {
+						remote-endpoint =
+						  <&funnel2_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&etf_in>;
+					};
+				};
+			};
+		};
+
+		replicator@3026000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x3026000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				port {
+					replicator_in: endpoint {
+						remote-endpoint =
+						  <&etf_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					replicator_out0: endpoint {
+						remote-endpoint =
+						  <&etr_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					replicator_out1: endpoint {
+						remote-endpoint =
+						  <&tpiu_in>;
+					};
+				};
+			};
+		};
+
+		etf@3027000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x3027000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				port {
+					etf_in: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf_out: endpoint {
+						remote-endpoint =
+						  <&replicator_in>;
+					};
+				};
+			};
+		};
+
+		etr@3028000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x3028000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr_in: endpoint {
+						remote-endpoint =
+						  <&replicator_out0>;
+					};
+				};
+			};
+		};
+
+		debug@3810000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x3810000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU0>;
+		};
+
+		etm@3840000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x3840000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			cpu = <&CPU0>;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel0_in0>;
+					};
+				};
+			};
+		};
+
+		debug@3910000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x3910000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU1>;
+		};
+
+		etm@3940000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x3940000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			cpu = <&CPU1>;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel0_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@39b0000 { /* APSS Funnel 0 */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x39b0000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_funnel0_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_funnel0_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel0_out: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		debug@3a10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x3a10000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU2>;
+		};
+
+		etm@3a40000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x3a40000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			cpu = <&CPU2>;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		debug@3b10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x3b10000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU3>;
+		};
+
+		etm@3b40000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0x3b40000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			cpu = <&CPU3>;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel1_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@3bb0000 { /* APSS Funnel 1 */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3bb0000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_funnel1_in0: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_funnel1_in1: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel1_out: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@3bc0000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x3bc0000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_merge_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&apss_funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_merge_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&apss_funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&funnel1_in>;
+					};
+				};
+			};
+		};
+
+		kryocc: clock-controller@6400000 {
+			compatible = "qcom,msm8996-apcc";
+			reg = <0x06400000 0x90000>;
+
+			clock-names = "xo", "sys_apcs_aux";
+			clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
+
+			#clock-cells = <1>;
+		};
+
+		usb3: usb@6af8800 {
+			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
+			reg = <0x06af8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
+			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
+				 <&gcc GCC_USB30_MASTER_CLK>,
+				 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
+				 <&gcc GCC_USB30_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <120000000>;
+
+			interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
+					<&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			power-domains = <&gcc USB30_GDSC>;
+			status = "disabled";
+
+			usb3_dwc3: usb@6a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x06a00000 0xcc00>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,hird-threshold = /bits/ 8 <0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,is-utmi-l1-suspend;
+				tx-fifo-resize;
+			};
+		};
+
+		usb3phy: phy@7410000 {
+			compatible = "qcom,msm8996-qmp-usb3-phy";
+			reg = <0x07410000 0x1c4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				<&gcc GCC_USB3_CLKREF_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_USB3_PHY_BCR>,
+				<&gcc GCC_USB3PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+			status = "disabled";
+
+			ssusb_phy_0: phy@7410200 {
+				reg = <0x07410200 0x200>,
+				      <0x07410400 0x130>,
+				      <0x07410600 0x1a8>;
+				#phy-cells = <0>;
+
+				#clock-cells = <0>;
+				clock-output-names = "usb3_phy_pipe_clk_src";
+				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+				clock-names = "pipe0";
+			};
+		};
+
+		hsusb_phy1: phy@7411000 {
+			compatible = "qcom,msm8996-qusb2-phy";
+			reg = <0x07411000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+			nvmem-cells = <&qusb2p_hstx_trim>;
+			status = "disabled";
+		};
+
+		hsusb_phy2: phy@7412000 {
+			compatible = "qcom,msm8996-qusb2-phy";
+			reg = <0x07412000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+			nvmem-cells = <&qusb2s_hstx_trim>;
+			status = "disabled";
+		};
+
+		sdhc1: mmc@7464900 {
+			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
+			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clock-names = "iface", "core", "xo";
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				<&gcc GCC_SDCC1_APPS_CLK>,
+				<&rpmcc RPM_SMD_XO_CLK_SRC>;
+			resets = <&gcc GCC_SDCC1_BCR>;
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&sdc1_state_on>;
+			pinctrl-1 = <&sdc1_state_off>;
+
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		sdhc2: mmc@74a4900 {
+			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
+			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clock-names = "iface", "core", "xo";
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				<&gcc GCC_SDCC2_APPS_CLK>,
+				<&rpmcc RPM_SMD_XO_CLK_SRC>;
+			resets = <&gcc GCC_SDCC2_BCR>;
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&sdc2_state_on>;
+			pinctrl-1 = <&sdc2_state_off>;
+
+			bus-width = <4>;
+			status = "disabled";
+		 };
+
+		blsp1_dma: dma-controller@7544000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07544000 0x2b000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		blsp1_uart2: serial@7570000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x07570000 0x1000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			pinctrl-1 = <&blsp1_uart2_sleep>;
+			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		blsp1_spi1: spi@7575000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x07575000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_spi1_default>;
+			pinctrl-1 = <&blsp1_spi1_sleep>;
+			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c3: i2c@7577000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07577000 0x1000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_i2c3_default>;
+			pinctrl-1 = <&blsp1_i2c3_sleep>;
+			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c6: i2c@757a000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x757a000 0x1000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_i2c6_default>;
+			pinctrl-1 = <&blsp1_i2c6_sleep>;
+			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_dma: dma-controller@7584000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07584000 0x2b000>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		blsp2_uart2: serial@75b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x075b0000 0x1000>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		blsp2_uart3: serial@75b1000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x075b1000 0x1000>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		blsp2_i2c1: i2c@75b5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x075b5000 0x1000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_i2c1_default>;
+			pinctrl-1 = <&blsp2_i2c1_sleep>;
+			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c2: i2c@75b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x075b6000 0x1000>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_i2c2_default>;
+			pinctrl-1 = <&blsp2_i2c2_sleep>;
+			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c3: i2c@75b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x075b7000 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			clock-frequency = <400000>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_i2c3_default>;
+			pinctrl-1 = <&blsp2_i2c3_sleep>;
+			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c5: i2c@75b9000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x75b9000 0x1000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp2_i2c5_default>;
+			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c6: i2c@75ba000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x75ba000 0x1000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_i2c6_default>;
+			pinctrl-1 = <&blsp2_i2c6_sleep>;
+			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_spi6: spi@75ba000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x075ba000 0x600>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_spi6_default>;
+			pinctrl-1 = <&blsp2_spi6_sleep>;
+			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+			dma-names = "tx", "rx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		usb2: usb@76f8800 {
+			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
+			reg = <0x076f8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq";
+
+			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
+				<&gcc GCC_USB20_MASTER_CLK>,
+				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
+				<&gcc GCC_USB20_SLEEP_CLK>,
+				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <60000000>;
+
+			power-domains = <&gcc USB30_GDSC>;
+			qcom,select-utmi-as-pipe-clk;
+			status = "disabled";
+
+			usb2_dwc3: usb@7600000 {
+				compatible = "snps,dwc3";
+				reg = <0x07600000 0xcc00>;
+				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&hsusb_phy2>;
+				phy-names = "usb2-phy";
+				maximum-speed = "high-speed";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+			};
+		};
+
+		slimbam: dma-controller@9184000 {
+			compatible = "qcom,bam-v1.7.0";
+			qcom,controlled-remotely;
+			reg = <0x09184000 0x32000>;
+			num-channels = <31>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,num-ees = <2>;
+		};
+
+		slim_msm: slim-ngd@91c0000 {
+			compatible = "qcom,slim-ngd-v1.5.0";
+			reg = <0x091c0000 0x2c000>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&slimbam 3>, <&slimbam 4>;
+			dma-names = "rx", "tx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		adsp_pil: remoteproc@9300000 {
+			compatible = "qcom,msm8996-adsp-pil";
+			reg = <0x09300000 0x80000>;
+
+			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+			clock-names = "xo";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,smem-states = <&adsp_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			power-domains = <&rpmpd MSM8996_VDDCX>;
+			power-domain-names = "cx";
+
+			status = "disabled";
+
+			smd-edge {
+				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+				label = "lpass";
+				mboxes = <&apcs_glb 8>;
+				qcom,smd-edge = <1>;
+				qcom,remote-pid = <2>;
+
+				apr {
+					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+					compatible = "qcom,apr-v2";
+					qcom,smd-channels = "apr_audio_svc";
+					qcom,domain = <APR_DOMAIN_ADSP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					service@3 {
+						reg = <APR_SVC_ADSP_CORE>;
+						compatible = "qcom,q6core";
+					};
+
+					q6afe: service@4 {
+						compatible = "qcom,q6afe";
+						reg = <APR_SVC_AFE>;
+						q6afedai: dais {
+							compatible = "qcom,q6afe-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							dai@1 {
+								reg = <1>;
+							};
+						};
+					};
+
+					q6asm: service@7 {
+						compatible = "qcom,q6asm";
+						reg = <APR_SVC_ASM>;
+						q6asmdai: dais {
+							compatible = "qcom,q6asm-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							iommus = <&lpass_q6_smmu 1>;
+						};
+					};
+
+					q6adm: service@8 {
+						compatible = "qcom,q6adm";
+						reg = <APR_SVC_ADM>;
+						q6routing: routing {
+							compatible = "qcom,q6adm-routing";
+							#sound-dai-cells = <0>;
+						};
+					};
+				};
+			};
+		};
+
+		apcs_glb: mailbox@9820000 {
+			compatible = "qcom,msm8996-apcs-hmss-global";
+			reg = <0x09820000 0x1000>;
+
+			#mbox-cells = <1>;
+			#clock-cells = <0>;
+		};
+
+		timer@9840000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x09840000 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@9850000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x09850000 0x1000>,
+				      <0x09860000 0x1000>;
+			};
+
+			frame@9870000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x09870000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@9880000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x09880000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@9890000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x09890000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@98a0000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x098a0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@98b0000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x098b0000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@98c0000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x098c0000 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		saw3: syscon@9a10000 {
+			compatible = "syscon";
+			reg = <0x09a10000 0x1000>;
+		};
+
+		cbf: clock-controller@9a11000 {
+			compatible = "qcom,msm8996-cbf";
+			reg = <0x09a11000 0x10000>;
+			clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
+			#clock-cells = <0>;
+			#interconnect-cells = <1>;
+		};
+
+		intc: interrupt-controller@9bc0000 {
+			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x40000>;
+			reg = <0x09bc0000 0x10000>,
+			      <0x09c00000 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	sound: sound {
+	};
+
+	thermal-zones {
+		cpu0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3_crit: cpu-crit {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-top-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 6>;
+
+			trips {
+				gpu1_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu1_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-bottom-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 7>;
+
+			trips {
+				gpu2_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu2_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		m4m-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				m4m_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		l3-or-venus-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				l3_or_venus_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cluster0-l2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				cluster0_l2_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cluster1-l2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 12>;
+
+			trips {
+				cluster1_l2_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		camera-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 1>;
+
+			trips {
+				camera_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-dsp-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 2>;
+
+			trips {
+				q6_dsp_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		mem-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 3>;
+
+			trips {
+				mem_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		modemtx-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens1 4>;
+
+			trips {
+				modemtx_alert0: trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index 89847ce0b307..bf70258ec040 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x804000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
 CONFIG_ENV_SIZE=0x4000
-CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
+CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c"
 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
 CONFIG_SYS_LOAD_ADDR=0x80080000
 CONFIG_DISTRO_DEFAULTS=y

-- 
2.43.1

[PATCH v4 37/39] dt-bindings: import headers for qcs404

[Caleb Connolly]

Import the headers needed for QCS404-evb.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
new file mode 100644
index 000000000000..838faef57c67
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, Linaro Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
+#define _DT_BINDINGS_CLK_TURING_QCS404_H
+
+#define TURING_Q6SS_Q6_AXIM_CLK		0
+#define TURING_Q6SS_AHBM_AON_CLK	1
+#define TURING_WRAPPER_AON_CLK		2
+#define TURING_Q6SS_AHBS_AON_CLK	3
+#define TURING_WRAPPER_QOS_AHBS_AON_CLK	4
+
+#endif

-- 
2.43.1

[PATCH v4 38/39] dts: qcs404-evb: replace with upstream DT

[Caleb Connolly]

Drop the U-Boot specific DTS in favour of upstream. We'll only include
the -4000 variant as that is what U-Boot already supported.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 arch/arm/dts/Makefile                    |    2 +-
 arch/arm/dts/pms405.dtsi                 |  149 +++
 arch/arm/dts/qcs404-evb-4000-u-boot.dtsi |   48 +
 arch/arm/dts/qcs404-evb-4000.dts         |   96 ++
 arch/arm/dts/qcs404-evb-uboot.dtsi       |   30 -
 arch/arm/dts/qcs404-evb.dts              |  390 -------
 arch/arm/dts/qcs404-evb.dtsi             |  389 +++++++
 arch/arm/dts/qcs404.dtsi                 | 1829 ++++++++++++++++++++++++++++++
 8 files changed, 2512 insertions(+), 421 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 54aaf022c2eb..c4f0873dbb1f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -635,7 +635,7 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
 	apq8096-db820c.dtb \
 	sdm845-db845c.dtb \
 	sdm845-samsung-starqltechn.dtb \
-	qcs404-evb.dtb
+	qcs404-evb-4000.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi
new file mode 100644
index 000000000000..461ad97032f7
--- /dev/null
+++ b/arch/arm/dts/pms405.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	thermal-zones {
+		pms405-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&pms405_temp>;
+
+			trips {
+				pms405_alert0: pms405-alert0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				pms405_crit: pms405-crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pms405_0: pms405@0 {
+		compatible = "qcom,pms405", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pms405_gpios: gpio@c000 {
+			compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pms405_gpios 0 0 12>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pon@800 {
+			compatible = "qcom,pms405-pon";
+			reg = <0x0800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
+		pms405_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pms405_adc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pms405_adc: adc@3100 {
+			compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <ADC5_REF_GND>;
+				qcom,pre-scaling = <1 1>;
+				label = "ref_gnd";
+			};
+
+			channel@1 {
+				reg = <ADC5_1P25VREF>;
+				qcom,pre-scaling = <1 1>;
+				label = "vref_1p25";
+			};
+
+			channel@131 {
+				reg = <ADC5_VPH_PWR>;
+				qcom,pre-scaling = <1 3>;
+				label = "vph_pwr";
+			};
+
+			channel@6 {
+				reg = <ADC5_DIE_TEMP>;
+				qcom,pre-scaling = <1 1>;
+				label = "die_temp";
+			};
+
+			channel@77 {
+				reg = <ADC5_AMUX_THM1_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				label = "pa_therm1";
+			};
+
+			channel@79 {
+				reg = <ADC5_AMUX_THM3_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				label = "pa_therm3";
+			};
+
+			channel@76 {
+				reg = <ADC5_XO_THERM_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				label = "xo_therm";
+			};
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+		};
+	};
+
+	pms405_1: pms405@1 {
+		compatible = "qcom,pms405", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+
+		pms405_spmi_regulators: regulators {
+			compatible = "qcom,pms405-regulators";
+		};
+	};
+};
diff --git a/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
new file mode 100644
index 000000000000..d3033ea42ec1
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/gpio/gpio.h>
+
+/delete-node/ &usb3_vbus_reg;
+/delete-node/ &usb_vbus_boost_pin;
+
+/ {
+	/* U-Boot uses different bindings for GPIO regulators, this
+	 * one is required for USB
+	 */
+	usb3_vbus_reg: usb3_vbus_reg {
+		compatible = "regulator-gpio";
+		regulator-name = "usb3_vbus_reg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		states = <0 0>, <5000000 1>;
+	};
+};
+
+&blsp1_uart2 {
+	/* This defines the bit clock divider which defines the baud rate.
+	 * 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
+	 * clock driver in U-Boot hardcodes a 1843200Hz frequency for the
+	 * UART core clock, and 1843200 / 16 = 115200.
+	 */
+	bit-rate = <0xFF>;
+};
+
+&gcc {
+	/* The clock framework in U-Boot "sort of" has the idea of linking an
+	 * individual clock to a device via uclass_priv. However the qcom clock
+	 * driver instead associates many clocks with a single device. This is
+	 * usually fine but it seems that assigned-clocks wreak havoc on this
+	 * and we wind up having a reference to the XO clock which is associated
+	 * with the qcom_clk device...
+	 * For now we'll just remove these properties, no other board has these.
+	 */
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clocks;
+};
+
+&usb3_dwc3 {
+	/* Make sure the VBUS supply is switched on */
+	vbus-supply = <&usb3_vbus_reg>;
+};
diff --git a/arch/arm/dts/qcs404-evb-4000.dts b/arch/arm/dts/qcs404-evb-4000.dts
new file mode 100644
index 000000000000..358827c2fbd3
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb-4000.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "qcs404-evb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
+	compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
+		     "qcom,qcs404";
+};
+
+&ethernet {
+	status = "okay";
+
+	snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 10000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet_defaults>;
+
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii";
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy1: phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			device_type = "ethernet-phy";
+			reg = <0x4>;
+		};
+	};
+};
+
+&tlmm {
+	ethernet_defaults: ethernet-defaults-state {
+		int-pins {
+			pins = "gpio61";
+			function = "rgmii_int";
+			bias-disable;
+			drive-strength = <2>;
+		};
+		mdc-pins {
+			pins = "gpio76";
+			function = "rgmii_mdc";
+			bias-pull-up;
+		};
+		mdio-pins {
+			pins = "gpio75";
+			function = "rgmii_mdio";
+			bias-pull-up;
+		};
+		tx-pins {
+			pins = "gpio67", "gpio66", "gpio65", "gpio64";
+			function = "rgmii_tx";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+		rx-pins {
+			pins = "gpio73", "gpio72", "gpio71", "gpio70";
+			function = "rgmii_rx";
+			bias-disable;
+			drive-strength = <2>;
+		};
+		tx-ctl-pins {
+			pins = "gpio68";
+			function = "rgmii_ctl";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+		rx-ctl-pins {
+			pins = "gpio74";
+			function = "rgmii_ctl";
+			bias-disable;
+			drive-strength = <2>;
+		};
+		tx-ck-pins {
+			pins = "gpio63";
+			function = "rgmii_ck";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+		rx-ck-pins {
+			pins = "gpio69";
+			function = "rgmii_ck";
+			bias-disable;
+			drive-strength = <2>;
+		};
+	};
+};
diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi
deleted file mode 100644
index b4c5f3fa4301..000000000000
--- a/arch/arm/dts/qcs404-evb-uboot.dtsi
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot addition to handle QCS404 EVB pre-relocation devices
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-/ {
-	soc {
-		bootph-all;
-
-		pinctrl_north@1300000 {
-			bootph-all;
-		};
-
-		clock-controller@1800000 {
-			bootph-all;
-		};
-
-		serial@78b1000 {
-			bootph-all;
-		};
-	};
-};
-
-&pms405_gpios {
-	usb_vbus_boost_pin {
-		gpios = <&pms405_gpios 2 0>;
-	};
-};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
deleted file mode 100644
index 07bf7dd0b32f..000000000000
--- a/arch/arm/dts/qcs404-evb.dts
+++ /dev/null
@@ -1,390 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm QCS404 based evaluation board device tree source
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-/dts-v1/;
-
-#include "skeleton64.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
-
-/ {
-	model = "Qualcomm Technologies, Inc. QCS404 EVB";
-	compatible = "qcom,qcs404-evb", "qcom,qcs404";
-	#address-cells = <0x2>;
-	#size-cells = <0x2>;
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		serial0 = &debug_uart;
-		i2c0 = &blsp1_i2c0;
-		i2c1 = &blsp1_i2c1;
-		i2c2 = &blsp1_i2c2;
-		i2c3 = &blsp1_i2c3;
-		i2c4 = &blsp1_i2c4;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x40000000>;
-	};
-
-	soc {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		ranges = <0x0 0x0 0x0 0xffffffff>;
-		compatible = "simple-bus";
-
-		soc_gpios: pinctrl_north@1300000 {
-			compatible = "qcom,qcs404-pinctrl";
-			reg = <0x1300000 0x200000>;
-			gpio-controller;
-			gpio-count = <120>;
-			gpio-bank-name="soc";
-			#gpio-cells = <2>;
-
-			blsp1_uart2: uart {
-				pins = "GPIO_17", "GPIO_18";
-				function = "blsp_uart2";
-			};
-
-			blsp1_i2c0_default: blsp1-i2c0-default {
-				pins = "GPIO_32", "GPIO_33";
-				function = "blsp_i2c0";
-			};
-
-			blsp1_i2c1_default: blsp1-i2c1-default {
-				pins = "GPIO_24", "GPIO_25";
-				function = "blsp_i2c1";
-			};
-
-			blsp1_i2c2_default: blsp1-i2c2-default {
-				sda {
-					pins = "GPIO_19";
-					function = "blsp_i2c_sda_a2";
-				};
-
-				scl {
-					pins = "GPIO_20";
-					function = "blsp_i2c_scl_a2";
-				};
-			};
-
-			blsp1_i2c3_default: blsp1-i2c3-default {
-				pins = "GPIO_84", "GPIO_85";
-				function = "blsp_i2c3";
-			};
-
-			blsp1_i2c4_default: blsp1-i2c4-default {
-				pins = "GPIO_117", "GPIO_118";
-				function = "blsp_i2c4";
-			};
-
-			ethernet_defaults: ethernet-defaults {
-				int {
-					pins = "GPIO_61";
-					function = "rgmii_int";
-					bias-disable;
-					drive-strength = <2>;
-				};
-				mdc {
-					pins = "GPIO_76";
-					function = "rgmii_mdc";
-					bias-pull-up;
-				};
-				mdio {
-					pins = "GPIO_75";
-					function = "rgmii_mdio";
-					bias-pull-up;
-				};
-				tx {
-					pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
-					function = "rgmii_tx";
-					bias-pull-up;
-					drive-strength = <16>;
-				};
-				rx {
-					pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
-					function = "rgmii_rx";
-					bias-disable;
-					drive-strength = <2>;
-				};
-				tx-ctl {
-					pins = "GPIO_68";
-					function = "rgmii_ctl";
-					bias-pull-up;
-					drive-strength = <16>;
-				};
-				rx-ctl {
-					pins = "GPIO_74";
-					function = "rgmii_ctl";
-					bias-disable;
-					drive-strength = <2>;
-				};
-				tx-ck {
-					pins = "GPIO_63";
-					function = "rgmii_ck";
-					bias-pull-up;
-					drive-strength = <16>;
-				};
-				rx-ck {
-					pins = "GPIO_69";
-					function = "rgmii_ck";
-					bias-disable;
-					drive-strength = <2>;
-				};
-			};
-		};
-
-		blsp1_i2c0: i2c@78b5000 {
-			compatible = "qcom,i2c-qup-v2.2.1";
-			reg = <0x078b5000 0x600>;
-			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-				 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
-			clock-names = "iface", "core";
-			pinctrl-names = "default";
-			pinctrl-0 = <&blsp1_i2c0_default>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		blsp1_i2c1: i2c@78b6000 {
-			compatible = "qcom,i2c-qup-v2.2.1";
-			reg = <0x078b6000 0x600>;
-			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
-			clock-names = "iface", "core";
-			pinctrl-names = "default";
-			pinctrl-0 = <&blsp1_i2c1_default>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		blsp1_i2c2: i2c@78b7000 {
-			compatible = "qcom,i2c-qup-v2.2.1";
-			reg = <0x078b7000 0x600>;
-			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-			clock-names = "iface", "core";
-			pinctrl-names = "default";
-			pinctrl-0 = <&blsp1_i2c2_default>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		blsp1_i2c3: i2c@78b8000 {
-			compatible = "qcom,i2c-qup-v2.2.1";
-			reg = <0x078b8000 0x600>;
-			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
-			clock-names = "iface", "core";
-			pinctrl-names = "default";
-			pinctrl-0 = <&blsp1_i2c3_default>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		blsp1_i2c4: i2c@78b9000 {
-			compatible = "qcom,i2c-qup-v2.2.1";
-			reg = <0x078b9000 0x600>;
-			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
-			clock-names = "iface", "core";
-			pinctrl-names = "default";
-			pinctrl-0 = <&blsp1_i2c4_default>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		gcc: clock-controller@1800000 {
-			compatible = "qcom,gcc-qcs404";
-			reg = <0x1800000 0x80000>;
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		debug_uart: serial@78b1000 {
-			compatible = "qcom,msm-uartdm-v1.4";
-			reg = <0x78b1000 0x200>;
-			clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-				<&gcc GCC_BLSP1_AHB_CLK>;
-			bit-rate = <0xFF>;
-			pinctrl-names = "uart";
-			pinctrl-0 = <&blsp1_uart2>;
-		};
-
-		sdhci@7804000 {
-			compatible = "qcom,sdhci-msm-v5";
-			reg = <0x7804000 0x1000 0x7805000 0x1000>;
-			clock = <&gcc GCC_SDCC1_APPS_CLK>,
-				<&gcc GCC_SDCC1_AHB_CLK>;
-			bus-width = <0x8>;
-			index = <0x0>;
-			non-removable;
-			mmc-ddr-1_8v;
-			mmc-hs400-1_8v;
-		};
-
-		usb3_phy: phy@78000 {
-			compatible = "qcom,usb-ss-28nm-phy";
-			#phy-cells = <0>;
-			reg = <0x78000 0x400>;
-			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
-				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
-			clock-names = "ahb", "pipe";
-			resets = <&gcc GCC_USB3_PHY_BCR>,
-				 <&gcc GCC_USB3PHY_PHY_BCR>;
-			reset-names = "com", "phy";
-		};
-
-		usb2_phy_prim: phy@7a000 {
-			compatible = "qcom,usb-hs-28nm-femtophy";
-			#phy-cells = <0>;
-			reg = <0x7a000 0x200>;
-			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
-				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
-			clock-names = "ahb", "sleep";
-			resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
-				 <&gcc GCC_USB2A_PHY_BCR>;
-			reset-names = "phy", "por";
-		};
-
-		usb2_phy_sec: phy@7c000 {
-			compatible = "qcom,usb-hs-28nm-femtophy";
-			#phy-cells = <0>;
-			reg = <0x7c000 0x200>;
-			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
-				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
-			clock-names = "ahb", "sleep";
-			resets = <&gcc GCC_QUSB2_PHY_BCR>,
-				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
-			reset-names = "phy", "por";
-		};
-
-		usb3: usb@7678800 {
-			compatible = "qcom,dwc3";
-			reg = <0x7678800 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&gcc GCC_USB30_MASTER_CLK>,
-				 <&gcc GCC_SYS_NOC_USB3_CLK>,
-				 <&gcc GCC_USB30_SLEEP_CLK>,
-				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
-			clock-names = "core", "iface", "sleep", "mock_utmi";
-
-			dwc3@7580000 {
-				compatible = "snps,dwc3";
-				reg = <0x7580000 0xcd00>;
-				phys = <&usb2_phy_prim>, <&usb3_phy>;
-				phy-names = "usb2-phy", "usb3-phy";
-				dr_mode = "host";
-				snps,has-lpm-erratum;
-				snps,hird-threshold = /bits/ 8 <0x10>;
-				snps,usb3_lpm_capable;
-				maximum-speed = "super-speed";
-			};
-		};
-
-		usb2: usb@79b8800 {
-			compatible = "qcom,dwc3";
-			reg = <0x79b8800 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
-				 <&gcc GCC_PCNOC_USB2_CLK>,
-				 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
-				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
-			clock-names = "core", "iface", "sleep", "mock_utmi";
-
-			dwc3@78c0000 {
-				compatible = "snps,dwc3";
-				reg = <0x78c0000 0xcc00>;
-				phys = <&usb2_phy_sec>;
-				phy-names = "usb2-phy";
-				dr_mode = "peripheral";
-				snps,has-lpm-erratum;
-				snps,hird-threshold = /bits/ 8 <0x10>;
-				snps,usb3_lpm_capable;
-				maximum-speed = "high-speed";
-			};
-		};
-
-		ethernet: ethernet@7a80000 {
-			compatible = "qcom,qcs404-ethqos";
-			reg = <0x07a80000 0x10000>,
-				<0x07a96000 0x100>;
-			reg-names = "stmmaceth", "rgmii";
-			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
-			clocks = <&gcc GCC_ETH_AXI_CLK>,
-				 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
-				 <&gcc GCC_ETH_PTP_CLK>,
-				 <&gcc GCC_ETH_RGMII_CLK>;
-
-			resets = <&gcc GCC_EMAC_BCR>;
-			reset-names = "emac";
-
-			snps,tso;
-			rx-fifo-depth = <4096>;
-			tx-fifo-depth = <4096>;
-
-			snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
-			snps,reset-active-low;
-			snps,reset-delays-us = <0 10000 10000>;
-
-			pinctrl-names = "default";
-			pinctrl-0 = <&ethernet_defaults>;
-
-			phy-handle = <&phy1>;
-			phy-mode = "rgmii";
-			max-speed = <1000>;
-
-			mdio {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
-				compatible = "snps,dwmac-mdio";
-				phy1: phy@3 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					device_type = "ethernet-phy";
-					reg = <0x3>;
-				};
-			};
-		};
-
-		spmi@200f000 {
-			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x200f000 0x001000>,
-			      <0x2400000 0x800000>,
-			      <0x2c00000 0x800000>;
-			reg-names = "core", "chnls", "obsrvr";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-
-			pms405_0: pms405@0 {
-				compatible = "qcom,spmi-pmic";
-				reg = <0x0 0x1>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
-
-				pms405_gpios: pms405_gpios@c000 {
-					compatible = "qcom,pms405-gpio";
-					reg = <0xc000 0x400>;
-					gpio-controller;
-					gpio-ranges = <&pms405_gpios 0 0 12>;
-					#gpio-cells = <2>;
-				};
-			};
-		};
-	};
-};
-
-#include "qcs404-evb-uboot.dtsi"
diff --git a/arch/arm/dts/qcs404-evb.dtsi b/arch/arm/dts/qcs404-evb.dtsi
new file mode 100644
index 000000000000..10655401528e
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb.dtsi
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "qcs404.dtsi"
+#include "pms405.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+	aliases {
+		serial0 = &blsp1_uart2;
+		serial1 = &blsp1_uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_ch0_3p3:
+	vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "eSMPS3_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	usb3_vbus_reg: regulator-usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "VBUS_BOOST_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_vbus_boost_pin>;
+		vin-supply = <&vph_pwr>;
+		enable-active-high;
+
+		/* TODO: Drop this when introducing role switching */
+		regulator-always-on;
+	};
+};
+
+&blsp1_uart3 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn3990-bt";
+		vddio-supply = <&vreg_l6_1p8>;
+		vddxo-supply = <&vreg_l5_1p8>;
+		vddrf-supply = <&vreg_l1_1p3>;
+		vddch0-supply = <&vdd_ch0_3p3>;
+
+		local-bd-address = [ 02 00 00 00 5a ad ];
+
+		max-speed = <3200000>;
+	};
+};
+
+&blsp1_dma {
+	qcom,controlled-remotely;
+};
+
+&blsp2_dma {
+	qcom,controlled-remotely;
+};
+
+&gcc {
+	protected-clocks = <GCC_BIMC_CDSP_CLK>,
+			   <GCC_CDSP_CFG_AHB_CLK>,
+			   <GCC_CDSP_BIMC_CLK_SRC>,
+			   <GCC_CDSP_TBU_CLK>,
+			   <141>, /* GCC_WCSS_Q6_AHB_CLK */
+			   <142>; /* GCC_WCSS_Q6_AXIM_CLK */
+};
+
+&pms405_spmi_regulators {
+	vdd_s3-supply = <&vph_pwr>;
+
+	pms405_s3: s3 {
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vdd_apc";
+		regulator-initial-mode = <1>;
+		regulator-min-microvolt = <1048000>;
+		regulator-max-microvolt = <1384000>;
+	};
+};
+
+&pcie {
+	status = "okay";
+
+	perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&perst_state>;
+};
+
+&pcie_phy {
+	status = "okay";
+
+	vdda-vp-supply = <&vreg_l3_1p05>;
+	vdda-vph-supply = <&vreg_l5_1p8>;
+};
+
+&remoteproc_adsp {
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	status = "okay";
+};
+
+&remoteproc_wcss {
+	status = "okay";
+};
+
+&rpm_requests {
+	regulators {
+		compatible = "qcom,rpm-pms405-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_l1_l2-supply = <&vreg_s5_1p35>;
+		vdd_l3_l8-supply = <&vreg_s5_1p35>;
+		vdd_l4-supply = <&vreg_s5_1p35>;
+		vdd_l5_l6-supply = <&vreg_s4_1p8>;
+		vdd_l7-supply = <&vph_pwr>;
+		vdd_l9-supply = <&vreg_s5_1p35>;
+		vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
+
+		vreg_s4_1p8: s4 {
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1920000>;
+		};
+
+		vreg_s5_1p35: s5 {
+			regulator-min-microvolt = <1352000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_l1_1p3: l1 {
+			regulator-min-microvolt = <1240000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_l2_1p275: l2 {
+			regulator-min-microvolt = <1048000>;
+			regulator-max-microvolt = <1280000>;
+		};
+
+		vreg_l3_1p05: l3 {
+			regulator-min-microvolt = <1048000>;
+			regulator-max-microvolt = <1160000>;
+		};
+
+		vreg_l4_1p2: l4 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1256000>;
+		};
+
+		vreg_l5_1p8: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vreg_l6_1p8: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vreg_l7_1p8: l7 {
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <3000000>;
+		};
+
+		vreg_l8_1p2: l8 {
+			regulator-min-microvolt = <1136000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_l10_3p3: l10 {
+			regulator-min-microvolt = <2936000>;
+			regulator-max-microvolt = <3088000>;
+		};
+
+		vreg_l11_sdc2: l11 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+		};
+
+		vreg_l12_3p3: l12 {
+			regulator-min-microvolt = <3050000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		vreg_l13_3p3: l13 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&sdcc1 {
+	status = "okay";
+
+	supports-cqe;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	bus-width = <8>;
+	non-removable;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
+
+&tlmm {
+	perst_state: perst-state {
+		pins = "gpio43";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	sdc1_on: sdc1-on-state {
+		clk-pins {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd-pins {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data-pins {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		rclk-pins {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc1_off: sdc1-off-state {
+		clk-pins {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd-pins {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data-pins {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		rclk-pins {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	usb3_id_pin: usb3-id-state {
+		pins = "gpio116";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};
+
+&pms405_gpios {
+	usb_vbus_boost_pin: usb-vbus-boost-state {
+		pinconf {
+			pins = "gpio3";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+			power-source = <1>;
+		};
+	};
+	usb3_vbus_pin: usb3-vbus-state {
+		pinconf {
+			pins = "gpio12";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			power-source = <1>;
+		};
+	};
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb2_phy_sec {
+	vdd-supply = <&vreg_l4_1p2>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	vdda3p3-supply = <&vreg_l12_3p3>;
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+
+};
+
+&usb3_dwc3 {
+	dr_mode = "host";
+};
+
+&usb2_phy_prim {
+	vdd-supply = <&vreg_l4_1p2>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	vdda3p3-supply = <&vreg_l12_3p3>;
+	status = "okay";
+};
+
+&usb3_phy {
+	vdd-supply = <&vreg_l3_1p05>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+	vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
+	vdd-1.8-xo-supply = <&vreg_l5_1p8>;
+	vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
+};
+
+/* PINCTRL - additions to nodes defined in qcs404.dtsi */
+
+&blsp1_uart2_default {
+	rx-pins {
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tx-pins {
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&blsp1_uart3_default {
+	cts-pins {
+		bias-disable;
+	};
+
+	rts-tx-pins {
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rx-pins {
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm/dts/qcs404.dtsi b/arch/arm/dts/qcs404.dtsi
new file mode 100644
index 000000000000..2721f32dfb71
--- /dev/null
+++ b/arch/arm/dts/qcs404.dtsi
@@ -0,0 +1,1829 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <125>;
+				exit-latency-us = <180>;
+				min-residency-us = <595>;
+				local-timer-stop;
+			};
+		};
+	};
+
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		opp-1094400000 {
+			opp-hz = /bits/ 64 <1094400000>;
+			required-opps = <&cpr_opp1>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			required-opps = <&cpr_opp2>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			required-opps = <&cpr_opp3>;
+		};
+	};
+
+	cpr_opp_table: opp-table-cpr {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			qcom,opp-fuse-level = <3>;
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-qcs404", "qcom,scm";
+			#reset-cells = <1>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	rpm: remoteproc {
+		compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
+
+		glink-edge {
+			compatible = "qcom,glink-rpm";
+
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+			mboxes = <&apcs_glb 0>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-qcs404";
+				qcom,glink-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
+					#clock-cells = <1>;
+					clocks = <&xo_board>;
+					clock-names = "xo";
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,qcs404-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp_ret: opp1 {
+							opp-level = <16>;
+						};
+
+						rpmpd_opp_ret_plus: opp2 {
+							opp-level = <32>;
+						};
+
+						rpmpd_opp_min_svs: opp3 {
+							opp-level = <48>;
+						};
+
+						rpmpd_opp_low_svs: opp4 {
+							opp-level = <64>;
+						};
+
+						rpmpd_opp_svs: opp5 {
+							opp-level = <128>;
+						};
+
+						rpmpd_opp_svs_plus: opp6 {
+							opp-level = <192>;
+						};
+
+						rpmpd_opp_nom: opp7 {
+							opp-level = <256>;
+						};
+
+						rpmpd_opp_nom_plus: opp8 {
+							opp-level = <320>;
+						};
+
+						rpmpd_opp_turbo: opp9 {
+							opp-level = <384>;
+						};
+
+						rpmpd_opp_turbo_no_cpr: opp10 {
+							opp-level = <416>;
+						};
+
+						rpmpd_opp_turbo_plus: opp11 {
+							opp-level = <512>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz_apps_mem: memory@85900000 {
+			reg = <0 0x85900000 0 0x500000>;
+			no-map;
+		};
+
+		xbl_mem: memory@85e00000 {
+			reg = <0 0x85e00000 0 0x100000>;
+			no-map;
+		};
+
+		smem_region: memory@85f00000 {
+			reg = <0 0x85f00000 0 0x200000>;
+			no-map;
+		};
+
+		tz_mem: memory@86100000 {
+			reg = <0 0x86100000 0 0x300000>;
+			no-map;
+		};
+
+		wlan_fw_mem: memory@86400000 {
+			reg = <0 0x86400000 0 0x1100000>;
+			no-map;
+		};
+
+		adsp_fw_mem: memory@87500000 {
+			reg = <0 0x87500000 0 0x1a00000>;
+			no-map;
+		};
+
+		cdsp_fw_mem: memory@88f00000 {
+			reg = <0 0x88f00000 0 0x600000>;
+			no-map;
+		};
+
+		wlan_msa_mem: memory@89500000 {
+			reg = <0 0x89500000 0 0x100000>;
+			no-map;
+		};
+
+		uefi_mem: memory@9f800000 {
+			reg = <0 0x9f800000 0 0x800000>;
+			no-map;
+		};
+	};
+
+	smem {
+		compatible = "qcom,smem";
+
+		memory-region = <&smem_region>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		turingcc: clock-controller@800000 {
+			compatible = "qcom,qcs404-turingcc";
+			reg = <0x00800000 0x30000>;
+			clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+
+			status = "disabled";
+		};
+
+		rpm_msg_ram: sram@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x6000>;
+		};
+
+		usb3_phy: phy@78000 {
+			compatible = "qcom,usb-ss-28nm-phy";
+			reg = <0x00078000 0x400>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
+			clock-names = "ref", "ahb", "pipe";
+			resets = <&gcc GCC_USB3_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_BCR>;
+			reset-names = "com", "phy";
+			status = "disabled";
+		};
+
+		usb2_phy_prim: phy@7a000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0007a000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+				 <&gcc GCC_USB2A_PHY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
+		usb2_phy_sec: phy@7c000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0007c000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_QUSB2_PHY_BCR>,
+				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
+		qfprom: qfprom@a4000 {
+			compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
+			reg = <0x000a4000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpr_efuse_speedbin: speedbin@13c {
+				reg = <0x13c 0x4>;
+				bits = <2 3>;
+			};
+
+			tsens_s0_p1: s0-p1@1f8 {
+				reg = <0x1f8 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s0_p2: s0-p2@1f8 {
+				reg = <0x1f8 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_s1_p1: s1-p1@1f9 {
+				reg = <0x1f9 0x2>;
+				bits = <4 6>;
+			};
+
+			tsens_s1_p2: s1-p2@1fa {
+				reg = <0x1fa 0x1>;
+				bits = <2 6>;
+			};
+
+			tsens_s2_p1: s2-p1@1fb {
+				reg = <0x1fb 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s2_p2: s2-p2@1fb {
+				reg = <0x1fb 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_s3_p1: s3-p1@1fc {
+				reg = <0x1fc 0x2>;
+				bits = <4 6>;
+			};
+
+			tsens_s3_p2: s3-p2@1fd {
+				reg = <0x1fd 0x1>;
+				bits = <2 6>;
+			};
+
+			tsens_s4_p1: s4-p1@1fe {
+				reg = <0x1fe 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s4_p2: s4-p2@1fe {
+				reg = <0x1fe 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_s5_p1: s5-p1@200 {
+				reg = <0x200 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s5_p2: s5-p2@200 {
+				reg = <0x200 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_s6_p1: s6-p1@201 {
+				reg = <0x201 0x2>;
+				bits = <4 6>;
+			};
+
+			tsens_s6_p2: s6-p2@202 {
+				reg = <0x202 0x1>;
+				bits = <2 6>;
+			};
+
+			tsens_s7_p1: s7-p1@203 {
+				reg = <0x203 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s7_p2: s7-p2@203 {
+				reg = <0x203 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_s8_p1: s8-p1@204 {
+				reg = <0x204 0x2>;
+				bits = <4 6>;
+			};
+
+			tsens_s8_p2: s8-p2@205 {
+				reg = <0x205 0x1>;
+				bits = <2 6>;
+			};
+
+			tsens_s9_p1: s9-p1@206 {
+				reg = <0x206 0x1>;
+				bits = <0 6>;
+			};
+
+			tsens_s9_p2: s9-p2@206 {
+				reg = <0x206 0x2>;
+				bits = <6 6>;
+			};
+
+			tsens_mode: mode@208 {
+				reg = <0x208 1>;
+				bits = <0 3>;
+			};
+
+			tsens_base1: base1@208 {
+				reg = <0x208 2>;
+				bits = <3 8>;
+			};
+
+			tsens_base2: base2@208 {
+				reg = <0x209 2>;
+				bits = <3 8>;
+			};
+
+			cpr_efuse_quot_offset1: qoffset1@231 {
+				reg = <0x231 0x4>;
+				bits = <4 7>;
+			};
+			cpr_efuse_quot_offset2: qoffset2@232 {
+				reg = <0x232 0x4>;
+				bits = <3 7>;
+			};
+			cpr_efuse_quot_offset3: qoffset3@233 {
+				reg = <0x233 0x4>;
+				bits = <2 7>;
+			};
+			cpr_efuse_init_voltage1: ivoltage1@229 {
+				reg = <0x229 0x4>;
+				bits = <4 6>;
+			};
+			cpr_efuse_init_voltage2: ivoltage2@22a {
+				reg = <0x22a 0x4>;
+				bits = <2 6>;
+			};
+			cpr_efuse_init_voltage3: ivoltage3@22b {
+				reg = <0x22b 0x4>;
+				bits = <0 6>;
+			};
+			cpr_efuse_quot1: quot1@22b {
+				reg = <0x22b 0x4>;
+				bits = <6 12>;
+			};
+			cpr_efuse_quot2: quot2@22d {
+				reg = <0x22d 0x4>;
+				bits = <2 12>;
+			};
+			cpr_efuse_quot3: quot3@230 {
+				reg = <0x230 0x4>;
+				bits = <0 12>;
+			};
+			cpr_efuse_ring1: ring1@228 {
+				reg = <0x228 0x4>;
+				bits = <0 3>;
+			};
+			cpr_efuse_ring2: ring2@228 {
+				reg = <0x228 0x4>;
+				bits = <4 3>;
+			};
+			cpr_efuse_ring3: ring3@229 {
+				reg = <0x229 0x4>;
+				bits = <0 3>;
+			};
+			cpr_efuse_revision: revision@218 {
+				reg = <0x218 0x4>;
+				bits = <3 3>;
+			};
+		};
+
+		rng: rng@e3000 {
+			compatible = "qcom,prng-ee";
+			reg = <0x000e3000 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		bimc: interconnect@400000 {
+			reg = <0x00400000 0x80000>;
+			compatible = "qcom,qcs404-bimc";
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+				<&rpmcc RPM_SMD_BIMC_A_CLK>;
+		};
+
+		tsens: thermal-sensor@4a9000 {
+			compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
+			reg = <0x004a9000 0x1000>, /* TM */
+			      <0x004a8000 0x1000>; /* SROT */
+			nvmem-cells = <&tsens_mode>,
+				      <&tsens_base1>, <&tsens_base2>,
+				      <&tsens_s0_p1>, <&tsens_s0_p2>,
+				      <&tsens_s1_p1>, <&tsens_s1_p2>,
+				      <&tsens_s2_p1>, <&tsens_s2_p2>,
+				      <&tsens_s3_p1>, <&tsens_s3_p2>,
+				      <&tsens_s4_p1>, <&tsens_s4_p2>,
+				      <&tsens_s5_p1>, <&tsens_s5_p2>,
+				      <&tsens_s6_p1>, <&tsens_s6_p2>,
+				      <&tsens_s7_p1>, <&tsens_s7_p2>,
+				      <&tsens_s8_p1>, <&tsens_s8_p2>,
+				      <&tsens_s9_p1>, <&tsens_s9_p2>;
+			nvmem-cell-names = "mode",
+					   "base1", "base2",
+					   "s0_p1", "s0_p2",
+					   "s1_p1", "s1_p2",
+					   "s2_p1", "s2_p2",
+					   "s3_p1", "s3_p2",
+					   "s4_p1", "s4_p2",
+					   "s5_p1", "s5_p2",
+					   "s6_p1", "s6_p2",
+					   "s7_p1", "s7_p2",
+					   "s8_p1", "s8_p2",
+					   "s9_p1", "s9_p2";
+			#qcom,sensors = <10>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow";
+			#thermal-sensor-cells = <1>;
+		};
+
+		pcnoc: interconnect@500000 {
+			reg = <0x00500000 0x15080>;
+			compatible = "qcom,qcs404-pcnoc";
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+				<&rpmcc RPM_SMD_PNOC_A_CLK>;
+		};
+
+		snoc: interconnect@580000 {
+			reg = <0x00580000 0x23080>;
+			compatible = "qcom,qcs404-snoc";
+			#interconnect-cells = <1>;
+			clock-names = "bus", "bus_a";
+			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+				<&rpmcc RPM_SMD_SNOC_A_CLK>;
+		};
+
+		remoteproc_cdsp: remoteproc@b00000 {
+			compatible = "qcom,qcs404-cdsp-pas";
+			reg = <0x00b00000 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&xo_board>;
+			clock-names = "xo";
+
+			/*
+			 * If the node was using the PIL binding, then include properties:
+			 * clocks = <&xo_board>,
+			 *          <&gcc GCC_CDSP_CFG_AHB_CLK>,
+			 *          <&gcc GCC_CDSP_TBU_CLK>,
+			 *          <&gcc GCC_BIMC_CDSP_CLK>,
+			 *          <&turingcc TURING_WRAPPER_AON_CLK>,
+			 *          <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
+			 *          <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
+			 *          <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
+			 * clock-names = "xo",
+			 *               "sway",
+			 *               "tbu",
+			 *               "bimc",
+			 *               "ahb_aon",
+			 *               "q6ss_slave",
+			 *               "q6ss_master",
+			 *               "q6_axim";
+			 * resets = <&gcc GCC_CDSP_RESTART>;
+			 * reset-names = "restart";
+			 * qcom,halt-regs = <&tcsr 0x19004>;
+			 */
+
+			memory-region = <&cdsp_fw_mem>;
+
+			qcom,smem-states = <&cdsp_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+
+				qcom,remote-pid = <5>;
+				mboxes = <&apcs_glb 12>;
+
+				label = "cdsp";
+			};
+		};
+
+		usb3: usb@7678800 {
+			compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
+			reg = <0x07678800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB30_MASTER_CLK>,
+				 <&gcc GCC_SYS_NOC_USB3_CLK>,
+				 <&gcc GCC_USB30_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+			status = "disabled";
+
+			usb3_dwc3: usb@7580000 {
+				compatible = "snps,dwc3";
+				reg = <0x07580000 0xcd00>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy_prim>, <&usb3_phy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				dr_mode = "otg";
+			};
+		};
+
+		usb2: usb@79b8800 {
+			compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
+			reg = <0x079b8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
+				 <&gcc GCC_PCNOC_USB2_CLK>,
+				 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <19200000>, <133333333>;
+			status = "disabled";
+
+			usb@78c0000 {
+				compatible = "snps,dwc3";
+				reg = <0x078c0000 0xcc00>;
+				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy_sec>;
+				phy-names = "usb2-phy";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				dr_mode = "peripheral";
+			};
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,qcs404-pinctrl";
+			reg = <0x01000000 0x200000>,
+			      <0x01300000 0x200000>,
+			      <0x07b00000 0x200000>;
+			reg-names = "south", "north", "east";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-ranges = <&tlmm 0 0 120>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp1_i2c0_default: blsp1-i2c0-default-state {
+				pins = "gpio32", "gpio33";
+				function = "blsp_i2c0";
+			};
+
+			blsp1_i2c1_default: blsp1-i2c1-default-state {
+				pins = "gpio24", "gpio25";
+				function = "blsp_i2c1";
+			};
+
+			blsp1_i2c2_default: blsp1-i2c2-default-state {
+				sda-pins {
+					pins = "gpio19";
+					function = "blsp_i2c_sda_a2";
+				};
+
+				scl-pins {
+					pins = "gpio20";
+					function = "blsp_i2c_scl_a2";
+				};
+			};
+
+			blsp1_i2c3_default: blsp1-i2c3-default-state {
+				pins = "gpio84", "gpio85";
+				function = "blsp_i2c3";
+			};
+
+			blsp1_i2c4_default: blsp1-i2c4-default-state {
+				pins = "gpio117", "gpio118";
+				function = "blsp_i2c4";
+			};
+
+			blsp1_uart0_default: blsp1-uart0-default-state {
+				pins = "gpio30", "gpio31", "gpio32", "gpio33";
+				function = "blsp_uart0";
+			};
+
+			blsp1_uart1_default: blsp1-uart1-default-state {
+				pins = "gpio22", "gpio23";
+				function = "blsp_uart1";
+			};
+
+			blsp1_uart2_default: blsp1-uart2-default-state {
+				rx-pins {
+					pins = "gpio18";
+					function = "blsp_uart_rx_a2";
+				};
+
+				tx-pins {
+					pins = "gpio17";
+					function = "blsp_uart_tx_a2";
+				};
+			};
+
+			blsp1_uart3_default: blsp1-uart3-default-state {
+				cts-pins {
+					pins = "gpio84";
+					function = "blsp_uart3";
+				};
+
+				rts-tx-pins {
+					pins = "gpio85", "gpio82";
+					function = "blsp_uart3";
+				};
+
+				rx-pins {
+					pins = "gpio83";
+					function = "blsp_uart3";
+				};
+			};
+
+			blsp2_i2c0_default: blsp2-i2c0-default-state {
+				pins = "gpio28", "gpio29";
+				function = "blsp_i2c5";
+			};
+
+			blsp1_spi0_default: blsp1-spi0-default-state {
+				pins = "gpio30", "gpio31", "gpio32", "gpio33";
+				function = "blsp_spi0";
+			};
+
+			blsp1_spi1_default: blsp1-spi1-default-state {
+				mosi-pins {
+					pins = "gpio22";
+					function = "blsp_spi_mosi_a1";
+				};
+
+				miso-pins {
+					pins = "gpio23";
+					function = "blsp_spi_miso_a1";
+				};
+
+				cs-n-pins {
+					pins = "gpio24";
+					function = "blsp_spi_cs_n_a1";
+				};
+
+				clk-pins {
+					pins = "gpio25";
+					function = "blsp_spi_clk_a1";
+				};
+			};
+
+			blsp1_spi2_default: blsp1-spi2-default-state {
+				pins = "gpio17", "gpio18", "gpio19", "gpio20";
+				function = "blsp_spi2";
+			};
+
+			blsp1_spi3_default: blsp1-spi3-default-state {
+				pins = "gpio82", "gpio83", "gpio84", "gpio85";
+				function = "blsp_spi3";
+			};
+
+			blsp1_spi4_default: blsp1-spi4-default-state {
+				pins = "gpio37", "gpio38", "gpio117", "gpio118";
+				function = "blsp_spi4";
+			};
+
+			blsp2_spi0_default: blsp2-spi0-default-state {
+				pins = "gpio26", "gpio27", "gpio28", "gpio29";
+				function = "blsp_spi5";
+			};
+
+			blsp2_uart0_default: blsp2-uart0-default-state {
+				pins = "gpio26", "gpio27", "gpio28", "gpio29";
+				function = "blsp_uart5";
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-qcs404";
+			reg = <0x01800000 0x80000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <&pcie_phy>,
+				 <0>,
+				 <0>,
+				 <0>;
+
+			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
+			assigned-clock-rates = <19200000>;
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x01905000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,qcs404-tcsr", "syscon";
+			reg = <0x01937000 0x25000>;
+		};
+
+		sram@290000 {
+			compatible = "qcom,rpm-stats";
+			reg = <0x00290000 0x10000>;
+		};
+
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x800000>,
+			      <0x02c00000 0x800000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		remoteproc_wcss: remoteproc@7400000 {
+			compatible = "qcom,qcs404-wcss-pas";
+			reg = <0x07400000 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
+					      <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&xo_board>;
+			clock-names = "xo";
+
+			memory-region = <&wlan_fw_mem>;
+
+			qcom,smem-states = <&wcss_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+				qcom,remote-pid = <1>;
+				mboxes = <&apcs_glb 16>;
+
+				label = "wcss";
+			};
+		};
+
+		pcie_phy: phy@7786000 {
+			compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+			reg = <0x07786000 0xb8>;
+
+			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+			resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+				 <&gcc GCC_PCIE_0_PIPE_ARES>;
+			reset-names = "phy", "pipe";
+
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		sdcc1: mmc@7804000 {
+			compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+
+			status = "disabled";
+		};
+
+		blsp1_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x25000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "okay";
+		};
+
+		blsp1_uart0: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart0_default>;
+			status = "disabled";
+		};
+
+		blsp1_uart1: serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b0000 0x200>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart1_default>;
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b1000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b1000 0x200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			status = "okay";
+		};
+
+		ethernet: ethernet@7a80000 {
+			compatible = "qcom,qcs404-ethqos";
+			reg = <0x07a80000 0x10000>,
+				<0x07a96000 0x100>;
+			reg-names = "stmmaceth", "rgmii";
+			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+			clocks = <&gcc GCC_ETH_AXI_CLK>,
+				<&gcc GCC_ETH_SLAVE_AHB_CLK>,
+				<&gcc GCC_ETH_PTP_CLK>,
+				<&gcc GCC_ETH_RGMII_CLK>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_lpi";
+
+			snps,tso;
+			rx-fifo-depth = <4096>;
+			tx-fifo-depth = <4096>;
+
+			status = "disabled";
+		};
+
+		wifi: wifi@a000000 {
+			compatible = "qcom,wcn3990-wifi";
+			reg = <0xa000000 0x800000>;
+			reg-names = "membase";
+			memory-region = <&wlan_msa_mem>;
+			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		blsp1_uart3: serial@78b2000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b2000 0x200>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart3_default>;
+			status = "disabled";
+		};
+
+		blsp1_i2c0: i2c@78b5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_i2c0_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi0: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_spi0_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c1: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b6000 0x600>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_i2c1_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi1: spi@78b6000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b6000 0x600>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_spi1_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c2: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_i2c2_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi2: spi@78b7000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_spi2_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c3: i2c@78b8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b8000 0x600>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_i2c3_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi3: spi@78b8000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b8000 0x600>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_spi3_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c4: i2c@78b9000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b9000 0x600>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_i2c4_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi4: spi@78b9000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b9000 0x600>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_spi4_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_dma: dma-controller@7ac4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07ac4000 0x17000>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		blsp2_uart0: serial@7aef000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x07aef000 0x200>;
+			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp2_uart0_default>;
+			status = "disabled";
+		};
+
+		blsp2_i2c0: i2c@7af5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07af5000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp2_i2c0_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_spi0: spi@7af5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x07af5000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp2_spi0_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		sram@8600000 {
+			compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
+			reg = <0x08600000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0x08600000 0x1000>;
+
+			pil-reloc@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
+			};
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>,
+			      <0x0b002000 0x1000>;
+		};
+
+		apcs_glb: mailbox@b011000 {
+			compatible = "qcom,qcs404-apcs-apps-global",
+				     "qcom,msm8916-apcs-kpss-global", "syscon";
+			reg = <0x0b011000 0x1000>;
+			#mbox-cells = <1>;
+			clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
+			clock-names = "pll", "aux";
+			#clock-cells = <0>;
+		};
+
+		apcs_hfpll: clock-controller@b016000 {
+			compatible = "qcom,hfpll";
+			reg = <0x0b016000 0x30>;
+			#clock-cells = <0>;
+			clock-output-names = "apcs_hfpll";
+			clocks = <&xo_board>;
+			clock-names = "xo";
+		};
+
+		watchdog@b017000 {
+			compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
+			reg = <0x0b017000 0x1000>;
+			clocks = <&sleep_clk>;
+		};
+
+		cpr: power-controller@b018000 {
+			compatible = "qcom,qcs404-cpr", "qcom,cpr";
+			reg = <0x0b018000 0x1000>;
+			interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&xo_board>;
+			clock-names = "ref";
+			vdd-apc-supply = <&pms405_s3>;
+			#power-domain-cells = <0>;
+			operating-points-v2 = <&cpr_opp_table>;
+			acc-syscon = <&tcsr>;
+
+			nvmem-cells = <&cpr_efuse_quot_offset1>,
+				<&cpr_efuse_quot_offset2>,
+				<&cpr_efuse_quot_offset3>,
+				<&cpr_efuse_init_voltage1>,
+				<&cpr_efuse_init_voltage2>,
+				<&cpr_efuse_init_voltage3>,
+				<&cpr_efuse_quot1>,
+				<&cpr_efuse_quot2>,
+				<&cpr_efuse_quot3>,
+				<&cpr_efuse_ring1>,
+				<&cpr_efuse_ring2>,
+				<&cpr_efuse_ring3>,
+				<&cpr_efuse_revision>;
+			nvmem-cell-names = "cpr_quotient_offset1",
+				"cpr_quotient_offset2",
+				"cpr_quotient_offset3",
+				"cpr_init_voltage1",
+				"cpr_init_voltage2",
+				"cpr_init_voltage3",
+				"cpr_quotient1",
+				"cpr_quotient2",
+				"cpr_quotient3",
+				"cpr_ring_osc1",
+				"cpr_ring_osc2",
+				"cpr_ring_osc3",
+				"cpr_fuse_revision";
+		};
+
+		timer@b120000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@b121000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+			};
+
+			frame@b123000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b123000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b124000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b125000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b126000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0xb127000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b128000 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		remoteproc_adsp: remoteproc@c700000 {
+			compatible = "qcom,qcs404-adsp-pas";
+			reg = <0x0c700000 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&xo_board>;
+			clock-names = "xo";
+
+			memory-region = <&adsp_fw_mem>;
+
+			qcom,smem-states = <&adsp_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
+
+				qcom,remote-pid = <2>;
+				mboxes = <&apcs_glb 8>;
+
+				label = "adsp";
+			};
+		};
+
+		pcie: pci@10000000 {
+			compatible = "qcom,pcie-qcs404";
+			reg = <0x10000000 0xf1d>,
+			      <0x10000f20 0xa8>,
+			      <0x07780000 0x2000>,
+			      <0x10001000 0x2000>;
+			reg-names = "dbi", "elbi", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
+				 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
+
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+			clock-names = "iface", "aux", "master_bus", "slave_bus";
+
+			resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+				 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+				 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+				 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE_0_BCR>,
+				 <&gcc GCC_PCIE_0_AHB_ARES>;
+			reset-names = "axi_m",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "pipe_sticky",
+				      "pwr",
+				      "ahb";
+
+			phys = <&pcie_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 0xff08>,
+			     <GIC_PPI 3 0xff08>,
+			     <GIC_PPI 4 0xff08>,
+			     <GIC_PPI 1 0xff08>;
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 10>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 18>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		wcss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	thermal-zones {
+		aoss-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 0>;
+
+			trips {
+				aoss_alert0: trip-point0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-hvx-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 1>;
+
+			trips {
+				q6_hvx_alert0: trip-point0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		lpass-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 2>;
+
+			trips {
+				lpass_alert0: trip-point0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		wlan-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 3>;
+
+			trips {
+				wlan_alert0: trip-point0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cluster-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 4>;
+
+			trips {
+				cluster_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cluster_alert1: trip-point1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cluster_crit: cluster-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cluster_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 5>;
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu0_alert1: trip-point1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu0_crit: cpu-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 6>;
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu1_alert1: trip-point1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu1_crit: cpu-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 7>;
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu2_alert1: trip-point1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu2_crit: cpu-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 8>;
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu3_alert1: trip-point1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu3_crit: cpu-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 9>;
+
+			trips {
+				gpu_alert0: trip-point0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+	};
+};

-- 
2.43.1

[PATCH v4 39/39] MAINTAINERS: Qualcomm: add some missing paths

[Caleb Connolly]

Add drivers and DTS files, as well as regex matches for
qcom/qualcomm/snapdragon.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 MAINTAINERS | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 46ba17647f3e..8b048b1faf7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -576,18 +576,22 @@ M:	Caleb Connolly <caleb.connolly@linaro.org>
 M:	Neil Armstrong <neil.armstrong@linaro.org>
 R:	Sumit Garg <sumit.garg@linaro.org>
 S:	Maintained
-F:	arch/arm/mach-snapdragon/
-F:	drivers/button/button-qcom-pmic.c
-F:	drivers/clk/qcom/
+F:	arch/arm/dts/msm8*.dtsi
+F:	arch/arm/dts/pm8???.dtsi
+F:	arch/arm/dts/pms405.dtsi
+F:	arch/arm/dts/sdm845.dtsi
+F:	drivers/*/*/pm8???-*
 F:	drivers/gpio/msm_gpio.c
 F:	drivers/mmc/msm_sdhci.c
 F:	drivers/phy/msm8916-usbh-phy.c
-F:	drivers/pinctrl/qcom/
 F:	drivers/serial/serial_msm.c
 F:	drivers/serial/serial_msm_geni.c
 F:	drivers/smem/msm_smem.c
 F:	drivers/spmi/spmi-msm.c
 F:	drivers/usb/host/ehci-msm.c
+N:	qcom
+N:	snapdragon
+N:	qualcomm
 
 ARM STI
 M:	Patrice Chotard <patrice.chotard@foss.st.com>

-- 
2.43.1

Re: [PATCH v4 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER

[Ilias Apalodimas]

On Thu, Feb 15, 2024 at 08:52:37PM +0000, Caleb Connolly wrote:
> db820c predated support for prepending the kernel image header
> automatically, drop it's custom linker script and head.S in favour of
> this generic support.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/Kconfig          |   1 +
>  board/qualcomm/dragonboard820c/Makefile   |   1 -
>  board/qualcomm/dragonboard820c/head.S     |  33 ---------
>  board/qualcomm/dragonboard820c/u-boot.lds | 111 ------------------------------
>  4 files changed, 1 insertion(+), 145 deletions(-)
>
> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
> index ad6671081910..f897c393464f 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C
>
>  config TARGET_DRAGONBOARD820C
>  	bool "96Boards Dragonboard 820C"
> +	select LINUX_KERNEL_IMAGE_HEADER
>  	imply CLK_QCOM_APQ8096
>  	imply PINCTRL_QCOM_APQ8096
>  	imply BUTTON_QCOM_PMIC
> diff --git a/board/qualcomm/dragonboard820c/Makefile b/board/qualcomm/dragonboard820c/Makefile
> index 643311f5b3ba..2ae6d16364aa 100644
> --- a/board/qualcomm/dragonboard820c/Makefile
> +++ b/board/qualcomm/dragonboard820c/Makefile
> @@ -3,4 +3,3 @@
>  # (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
>
>  obj-y	:= dragonboard820c.o
> -extra-y += head.o
> diff --git a/board/qualcomm/dragonboard820c/head.S b/board/qualcomm/dragonboard820c/head.S
> deleted file mode 100644
> index b052a858fd32..000000000000
> --- a/board/qualcomm/dragonboard820c/head.S
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * ARM64 header for proper chain-loading with Little Kernel.
> - *
> - * Little Kernel shipped with Dragonboard820C boots standard Linux images for
> - * ARM64. This file adds header that is required to boot U-Boot properly.
> - *
> - * For details see:
> - * https://www.kernel.org/doc/Documentation/arm64/booting.txt
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - */
> -
> -#include <config.h>
> -
> -/*
> - *   per document in linux/Doc/arm64/booting.text
> - */
> -.global _arm64_header
> -_arm64_header:
> -	b _start
> -	.word 0
> -	.quad   CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
> -	.quad   0    /* Effective size of kernel image, little-endian */
> -	.quad   0    /* kernel flags, little-endian */
> -	.quad   0    /* reserved */
> -	.quad   0    /* reserved */
> -	.quad   0    /* reserved */
> -	.byte   0x41 /* Magic number, "ARM\x64" */
> -	.byte   0x52
> -	.byte   0x4d
> -	.byte   0x64
> -	.word   0    /* reserved (used for PE COFF offset) */
> diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds
> deleted file mode 100644
> index 5251b59fbe76..000000000000
> --- a/board/qualcomm/dragonboard820c/u-boot.lds
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Override linker script for fastboot-readable images
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - *
> - * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
> - */
> -
> -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
> -OUTPUT_ARCH(aarch64)
> -ENTRY(_arm64_header)
> -SECTIONS
> -{
> -	. = 0x00000000;
> -
> -	. = ALIGN(8);
> -	.text :
> -	{
> -		*(.__image_copy_start)
> -		board/qualcomm/dragonboard820c/head.o (.text*)
> -		CPUDIR/start.o (.text*)
> -	}
> -
> -	/* This needs to come before *(.text*) */
> -	.efi_runtime : {
> -                __efi_runtime_start = .;
> -		*(.text.efi_runtime*)
> -		*(.rodata.efi_runtime*)
> -		*(.data.efi_runtime*)
> -                __efi_runtime_stop = .;
> -	}
> -
> -	.text_rest :
> -	{
> -		*(.text*)
> -	}
> -
> -	. = ALIGN(8);
> -	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> -
> -	. = ALIGN(8);
> -	.data : {
> -		*(.data*)
> -	}
> -
> -	. = ALIGN(8);
> -
> -	. = .;
> -
> -	. = ALIGN(8);
> -	__u_boot_list : {
> -		KEEP(*(SORT(__u_boot_list*)));
> -	}
> -
> -	. = ALIGN(8);
> -
> -	.efi_runtime_rel : {
> -                __efi_runtime_rel_start = .;
> -		*(.rel*.efi_runtime)
> -		*(.rel*.efi_runtime.*)
> -                __efi_runtime_rel_stop = .;
> -	}
> -
> -	. = ALIGN(8);
> -
> -	.image_copy_end :
> -	{
> -		*(.__image_copy_end)
> -	}
> -
> -	. = ALIGN(8);
> -
> -	.rel_dyn_start :
> -	{
> -		*(.__rel_dyn_start)
> -	}
> -
> -	.rela.dyn : {
> -		*(.rela*)
> -	}
> -
> -	.rel_dyn_end :
> -	{
> -		*(.__rel_dyn_end)
> -	}
> -
> -	_end = .;
> -
> -	. = ALIGN(8);
> -
> -	.bss_start : {
> -		KEEP(*(.__bss_start));
> -	}
> -
> -	.bss : {
> -		*(.bss*)
> -		 . = ALIGN(8);
> -	}
> -
> -	.bss_end : {
> -		KEEP(*(.__bss_end));
> -	}
> -
> -	/DISCARD/ : { *(.dynsym) }
> -	/DISCARD/ : { *(.dynstr*) }
> -	/DISCARD/ : { *(.dynamic*) }
> -	/DISCARD/ : { *(.plt*) }
> -	/DISCARD/ : { *(.interp*) }
> -	/DISCARD/ : { *(.gnu*) }
> -}
>
> --
> 2.43.1
>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

Re: [PATCH v4 02/39] usb: dwc3-generic: support external vbus regulator

[Jonas Karlman]

On 2024-02-15 21:52, Caleb Connolly wrote:
> Add support for a vbus-supply regulator specified in devicetree. This
> provides generic support to avoid hardcoded GPIO configuration in board
> init code.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
> This patch has no dependencies
> 
> Cc: Marek Vasut <marex@denx.de>
> ---
>  drivers/usb/dwc3/dwc3-generic.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 6fb2de8a5ace..48da621ba966 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -21,6 +21,7 @@
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
>  #include <malloc.h>
> +#include <power/regulator.h>
>  #include <usb.h>
>  #include "core.h"
>  #include "gadget.h"
> @@ -47,6 +48,7 @@ struct dwc3_generic_priv {
>  struct dwc3_generic_host_priv {
>  	struct xhci_ctrl xhci_ctrl;
>  	struct dwc3_generic_priv gen_priv;
> +	struct udevice *vbus_dev;

vbus_supply may be a better name, it is a name used by other drivers.

>  };
>  
>  static int dwc3_generic_probe(struct udevice *dev,
> @@ -240,6 +242,13 @@ static int dwc3_generic_host_probe(struct udevice *dev)
>  	if (rc)
>  		return rc;
>  
> +	rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_dev);
> +	if (rc)
> +		debug("%s: No vbus regulator found: %d\n", dev->name, rc);
> +
> +	if (priv->vbus_dev)
> +		regulator_set_enable(priv->vbus_dev, true);

This should use the following form:

	rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
	if (rc && rc != -ENOSYS)
		return rc;

That should only report an error if there is an error enabling the
regulator, or -ENOSYS if regulator support has been disabled.

Because fixed and gpio regulators now are referenced counted you will
need to clean up and disable the supply if the call to xhci_register()
fails, something like following should probably work:

	rc = xhci_register(dev, hccr, hcor);
	if (rc)
		regulator_set_enable_if_allowed(priv->vbus_supply, false);

	return rc;

> +
>  	hccr = (struct xhci_hccr *)priv->gen_priv.base;
>  	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
>  			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
> @@ -256,6 +265,9 @@ static int dwc3_generic_host_remove(struct udevice *dev)
>  	if (rc)
>  		return rc;
>  
> +	if (priv->vbus_dev)
> +		regulator_set_enable(priv->vbus_dev, false);

This can safely use the following without any if check:

	regulator_set_enable_if_allowed(priv->vbus_supply, false);

Regards,
Jonas

> +
>  	return dwc3_generic_remove(dev, &priv->gen_priv);
>  }
>  
> 

Re: [PATCH v4 00/39] Qualcomm generic board support

[Sumit Garg]

Hi Caleb,

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Historically, Qualcomm boards in U-Boot have all had their own
> board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their
> own hardcoded sysmap-xyz.c file, and their own U-Boot specific
> devicetree with little/no compatibility with upstream DT.
>
> This series makes a few final prepatory changes, and then replaces
> almost all of the board specific code with generic alternatives. The end
> result is that all Qualcomm boards both current and future (with the
> exception of the db410c and db820c) can be supported by a single U-Boot
> binary by just providing the correct DT. New boards can be added without
> introducing any addition mach/ or board/ code or config options.
>
> Due to the nature of this change, the patch ("mach-snapdragon:
> generalise board support") has become pretty big, I tried a few
> different ways to represent this in git history, but the other methods
> (e.g. adding a stub "generic" target and removing it again) were more
> confusing and made for much messier git history. The current patch is
> mostly atomic, but requires regenerating the config.
>
> The QCS404 EVB board had some code to enable the USB VBUS regulator,
> this is dropped in favour of a adding a new vbus-supply property to the
> dwc3-generic driver. This will also be used by the dragonboard845c in a
> future patch. This handles the common case of a board requiring some
> regulator be enabled for USB host mode.
>
> A more detailed description of the changes is below.
>
> == Memory map ==
>
> The memory map was historically hardcoded into U-Boot, this meant that
> U-Boot had to be built for a specific variant of a device. This is
> changed to instead read the memory map from the DT /memory node.
>
> Additionally, most boards mapped addresss 0x0 as valid, as a result if a
> null pointer access happens then it will cause a bus stall (and board
> hang). This is fixed so that null pointer accesses will now correctly
> throw an exception.
>
> == DT loading ==
>
> Previously, boards used the FDT blob embedded into U-Boot (via
> OF_SEPARATE). However, most Qualcomm boards run U-Boot as a secondary
> bootloader, so we can instead rely on the first-stage bootloader to
> populate some useful FDT properties for us (notably the /memory node and
> KASLR seed) and fetch the DTB that it provides. Combined with the memory
> map changes above, this let's us entirely avoid configuring the memory
> map explicitly.
>
> == defconfig ==
>
> Most of the board defconfigs and config headers were quite similar, to
> simplify maintenance going forward, all the fully generic boards (sdm845
> and qcs404-evb so far) are adapted to use the new qcom_defconfig. Going
> forward, all new Qualcomm boards should be supported by this defconfig.
> A notable exception is for specific usecases (like U-Boot as the primary
> bootloader).
>
> == The older dragonboards ==
>
> The db410c and db820c both have some custom board init code, as a result
> they aren't yet binary compatible. mach-snapdragon is adjusted so
> that all the necessary config options (e.g. CONFIG_SYS_BOARD) can be set
> from their defconfigs, this makes it possible to enable support for new
> boards without introducing additional config options.
>
> The db410c can run U-Boot either chainloaded like the other boards, or
> as a first-stage bootloader replacing aboot. However it was hardcoded to
> only build for the latter option. This series introduces a new
> "chainloaded" defconfig to enable easier testing via fastboot.
>
> == dynamic environment variables ==
>
> This series also introduces runtime-allocated load addresses via the lmb
> allocator. This allows for booting on boards with vastly different
> memory layouts without any pre-calculation or macro magic in the config
> header. This feature is based on similar code in mach-apple.
>
> The soc, board, and fdtfile environment variables are also generated
> automatically. Many Qualcomm boards follow a similar scheme for DTB
> naming such that the name can often be derived from the root compatible
> properties. This is intended to cover the most common cases and be a
> simple solution for booting generic distro images without having to
> explicitly choose the right DTB. The U-Boot DTS can be tweaked if
> necessary to produce the correct name, the variable can be overwritten,
> or a bootloader like GRUB can load the devicetree instead.
>
> == Upstream DT ==
>
> All Qualcomm boards have had their devicetree files replaced with the
> upstream versions. Previous patch series made the necessary driver
> adjustments to fully support the upstream DT format. All future
> Qualcomm boards should use upstream DTS by default.
>
> Once Sumit's work to import dt-rebasing has been merged, we will drop
> the imported DT and bindings again.
>
> ---
> I have tested this series on the Dragonboard410c, Dragonboard820c, and
> Dragonboard845c. I unfortunately don't have access to a QCS404 EVB board
> to test.

Thanks for incorporating my feedback (on ML as well as offline) to
resolve regressions seen on db41c and qcs404.

Feel free to add following to corresponding patches:

Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404

-Sumit

>
> This series is based on the qcom-next branch [1] and depends on my PMIC
> fixes series [2], an integration branch for testing can be found at [3].
> The non-qualcomm-specific changes (patches 1 and 2) don't have any
> dependencies.
>
> [1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon
> [2]: https://lore.kernel.org/u-boot/20231114-b4-qcom-dt-compat-v3-0-88a92f8f00ba@linaro.org/
> [3]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-common-target
>
> ---
> Changes in v4:
> - Drop unreachable return in ehci_usb_of_bind()
> - Adjust error reporting in msm_sdc_clk_init() to not print ret which
>   will always be 0.
> - Simplify qcom_pmic_gpio and associated pinctrrl driver.
> - Fix the bit clock divider on QCS404 (thanks Sumit).
> - Make QCS404 pinctrl driver compatible with upstream DT.
> - Fix qcs404_clk_set_rate() return values + move some things that should
>   be in enable.
> - Optimise reserved memory carveout algorithm and fix the last regions
>   always getting skipped.
> - Adjust APQ8016 to probe the pinctrl driver pre-relocation so that UART
>   can be initialised.
> - Stub in support for special pins in the Qualcomm pinctrl driver - we
>   don't support them yet but in most cases they're already configured
>   correctly and can be safely skipped.
> - Improve readability of sdhci msm_sdc_clk_init() and use log_warning()
>   instead of printf().
> - Add missing CONFIG_SAVE_PREV_BL options to qcom_defconfig
> - Document known issue only affecting qcs404 where in the msm_sdhci driver
>   the xo_board clock somehow becomes associated with the qcom_clock device
>   resulting in qcs404_clk_set_rate() being called for clock id 0. This
>   doesn't seem to cause any issues but has proven somewhat elusive to debug.
> - Add a link to the APQ8016 TRM in doc/board/qualcomm/dragonboard410c.rst
> - Link to v3: https://lore.kernel.org/r/20240130-b4-qcom-common-target-v3-0-e523cbf9e556@linaro.org
>
> Changes in v3:
> - Remove dragonboard410c.dts file
> - Introduce generic board_usb_init() function.
> - Remove db410c specific dead code (smem RAM layout)
> - Fix pinctrl DT compatibility for msm8916/msm8996
> - Reference git tag where DT and headers were taken from Linux.
> - Adjust ramdisk allocation size to 128M
> - Improve documentation wording, reference buildman
> - Fix mapping for reserved regions to avoid speculative pre-fetching
> - Apply quicksort to memory banks read from DT to ensure ordering
> - Link to v2: https://lore.kernel.org/r/20231219-b4-qcom-common-target-v2-0-b6dd9704219e@linaro.org
>
> Changes in v2:
> - Split DTS changes to reduce patch size.
> - Import full board DTS files from Linux too, and introduce -u-boot.dtsi
>   files where necessary to make any U-Boot specific changes.
> - Add a pinctrl driver for qcom PMIC GPIOs
> - Always enable LINUX_KERNEL_IMAGE_HEADER
> - Link to v1: https://lore.kernel.org/r/20231121-b4-qcom-common-target-v1-0-9492198e0c15@linaro.org
>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Sumit Garg <sumit.garg@linaro.org>
> To: Ramon Fried <rfried.dev@gmail.com>
> Cc: Marek Vasut <marex@denx.de>
> To: Dzmitry Sankouski <dsankouski@gmail.com>
> To: Caleb Connolly <caleb.connolly@linaro.org>
> To: Peng Fan <peng.fan@nxp.com>
> To: Jaehoon Chung <jh80.chung@samsung.com>
> To: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
> To: Lukasz Majewski <lukma@denx.de>
> To: Sean Anderson <seanga2@gmail.com>
> To: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
> To: Stephan Gerhold <stephan@gerhold.net>
> Cc:  <u-boot@lists.denx.de>
>
> ---
> Caleb Connolly (39):
>       arm: init: export prev_bl_fdt_addr
>       usb: dwc3-generic: support external vbus regulator
>       mmc: msm_sdhci: use modern clock handling
>       dt-bindings: drop msm_sdhci binding
>       clk/qcom: use upstream compatible properties
>       clock/qcom: qcs404: fix clk_set_rate
>       serial: msm: add debug UART
>       serial: msm: fix clock handling and pinctrl
>       gpio: qcom_pmic: 1-based GPIOs
>       gpio: qcom_pmic: add a quirk to skip GPIO configuration
>       gpio: qcom_pmic: add pinctrl driver
>       sandbox: dts: fix qcom pmic gpio
>       pinctrl: qcom: stub support for special GPIOs
>       pinctrl: qcom: fix DT compatibility
>       pinctrl: qcom: apq8016: init pre-reloaction
>       board: dragonboard410c: add chainloaded config fragment
>       board: dragonboard410c: upstream DT compat
>       board: dragonboard410c: import board code from mach-snapdragon
>       board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER
>       mach-snapdragon: generalise board support
>       mach-snapdragon: dynamic load addresses
>       mach-snapdragon: generate fdtfile automatically
>       mach-snapdragon: carve out no-map regions
>       board: qcs404-evb: drop board code
>       doc: board/qualcomm: document generic targets
>       doc: board/qualcomm: link to APQ8016 TRM
>       dt-bindings: import headers for SDM845
>       dts: sdm845: import supporting dtsi files
>       dts: sdm845: replace with upstream DTS
>       dt-bindings: import headers for MSM8916
>       dts: msm8916: import PMIC dtsi files
>       dts: msm8916: replace with upstream DTS
>       dt-bindings: import headers for MSM8996
>       dts: msm8996: import PMIC dtsi files
>       dts: dragonboard820c: use correct bindings for clocks
>       dts: msm8996: replace with upstream DTS
>       dt-bindings: import headers for qcs404
>       dts: qcs404-evb: replace with upstream DT
>       MAINTAINERS: Qualcomm: add some missing paths
>
>  MAINTAINERS                                        |   12 +-
>  arch/arm/Kconfig                                   |    4 +
>  arch/arm/dts/Makefile                              |    9 +-
>  arch/arm/dts/apq8016-sbc-u-boot.dtsi               |   20 +
>  arch/arm/dts/apq8016-sbc.dts                       |  729 +++
>  arch/arm/dts/apq8096-db820c-u-boot.dtsi            |   14 +
>  arch/arm/dts/apq8096-db820c.dts                    | 1137 ++++
>  arch/arm/dts/dragonboard410c-uboot.dtsi            |   44 -
>  arch/arm/dts/dragonboard410c.dts                   |  209 -
>  arch/arm/dts/dragonboard820c-uboot.dtsi            |   32 -
>  arch/arm/dts/dragonboard820c.dts                   |  151 -
>  arch/arm/dts/dragonboard845c-uboot.dtsi            |   26 -
>  arch/arm/dts/dragonboard845c.dts                   |   48 -
>  arch/arm/dts/msm8916-pm8916.dtsi                   |  157 +
>  arch/arm/dts/msm8916.dtsi                          | 2702 +++++++++
>  arch/arm/dts/msm8996.dtsi                          | 3884 +++++++++++++
>  arch/arm/dts/pm8916.dtsi                           |  178 +
>  arch/arm/dts/pm8994.dtsi                           |  152 +
>  arch/arm/dts/pm8998.dtsi                           |  130 +
>  arch/arm/dts/pmi8994.dtsi                          |   65 +
>  arch/arm/dts/pmi8998.dtsi                          |   98 +
>  arch/arm/dts/pms405.dtsi                           |  149 +
>  arch/arm/dts/qcs404-evb-4000-u-boot.dtsi           |   48 +
>  arch/arm/dts/qcs404-evb-4000.dts                   |   96 +
>  arch/arm/dts/qcs404-evb-uboot.dtsi                 |   30 -
>  arch/arm/dts/qcs404-evb.dts                        |  390 --
>  arch/arm/dts/qcs404-evb.dtsi                       |  389 ++
>  arch/arm/dts/qcs404.dtsi                           | 1829 ++++++
>  arch/arm/dts/sdm845-db845c.dts                     | 1190 ++++
>  .../arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi |   16 +
>  arch/arm/dts/sdm845-samsung-starqltechn.dts        |  460 ++
>  arch/arm/dts/sdm845-wcd9340.dtsi                   |   86 +
>  arch/arm/dts/sdm845.dtsi                           | 5801 +++++++++++++++++++-
>  arch/arm/dts/starqltechn-uboot.dtsi                |   27 -
>  arch/arm/dts/starqltechn.dts                       |   68 -
>  arch/arm/lib/save_prev_bl_data.c                   |    5 +
>  arch/arm/mach-snapdragon/Kconfig                   |   95 +-
>  arch/arm/mach-snapdragon/Makefile                  |    8 +-
>  arch/arm/mach-snapdragon/board.c                   |  468 ++
>  arch/arm/mach-snapdragon/dram.c                    |   99 -
>  arch/arm/mach-snapdragon/include/mach/dram.h       |   12 -
>  arch/arm/mach-snapdragon/include/mach/gpio.h       |    2 +
>  arch/arm/mach-snapdragon/include/mach/misc.h       |   13 -
>  arch/arm/mach-snapdragon/init_sdm845.c             |   73 -
>  arch/arm/mach-snapdragon/misc.c                    |   55 -
>  arch/arm/mach-snapdragon/sysmap-apq8016.c          |   31 -
>  arch/arm/mach-snapdragon/sysmap-apq8096.c          |   31 -
>  arch/arm/mach-snapdragon/sysmap-qcs404.c           |   43 -
>  arch/arm/mach-snapdragon/sysmap-sdm845.c           |   31 -
>  arch/sandbox/dts/sandbox.dtsi                      |    9 +-
>  board/qualcomm/dragonboard410c/Kconfig             |   15 -
>  board/qualcomm/dragonboard410c/Makefile            |    2 +-
>  .../dragonboard410c/configs/chainloaded.config     |    7 +
>  board/qualcomm/dragonboard410c/dragonboard410c.c   |  130 +-
>  board/qualcomm/dragonboard820c/Kconfig             |   15 -
>  board/qualcomm/dragonboard820c/Makefile            |    1 -
>  board/qualcomm/dragonboard820c/dragonboard820c.c   |   39 +-
>  board/qualcomm/dragonboard820c/head.S              |   33 -
>  board/qualcomm/dragonboard820c/u-boot.lds          |  111 -
>  board/qualcomm/dragonboard845c/Kconfig             |   12 -
>  board/qualcomm/qcs404-evb/Kconfig                  |   15 -
>  board/qualcomm/qcs404-evb/Makefile                 |    6 -
>  board/qualcomm/qcs404-evb/qcs404-evb.c             |   62 -
>  configs/dragonboard410c_defconfig                  |    8 +-
>  configs/dragonboard820c_defconfig                  |    8 +-
>  configs/dragonboard845c_defconfig                  |   29 -
>  configs/qcom_defconfig                             |   67 +
>  configs/qcs404evb_defconfig                        |   55 -
>  configs/starqltechn_defconfig                      |   41 -
>  doc/board/qualcomm/board.rst                       |  125 +
>  doc/board/qualcomm/debugging.rst                   |   61 +
>  doc/board/qualcomm/dragonboard410c.rst             |    2 +
>  doc/board/qualcomm/index.rst                       |    4 +-
>  doc/board/qualcomm/qcs404.rst                      |   79 -
>  doc/board/qualcomm/sdm845.rst                      |  167 -
>  doc/device-tree-bindings/mmc/msm_sdhci.txt         |   25 -
>  doc/device-tree-bindings/usb/ehci-msm.txt          |   10 -
>  drivers/clk/qcom/clock-apq8016.c                   |    9 +-
>  drivers/clk/qcom/clock-apq8096.c                   |    7 +-
>  drivers/clk/qcom/clock-qcs404.c                    |   25 +-
>  drivers/gpio/msm_gpio.c                            |   20 +
>  drivers/gpio/qcom_pmic_gpio.c                      |  275 +-
>  drivers/mmc/msm_sdhci.c                            |   69 +-
>  drivers/phy/qcom/msm8916-usbh-phy.c                |    4 +-
>  drivers/pinctrl/qcom/pinctrl-apq8016.c             |   29 +-
>  drivers/pinctrl/qcom/pinctrl-apq8096.c             |   16 +-
>  drivers/pinctrl/qcom/pinctrl-qcom.c                |   12 +
>  drivers/pinctrl/qcom/pinctrl-qcs404.c              |   58 +-
>  drivers/serial/Kconfig                             |    8 +
>  drivers/serial/serial_msm.c                        |   62 +-
>  drivers/usb/dwc3/dwc3-generic.c                    |   12 +
>  drivers/usb/host/ehci-msm.c                        |   22 +-
>  include/configs/dragonboard845c.h                  |   20 -
>  include/configs/qcom.h                             |   21 +
>  include/configs/qcs404-evb.h                       |   20 -
>  include/configs/sdm845.h                           |   26 -
>  include/dt-bindings/arm/coresight-cti-dt.h         |   37 +
>  include/dt-bindings/clock/qcom,camcc-sdm845.h      |  116 +
>  include/dt-bindings/clock/qcom,dispcc-sdm845.h     |   56 +
>  include/dt-bindings/clock/qcom,gcc-msm8916.h       |  179 +
>  include/dt-bindings/clock/qcom,gcc-msm8996.h       |  362 ++
>  include/dt-bindings/clock/qcom,gpucc-sdm845.h      |   24 +
>  include/dt-bindings/clock/qcom,lpass-sdm845.h      |   15 +
>  include/dt-bindings/clock/qcom,mmcc-msm8996.h      |  295 +
>  include/dt-bindings/clock/qcom,rpmcc.h             |  174 +
>  include/dt-bindings/clock/qcom,rpmh.h              |   37 +
>  include/dt-bindings/clock/qcom,turingcc-qcs404.h   |   15 +
>  include/dt-bindings/clock/qcom,videocc-sdm845.h    |   35 +
>  include/dt-bindings/dma/qcom-gpi.h                 |   11 +
>  include/dt-bindings/firmware/qcom,scm.h            |   39 +
>  include/dt-bindings/iio/qcom,spmi-vadc.h           |  300 +
>  include/dt-bindings/interconnect/qcom,msm8916.h    |  100 +
>  .../dt-bindings/interconnect/qcom,msm8996-cbf.h    |   12 +
>  include/dt-bindings/interconnect/qcom,msm8996.h    |  163 +
>  include/dt-bindings/interconnect/qcom,osm-l3.h     |   15 +
>  include/dt-bindings/interconnect/qcom,sdm845.h     |  150 +
>  include/dt-bindings/phy/phy-qcom-qmp.h             |   20 +
>  include/dt-bindings/phy/phy-qcom-qusb2.h           |   37 +
>  include/dt-bindings/pinctrl/qcom,pmic-gpio.h       |  164 +
>  include/dt-bindings/pinctrl/qcom,pmic-mpp.h        |  106 +
>  include/dt-bindings/power/qcom-rpmpd.h             |  412 ++
>  .../dt-bindings/regulator/qcom,rpmh-regulator.h    |   36 +
>  include/dt-bindings/reset/qcom,gcc-msm8916.h       |  100 +
>  include/dt-bindings/reset/qcom,sdm845-aoss.h       |   17 +
>  include/dt-bindings/reset/qcom,sdm845-pdc.h        |   22 +
>  include/dt-bindings/soc/qcom,apr.h                 |   28 +
>  include/dt-bindings/soc/qcom,rpmh-rsc.h            |   14 +
>  include/dt-bindings/sound/apq8016-lpass.h          |    9 +
>  include/dt-bindings/sound/qcom,lpass.h             |   46 +
>  include/dt-bindings/sound/qcom,q6afe.h             |    9 +
>  include/dt-bindings/sound/qcom,q6asm.h             |   26 +
>  include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h |  234 +
>  include/dt-bindings/sound/qcom,wcd9335.h           |   15 +
>  include/init.h                                     |   11 +
>  134 files changed, 23997 insertions(+), 2643 deletions(-)
> ---
> base-commit: 22f391e8be11986bae824509470cf11e7bac31b0
>
> // Caleb (they/them)
>

Re: [PATCH v4 06/39] clock/qcom: qcs404: fix clk_set_rate

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> We should be returning the rate that we set the clock to, drivers like
> MMC rely on this. So fix it.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/clk/qcom/clock-qcs404.c | 25 +++++++++++++------------
>   1 file changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
> index f5b352803927..958312b88842 100644
> --- a/drivers/clk/qcom/clock-qcs404.c
> +++ b/drivers/clk/qcom/clock-qcs404.c
> @@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
>   
>   	switch (clk->id) {
>   	case GCC_BLSP1_UART2_APPS_CLK:
> -		/* UART: 115200 */
> +		/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
>   		clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
>   				     CFG_CLK_SRC_CXO, 16);
>   		clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
> -		break;
> -	case GCC_BLSP1_AHB_CLK:
> -		clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
> -		break;
> +		return 1843200;
>   	case GCC_SDCC1_APPS_CLK:
>   		/* SDCC1: 200MHz */
>   		clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
>   				     CFG_CLK_SRC_GPLL0, 8);
>   		clk_enable_gpll0(priv->base, &gpll0_vote_clk);
>   		clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
> -		break;
> -	case GCC_SDCC1_AHB_CLK:
> -		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
> -		break;
> +		return rate;
>   	case GCC_ETH_RGMII_CLK:
>   		if (rate == 250000000)
>   			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
> @@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
>   		else if (rate == 5000000)
>   			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
>   					     CFG_CLK_SRC_GPLL1, 8);
> -		break;
> -	default:
> -		return 0;
> +		return rate;
>   	}
>   
> +	/* There is a bug only seeming to affect this board where the MMC driver somehow calls
> +	 * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
> +	 * The only clock with ID 0 is the xo_board clock which should not be associated with
> +	 * this device...
> +	 */
> +	log_debug("Unknown clock id %ld\n", clk->id);
>   	return 0;
>   }
>   
> @@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
>   		clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
>   				 CFG_CLK_SRC_CXO);
>   		break;
> +	case GCC_SDCC1_AHB_CLK:
> +		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
> +		break;
>   	default:
>   		return 0;
>   	}
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 07/39] serial: msm: add debug UART

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Introduce support for early debugging. This relies on the previous stage
> bootloader to initialise the UART clocks, when running with U-Boot as
> the primary bootloader this feature doesn't work. It will require a way
> to configure the clocks before the driver model is available.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/serial/Kconfig      |  8 ++++++++
>   drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++
>   2 files changed, 45 insertions(+)
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 26460c4e0cab..fbd351a47859 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -319,6 +319,14 @@ config DEBUG_UART_S5P
>   	  will need to provide parameters to make this work. The driver will
>   	  be available until the real driver-model serial is running.
>   
> +config DEBUG_UART_MSM
> +	bool "Qualcomm QUP UART debug"
> +	depends on ARCH_SNAPDRAGON
> +	help
> +	  Select this to enable a debug UART using the serial_msm driver. You
> +	  will need to provide parameters to make this work. The driver will
> +	  be available until the real driver-model serial is running.
> +
>   config DEBUG_UART_MSM_GENI
>   	bool "Qualcomm snapdragon"
>   	depends on ARCH_SNAPDRAGON
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index f4d96313b931..44b93bd7ff21 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = {
>   	.probe = msm_serial_probe,
>   	.ops	= &msm_serial_ops,
>   };
> +
> +#ifdef CONFIG_DEBUG_UART_MSM
> +
> +static struct msm_serial_data init_serial_data = {
> +	.base = CONFIG_VAL(DEBUG_UART_BASE),
> +	.clk_rate = 7372800,
> +};
> +
> +#include <debug_uart.h>
> +
> +/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
> +//int apq8016_clk_init_uart(phys_addr_t gcc_base);
> +
> +static inline void _debug_uart_init(void)
> +{
> +	/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
> +	//apq8016_clk_init_uart(0x1800000);
> +	uart_dm_init(&init_serial_data);
> +}
> +
> +static inline void _debug_uart_putc(int ch)
> +{
> +	struct msm_serial_data *priv = &init_serial_data;
> +
> +	while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
> +	       !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
> +		;
> +
> +	writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
> +
> +	writel(1, priv->base + UARTDM_NCF_TX);
> +	writel(ch, priv->base + UARTDM_TF);
> +}
> +
> +DEBUG_UART_FUNCS
> +
> +#endif
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 08/39] serial: msm: fix clock handling and pinctrl

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Use the modern helpers to fetch the clock and use the correct property
> ("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
> as no boards have a "uart" pinctrl state and this prints confusing
> errors.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   arch/arm/dts/dragonboard410c.dts |  3 ++-
>   arch/arm/dts/dragonboard820c.dts |  3 ++-
>   drivers/serial/serial_msm.c      | 25 +++++--------------------
>   3 files changed, 9 insertions(+), 22 deletions(-)
> 
> diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
> index 02c824d0226c..c395e6cc0427 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -84,7 +84,8 @@
>   		serial@78b0000 {
>   			compatible = "qcom,msm-uartdm-v1.4";
>   			reg = <0x78b0000 0x200>;
> -			clock = <&clkc 4>;
> +			clocks = <&clkc 4>;
> +			clock-names = "core";
>   			pinctrl-names = "uart";
>   			pinctrl-0 = <&blsp1_uart>;
>   		};
> diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
> index 146a0af8aafe..86b7f83d36d6 100644
> --- a/arch/arm/dts/dragonboard820c.dts
> +++ b/arch/arm/dts/dragonboard820c.dts
> @@ -78,7 +78,8 @@
>   		blsp2_uart2: serial@75b0000 {
>   			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>   			reg = <0x75b0000 0x1000>;
> -			clock = <&gcc 4>;
> +			clocks = <&gcc 4>;
> +			clock-names = "core";
>   			pinctrl-names = "uart";
>   			pinctrl-0 = <&blsp8_uart>;
>   		};
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index 44b93bd7ff21..ac4280c6c4c2 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev)
>   {
>   	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
>   					"clock-frequency", 115200);
> -	uint clkd[2]; /* clk_id and clk_no */
> -	int clk_offset;
> -	struct udevice *clk_dev;
>   	struct clk clk;
>   	int ret;
>   
> -	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
> -				   clkd, 2);
> -	if (ret)
> -		return ret;
> -
> -	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -	if (clk_offset < 0)
> -		return clk_offset;
> -
> -	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -	if (ret)
> -		return ret;
> -
> -	clk.id = clkd[1];
> -	ret = clk_request(clk_dev, &clk);
> -	if (ret < 0)
> +	ret = clk_get_by_name(dev, "core", &clk);
> +	if (ret < 0) {
> +		pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
>   		return ret;
> +	}
>   
>   	ret = clk_set_rate(&clk, clk_rate);
>   	if (ret < 0)
> @@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev)
>   	if (ret)
>   		return ret;
>   
> -	pinctrl_select_state(dev, "uart");
>   	uart_dm_init(priv);
>   
>   	return 0;
> @@ -251,6 +235,7 @@ U_BOOT_DRIVER(serial_msm) = {
>   	.priv_auto	= sizeof(struct msm_serial_data),
>   	.probe = msm_serial_probe,
>   	.ops	= &msm_serial_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
>   };
>   
>   #ifdef CONFIG_DEBUG_UART_MSM
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 12/39] sandbox: dts: fix qcom pmic gpio

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Adjust the DT to match upstream bindings.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   arch/sandbox/dts/sandbox.dtsi | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
> index 241f397ba6e7..c93ce7128942 100644
> --- a/arch/sandbox/dts/sandbox.dtsi
> +++ b/arch/sandbox/dts/sandbox.dtsi
> @@ -419,17 +419,16 @@
>   		#size-cells = <0x1>;
>   		pm8916@0 {
>   			compatible = "qcom,spmi-pmic";
> -			reg = <0x0 0x1>;
> +			reg = <0x0 0x0>;
>   			#address-cells = <0x1>;
> -			#size-cells = <0x1>;
> +			#size-cells = <0x0>;
>   
>   			spmi_gpios: gpios@c000 {
>   				compatible = "qcom,pm8916-gpio";
> -				reg = <0xc000 0x400>;
> +				reg = <0xc000>;
>   				gpio-controller;
> -				gpio-count = <4>;
> +				gpio-ranges = <&spmi_gpios 0 0 4>;
>   				#gpio-cells = <2>;
> -				gpio-bank-name="spmi";
>   			};
>   		};
>   	};
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 15/39] pinctrl: qcom: apq8016: init pre-reloaction

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> On the DB410c we support running as a first stage bootloader. This
> requires initialising the GPIOs which are muxed to UART before they can
> be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
> that we do this early enough.
> 
> This is required to prevent the first few lines of UART log from being
> dropped.
> 
> Reported-by: Sumit Garg <sumit.garg@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index 10796710ba7a..df5bd1c19f6e 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -73,4 +73,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
>   	.of_match	= msm_pinctrl_ids,
>   	.ops		= &msm_pinctrl_ops,
>   	.bind		= msm_pinctrl_bind,
> +	.flags		= DM_FLAG_PRE_RELOC,
>   };
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 14/39] pinctrl: qcom: fix DT compatibility

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
> for SoCs where we're now using upstream DT.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/pinctrl/qcom/pinctrl-apq8016.c | 26 +++++++--------
>   drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +++++-----
>   drivers/pinctrl/qcom/pinctrl-qcs404.c  | 58 ++++++++++++++++++++++++++++------
>   3 files changed, 69 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index 8149ffd83cc4..10796710ba7a 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -14,18 +14,18 @@
>   #define MAX_PIN_NAME_LEN 32
>   static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>   static const char * const msm_pinctrl_pins[] = {
> -	"SDC1_CLK",
> -	"SDC1_CMD",
> -	"SDC1_DATA",
> -	"SDC2_CLK",
> -	"SDC2_CMD",
> -	"SDC2_DATA",
> -	"QDSD_CLK",
> -	"QDSD_CMD",
> -	"QDSD_DATA0",
> -	"QDSD_DATA1",
> -	"QDSD_DATA2",
> -	"QDSD_DATA3",
> +	"sdc1_clk",
> +	"sdc1_cmd",
> +	"sdc1_data",
> +	"sdc2_clk",
> +	"sdc2_cmd",
> +	"sdc2_data",
> +	"qdsd_clk",
> +	"qdsd_cmd",
> +	"qdsd_data0",
> +	"qdsd_data1",
> +	"qdsd_data2",
> +	"qdsd_data3",
>   };
>   
>   static const struct pinctrl_function msm_pinctrl_functions[] = {
> @@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
>   					unsigned int selector)
>   {
>   	if (selector < 122) {
> -		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>   		return pin_name;
>   	} else {
>   		return msm_pinctrl_pins[selector - 122];
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> index d64ab1ff7bee..f2eeb4cf469a 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> @@ -14,13 +14,13 @@
>   #define MAX_PIN_NAME_LEN 32
>   static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>   static const char * const msm_pinctrl_pins[] = {
> -	"SDC1_CLK",
> -	"SDC1_CMD",
> -	"SDC1_DATA",
> -	"SDC2_CLK",
> -	"SDC2_CMD",
> -	"SDC2_DATA",
> -	"SDC1_RCLK",
> +	"sdc1_clk",
> +	"sdc1_cmd",
> +	"sdc1_data",
> +	"sdc2_clk",
> +	"sdc2_cmd",
> +	"sdc2_data",
> +	"sdc1_rclk",
>   };
>   
>   static const struct pinctrl_function msm_pinctrl_functions[] = {
> @@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
>   					unsigned int selector)
>   {
>   	if (selector < 150) {
> -		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>   		return pin_name;
>   	} else {
>   		return msm_pinctrl_pins[selector - 150];
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> index ac00afa2a1f4..5066f2bba6b3 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> @@ -10,20 +10,24 @@
>   
>   #include "pinctrl-qcom.h"
>   
> +#define NORTH	0x00300000
> +#define SOUTH	0x00000000
> +#define EAST	0x06b00000
> +
>   #define MAX_PIN_NAME_LEN 32
>   static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>   static const char * const msm_pinctrl_pins[] = {
> -	"SDC1_RCLK",
> -	"SDC1_CLK",
> -	"SDC1_CMD",
> -	"SDC1_DATA",
> -	"SDC2_CLK",
> -	"SDC2_CMD",
> -	"SDC2_DATA",
> +	"sdc1_rclk",
> +	"sdc1_clk",
> +	"sdc1_cmd",
> +	"sdc1_data",
> +	"sdc2_clk",
> +	"sdc2_cmd",
> +	"sdc2_data",
>   };
>   
>   static const struct pinctrl_function msm_pinctrl_functions[] = {
> -	{"blsp_uart2", 1},
> +	{"gpio", 0},
>   	{"rgmii_int", 1},
>   	{"rgmii_ck", 1},
>   	{"rgmii_tx", 1},
> @@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
>   	{"blsp_i2c_scl_a2", 3},
>   	{"blsp_i2c3", 2},
>   	{"blsp_i2c4", 1},
> +	{"blsp_uart_tx_a2", 1},
> +	{"blsp_uart_rx_a2", 1},
> +};
> +
> +static const unsigned int qcs404_pin_offsets[] = {
> +	[0] = SOUTH,    [1] = SOUTH,    [2] = SOUTH,    [3] = SOUTH,    [4] = SOUTH,
> +	[5] = SOUTH,   [6] = SOUTH,   [7] = SOUTH,   [8] = SOUTH,    [9] = SOUTH,
> +	[10] = SOUTH,   [11] = SOUTH,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
> +	[15] = SOUTH,  [16] = SOUTH,  [17] = NORTH,  [18] = NORTH,  [19] = NORTH,
> +	[20] = NORTH,  [21] = SOUTH,  [22] = NORTH,  [23] = NORTH,  [24] = NORTH,
> +	[25] = NORTH,  [26] = EAST,  [27] = EAST,   [28] = EAST,   [29] = EAST,
> +	[30] = NORTH,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = SOUTH,
> +	[35] = SOUTH,  [36] = NORTH,  [37] = NORTH,  [38] = NORTH,  [39] = EAST,
> +	[40] = EAST,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
> +	[45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = EAST,
> +	[50] = EAST,  [51] = EAST,  [52] = EAST,  [53] = EAST,  [54] = EAST,
> +	[55] = EAST,  [56] = EAST,  [57] = EAST,  [58] = EAST,  [59] = EAST,
> +	[60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
> +	[65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = NORTH,
> +	[70] = NORTH,   [71] = NORTH,   [72] = NORTH,   [73] = NORTH,   [74] = NORTH,
> +	[75] = NORTH,   [76] = NORTH,   [77] = NORTH,   [78] = EAST,   [79] = EAST,
> +	[80] = EAST,  [81] = EAST,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
> +	[85] = NORTH,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = EAST,
> +	[90] = EAST,  [91] = EAST,  [92] = EAST,  [93] = EAST,  [94] = EAST,
> +	[95] = EAST,  [96] = EAST,  [97] = EAST,  [98] = EAST,  [99] = EAST,
> +	[100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST,
> +	[105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST,
> +	[110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST,
> +	[115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST,
> +	/*
> +	 * There's 126 pins but the last ones are special and have non-standard registers
> +	 * so we leave them out here. The pinctrl and GPIO drivers both currently ignore
> +	 * these pins.
> +	 */
>   };
>   
>   static const char *qcs404_get_function_name(struct udevice *dev,
> @@ -49,7 +87,7 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
>   				       unsigned int selector)
>   {
>   	if (selector < 120) {
> -		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>   		return pin_name;
>   	} else {
>   		return msm_pinctrl_pins[selector - 120];
> @@ -62,7 +100,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector)
>   }
>   
>   static struct msm_pinctrl_data qcs404_data = {
> -	.pin_data = { .pin_count = 126, },
> +	.pin_data = { .pin_count = 126, .pin_offsets = qcs404_pin_offsets, .special_pins_start = 120, },
>   	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
>   	.get_function_name = qcs404_get_function_name,
>   	.get_function_mux = qcs404_get_function_mux,
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 13/39] pinctrl: qcom: stub support for special GPIOs

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Most platforms have a handful of "special" GPIOs, like the MMC
> clock/data lanes, UFS reset, etc. These don't follow the usually naming
> scheme of "gpioX" and also have unique capabilities and registers. We
> can get away without supporting them all for now, but DT compatibility
> is still an issue.
> 
> Add support for allowing these to be specified after the other pins, and
> make all pinmux/pinconf calls for them nop.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   arch/arm/mach-snapdragon/include/mach/gpio.h |  2 ++
>   drivers/gpio/msm_gpio.c                      | 20 ++++++++++++++++++++
>   drivers/pinctrl/qcom/pinctrl-qcom.c          | 12 ++++++++++++
>   3 files changed, 34 insertions(+)
> 
> diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
> index 8dac62f870b9..c373f5a4cf3d 100644
> --- a/arch/arm/mach-snapdragon/include/mach/gpio.h
> +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
> @@ -13,6 +13,8 @@
>   struct msm_pin_data {
>   	int pin_count;
>   	const unsigned int *pin_offsets;
> +	/* Index of first special pin, these are ignored for now */
> +	unsigned int special_pins_start;
>   };
>   
>   static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> index 80cd28bb231f..8a5e8730e911 100644
> --- a/drivers/gpio/msm_gpio.c
> +++ b/drivers/gpio/msm_gpio.c
> @@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
>   {
>   	struct msm_gpio_bank *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (gpio >= priv->pin_data->special_pins_start)
> +		return 0;
> +
>   	/* Disable OE bit */
>   	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
>   			GPIO_OE_MASK, GPIO_OE_DISABLE);
> @@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
>   {
>   	struct msm_gpio_bank *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (gpio >= priv->pin_data->special_pins_start)
> +		return 0;
> +
>   	value = !!value;
>   	/* set value */
>   	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
> @@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
>   {
>   	struct msm_gpio_bank *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (gpio >= priv->pin_data->special_pins_start)
> +		return 0;
> +
>   	value = !!value;
>   	/* set value */
>   	writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
> @@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
>   {
>   	struct msm_gpio_bank *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (gpio >= priv->pin_data->special_pins_start)
> +		return 0;
> +
>   	return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
>   }
>   
> @@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
>   {
>   	struct msm_gpio_bank *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (gpio >= priv->pin_data->special_pins_start)
> +		return 0;
> +
>   	if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
>   		return GPIOF_OUTPUT;
>   
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
> index dc3d8c4d9034..1ea4d21c41fc 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
> @@ -83,6 +83,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
>   {
>   	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins, assume they're in the correct state */
> +	if (pin_selector >= priv->data->pin_data.special_pins_start)
> +		return 0;
> +
>   	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
>   			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
>   			priv->data->get_function_mux(func_selector) << 2);
> @@ -94,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
>   {
>   	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
>   
> +	/* Always NOP for special pins */
> +	if (pin_selector >= priv->data->pin_data.special_pins_start)
> +		return 0;
> +
>   	switch (param) {
>   	case PIN_CONFIG_DRIVE_STRENGTH:
>   		argument = (argument / 2) - 1;
> @@ -136,6 +144,10 @@ int msm_pinctrl_bind(struct udevice *dev)
>   	const char *name;
>   	int ret;
>   
> +	/* Make sure we don't indadvertently treat all pins as special pins. */
> +	if (!data->pin_data.special_pins_start)
> +		data->pin_data.special_pins_start = data->pin_data.pin_count;
> +
>   	drv = lists_driver_lookup_name("pinctrl_qcom");
>   	if (!drv)
>   		return -ENOENT;
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 21/39] mach-snapdragon: dynamic load addresses

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Heavily inspired by Apple board code. Use the LMB allocator to configure
> load addresses at runtime, and implement a lookup table for selecting a
> devicetree.
> 
> As some Qualcomm RBx boards have different RAM capacities and base
> addresses, it isn't possible to hardcode these regions.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   arch/arm/Kconfig                                 |  1 +
>   arch/arm/mach-snapdragon/board.c                 | 34 ++++++++++++++++++++++++
>   board/qualcomm/dragonboard410c/dragonboard410c.c |  2 +-
>   3 files changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 672577d0ddcc..0dba77f86b49 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1095,6 +1095,7 @@ config ARCH_SNAPDRAGON
>   	select OF_SEPARATE
>   	select SMEM
>   	select SPMI
> +	select BOARD_LATE_INIT
>   	select OF_BOARD
>   	select SAVE_PREV_BL_FDT_ADDR
>   	select LINUX_KERNEL_IMAGE_HEADER
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index a1867852bcca..f445bed3af00 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -22,6 +22,7 @@
>   #include <linux/bug.h>
>   #include <linux/psci.h>
>   #include <linux/sizes.h>
> +#include <lmb.h>
>   #include <malloc.h>
>   #include <usb.h>
>   
> @@ -159,6 +160,39 @@ int board_init(void)
>   	return 0;
>   }
>   
> +void __weak qcom_late_init(void)
> +{
> +}
> +
> +#define KERNEL_COMP_SIZE	SZ_64M
> +
> +#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
> +
> +/* Stolen from arch/arm/mach-apple/board.c */
> +int board_late_init(void)
> +{
> +	struct lmb lmb;
> +	u32 status = 0;
> +
> +	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
> +
> +	/* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */
> +	status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
> +	status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
> +	status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE));
> +	status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
> +	status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
> +	status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
> +	status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
> +
> +	if (status)
> +		log_warning("%s: Failed to set run time variables\n", __func__);
> +
> +	qcom_late_init();
> +
> +	return 0;
> +}
> +
>   static void build_mem_map(void)
>   {
>   	int i;
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 0136cc2237de..fbbfc0e65e24 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -88,7 +88,7 @@ int misc_init_r(void)
>   	return 0;
>   }
>   
> -int board_late_init(void)
> +int qcom_late_init(void)
>   {
>   	char serial[16];
>   
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 26/39] doc: board/qualcomm: link to APQ8016 TRM

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> The MSM8916/APQ8016 Technical Reference Manual is publicly available and
> contains a lot of useful register maps for many core parts of the SoC.
> Include an archive.org link to it in the dragonboard410c documentation.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   doc/board/qualcomm/dragonboard410c.rst | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/doc/board/qualcomm/dragonboard410c.rst b/doc/board/qualcomm/dragonboard410c.rst
> index d0de9dbcbc9a..34629241110c 100644
> --- a/doc/board/qualcomm/dragonboard410c.rst
> +++ b/doc/board/qualcomm/dragonboard410c.rst
> @@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can replace LK entirely.
>   
>   .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/
>   
> +.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf
> +
>   Installation
>   ------------
>   First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``::
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 11/39] gpio: qcom_pmic: add pinctrl driver

[Neil Armstrong]

On 15/02/2024 21:52, Caleb Connolly wrote:
> Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
> necessary to make proper use of upstream DT bindings specifically on the
> dragonboard410c where they're used to switch between USB host and device
> modes.
> 
> Only support for driving the pins as output low or high is enabled for
> now.
> 
> To minimise duplicated code and allow for sharing common DT data, the
> pinctrl driver is initialised as a child of the existing GPIO driver.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/gpio/qcom_pmic_gpio.c | 257 +++++++++++++++++++++++++++++-------------
>   1 file changed, 176 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> index 198cd84bc31e..9eca1556c356 100644
> --- a/drivers/gpio/qcom_pmic_gpio.c
> +++ b/drivers/gpio/qcom_pmic_gpio.c
> @@ -7,10 +7,14 @@
>   
>   #include <common.h>
>   #include <dm.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dm/pinctrl.h>
>   #include <log.h>
>   #include <power/pmic.h>
>   #include <spmi/spmi.h>
>   #include <asm/io.h>
> +#include <stdlib.h>
>   #include <asm/gpio.h>
>   #include <linux/bitops.h>
>   
> @@ -73,17 +77,54 @@ enum pmic_gpio_quirks {
>   	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
>   };
>   
> -struct qcom_gpio_bank {
> +struct qcom_pmic_gpio_data {
>   	uint32_t pid; /* Peripheral ID on SPMI bus */
>   	bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
> +	u32 pin_count;
> +	struct udevice *pmic; /* Reference to pmic device for read/write */
>   };
>   
> -static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
> +/* dev can be the GPIO or pinctrl device */
> +static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
> +{
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	u32 gpio_base = plat->pid + REG_OFFSET(offset);
> +	u32 reg_ctl_val;
> +	int ret = 0;
> +
> +	/* Select the mode and output */
> +	if (plat->lv_mv_type) {
> +		if (input)
> +			reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
> +		else
> +			reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
> +	} else {
> +		if (input)
> +			reg_ctl_val = REG_CTL_MODE_INPUT;
> +		else
> +			reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
> +	}
> +
> +	ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (plat->lv_mv_type && !input) {
> +		ret = pmic_reg_write(plat->pmic,
> +				     gpio_base + REG_LV_MV_OUTPUT_CTL,
> +				     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
>   				   bool input, int value)
>   {
> -	struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> -	uint32_t reg_ctl_val;
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>   	ulong quirks = dev_get_driver_data(dev);
>   	int ret = 0;
>   
> @@ -97,33 +138,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>   	if (ret < 0)
>   		return ret;
>   
> -	/* Select the mode and output */
> -	if (priv->lv_mv_type) {
> -		if (input)
> -			reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
> -		else
> -			reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
> -	} else {
> -		if (input)
> -			reg_ctl_val = REG_CTL_MODE_INPUT;
> -		else
> -			reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
> -	}
> -
> -	ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
> -	if (ret < 0)
> -		return ret;
> -
> -	if (priv->lv_mv_type && !input) {
> -		ret = pmic_reg_write(dev->parent,
> -				     gpio_base + REG_LV_MV_OUTPUT_CTL,
> -				     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
> -		if (ret < 0)
> -			return ret;
> -	}
> +	_qcom_gpio_set_direction(dev, offset, input, value);
>   
>   	/* Set the right pull (no pull) */
> -	ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
> +	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
>   			     REG_DIG_PULL_NO_PU);
>   	if (ret < 0)
>   		return ret;
> @@ -131,13 +149,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>   	/* Configure output pin drivers if needed */
>   	if (!input) {
>   		/* Select the VIN - VIN0, pin is input so it doesn't matter */
> -		ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
> +		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
>   				     REG_DIG_VIN_VIN0);
>   		if (ret < 0)
>   			return ret;
>   
>   		/* Set the right dig out control */
> -		ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
> +		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
>   				     REG_DIG_OUT_CTL_CMOS |
>   				     REG_DIG_OUT_CTL_DRIVE_L);
>   		if (ret < 0)
> @@ -162,15 +180,15 @@ static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
>   
>   static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
>   {
> -	struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>   	int reg;
>   
> -	reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
> +	reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
>   	if (reg < 0)
>   		return reg;
>   
> -	if (priv->lv_mv_type) {
> +	if (plat->lv_mv_type) {
>   		switch (reg & REG_CTL_LV_MV_MODE_MASK) {
>   		case REG_CTL_LV_MV_MODE_INPUT:
>   			return GPIOF_INPUT;
> @@ -195,11 +213,11 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
>   
>   static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
>   {
> -	struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>   	int reg;
>   
> -	reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
> +	reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
>   	if (reg < 0)
>   		return reg;
>   
> @@ -209,11 +227,11 @@ static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
>   static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
>   			       int value)
>   {
> -	struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -	uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>   
>   	/* Set the output value of the gpio */
> -	if (priv->lv_mv_type)
> +	if (plat->lv_mv_type)
>   		return pmic_clrsetbits(dev->parent,
>   				       gpio_base + REG_LV_MV_OUTPUT_CTL,
>   				       REG_LV_MV_OUTPUT_CTL_MASK,
> @@ -253,63 +271,74 @@ static const struct dm_gpio_ops qcom_gpio_ops = {
>   	.xlate			= qcom_gpio_xlate,
>   };
>   
> +static int qcom_gpio_bind(struct udevice *dev)
> +{
> +	
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	ulong quirks = dev_get_driver_data(dev);
> +	struct udevice *child;
> +	struct driver *drv;
> +	int ret;
> +
> +	drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
> +	if (!drv) {
> +		log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
> +		return -ENOENT;
> +	}
> +
> +	/* Bind the GPIO driver as a child of the PMIC. */
> +	ret = device_bind_with_driver_data(dev, drv,
> +					   dev->name,
> +					   quirks, dev_ofnode(dev), &child);
> +	if (ret)
> +		return log_msg_ret("bind", ret);
> +
> +	dev_set_plat(child, plat);
> +
> +	return 0;
> +}
> +
>   static int qcom_gpio_probe(struct udevice *dev)
>   {
> -	struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -	int reg;
> +	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +	struct ofnode_phandle_args args;
> +	int val, ret;
>   	u64 pid;
>   
> +	plat->pmic = dev->parent;
> +
>   	pid = dev_read_addr(dev);
>   	if (pid == FDT_ADDR_T_NONE)
>   		return log_msg_ret("bad address", -EINVAL);
>   
> -	priv->pid = pid;
> +	plat->pid = pid;
>   
>   	/* Do a sanity check */
> -	reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
> -	if (reg != REG_TYPE_VAL)
> +	val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
> +	if (val != REG_TYPE_VAL)
>   		return log_msg_ret("bad type", -ENXIO);
>   
> -	reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
> -	if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH &&
> -	    reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV)
> +	val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
> +	if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
> +	    val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
>   		return log_msg_ret("bad subtype", -ENXIO);
>   
> -	priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV ||
> -			   reg == REG_SUBTYPE_GPIO_MV;
> -
> -	return 0;
> -}
> -
> -/*
> - * Parse basic GPIO count specified via the gpio-ranges property
> - * as specified in Linux devicetrees
> - * Returns < 0 on error, otherwise gpio count
> - */
> -static int qcom_gpio_of_parse_ranges(struct udevice *dev)
> -{
> -	int ret;
> -	struct ofnode_phandle_args args;
> +	plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
> +			   val == REG_SUBTYPE_GPIO_MV;
>   
> +	/*
> +	 * Parse basic GPIO count specified via the gpio-ranges property
> +	 * as specified in upstream devicetrees
> +	 */
>   	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
>   					     NULL, 3, 0, &args);
>   	if (ret)
>   		return log_msg_ret("gpio-ranges", ret);
>   
> -	return args.args[2];
> -}
> -
> -static int qcom_gpio_of_to_plat(struct udevice *dev)
> -{
> -	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> -	int ret;
> -
> -	ret = qcom_gpio_of_parse_ranges(dev);
> -	if (ret > 0)
> -		uc_priv->gpio_count = ret;
> -	else
> -		return ret;
> +	plat->pin_count = args.args[2];
>   
> +	uc_priv->gpio_count = plat->pin_count;
>   	uc_priv->bank_name = "pmic";
>   
>   	return 0;
> @@ -327,9 +356,75 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = {
>   	.name	= "qcom_pmic_gpio",
>   	.id	= UCLASS_GPIO,
>   	.of_match = qcom_gpio_ids,
> -	.of_to_plat = qcom_gpio_of_to_plat,
> -	.probe	= qcom_gpio_probe,
> +	.bind	= qcom_gpio_bind,
> +	.probe = qcom_gpio_probe,
>   	.ops	= &qcom_gpio_ops,
> -	.priv_auto	= sizeof(struct qcom_gpio_bank),
> +	.plat_auto = sizeof(struct qcom_pmic_gpio_data),
> +	.flags = DM_FLAG_ALLOC_PDATA,
>   };
>   
> +static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
> +	{ "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
> +	{ "output-low", PIN_CONFIG_OUTPUT, 0 },
> +};
> +
> +static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
> +{
> +	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +
> +	return plat->pin_count;
> +}
> +
> +static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector)
> +{
> +	static char name[8];
> +
> +	/* DT indexes from 1 */
> +	snprintf(name, sizeof(name), "gpio%u", selector + 1);
> +
> +	return name;
> +}
> +
> +static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
> +					 unsigned int param, unsigned int arg)
> +{
> +	/* We only support configuring the pin as an output, either low or high */
> +	return _qcom_gpio_set_direction(dev, selector, false,
> +					param == PIN_CONFIG_OUTPUT_ENABLE);
> +}
> +
> +static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector)
> +{
> +	if (!selector)
> +		return "normal";
> +	return NULL;
> +}
> +
> +static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
> +{
> +	return 1;
> +}
> +
> +static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
> +						    unsigned int func_selector)
> +{
> +	return 0;
> +}
> +
> +struct pinctrl_ops qcom_pmic_pinctrl_ops = {
> +	.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
> +	.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
> +	.set_state = pinctrl_generic_set_state,
> +	.pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
> +	.pinconf_params = qcom_pmic_pinctrl_conf_params,
> +	.pinconf_set = qcom_pmic_pinctrl_pinconf_set,
> +	.get_function_name = qcom_pmic_pinctrl_get_function_name,
> +	.get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
> +	.pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
> +};
> +
> +U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
> +	.name	= "qcom_pmic_pinctrl",
> +	.id	= UCLASS_PINCTRL,
> +	.ops	= &qcom_pmic_pinctrl_ops,
> +};
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v4 01/39] arm: init: export prev_bl_fdt_addr

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> When booting U-Boot on board with a locked down first-stage bootloader,
> we emulate the Linux boot header. By passing the U-Boot FDT through this
> first-stage bootloader and retrieving it afterwards we can pre-populate
> the memory nodes and other info like the KASLR address.
>
> Add a function to export the FDT addr so that boards can use it over the
> built-in FDT.
>
> Don't check is_addr_accessible() here because we might not yet have a
> valid mem_map if it's going to be populated from the FDT, let the board
> do their own validation instead.
>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/lib/save_prev_bl_data.c |  5 +++++
>  include/init.h                   | 11 +++++++++++
>  2 files changed, 16 insertions(+)

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

>
> diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c
> index f7b23faf0d66..b286bac9bf00 100644
> --- a/arch/arm/lib/save_prev_bl_data.c
> +++ b/arch/arm/lib/save_prev_bl_data.c
> @@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr)
>         return false;
>  }
>
> +phys_addr_t get_prev_bl_fdt_addr(void)
> +{
> +       return reg0;
> +}
> +
>  int save_prev_bl_data(void)
>  {
>         struct fdt_header *fdt_blob;
> diff --git a/include/init.h b/include/init.h
> index 9a1951d10a01..630d86729c4e 100644
> --- a/include/init.h
> +++ b/include/init.h
> @@ -168,6 +168,17 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)
>   * Return: 0 if ok; -ENODATA on error
>   */
>  int save_prev_bl_data(void);
> +
> +/**
> + * get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address
> + * of the FDT passed by the previous bootloader.
> + *
> + * Return: the address of the FDT passed by the previous bootloader
> + * or 0 if not found.
> + */
> +phys_addr_t get_prev_bl_fdt_addr(void);
> +#else
> +#define get_prev_bl_fdt_addr() 0LLU
>  #endif
>
>  /**
>
> --
> 2.43.1
>

Re: [PATCH v4 03/39] mmc: msm_sdhci: use modern clock handling

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Use the clk_* helper functions and the correct property name for clocks.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++----------------
>  1 file changed, 47 insertions(+), 22 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> index fe1e754bfde0..b63538fce20c 100644
> --- a/drivers/mmc/msm_sdhci.c
> +++ b/drivers/mmc/msm_sdhci.c
> @@ -44,6 +44,7 @@ struct msm_sdhc_plat {
>  struct msm_sdhc {
>         struct sdhci_host host;
>         void *base;
> +       struct clk_bulk clks;
>  };
>
>  struct msm_sdhc_variant_info {
> @@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  static int msm_sdc_clk_init(struct udevice *dev)
>  {
> -       int node = dev_of_offset(dev);
> -       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
> -                                       400000);
> -       uint clkd[2]; /* clk_id and clk_no */
> -       int clk_offset;
> -       struct udevice *clk_dev;
> -       struct clk clk;
> -       int ret;
> +       struct msm_sdhc *prv = dev_get_priv(dev);
> +       ofnode node = dev_ofnode(dev);
> +       uint clk_rate;
> +       int ret, i = 0, n_clks;
> +       const char *clk_name;
>
> -       ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
> +       ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
>         if (ret)
> -               return ret;
> +               clk_rate = 400000;
>
> -       clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -       if (clk_offset < 0)
> -               return clk_offset;
> -
> -       ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -       if (ret)
> +       ret = clk_get_bulk(dev, &prv->clks);
> +       if (ret) {
> +               log_warning("Couldn't get mmc clocks: %d\n", ret);
>                 return ret;
> +       }
>
> -       clk.id = clkd[1];
> -       ret = clk_request(clk_dev, &clk);
> -       if (ret < 0)
> +       ret = clk_enable_bulk(&prv->clks);
> +       if (ret) {
> +               log_warning("Couldn't enable mmc clocks: %d\n", ret);
>                 return ret;
> +       }
>
> -       ret = clk_set_rate(&clk, clk_rate);
> -       if (ret < 0)
> -               return ret;
> +       /* If clock-names is unspecified, then the first clock is the core clock */
> +       if (!ofnode_get_property(node, "clock-names", &n_clks)) {
> +               if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
> +                       log_warning("Couldn't set core clock rate: %d\n", ret);
> +                       return -EINVAL;
> +               }
> +       }
> +
> +       /* Find the index of the "core" clock */
> +       while (i < n_clks) {
> +               ofnode_read_string_index(node, "clock-names", i, &clk_name);
> +               if (!strcmp(clk_name, "core"))
> +                       break;
> +               i++;
> +       }
> +
> +       if (i >= prv->clks.count) {
> +               log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
> +                      prv->clks.count);
> +               return -EINVAL;
> +       }
> +
> +       /* The clock is already enabled by the clk_bulk above */
> +       ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
> +       /* If we get a rate of 0 then something has probably gone wrong. */
> +       if (ret == 0) {
> +               log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
> +               return -EINVAL;
> +       }
>
>         return 0;
>  }
> @@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev)
>         if (!var_info->mci_removed)
>                 writel(0, priv->base + SDCC_MCI_HC_MODE);
>
> +       clk_release_bulk(&priv->clks);
> +
>         return 0;
>  }
>
>
> --
> 2.43.1
>

Re: [PATCH v4 04/39] dt-bindings: drop msm_sdhci binding

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> The upstream DT is supported here, so drop the U-Boot specific binding
> docs.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 -------------------------
>  1 file changed, 25 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt b/doc/device-tree-bindings/mmc/msm_sdhci.txt
> deleted file mode 100644
> index 08a290c66931..000000000000
> --- a/doc/device-tree-bindings/mmc/msm_sdhci.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Qualcomm Snapdragon SDHCI controller
> -
> -Required properties:
> -- compatible : "qcom,sdhci-msm-v4"
> -- reg: Base address and length of registers:
> -       - Host controller registers (SDHCI)
> -       - SD Core registers
> -- clock: interface clock (must accept SD bus clock as a frequency)
> -
> -Optional properties:
> -- index: If there is more than one controller - controller index (required
> -       by generic SDHCI code).
> -- bus_width: Width of SD/eMMC bus (default 4)
> -- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
> -
> -Example:
> -
> -sdhci@07864000 {
> -       compatible = "qcom,sdhci-msm-v4";
> -       reg = <0x7864900 0x11c 0x7864000 0x800>;
> -       index = <0x1>;
> -       bus-width = <0x4>;
> -       clock = <&clkc 1>;
> -       clock-frequency = <200000000>;
> -};
>
> --
> 2.43.1
>

Re: [PATCH v4 05/39] clk/qcom: use upstream compatible properties

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Adjust the apq8016 and apq8096 drivers to use the upstream compatible
> properties, and adjust the associated dts files in U-Boot.

It looks like you haven't adjusted the dts file for db820c. However,
later patches drop them completely so I am not too worried about it.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/dragonboard410c.dts | 2 +-
>  drivers/clk/qcom/clock-apq8016.c | 2 +-
>  drivers/clk/qcom/clock-apq8096.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
> index 6a4e3ccf17b1..02c824d0226c 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -75,7 +75,7 @@
>                         };
>                 };
>                 clkc: qcom,gcc@1800000 {
> -                       compatible = "qcom,gcc-apq8016";
> +                       compatible = "qcom,gcc-msm8916";
>                         reg = <0x1800000 0x80000>;
>                         #address-cells = <0x1>;
>                         #size-cells = <0x0>;
> diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
> index c0ce570edc79..0af7191cff52 100644
> --- a/drivers/clk/qcom/clock-apq8016.c
> +++ b/drivers/clk/qcom/clock-apq8016.c
> @@ -145,7 +145,7 @@ static struct msm_clk_data apq8016_clk_data = {
>
>  static const struct udevice_id gcc_apq8016_of_match[] = {
>         {
> -               .compatible = "qcom,gcc-apq8016",
> +               .compatible = "qcom,gcc-msm8916",
>                 .data = (ulong)&apq8016_clk_data,
>         },
>         { }
> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> index cf1a347309a5..1e6fdb5cd42d 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -123,7 +123,7 @@ static struct msm_clk_data apq8096_clk_data = {
>
>  static const struct udevice_id gcc_apq8096_of_match[] = {
>         {
> -               .compatible = "qcom,gcc-apq8096",
> +               .compatible = "qcom,gcc-msm8996",
>                 .data = (ulong)&apq8096_clk_data,
>         },
>         { }
>
> --
> 2.43.1
>

Re: [PATCH v4 09/39] gpio: qcom_pmic: 1-based GPIOs

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Qualcomm PMICs number their GPIOs starting from 1, implement a custom
> .xlate method to handle this.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/gpio/qcom_pmic_gpio.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> index 6167c8411678..2a4fef8d28cb 100644
> --- a/drivers/gpio/qcom_pmic_gpio.c
> +++ b/drivers/gpio/qcom_pmic_gpio.c
> @@ -209,12 +209,34 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
>                                        REG_CTL_OUTPUT_MASK, !!value);
>  }
>
> +static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
> +                          struct ofnode_phandle_args *args)
> +{
> +       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +
> +       if (args->args_count < 1)
> +               return -EINVAL;
> +
> +       /* GPIOs in DT are 1-based */
> +       desc->offset = args->args[0] - 1;
> +       if (desc->offset >= uc_priv->gpio_count)
> +               return -EINVAL;
> +
> +       if (args->args_count < 2)
> +               return 0;
> +
> +       desc->flags = gpio_flags_xlate(args->args[1]);
> +
> +       return 0;
> +}
> +
>  static const struct dm_gpio_ops qcom_gpio_ops = {
>         .direction_input        = qcom_gpio_direction_input,
>         .direction_output       = qcom_gpio_direction_output,
>         .get_value              = qcom_gpio_get_value,
>         .set_value              = qcom_gpio_set_value,
>         .get_function           = qcom_gpio_get_function,
> +       .xlate                  = qcom_gpio_xlate,
>  };
>
>  static int qcom_gpio_probe(struct udevice *dev)
>
> --
> 2.43.1
>

Re: [PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Some platforms hard reset when attempting to configure PMIC GPIOs. Add
> support for quirks specified in match data with a single quirk to skip
> this configuration. We rely on the GPIO already be configured correctly,
> which is always the case for volume up (the only current user of these
> GPIOs).

I can't find a similar quirk in the counterpart Linux driver
(drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are
missing in the U-Boot driver?

-Sumit

>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> index 2a4fef8d28cb..198cd84bc31e 100644
> --- a/drivers/gpio/qcom_pmic_gpio.c
> +++ b/drivers/gpio/qcom_pmic_gpio.c
> @@ -64,6 +64,15 @@
>  #define REG_EN_CTL             0x46
>  #define REG_EN_CTL_ENABLE      (1 << 7)
>
> +/**
> + * pmic_gpio_match_data - platform specific configuration
> + *
> + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
> + */
> +enum pmic_gpio_quirks {
> +       QCOM_PMIC_QUIRK_READONLY = (1 << 0),
> +};
> +
>  struct qcom_gpio_bank {
>         uint32_t pid; /* Peripheral ID on SPMI bus */
>         bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
> @@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>         struct qcom_gpio_bank *priv = dev_get_priv(dev);
>         uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
>         uint32_t reg_ctl_val;
> -       int ret;
> +       ulong quirks = dev_get_driver_data(dev);
> +       int ret = 0;
> +
> +       /* Some PMICs don't like their GPIOs being configured */
> +       if (quirks & QCOM_PMIC_QUIRK_READONLY)
> +               return 0;
>
>         /* Disable the GPIO */
>         ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
> @@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
>  static const struct udevice_id qcom_gpio_ids[] = {
>         { .compatible = "qcom,pm8916-gpio" },
>         { .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
> -       { .compatible = "qcom,pm8998-gpio" },
> +       { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
>         { .compatible = "qcom,pms405-gpio" },
>         { }
>  };
>
> --
> 2.43.1
>

Re: [PATCH v4 06/39] clock/qcom: qcs404: fix clk_set_rate

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> We should be returning the rate that we set the clock to, drivers like
> MMC rely on this. So fix it.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/clk/qcom/clock-qcs404.c | 25 +++++++++++++------------
>  1 file changed, 13 insertions(+), 12 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
> index f5b352803927..958312b88842 100644
> --- a/drivers/clk/qcom/clock-qcs404.c
> +++ b/drivers/clk/qcom/clock-qcs404.c
> @@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
>
>         switch (clk->id) {
>         case GCC_BLSP1_UART2_APPS_CLK:
> -               /* UART: 115200 */
> +               /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
>                 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
>                                      CFG_CLK_SRC_CXO, 16);
>                 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
> -               break;
> -       case GCC_BLSP1_AHB_CLK:
> -               clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
> -               break;
> +               return 1843200;
>         case GCC_SDCC1_APPS_CLK:
>                 /* SDCC1: 200MHz */
>                 clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
>                                      CFG_CLK_SRC_GPLL0, 8);
>                 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
>                 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
> -               break;
> -       case GCC_SDCC1_AHB_CLK:
> -               clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
> -               break;
> +               return rate;
>         case GCC_ETH_RGMII_CLK:
>                 if (rate == 250000000)
>                         clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
> @@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
>                 else if (rate == 5000000)
>                         clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
>                                              CFG_CLK_SRC_GPLL1, 8);
> -               break;
> -       default:
> -               return 0;
> +               return rate;
>         }
>
> +       /* There is a bug only seeming to affect this board where the MMC driver somehow calls
> +        * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
> +        * The only clock with ID 0 is the xo_board clock which should not be associated with
> +        * this device...
> +        */
> +       log_debug("Unknown clock id %ld\n", clk->id);
>         return 0;
>  }
>
> @@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
>                 clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
>                                  CFG_CLK_SRC_CXO);
>                 break;
> +       case GCC_SDCC1_AHB_CLK:
> +               clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
> +               break;
>         default:
>                 return 0;
>         }
>
> --
> 2.43.1
>

Re: [PATCH v4 07/39] serial: msm: add debug UART

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Introduce support for early debugging. This relies on the previous stage
> bootloader to initialise the UART clocks, when running with U-Boot as
> the primary bootloader this feature doesn't work. It will require a way
> to configure the clocks before the driver model is available.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/serial/Kconfig      |  8 ++++++++
>  drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 45 insertions(+)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 26460c4e0cab..fbd351a47859 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -319,6 +319,14 @@ config DEBUG_UART_S5P
>           will need to provide parameters to make this work. The driver will
>           be available until the real driver-model serial is running.
>
> +config DEBUG_UART_MSM
> +       bool "Qualcomm QUP UART debug"
> +       depends on ARCH_SNAPDRAGON

Since this debug UART only works for chainloaded configuration, can we
somehow add explicit dependency here? Something like !REMAKE_ELF?

-Sumit

> +       help
> +         Select this to enable a debug UART using the serial_msm driver. You
> +         will need to provide parameters to make this work. The driver will
> +         be available until the real driver-model serial is running.
> +
>  config DEBUG_UART_MSM_GENI
>         bool "Qualcomm snapdragon"
>         depends on ARCH_SNAPDRAGON
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index f4d96313b931..44b93bd7ff21 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = {
>         .probe = msm_serial_probe,
>         .ops    = &msm_serial_ops,
>  };
> +
> +#ifdef CONFIG_DEBUG_UART_MSM
> +
> +static struct msm_serial_data init_serial_data = {
> +       .base = CONFIG_VAL(DEBUG_UART_BASE),
> +       .clk_rate = 7372800,
> +};
> +
> +#include <debug_uart.h>
> +
> +/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
> +//int apq8016_clk_init_uart(phys_addr_t gcc_base);
> +
> +static inline void _debug_uart_init(void)
> +{
> +       /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
> +       //apq8016_clk_init_uart(0x1800000);
> +       uart_dm_init(&init_serial_data);
> +}
> +
> +static inline void _debug_uart_putc(int ch)
> +{
> +       struct msm_serial_data *priv = &init_serial_data;
> +
> +       while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
> +              !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
> +               ;
> +
> +       writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
> +
> +       writel(1, priv->base + UARTDM_NCF_TX);
> +       writel(ch, priv->base + UARTDM_TF);
> +}
> +
> +DEBUG_UART_FUNCS
> +
> +#endif
>
> --
> 2.43.1
>

Re: [PATCH v4 08/39] serial: msm: fix clock handling and pinctrl

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Use the modern helpers to fetch the clock and use the correct property
> ("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
> as no boards have a "uart" pinctrl state and this prints confusing
> errors.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/dragonboard410c.dts |  3 ++-
>  arch/arm/dts/dragonboard820c.dts |  3 ++-
>  drivers/serial/serial_msm.c      | 25 +++++--------------------
>  3 files changed, 9 insertions(+), 22 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
> index 02c824d0226c..c395e6cc0427 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -84,7 +84,8 @@
>                 serial@78b0000 {
>                         compatible = "qcom,msm-uartdm-v1.4";
>                         reg = <0x78b0000 0x200>;
> -                       clock = <&clkc 4>;
> +                       clocks = <&clkc 4>;
> +                       clock-names = "core";
>                         pinctrl-names = "uart";
>                         pinctrl-0 = <&blsp1_uart>;
>                 };
> diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
> index 146a0af8aafe..86b7f83d36d6 100644
> --- a/arch/arm/dts/dragonboard820c.dts
> +++ b/arch/arm/dts/dragonboard820c.dts
> @@ -78,7 +78,8 @@
>                 blsp2_uart2: serial@75b0000 {
>                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>                         reg = <0x75b0000 0x1000>;
> -                       clock = <&gcc 4>;
> +                       clocks = <&gcc 4>;
> +                       clock-names = "core";
>                         pinctrl-names = "uart";
>                         pinctrl-0 = <&blsp8_uart>;
>                 };
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index 44b93bd7ff21..ac4280c6c4c2 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev)
>  {
>         uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
>                                         "clock-frequency", 115200);
> -       uint clkd[2]; /* clk_id and clk_no */
> -       int clk_offset;
> -       struct udevice *clk_dev;
>         struct clk clk;
>         int ret;
>
> -       ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
> -                                  clkd, 2);
> -       if (ret)
> -               return ret;
> -
> -       clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -       if (clk_offset < 0)
> -               return clk_offset;
> -
> -       ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -       if (ret)
> -               return ret;
> -
> -       clk.id = clkd[1];
> -       ret = clk_request(clk_dev, &clk);
> -       if (ret < 0)
> +       ret = clk_get_by_name(dev, "core", &clk);
> +       if (ret < 0) {
> +               pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
>                 return ret;
> +       }
>
>         ret = clk_set_rate(&clk, clk_rate);
>         if (ret < 0)
> @@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev)
>         if (ret)
>                 return ret;
>
> -       pinctrl_select_state(dev, "uart");
>         uart_dm_init(priv);
>
>         return 0;
> @@ -251,6 +235,7 @@ U_BOOT_DRIVER(serial_msm) = {
>         .priv_auto      = sizeof(struct msm_serial_data),
>         .probe = msm_serial_probe,
>         .ops    = &msm_serial_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
>  };
>
>  #ifdef CONFIG_DEBUG_UART_MSM
>
> --
> 2.43.1
>

Re: [PATCH v4 11/39] gpio: qcom_pmic: add pinctrl driver

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
> necessary to make proper use of upstream DT bindings specifically on the
> dragonboard410c where they're used to switch between USB host and device
> modes.
>
> Only support for driving the pins as output low or high is enabled for
> now.
>
> To minimise duplicated code and allow for sharing common DT data, the
> pinctrl driver is initialised as a child of the existing GPIO driver.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/gpio/qcom_pmic_gpio.c | 257 +++++++++++++++++++++++++++++-------------
>  1 file changed, 176 insertions(+), 81 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> index 198cd84bc31e..9eca1556c356 100644
> --- a/drivers/gpio/qcom_pmic_gpio.c
> +++ b/drivers/gpio/qcom_pmic_gpio.c
> @@ -7,10 +7,14 @@
>
>  #include <common.h>
>  #include <dm.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dm/pinctrl.h>
>  #include <log.h>
>  #include <power/pmic.h>
>  #include <spmi/spmi.h>
>  #include <asm/io.h>
> +#include <stdlib.h>
>  #include <asm/gpio.h>
>  #include <linux/bitops.h>
>
> @@ -73,17 +77,54 @@ enum pmic_gpio_quirks {
>         QCOM_PMIC_QUIRK_READONLY = (1 << 0),
>  };
>
> -struct qcom_gpio_bank {
> +struct qcom_pmic_gpio_data {
>         uint32_t pid; /* Peripheral ID on SPMI bus */
>         bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
> +       u32 pin_count;
> +       struct udevice *pmic; /* Reference to pmic device for read/write */
>  };
>
> -static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
> +/* dev can be the GPIO or pinctrl device */
> +static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
> +{
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       u32 gpio_base = plat->pid + REG_OFFSET(offset);
> +       u32 reg_ctl_val;
> +       int ret = 0;
> +
> +       /* Select the mode and output */
> +       if (plat->lv_mv_type) {
> +               if (input)
> +                       reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
> +               else
> +                       reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
> +       } else {
> +               if (input)
> +                       reg_ctl_val = REG_CTL_MODE_INPUT;
> +               else
> +                       reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
> +       }
> +
> +       ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
> +       if (ret < 0)
> +               return ret;
> +
> +       if (plat->lv_mv_type && !input) {
> +               ret = pmic_reg_write(plat->pmic,
> +                                    gpio_base + REG_LV_MV_OUTPUT_CTL,
> +                                    !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
> +               if (ret < 0)
> +                       return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
>                                    bool input, int value)
>  {
> -       struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> -       uint32_t reg_ctl_val;
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>         ulong quirks = dev_get_driver_data(dev);
>         int ret = 0;
>
> @@ -97,33 +138,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>         if (ret < 0)
>                 return ret;
>
> -       /* Select the mode and output */
> -       if (priv->lv_mv_type) {
> -               if (input)
> -                       reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
> -               else
> -                       reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
> -       } else {
> -               if (input)
> -                       reg_ctl_val = REG_CTL_MODE_INPUT;
> -               else
> -                       reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
> -       }
> -
> -       ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
> -       if (ret < 0)
> -               return ret;
> -
> -       if (priv->lv_mv_type && !input) {
> -               ret = pmic_reg_write(dev->parent,
> -                                    gpio_base + REG_LV_MV_OUTPUT_CTL,
> -                                    !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
> -               if (ret < 0)
> -                       return ret;
> -       }
> +       _qcom_gpio_set_direction(dev, offset, input, value);
>
>         /* Set the right pull (no pull) */
> -       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
> +       ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
>                              REG_DIG_PULL_NO_PU);
>         if (ret < 0)
>                 return ret;
> @@ -131,13 +149,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>         /* Configure output pin drivers if needed */
>         if (!input) {
>                 /* Select the VIN - VIN0, pin is input so it doesn't matter */
> -               ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
> +               ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
>                                      REG_DIG_VIN_VIN0);
>                 if (ret < 0)
>                         return ret;
>
>                 /* Set the right dig out control */
> -               ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
> +               ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
>                                      REG_DIG_OUT_CTL_CMOS |
>                                      REG_DIG_OUT_CTL_DRIVE_L);
>                 if (ret < 0)
> @@ -162,15 +180,15 @@ static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
>
>  static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
>  {
> -       struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>         int reg;
>
> -       reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
> +       reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
>         if (reg < 0)
>                 return reg;
>
> -       if (priv->lv_mv_type) {
> +       if (plat->lv_mv_type) {
>                 switch (reg & REG_CTL_LV_MV_MODE_MASK) {
>                 case REG_CTL_LV_MV_MODE_INPUT:
>                         return GPIOF_INPUT;
> @@ -195,11 +213,11 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
>
>  static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
>  {
> -       struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>         int reg;
>
> -       reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
> +       reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
>         if (reg < 0)
>                 return reg;
>
> @@ -209,11 +227,11 @@ static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
>  static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
>                                int value)
>  {
> -       struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
>
>         /* Set the output value of the gpio */
> -       if (priv->lv_mv_type)
> +       if (plat->lv_mv_type)
>                 return pmic_clrsetbits(dev->parent,
>                                        gpio_base + REG_LV_MV_OUTPUT_CTL,
>                                        REG_LV_MV_OUTPUT_CTL_MASK,
> @@ -253,63 +271,74 @@ static const struct dm_gpio_ops qcom_gpio_ops = {
>         .xlate                  = qcom_gpio_xlate,
>  };
>
> +static int qcom_gpio_bind(struct udevice *dev)
> +{
> +
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       ulong quirks = dev_get_driver_data(dev);
> +       struct udevice *child;
> +       struct driver *drv;
> +       int ret;
> +
> +       drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
> +       if (!drv) {
> +               log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
> +               return -ENOENT;
> +       }
> +
> +       /* Bind the GPIO driver as a child of the PMIC. */
> +       ret = device_bind_with_driver_data(dev, drv,
> +                                          dev->name,
> +                                          quirks, dev_ofnode(dev), &child);
> +       if (ret)
> +               return log_msg_ret("bind", ret);
> +
> +       dev_set_plat(child, plat);
> +
> +       return 0;
> +}
> +
>  static int qcom_gpio_probe(struct udevice *dev)
>  {
> -       struct qcom_gpio_bank *priv = dev_get_priv(dev);
> -       int reg;
> +       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +       struct ofnode_phandle_args args;
> +       int val, ret;
>         u64 pid;
>
> +       plat->pmic = dev->parent;
> +
>         pid = dev_read_addr(dev);
>         if (pid == FDT_ADDR_T_NONE)
>                 return log_msg_ret("bad address", -EINVAL);
>
> -       priv->pid = pid;
> +       plat->pid = pid;
>
>         /* Do a sanity check */
> -       reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
> -       if (reg != REG_TYPE_VAL)
> +       val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
> +       if (val != REG_TYPE_VAL)
>                 return log_msg_ret("bad type", -ENXIO);
>
> -       reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
> -       if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH &&
> -           reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV)
> +       val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
> +       if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
> +           val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
>                 return log_msg_ret("bad subtype", -ENXIO);
>
> -       priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV ||
> -                          reg == REG_SUBTYPE_GPIO_MV;
> -
> -       return 0;
> -}
> -
> -/*
> - * Parse basic GPIO count specified via the gpio-ranges property
> - * as specified in Linux devicetrees
> - * Returns < 0 on error, otherwise gpio count
> - */
> -static int qcom_gpio_of_parse_ranges(struct udevice *dev)
> -{
> -       int ret;
> -       struct ofnode_phandle_args args;
> +       plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
> +                          val == REG_SUBTYPE_GPIO_MV;
>
> +       /*
> +        * Parse basic GPIO count specified via the gpio-ranges property
> +        * as specified in upstream devicetrees
> +        */
>         ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
>                                              NULL, 3, 0, &args);
>         if (ret)
>                 return log_msg_ret("gpio-ranges", ret);
>
> -       return args.args[2];
> -}
> -
> -static int qcom_gpio_of_to_plat(struct udevice *dev)
> -{
> -       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> -       int ret;
> -
> -       ret = qcom_gpio_of_parse_ranges(dev);
> -       if (ret > 0)
> -               uc_priv->gpio_count = ret;
> -       else
> -               return ret;
> +       plat->pin_count = args.args[2];
>
> +       uc_priv->gpio_count = plat->pin_count;
>         uc_priv->bank_name = "pmic";
>
>         return 0;
> @@ -327,9 +356,75 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = {
>         .name   = "qcom_pmic_gpio",
>         .id     = UCLASS_GPIO,
>         .of_match = qcom_gpio_ids,
> -       .of_to_plat = qcom_gpio_of_to_plat,
> -       .probe  = qcom_gpio_probe,
> +       .bind   = qcom_gpio_bind,
> +       .probe = qcom_gpio_probe,
>         .ops    = &qcom_gpio_ops,
> -       .priv_auto      = sizeof(struct qcom_gpio_bank),
> +       .plat_auto = sizeof(struct qcom_pmic_gpio_data),
> +       .flags = DM_FLAG_ALLOC_PDATA,
>  };
>
> +static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
> +       { "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
> +       { "output-low", PIN_CONFIG_OUTPUT, 0 },
> +};
> +
> +static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
> +{
> +       struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
> +
> +       return plat->pin_count;
> +}
> +
> +static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector)
> +{
> +       static char name[8];
> +
> +       /* DT indexes from 1 */
> +       snprintf(name, sizeof(name), "gpio%u", selector + 1);
> +
> +       return name;
> +}
> +
> +static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
> +                                        unsigned int param, unsigned int arg)
> +{
> +       /* We only support configuring the pin as an output, either low or high */
> +       return _qcom_gpio_set_direction(dev, selector, false,
> +                                       param == PIN_CONFIG_OUTPUT_ENABLE);
> +}
> +
> +static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector)
> +{
> +       if (!selector)
> +               return "normal";
> +       return NULL;
> +}
> +
> +static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
> +{
> +       return 1;
> +}
> +
> +static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
> +                                                   unsigned int func_selector)
> +{
> +       return 0;
> +}
> +
> +struct pinctrl_ops qcom_pmic_pinctrl_ops = {
> +       .get_pins_count = qcom_pmic_pinctrl_get_pins_count,
> +       .get_pin_name = qcom_pmic_pinctrl_get_pin_name,
> +       .set_state = pinctrl_generic_set_state,
> +       .pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
> +       .pinconf_params = qcom_pmic_pinctrl_conf_params,
> +       .pinconf_set = qcom_pmic_pinctrl_pinconf_set,
> +       .get_function_name = qcom_pmic_pinctrl_get_function_name,
> +       .get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
> +       .pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
> +};
> +
> +U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
> +       .name   = "qcom_pmic_pinctrl",
> +       .id     = UCLASS_PINCTRL,
> +       .ops    = &qcom_pmic_pinctrl_ops,
> +};
>
> --
> 2.43.1
>

Re: [PATCH v4 12/39] sandbox: dts: fix qcom pmic gpio

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Adjust the DT to match upstream bindings.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/sandbox/dts/sandbox.dtsi | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
> index 241f397ba6e7..c93ce7128942 100644
> --- a/arch/sandbox/dts/sandbox.dtsi
> +++ b/arch/sandbox/dts/sandbox.dtsi
> @@ -419,17 +419,16 @@
>                 #size-cells = <0x1>;
>                 pm8916@0 {
>                         compatible = "qcom,spmi-pmic";
> -                       reg = <0x0 0x1>;
> +                       reg = <0x0 0x0>;
>                         #address-cells = <0x1>;
> -                       #size-cells = <0x1>;
> +                       #size-cells = <0x0>;
>
>                         spmi_gpios: gpios@c000 {
>                                 compatible = "qcom,pm8916-gpio";
> -                               reg = <0xc000 0x400>;
> +                               reg = <0xc000>;
>                                 gpio-controller;
> -                               gpio-count = <4>;
> +                               gpio-ranges = <&spmi_gpios 0 0 4>;
>                                 #gpio-cells = <2>;
> -                               gpio-bank-name="spmi";
>                         };
>                 };
>         };
>
> --
> 2.43.1
>

Re: [PATCH v4 15/39] pinctrl: qcom: apq8016: init pre-reloaction

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> On the DB410c we support running as a first stage bootloader. This
> requires initialising the GPIOs which are muxed to UART before they can
> be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
> that we do this early enough.
>
> This is required to prevent the first few lines of UART log from being
> dropped.
>
> Reported-by: Sumit Garg <sumit.garg@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index 10796710ba7a..df5bd1c19f6e 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -73,4 +73,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
>         .of_match       = msm_pinctrl_ids,
>         .ops            = &msm_pinctrl_ops,
>         .bind           = msm_pinctrl_bind,
> +       .flags          = DM_FLAG_PRE_RELOC,
>  };
>
> --
> 2.43.1
>

Re: [PATCH v4 03/39] mmc: msm_sdhci: use modern clock handling

[Dan Carpenter]

On Thu, Feb 15, 2024 at 08:52:21PM +0000, Caleb Connolly wrote:
>  static int msm_sdc_clk_init(struct udevice *dev)
>  {
> -	int node = dev_of_offset(dev);
> -	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
> -					400000);
> -	uint clkd[2]; /* clk_id and clk_no */
> -	int clk_offset;
> -	struct udevice *clk_dev;
> -	struct clk clk;
> -	int ret;
> +	struct msm_sdhc *prv = dev_get_priv(dev);
> +	ofnode node = dev_ofnode(dev);
> +	uint clk_rate;
> +	int ret, i = 0, n_clks;
> +	const char *clk_name;
>  
> -	ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
> +	ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
>  	if (ret)
> -		return ret;
> +		clk_rate = 400000;
>  
> -	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -	if (clk_offset < 0)
> -		return clk_offset;
> -
> -	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -	if (ret)
> +	ret = clk_get_bulk(dev, &prv->clks);
> +	if (ret) {
> +		log_warning("Couldn't get mmc clocks: %d\n", ret);
>  		return ret;
> +	}
>  
> -	clk.id = clkd[1];
> -	ret = clk_request(clk_dev, &clk);
> -	if (ret < 0)
> +	ret = clk_enable_bulk(&prv->clks);
> +	if (ret) {
> +		log_warning("Couldn't enable mmc clocks: %d\n", ret);
>  		return ret;
> +	}
>  
> -	ret = clk_set_rate(&clk, clk_rate);
> -	if (ret < 0)
> -		return ret;
> +	/* If clock-names is unspecified, then the first clock is the core clock */
> +	if (!ofnode_get_property(node, "clock-names", &n_clks)) {
> +		if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
> +			log_warning("Couldn't set core clock rate: %d\n", ret);

s/ret/clk_rate/

regards,
dan carpenter

> +			return -EINVAL;
> +		}
> +	}
> +
> +	/* Find the index of the "core" clock */
> +	while (i < n_clks) {
> +		ofnode_read_string_index(node, "clock-names", i, &clk_name);
> +		if (!strcmp(clk_name, "core"))
> +			break;
> +		i++;
> +	}
> +
> +	if (i >= prv->clks.count) {
> +		log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
> +		       prv->clks.count);
> +		return -EINVAL;
> +	}
> +
> +	/* The clock is already enabled by the clk_bulk above */
> +	ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
> +	/* If we get a rate of 0 then something has probably gone wrong. */
> +	if (ret == 0) {
> +		log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
> +		return -EINVAL;
> +	}
>  
>  	return 0;
>  }

Re: [PATCH v4 07/39] serial: msm: add debug UART

[Caleb Connolly]

On 20/02/2024 06:08, Sumit Garg wrote:
> On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>>
>> Introduce support for early debugging. This relies on the previous stage
>> bootloader to initialise the UART clocks, when running with U-Boot as
>> the primary bootloader this feature doesn't work. It will require a way
>> to configure the clocks before the driver model is available.
>>
>> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
>> ---
>>  drivers/serial/Kconfig      |  8 ++++++++
>>  drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++
>>  2 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 26460c4e0cab..fbd351a47859 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -319,6 +319,14 @@ config DEBUG_UART_S5P
>>           will need to provide parameters to make this work. The driver will
>>           be available until the real driver-model serial is running.
>>
>> +config DEBUG_UART_MSM
>> +       bool "Qualcomm QUP UART debug"
>> +       depends on ARCH_SNAPDRAGON
> 
> Since this debug UART only works for chainloaded configuration, can we
> somehow add explicit dependency here? Something like !REMAKE_ELF?

With a small patch (which didn't make it into v4 apparently) the
apq8016_clk_init_uart() function from clock-apq8016 can be adjusted to
just take a base address rather than "struct msm_clk_priv". It can then
be called from debug_uart_init() and allows for debug UART to be used
when U-Boot is running as the first stage.

This is definitely not ideal (although fwiw if the GPLLs were configured
right then this same function could maybe work on QCS404 as well - the
RCGs are at the same physical addresses), but I don't think gating it
behind REMAKE_ELF or something is a great solution here.
> 
> -Sumit
> 
>> +       help
>> +         Select this to enable a debug UART using the serial_msm driver. You
>> +         will need to provide parameters to make this work. The driver will
>> +         be available until the real driver-model serial is running.
>> +
>>  config DEBUG_UART_MSM_GENI
>>         bool "Qualcomm snapdragon"
>>         depends on ARCH_SNAPDRAGON
>> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
>> index f4d96313b931..44b93bd7ff21 100644
>> --- a/drivers/serial/serial_msm.c
>> +++ b/drivers/serial/serial_msm.c
>> @@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = {
>>         .probe = msm_serial_probe,
>>         .ops    = &msm_serial_ops,
>>  };
>> +
>> +#ifdef CONFIG_DEBUG_UART_MSM
>> +
>> +static struct msm_serial_data init_serial_data = {
>> +       .base = CONFIG_VAL(DEBUG_UART_BASE),
>> +       .clk_rate = 7372800,
>> +};
>> +
>> +#include <debug_uart.h>
>> +
>> +/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
>> +//int apq8016_clk_init_uart(phys_addr_t gcc_base);
>> +
>> +static inline void _debug_uart_init(void)
>> +{
>> +       /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
>> +       //apq8016_clk_init_uart(0x1800000);
>> +       uart_dm_init(&init_serial_data);
>> +}
>> +
>> +static inline void _debug_uart_putc(int ch)
>> +{
>> +       struct msm_serial_data *priv = &init_serial_data;
>> +
>> +       while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
>> +              !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
>> +               ;
>> +
>> +       writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
>> +
>> +       writel(1, priv->base + UARTDM_NCF_TX);
>> +       writel(ch, priv->base + UARTDM_TF);
>> +}
>> +
>> +DEBUG_UART_FUNCS
>> +
>> +#endif
>>
>> --
>> 2.43.1
>>

-- 
// Caleb (they/them)

Re: [PATCH v4 13/39] pinctrl: qcom: stub support for special GPIOs

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Most platforms have a handful of "special" GPIOs, like the MMC
> clock/data lanes, UFS reset, etc. These don't follow the usually naming

s/usually/usual/

> scheme of "gpioX" and also have unique capabilities and registers. We
> can get away without supporting them all for now, but DT compatibility
> is still an issue.
>
> Add support for allowing these to be specified after the other pins, and
> make all pinmux/pinconf calls for them nop.

Yeah earlier incorrect configuration was done for these pins. So
having them nop is an improvement.

>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/include/mach/gpio.h |  2 ++
>  drivers/gpio/msm_gpio.c                      | 20 ++++++++++++++++++++
>  drivers/pinctrl/qcom/pinctrl-qcom.c          | 12 ++++++++++++
>  3 files changed, 34 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
> index 8dac62f870b9..c373f5a4cf3d 100644
> --- a/arch/arm/mach-snapdragon/include/mach/gpio.h
> +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
> @@ -13,6 +13,8 @@
>  struct msm_pin_data {
>         int pin_count;
>         const unsigned int *pin_offsets;
> +       /* Index of first special pin, these are ignored for now */
> +       unsigned int special_pins_start;
>  };
>
>  static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> index 80cd28bb231f..8a5e8730e911 100644
> --- a/drivers/gpio/msm_gpio.c
> +++ b/drivers/gpio/msm_gpio.c
> @@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
>  {
>         struct msm_gpio_bank *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (gpio >= priv->pin_data->special_pins_start)
> +               return 0;
> +
>         /* Disable OE bit */
>         clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
>                         GPIO_OE_MASK, GPIO_OE_DISABLE);
> @@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
>  {
>         struct msm_gpio_bank *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (gpio >= priv->pin_data->special_pins_start)
> +               return 0;
> +
>         value = !!value;
>         /* set value */
>         writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
> @@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
>  {
>         struct msm_gpio_bank *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (gpio >= priv->pin_data->special_pins_start)
> +               return 0;
> +
>         value = !!value;
>         /* set value */
>         writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
> @@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
>  {
>         struct msm_gpio_bank *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (gpio >= priv->pin_data->special_pins_start)
> +               return 0;
> +
>         return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
>  }
>
> @@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
>  {
>         struct msm_gpio_bank *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (gpio >= priv->pin_data->special_pins_start)
> +               return 0;
> +
>         if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
>                 return GPIOF_OUTPUT;
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
> index dc3d8c4d9034..1ea4d21c41fc 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
> @@ -83,6 +83,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
>  {
>         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins, assume they're in the correct state */
> +       if (pin_selector >= priv->data->pin_data.special_pins_start)
> +               return 0;
> +
>         clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
>                         TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
>                         priv->data->get_function_mux(func_selector) << 2);
> @@ -94,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
>  {
>         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
>
> +       /* Always NOP for special pins */
> +       if (pin_selector >= priv->data->pin_data.special_pins_start)
> +               return 0;
> +
>         switch (param) {
>         case PIN_CONFIG_DRIVE_STRENGTH:
>                 argument = (argument / 2) - 1;
> @@ -136,6 +144,10 @@ int msm_pinctrl_bind(struct udevice *dev)
>         const char *name;
>         int ret;
>
> +       /* Make sure we don't indadvertently treat all pins as special pins. */
> +       if (!data->pin_data.special_pins_start)
> +               data->pin_data.special_pins_start = data->pin_data.pin_count;
> +
>         drv = lists_driver_lookup_name("pinctrl_qcom");
>         if (!drv)
>                 return -ENOENT;
>
> --
> 2.43.1
>

Re: [PATCH v4 14/39] pinctrl: qcom: fix DT compatibility

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
> for SoCs where we're now using upstream DT.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-apq8016.c | 26 +++++++--------
>  drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +++++-----
>  drivers/pinctrl/qcom/pinctrl-qcs404.c  | 58 ++++++++++++++++++++++++++++------
>  3 files changed, 69 insertions(+), 31 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index 8149ffd83cc4..10796710ba7a 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -14,18 +14,18 @@
>  #define MAX_PIN_NAME_LEN 32
>  static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>  static const char * const msm_pinctrl_pins[] = {
> -       "SDC1_CLK",
> -       "SDC1_CMD",
> -       "SDC1_DATA",
> -       "SDC2_CLK",
> -       "SDC2_CMD",
> -       "SDC2_DATA",
> -       "QDSD_CLK",
> -       "QDSD_CMD",
> -       "QDSD_DATA0",
> -       "QDSD_DATA1",
> -       "QDSD_DATA2",
> -       "QDSD_DATA3",
> +       "sdc1_clk",
> +       "sdc1_cmd",
> +       "sdc1_data",
> +       "sdc2_clk",
> +       "sdc2_cmd",
> +       "sdc2_data",
> +       "qdsd_clk",
> +       "qdsd_cmd",
> +       "qdsd_data0",
> +       "qdsd_data1",
> +       "qdsd_data2",
> +       "qdsd_data3",
>  };
>
>  static const struct pinctrl_function msm_pinctrl_functions[] = {
> @@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
>                                         unsigned int selector)
>  {
>         if (selector < 122) {
> -               snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +               snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>                 return pin_name;
>         } else {
>                 return msm_pinctrl_pins[selector - 122];
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> index d64ab1ff7bee..f2eeb4cf469a 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> @@ -14,13 +14,13 @@
>  #define MAX_PIN_NAME_LEN 32
>  static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>  static const char * const msm_pinctrl_pins[] = {
> -       "SDC1_CLK",
> -       "SDC1_CMD",
> -       "SDC1_DATA",
> -       "SDC2_CLK",
> -       "SDC2_CMD",
> -       "SDC2_DATA",
> -       "SDC1_RCLK",
> +       "sdc1_clk",
> +       "sdc1_cmd",
> +       "sdc1_data",
> +       "sdc2_clk",
> +       "sdc2_cmd",
> +       "sdc2_data",
> +       "sdc1_rclk",
>  };
>
>  static const struct pinctrl_function msm_pinctrl_functions[] = {
> @@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
>                                         unsigned int selector)
>  {
>         if (selector < 150) {
> -               snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +               snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>                 return pin_name;
>         } else {
>                 return msm_pinctrl_pins[selector - 150];
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> index ac00afa2a1f4..5066f2bba6b3 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> @@ -10,20 +10,24 @@
>
>  #include "pinctrl-qcom.h"
>
> +#define NORTH  0x00300000
> +#define SOUTH  0x00000000
> +#define EAST   0x06b00000
> +
>  #define MAX_PIN_NAME_LEN 32
>  static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>  static const char * const msm_pinctrl_pins[] = {
> -       "SDC1_RCLK",
> -       "SDC1_CLK",
> -       "SDC1_CMD",
> -       "SDC1_DATA",
> -       "SDC2_CLK",
> -       "SDC2_CMD",
> -       "SDC2_DATA",
> +       "sdc1_rclk",
> +       "sdc1_clk",
> +       "sdc1_cmd",
> +       "sdc1_data",
> +       "sdc2_clk",
> +       "sdc2_cmd",
> +       "sdc2_data",
>  };
>
>  static const struct pinctrl_function msm_pinctrl_functions[] = {
> -       {"blsp_uart2", 1},
> +       {"gpio", 0},
>         {"rgmii_int", 1},
>         {"rgmii_ck", 1},
>         {"rgmii_tx", 1},
> @@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
>         {"blsp_i2c_scl_a2", 3},
>         {"blsp_i2c3", 2},
>         {"blsp_i2c4", 1},
> +       {"blsp_uart_tx_a2", 1},
> +       {"blsp_uart_rx_a2", 1},
> +};
> +
> +static const unsigned int qcs404_pin_offsets[] = {
> +       [0] = SOUTH,    [1] = SOUTH,    [2] = SOUTH,    [3] = SOUTH,    [4] = SOUTH,
> +       [5] = SOUTH,   [6] = SOUTH,   [7] = SOUTH,   [8] = SOUTH,    [9] = SOUTH,
> +       [10] = SOUTH,   [11] = SOUTH,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
> +       [15] = SOUTH,  [16] = SOUTH,  [17] = NORTH,  [18] = NORTH,  [19] = NORTH,
> +       [20] = NORTH,  [21] = SOUTH,  [22] = NORTH,  [23] = NORTH,  [24] = NORTH,
> +       [25] = NORTH,  [26] = EAST,  [27] = EAST,   [28] = EAST,   [29] = EAST,
> +       [30] = NORTH,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = SOUTH,
> +       [35] = SOUTH,  [36] = NORTH,  [37] = NORTH,  [38] = NORTH,  [39] = EAST,
> +       [40] = EAST,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
> +       [45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = EAST,
> +       [50] = EAST,  [51] = EAST,  [52] = EAST,  [53] = EAST,  [54] = EAST,
> +       [55] = EAST,  [56] = EAST,  [57] = EAST,  [58] = EAST,  [59] = EAST,
> +       [60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
> +       [65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = NORTH,
> +       [70] = NORTH,   [71] = NORTH,   [72] = NORTH,   [73] = NORTH,   [74] = NORTH,
> +       [75] = NORTH,   [76] = NORTH,   [77] = NORTH,   [78] = EAST,   [79] = EAST,
> +       [80] = EAST,  [81] = EAST,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
> +       [85] = NORTH,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = EAST,
> +       [90] = EAST,  [91] = EAST,  [92] = EAST,  [93] = EAST,  [94] = EAST,
> +       [95] = EAST,  [96] = EAST,  [97] = EAST,  [98] = EAST,  [99] = EAST,
> +       [100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST,
> +       [105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST,
> +       [110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST,
> +       [115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST,
> +       /*
> +        * There's 126 pins but the last ones are special and have non-standard registers
> +        * so we leave them out here. The pinctrl and GPIO drivers both currently ignore
> +        * these pins.
> +        */
>  };
>
>  static const char *qcs404_get_function_name(struct udevice *dev,
> @@ -49,7 +87,7 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
>                                        unsigned int selector)
>  {
>         if (selector < 120) {
> -               snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +               snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>                 return pin_name;
>         } else {
>                 return msm_pinctrl_pins[selector - 120];
> @@ -62,7 +100,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector)
>  }
>
>  static struct msm_pinctrl_data qcs404_data = {
> -       .pin_data = { .pin_count = 126, },
> +       .pin_data = { .pin_count = 126, .pin_offsets = qcs404_pin_offsets, .special_pins_start = 120, },
>         .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
>         .get_function_name = qcs404_get_function_name,
>         .get_function_mux = qcs404_get_function_mux,
>
> --
> 2.43.1
>

Re: [PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Add a config fragment for building U-Boot such that it can be
> chainloaded by aboot/LK rather than being flashed directly to the aboot
> partition.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++++++
>  1 file changed, 7 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config
> new file mode 100644
> index 000000000000..3fd064924a1f
> --- /dev/null
> +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config
> @@ -0,0 +1,7 @@
> +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
> +CONFIG_TEXT_BASE=0x0
> +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set
> +# CONFIG_REMAKE_ELF is not set
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_INIT_SP_RELATIVE=y
> +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
>
> --
> 2.43.1
>

Re: [PATCH v4 17/39] board: dragonboard410c: upstream DT compat

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Use the root compatible strings from upstream Linux, add missing
> '#clock-cells' property to the gcc node.
>
> Adjust some of the msm8916/apq8016 drivers to use the correct upstream
> compatible properties and DT bindings.
>
> This prepares us to switch to upstream DT in a future patch.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/dragonboard410c.dts                 |  25 +++-
>  board/qualcomm/dragonboard410c/dragonboard410c.c |  93 +++---------
>  doc/device-tree-bindings/usb/ehci-msm.txt        |  10 --
>  drivers/clk/qcom/clock-apq8016.c                 |   7 +-
>  drivers/phy/qcom/msm8916-usbh-phy.c              |   4 +-
>  drivers/pinctrl/qcom/pinctrl-apq8016.c           |   2 +-
>  drivers/usb/host/ehci-msm.c                      |  22 ++-
>  include/dt-bindings/clock/qcom,gcc-msm8916.h     | 179 +++++++++++++++++++++++
>  8 files changed, 246 insertions(+), 96 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
> index c395e6cc0427..453642b25705 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -12,7 +12,7 @@
>
>  / {
>         model = "Qualcomm Technologies, Inc. Dragonboard 410c";
> -       compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
> +       compatible = "qcom,apq8016-sbc", "qcom,apq8016";
>         qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
>         qcom,board-id = <0x10018 0x0>;
>         #address-cells = <0x2>;
> @@ -79,6 +79,7 @@
>                         reg = <0x1800000 0x80000>;
>                         #address-cells = <0x1>;
>                         #size-cells = <0x0>;
> +                       #clock-cells = <0x1>;
>                 };
>
>                 serial@78b0000 {
> @@ -91,15 +92,25 @@
>                 };
>
>                 ehci@78d9000 {
> -                       compatible = "qcom,ehci-host";
> +                       compatible = "qcom,ci-hdrc";
>                         reg = <0x78d9000 0x400>;
>                         phys = <&ehci_phy>;
> -               };
>
> -               ehci_phy: ehci_phy@78d9000 {
> -                       compatible = "qcom,apq8016-usbphy";
> -                       reg = <0x78d9000 0x400>;
> -                       #phy-cells = <0>;
> +                       ulpi {
> +                               usb_hs_phy: phy {
> +                                       compatible = "qcom,usb-hs-phy-msm8916",
> +                                                    "qcom,usb-hs-phy";
> +                                       #phy-cells = <0>;
> +                                       clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> +                                       clock-names = "ref", "sleep";
> +                                       resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
> +                                       reset-names = "phy", "por";
> +                                       qcom,init-seq = /bits/ 8 <0x0 0x44>,
> +                                                                <0x1 0x6b>,
> +                                                                <0x2 0x24>,
> +                                                                <0x3 0x13>;
> +                               };
> +                       };
>                 };
>
>                 sdhci@07824000 {
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 350e0e9e20aa..1adac07569ae 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -9,6 +9,7 @@
>  #include <common.h>
>  #include <cpu_func.h>
>  #include <dm.h>
> +#include <dm/pinctrl.h>
>  #include <env.h>
>  #include <init.h>
>  #include <net.h>
> @@ -23,84 +24,32 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -int dram_init(void)
> -{
> -       gd->ram_size = PHYS_SDRAM_1_SIZE;
> -
> -       return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> -       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> -       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -
> -       return 0;
> -}
> +#define USB_HUB_RESET_GPIO 2
> +#define USB_SW_SELECT_GPIO 3
>
>  int board_usb_init(int index, enum usb_init_type init)
>  {
> -       static struct udevice *pmic_gpio;
> -       static struct gpio_desc hub_reset, usb_sel;
> -       int ret = 0, node;
> +       struct udevice *usb;
> +       int ret = 0;
>
> -       if (!pmic_gpio) {
> -               ret = uclass_get_device_by_name(UCLASS_GPIO,
> -                                               "pm8916_gpios@c000",
> -                                               &pmic_gpio);
> -               if (ret < 0) {
> -                       printf("Failed to find pm8916_gpios@c000 node.\n");
> -                       return ret;
> -               }
> +       /* USB device */
> +       ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
> +       if (ret) {
> +               printf("Cannot find USB device\n");
> +               return ret;
>         }
>
> -       /* Try to request gpios needed to start usb host on dragonboard */
> -       if (!dm_gpio_is_valid(&hub_reset)) {
> -               node = fdt_subnode_offset(gd->fdt_blob,
> -                                         dev_of_offset(pmic_gpio),
> -                                         "usb_hub_reset_pm");
> -               if (node < 0) {
> -                       printf("Failed to find usb_hub_reset_pm dt node.\n");
> -                       return node;
> -               }
> -               ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
> -                                                "gpios", 0, &hub_reset, 0);
> -               if (ret < 0) {
> -                       printf("Failed to request usb_hub_reset_pm gpio.\n");
> -                       return ret;
> -               }
> -       }
> -
> -       if (!dm_gpio_is_valid(&usb_sel)) {
> -               node = fdt_subnode_offset(gd->fdt_blob,
> -                                         dev_of_offset(pmic_gpio),
> -                                         "usb_sw_sel_pm");
> -               if (node < 0) {
> -                       printf("Failed to find usb_sw_sel_pm dt node.\n");
> -                       return 0;
> -               }
> -               ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
> -                                                "gpios", 0, &usb_sel, 0);
> -               if (ret < 0) {
> -                       printf("Failed to request usb_sw_sel_pm gpio.\n");
> -                       return ret;
> -               }
> -       }
> -
> -       if (init == USB_INIT_HOST) {
> -               /* Start USB Hub */
> -               dm_gpio_set_dir_flags(&hub_reset,
> -                                     GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
> -               mdelay(100);
> -               /* Switch usb to host connectors */
> -               dm_gpio_set_dir_flags(&usb_sel,
> -                                     GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
> -               mdelay(100);
> -       } else { /* Device */
> -               /* Disable hub */
> -               dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
> -               /* Switch back to device connector */
> -               dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
> +       /* Select "default" or "device" pinctrl */
> +       switch (init) {
> +       case USB_INIT_HOST:
> +               pinctrl_select_state(usb, "default");
> +               break;
> +       case USB_INIT_DEVICE:
> +               pinctrl_select_state(usb, "device");
> +               break;
> +       default:
> +               debug("Unknown usb_init_type %d\n", init);
> +               break;
>         }
>
>         return 0;
> diff --git a/doc/device-tree-bindings/usb/ehci-msm.txt b/doc/device-tree-bindings/usb/ehci-msm.txt
> deleted file mode 100644
> index 205bb07220fb..000000000000
> --- a/doc/device-tree-bindings/usb/ehci-msm.txt
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
> -
> -Required properties:
> -- compatible: must be "qcom,ehci-host"
> -- reg: start address and size of the registers
> -
> -ehci@78d9000 {
> -       compatible = "qcom,ehci-host";
> -       reg = <0x78d9000 0x400>;
> -};
> diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
> index 0af7191cff52..9de0ad5ed32d 100644
> --- a/drivers/clk/qcom/clock-apq8016.c
> +++ b/drivers/clk/qcom/clock-apq8016.c
> @@ -13,6 +13,7 @@
>  #include <errno.h>
>  #include <asm/io.h>
>  #include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8916.h>
>
>  #include "clock-qcom.h"
>
> @@ -125,13 +126,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
>         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>
>         switch (clk->id) {
> -       case 0: /* SDC1 */
> +       case GCC_SDCC1_APPS_CLK: /* SDC1 */
>                 return clk_init_sdc(priv, 0, rate);
>                 break;
> -       case 1: /* SDC2 */
> +       case GCC_SDCC2_APPS_CLK: /* SDC2 */
>                 return clk_init_sdc(priv, 1, rate);
>                 break;
> -       case 4: /* UART2 */
> +       case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
>                 return clk_init_uart(priv);
>                 break;
>         default:
> diff --git a/drivers/phy/qcom/msm8916-usbh-phy.c b/drivers/phy/qcom/msm8916-usbh-phy.c
> index 7c9d030a4d8a..f52046f7cb02 100644
> --- a/drivers/phy/qcom/msm8916-usbh-phy.c
> +++ b/drivers/phy/qcom/msm8916-usbh-phy.c
> @@ -74,7 +74,7 @@ static int msm_phy_probe(struct udevice *dev)
>  {
>         struct msm_phy_priv *priv = dev_get_priv(dev);
>
> -       priv->regs = dev_remap_addr(dev);
> +       priv->regs = dev_remap_addr(dev_get_parent(dev));
>         if (!priv->regs)
>                 return -EINVAL;
>
> @@ -96,7 +96,7 @@ static struct phy_ops msm_phy_ops = {
>  };
>
>  static const struct udevice_id msm_phy_ids[] = {
> -       { .compatible = "qcom,apq8016-usbphy" },
> +       { .compatible = "qcom,usb-hs-phy-msm8916" },
>         { }
>  };
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index df5bd1c19f6e..c8f4eeae6082 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -29,7 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
>  };
>
>  static const struct pinctrl_function msm_pinctrl_functions[] = {
> -       {"blsp1_uart", 2},
> +       {"blsp_uart2", 2},
>  };
>
>  static const char *apq8016_get_function_name(struct udevice *dev,
> diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
> index dd0d153500cb..98fe7bc3bcb1 100644
> --- a/drivers/usb/host/ehci-msm.c
> +++ b/drivers/usb/host/ehci-msm.c
> @@ -9,6 +9,7 @@
>
>  #include <common.h>
>  #include <dm.h>
> +#include <dm/lists.h>
>  #include <errno.h>
>  #include <usb.h>
>  #include <usb/ehci-ci.h>
> @@ -119,6 +120,24 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
>         return 0;
>  }
>
> +static int ehci_usb_of_bind(struct udevice *dev)
> +{
> +       ofnode ulpi_node = ofnode_first_subnode(dev_ofnode(dev));
> +       ofnode phy_node;
> +
> +       if (!ofnode_valid(ulpi_node))
> +               return 0;
> +
> +       phy_node = ofnode_first_subnode(ulpi_node);
> +       if (!ofnode_valid(phy_node)) {
> +               printf("%s: ulpi subnode with no phy\n", __func__);
> +               return -ENOENT;
> +       }
> +
> +       return device_bind_driver_to_node(dev, "msm8916_usbphy", "msm8916_usbphy",
> +                                         phy_node, NULL);
> +}
> +
>  #if defined(CONFIG_CI_UDC)
>  /* Little quirk that MSM needs with Chipidea controller
>   * Must reinit phy after reset
> @@ -132,7 +151,7 @@ void ci_init_after_reset(struct ehci_ctrl *ctrl)
>  #endif
>
>  static const struct udevice_id ehci_usb_ids[] = {
> -       { .compatible = "qcom,ehci-host", },
> +       { .compatible = "qcom,ci-hdrc", },
>         { }
>  };
>
> @@ -141,6 +160,7 @@ U_BOOT_DRIVER(usb_ehci) = {
>         .id     = UCLASS_USB,
>         .of_match = ehci_usb_ids,
>         .of_to_plat = ehci_usb_of_to_plat,
> +       .bind = ehci_usb_of_bind,
>         .probe = ehci_usb_probe,
>         .remove = ehci_usb_remove,
>         .ops    = &ehci_usb_ops,
> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
> new file mode 100644
> index 000000000000..563034406184
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
> @@ -0,0 +1,179 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2015 Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
> +#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
> +
> +#define GPLL0                                  0
> +#define GPLL0_VOTE                             1
> +#define BIMC_PLL                               2
> +#define BIMC_PLL_VOTE                          3
> +#define GPLL1                                  4
> +#define GPLL1_VOTE                             5
> +#define GPLL2                                  6
> +#define GPLL2_VOTE                             7
> +#define PCNOC_BFDCD_CLK_SRC                    8
> +#define SYSTEM_NOC_BFDCD_CLK_SRC               9
> +#define CAMSS_AHB_CLK_SRC                      10
> +#define APSS_AHB_CLK_SRC                       11
> +#define CSI0_CLK_SRC                           12
> +#define CSI1_CLK_SRC                           13
> +#define GFX3D_CLK_SRC                          14
> +#define VFE0_CLK_SRC                           15
> +#define BLSP1_QUP1_I2C_APPS_CLK_SRC            16
> +#define BLSP1_QUP1_SPI_APPS_CLK_SRC            17
> +#define BLSP1_QUP2_I2C_APPS_CLK_SRC            18
> +#define BLSP1_QUP2_SPI_APPS_CLK_SRC            19
> +#define BLSP1_QUP3_I2C_APPS_CLK_SRC            20
> +#define BLSP1_QUP3_SPI_APPS_CLK_SRC            21
> +#define BLSP1_QUP4_I2C_APPS_CLK_SRC            22
> +#define BLSP1_QUP4_SPI_APPS_CLK_SRC            23
> +#define BLSP1_QUP5_I2C_APPS_CLK_SRC            24
> +#define BLSP1_QUP5_SPI_APPS_CLK_SRC            25
> +#define BLSP1_QUP6_I2C_APPS_CLK_SRC            26
> +#define BLSP1_QUP6_SPI_APPS_CLK_SRC            27
> +#define BLSP1_UART1_APPS_CLK_SRC               28
> +#define BLSP1_UART2_APPS_CLK_SRC               29
> +#define CCI_CLK_SRC                            30
> +#define CAMSS_GP0_CLK_SRC                      31
> +#define CAMSS_GP1_CLK_SRC                      32
> +#define JPEG0_CLK_SRC                          33
> +#define MCLK0_CLK_SRC                          34
> +#define MCLK1_CLK_SRC                          35
> +#define CSI0PHYTIMER_CLK_SRC                   36
> +#define CSI1PHYTIMER_CLK_SRC                   37
> +#define CPP_CLK_SRC                            38
> +#define CRYPTO_CLK_SRC                         39
> +#define GP1_CLK_SRC                            40
> +#define GP2_CLK_SRC                            41
> +#define GP3_CLK_SRC                            42
> +#define BYTE0_CLK_SRC                          43
> +#define ESC0_CLK_SRC                           44
> +#define MDP_CLK_SRC                            45
> +#define PCLK0_CLK_SRC                          46
> +#define VSYNC_CLK_SRC                          47
> +#define PDM2_CLK_SRC                           48
> +#define SDCC1_APPS_CLK_SRC                     49
> +#define SDCC2_APPS_CLK_SRC                     50
> +#define APSS_TCU_CLK_SRC                       51
> +#define USB_HS_SYSTEM_CLK_SRC                  52
> +#define VCODEC0_CLK_SRC                                53
> +#define GCC_BLSP1_AHB_CLK                      54
> +#define GCC_BLSP1_SLEEP_CLK                    55
> +#define GCC_BLSP1_QUP1_I2C_APPS_CLK            56
> +#define GCC_BLSP1_QUP1_SPI_APPS_CLK            57
> +#define GCC_BLSP1_QUP2_I2C_APPS_CLK            58
> +#define GCC_BLSP1_QUP2_SPI_APPS_CLK            59
> +#define GCC_BLSP1_QUP3_I2C_APPS_CLK            60
> +#define GCC_BLSP1_QUP3_SPI_APPS_CLK            61
> +#define GCC_BLSP1_QUP4_I2C_APPS_CLK            62
> +#define GCC_BLSP1_QUP4_SPI_APPS_CLK            63
> +#define GCC_BLSP1_QUP5_I2C_APPS_CLK            64
> +#define GCC_BLSP1_QUP5_SPI_APPS_CLK            65
> +#define GCC_BLSP1_QUP6_I2C_APPS_CLK            66
> +#define GCC_BLSP1_QUP6_SPI_APPS_CLK            67
> +#define GCC_BLSP1_UART1_APPS_CLK               68
> +#define GCC_BLSP1_UART2_APPS_CLK               69
> +#define GCC_BOOT_ROM_AHB_CLK                   70
> +#define GCC_CAMSS_CCI_AHB_CLK                  71
> +#define GCC_CAMSS_CCI_CLK                      72
> +#define GCC_CAMSS_CSI0_AHB_CLK                 73
> +#define GCC_CAMSS_CSI0_CLK                     74
> +#define GCC_CAMSS_CSI0PHY_CLK                  75
> +#define GCC_CAMSS_CSI0PIX_CLK                  76
> +#define GCC_CAMSS_CSI0RDI_CLK                  77
> +#define GCC_CAMSS_CSI1_AHB_CLK                 78
> +#define GCC_CAMSS_CSI1_CLK                     79
> +#define GCC_CAMSS_CSI1PHY_CLK                  80
> +#define GCC_CAMSS_CSI1PIX_CLK                  81
> +#define GCC_CAMSS_CSI1RDI_CLK                  82
> +#define GCC_CAMSS_CSI_VFE0_CLK                 83
> +#define GCC_CAMSS_GP0_CLK                      84
> +#define GCC_CAMSS_GP1_CLK                      85
> +#define GCC_CAMSS_ISPIF_AHB_CLK                        86
> +#define GCC_CAMSS_JPEG0_CLK                    87
> +#define GCC_CAMSS_JPEG_AHB_CLK                 88
> +#define GCC_CAMSS_JPEG_AXI_CLK                 89
> +#define GCC_CAMSS_MCLK0_CLK                    90
> +#define GCC_CAMSS_MCLK1_CLK                    91
> +#define GCC_CAMSS_MICRO_AHB_CLK                        92
> +#define GCC_CAMSS_CSI0PHYTIMER_CLK             93
> +#define GCC_CAMSS_CSI1PHYTIMER_CLK             94
> +#define GCC_CAMSS_AHB_CLK                      95
> +#define GCC_CAMSS_TOP_AHB_CLK                  96
> +#define GCC_CAMSS_CPP_AHB_CLK                  97
> +#define GCC_CAMSS_CPP_CLK                      98
> +#define GCC_CAMSS_VFE0_CLK                     99
> +#define GCC_CAMSS_VFE_AHB_CLK                  100
> +#define GCC_CAMSS_VFE_AXI_CLK                  101
> +#define GCC_CRYPTO_AHB_CLK                     102
> +#define GCC_CRYPTO_AXI_CLK                     103
> +#define GCC_CRYPTO_CLK                         104
> +#define GCC_OXILI_GMEM_CLK                     105
> +#define GCC_GP1_CLK                            106
> +#define GCC_GP2_CLK                            107
> +#define GCC_GP3_CLK                            108
> +#define GCC_MDSS_AHB_CLK                       109
> +#define GCC_MDSS_AXI_CLK                       110
> +#define GCC_MDSS_BYTE0_CLK                     111
> +#define GCC_MDSS_ESC0_CLK                      112
> +#define GCC_MDSS_MDP_CLK                       113
> +#define GCC_MDSS_PCLK0_CLK                     114
> +#define GCC_MDSS_VSYNC_CLK                     115
> +#define GCC_MSS_CFG_AHB_CLK                    116
> +#define GCC_OXILI_AHB_CLK                      117
> +#define GCC_OXILI_GFX3D_CLK                    118
> +#define GCC_PDM2_CLK                           119
> +#define GCC_PDM_AHB_CLK                                120
> +#define GCC_PRNG_AHB_CLK                       121
> +#define GCC_SDCC1_AHB_CLK                      122
> +#define GCC_SDCC1_APPS_CLK                     123
> +#define GCC_SDCC2_AHB_CLK                      124
> +#define GCC_SDCC2_APPS_CLK                     125
> +#define GCC_GTCU_AHB_CLK                       126
> +#define GCC_JPEG_TBU_CLK                       127
> +#define GCC_MDP_TBU_CLK                                128
> +#define GCC_SMMU_CFG_CLK                       129
> +#define GCC_VENUS_TBU_CLK                      130
> +#define GCC_VFE_TBU_CLK                                131
> +#define GCC_USB2A_PHY_SLEEP_CLK                        132
> +#define GCC_USB_HS_AHB_CLK                     133
> +#define GCC_USB_HS_SYSTEM_CLK                  134
> +#define GCC_VENUS0_AHB_CLK                     135
> +#define GCC_VENUS0_AXI_CLK                     136
> +#define GCC_VENUS0_VCODEC0_CLK                 137
> +#define BIMC_DDR_CLK_SRC                       138
> +#define GCC_APSS_TCU_CLK                       139
> +#define GCC_GFX_TCU_CLK                                140
> +#define BIMC_GPU_CLK_SRC                       141
> +#define GCC_BIMC_GFX_CLK                       142
> +#define GCC_BIMC_GPU_CLK                       143
> +#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC         144
> +#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC         145
> +#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC         146
> +#define ULTAUDIO_XO_CLK_SRC                    147
> +#define ULTAUDIO_AHBFABRIC_CLK_SRC             148
> +#define CODEC_DIGCODEC_CLK_SRC                 149
> +#define GCC_ULTAUDIO_PCNOC_MPORT_CLK           150
> +#define GCC_ULTAUDIO_PCNOC_SWAY_CLK            151
> +#define GCC_ULTAUDIO_AVSYNC_XO_CLK             152
> +#define GCC_ULTAUDIO_STC_XO_CLK                        153
> +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK    154
> +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK        155
> +#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK         156
> +#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK         157
> +#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK         158
> +#define GCC_CODEC_DIGCODEC_CLK                 159
> +#define GCC_MSS_Q6_BIMC_AXI_CLK                        160
> +
> +/* Indexes for GDSCs */
> +#define BIMC_GDSC                              0
> +#define VENUS_GDSC                             1
> +#define MDSS_GDSC                              2
> +#define JPEG_GDSC                              3
> +#define VFE_GDSC                               4
> +#define OXILI_GDSC                             5
> +
> +#endif
>
> --
> 2.43.1
>

Re: [PATCH v4 18/39] board: dragonboard410c: import board code from mach-snapdragon

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Some of the db410c board support code was written to be generic and
> placed in mach-snapdragon. However, as the db410c is the only board
> using this, move the code out of mach-snapdragon. This makes is more

s/makes is more/makes it more/

> obvious what code is relevant for which targets and helps tidy things up
> a little more.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/Makefile                |  2 -
>  arch/arm/mach-snapdragon/dram.c                  | 99 ------------------------
>  arch/arm/mach-snapdragon/include/mach/dram.h     | 12 ---
>  arch/arm/mach-snapdragon/include/mach/misc.h     | 13 ----
>  arch/arm/mach-snapdragon/misc.c                  | 55 -------------
>  board/qualcomm/dragonboard410c/Makefile          |  2 +-
>  board/qualcomm/dragonboard410c/dragonboard410c.c | 48 +++++++++++-
>  7 files changed, 45 insertions(+), 186 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
> index 3a3a297c1768..d02432df8b04 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -6,6 +6,4 @@ obj-$(CONFIG_SDM845) += sysmap-sdm845.o
>  obj-$(CONFIG_SDM845) += init_sdm845.o
>  obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
>  obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
> -obj-y += misc.o
> -obj-y += dram.o
>  obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
> diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
> deleted file mode 100644
> index 499dfdf0da6e..000000000000
> --- a/arch/arm/mach-snapdragon/dram.c
> +++ /dev/null
> @@ -1,99 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Onboard memory detection for Snapdragon boards
> - *
> - * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
> - *
> - */
> -
> -#include <common.h>
> -#include <dm.h>
> -#include <log.h>
> -#include <part.h>
> -#include <smem.h>
> -#include <fdt_support.h>
> -#include <asm/arch/dram.h>
> -
> -#define SMEM_USABLE_RAM_PARTITION_TABLE 402
> -#define RAM_PART_NAME_LENGTH            16
> -#define RAM_NUM_PART_ENTRIES            32
> -#define CATEGORY_SDRAM 0x0E
> -#define TYPE_SYSMEM 0x01
> -
> -struct smem_ram_ptable_hdr {
> -       u32 magic[2];
> -       u32 version;
> -       u32 reserved;
> -       u32 len;
> -} __attribute__ ((__packed__));
> -
> -struct smem_ram_ptn {
> -       char name[RAM_PART_NAME_LENGTH];
> -       u64 start;
> -       u64 size;
> -       u32 attr;
> -       u32 category;
> -       u32 domain;
> -       u32 type;
> -       u32 num_partitions;
> -       u32 reserved[3];
> -} __attribute__ ((__packed__));
> -
> -struct smem_ram_ptable {
> -       struct smem_ram_ptable_hdr hdr;
> -       u32 reserved;     /* Added for 8 bytes alignment of header */
> -       struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
> -} __attribute__ ((__packed__));
> -
> -#ifndef MEMORY_BANKS_MAX
> -#define MEMORY_BANKS_MAX 4
> -#endif
> -
> -int msm_fixup_memory(void *blob)
> -{
> -       u64 bank_start[MEMORY_BANKS_MAX];
> -       u64 bank_size[MEMORY_BANKS_MAX];
> -       size_t size;
> -       int i;
> -       int count = 0;
> -       struct udevice *smem;
> -       int ret;
> -       struct smem_ram_ptable *ram_ptable;
> -       struct smem_ram_ptn *p;
> -
> -       ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem);
> -       if (ret < 0) {
> -               printf("Failed to find SMEM node. Check device tree\n");
> -               return 0;
> -       }
> -
> -       ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size);
> -
> -       if (!ram_ptable) {
> -               printf("Failed to find SMEM partition.\n");
> -               return -ENODEV;
> -       }
> -
> -       /* Check validy of RAM */
> -       for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
> -               p = &ram_ptable->parts[i];
> -               if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
> -                       bank_start[count] = p->start;
> -                       bank_size[count] = p->size;
> -                       debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n",
> -                                       count, p->start, p->size);
> -                       count++;
> -               }
> -       }
> -
> -       if (!count) {
> -               printf("Failed to detect any memory bank\n");
> -               return -ENODEV;
> -       }
> -
> -       ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
> -       if (ret)
> -               return ret;
> -
> -       return 0;
> -}
> diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h b/arch/arm/mach-snapdragon/include/mach/dram.h
> deleted file mode 100644
> index 0a9eedda414c..000000000000
> --- a/arch/arm/mach-snapdragon/include/mach/dram.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Snapdragon DRAM
> - * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
> - */
> -
> -#ifndef DRAM_H
> -#define DRAM_H
> -
> -int msm_fixup_memory(void *blob);
> -
> -#endif
> diff --git a/arch/arm/mach-snapdragon/include/mach/misc.h b/arch/arm/mach-snapdragon/include/mach/misc.h
> deleted file mode 100644
> index c60e3e472470..000000000000
> --- a/arch/arm/mach-snapdragon/include/mach/misc.h
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Snapdragon DRAM
> - * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
> - */
> -
> -#ifndef MISC_H
> -#define MISC_H
> -
> -u32 msm_board_serial(void);
> -void msm_generate_mac_addr(u8 *mac);
> -
> -#endif
> diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c
> deleted file mode 100644
> index 7d452f4529b7..000000000000
> --- a/arch/arm/mach-snapdragon/misc.c
> +++ /dev/null
> @@ -1,55 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Miscellaneous Snapdragon functionality
> - *
> - * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
> - *
> - */
> -
> -#include <common.h>
> -#include <mmc.h>
> -#include <asm/arch/misc.h>
> -#include <asm/unaligned.h>
> -
> -/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
> -#define UNSTUFF_BITS(resp, start, size) \
> -       ({ \
> -               const int __size = size; \
> -               const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
> -               const int __off = 3 - ((start) / 32); \
> -               const int __shft = (start) & 31; \
> -               u32 __res; \
> -                                       \
> -               __res = resp[__off] >> __shft; \
> -               if (__size + __shft > 32) \
> -                       __res |= resp[__off - 1] << ((32 - __shft) % 32); \
> -               __res & __mask; \
> -       })
> -
> -u32 msm_board_serial(void)
> -{
> -       struct mmc *mmc_dev;
> -
> -       mmc_dev = find_mmc_device(0);
> -       if (!mmc_dev)
> -               return 0;
> -
> -       if (mmc_init(mmc_dev))
> -               return 0;
> -
> -       return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
> -}
> -
> -void msm_generate_mac_addr(u8 *mac)
> -{
> -       /* use locally adminstrated pool */
> -       mac[0] = 0x02;
> -       mac[1] = 0x00;
> -
> -       /*
> -        * Put the 32-bit serial number in the last 32-bit of the MAC address.
> -        * Use big endian order so it is consistent with the serial number
> -        * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
> -        */
> -       put_unaligned_be32(msm_board_serial(), &mac[2]);
> -}
> diff --git a/board/qualcomm/dragonboard410c/Makefile b/board/qualcomm/dragonboard410c/Makefile
> index 1b99c8b0efef..189f83813325 100644
> --- a/board/qualcomm/dragonboard410c/Makefile
> +++ b/board/qualcomm/dragonboard410c/Makefile
> @@ -2,4 +2,4 @@
>  #
>  # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
>
> -obj-y  := dragonboard410c.o
> +obj-y := dragonboard410c.o
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 1adac07569ae..40b5448c6ef1 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -12,14 +12,13 @@
>  #include <dm/pinctrl.h>
>  #include <env.h>
>  #include <init.h>
> +#include <mmc.h>
>  #include <net.h>
>  #include <usb.h>
>  #include <asm/cache.h>
>  #include <asm/global_data.h>
>  #include <asm/gpio.h>
>  #include <fdt_support.h>
> -#include <asm/arch/dram.h>
> -#include <asm/arch/misc.h>
>  #include <linux/delay.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -55,6 +54,49 @@ int board_usb_init(int index, enum usb_init_type init)
>         return 0;
>  }
>
> +/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
> +#define UNSTUFF_BITS(resp, start, size) \
> +       ({ \
> +               const int __size = size; \
> +               const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
> +               const int __off = 3 - ((start) / 32); \
> +               const int __shft = (start) & 31; \
> +               u32 __res; \
> +                                       \
> +               __res = resp[__off] >> __shft; \
> +               if (__size + __shft > 32) \
> +                       __res |= resp[__off - 1] << ((32 - __shft) % 32); \
> +               __res & __mask; \
> +       })
> +
> +static u32 msm_board_serial(void)
> +{
> +       struct mmc *mmc_dev;
> +
> +       mmc_dev = find_mmc_device(0);
> +       if (!mmc_dev)
> +               return 0;
> +
> +       if (mmc_init(mmc_dev))
> +               return 0;
> +
> +       return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
> +}
> +
> +static void msm_generate_mac_addr(u8 *mac)
> +{
> +       /* use locally adminstrated pool */
> +       mac[0] = 0x02;
> +       mac[1] = 0x00;
> +
> +       /*
> +        * Put the 32-bit serial number in the last 32-bit of the MAC address.
> +        * Use big endian order so it is consistent with the serial number
> +        * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
> +        */
> +       put_unaligned_be32(msm_board_serial(), &mac[2]);
> +}
> +
>  /* Check for vol- button - if pressed - stop autoboot */
>  int misc_init_r(void)
>  {
> @@ -103,8 +145,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
>  {
>         u8 mac[ARP_HLEN];
>
> -       msm_fixup_memory(blob);
> -
>         if (!eth_env_get_enetaddr("wlanaddr", mac)) {
>                 msm_generate_mac_addr(mac);
>         };
>
> --
> 2.43.1
>

Re: [PATCH v4 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> db820c predated support for prepending the kernel image header
> automatically, drop it's custom linker script and head.S in favour of
> this generic support.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/Kconfig          |   1 +
>  board/qualcomm/dragonboard820c/Makefile   |   1 -
>  board/qualcomm/dragonboard820c/head.S     |  33 ---------
>  board/qualcomm/dragonboard820c/u-boot.lds | 111 ------------------------------
>  4 files changed, 1 insertion(+), 145 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
> index ad6671081910..f897c393464f 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C
>
>  config TARGET_DRAGONBOARD820C
>         bool "96Boards Dragonboard 820C"
> +       select LINUX_KERNEL_IMAGE_HEADER
>         imply CLK_QCOM_APQ8096
>         imply PINCTRL_QCOM_APQ8096
>         imply BUTTON_QCOM_PMIC
> diff --git a/board/qualcomm/dragonboard820c/Makefile b/board/qualcomm/dragonboard820c/Makefile
> index 643311f5b3ba..2ae6d16364aa 100644
> --- a/board/qualcomm/dragonboard820c/Makefile
> +++ b/board/qualcomm/dragonboard820c/Makefile
> @@ -3,4 +3,3 @@
>  # (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
>
>  obj-y  := dragonboard820c.o
> -extra-y += head.o
> diff --git a/board/qualcomm/dragonboard820c/head.S b/board/qualcomm/dragonboard820c/head.S
> deleted file mode 100644
> index b052a858fd32..000000000000
> --- a/board/qualcomm/dragonboard820c/head.S
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * ARM64 header for proper chain-loading with Little Kernel.
> - *
> - * Little Kernel shipped with Dragonboard820C boots standard Linux images for
> - * ARM64. This file adds header that is required to boot U-Boot properly.
> - *
> - * For details see:
> - * https://www.kernel.org/doc/Documentation/arm64/booting.txt
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - */
> -
> -#include <config.h>
> -
> -/*
> - *   per document in linux/Doc/arm64/booting.text
> - */
> -.global _arm64_header
> -_arm64_header:
> -       b _start
> -       .word 0
> -       .quad   CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
> -       .quad   0    /* Effective size of kernel image, little-endian */
> -       .quad   0    /* kernel flags, little-endian */
> -       .quad   0    /* reserved */
> -       .quad   0    /* reserved */
> -       .quad   0    /* reserved */
> -       .byte   0x41 /* Magic number, "ARM\x64" */
> -       .byte   0x52
> -       .byte   0x4d
> -       .byte   0x64
> -       .word   0    /* reserved (used for PE COFF offset) */
> diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds
> deleted file mode 100644
> index 5251b59fbe76..000000000000
> --- a/board/qualcomm/dragonboard820c/u-boot.lds
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Override linker script for fastboot-readable images
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - *
> - * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
> - */
> -
> -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
> -OUTPUT_ARCH(aarch64)
> -ENTRY(_arm64_header)
> -SECTIONS
> -{
> -       . = 0x00000000;
> -
> -       . = ALIGN(8);
> -       .text :
> -       {
> -               *(.__image_copy_start)
> -               board/qualcomm/dragonboard820c/head.o (.text*)
> -               CPUDIR/start.o (.text*)
> -       }
> -
> -       /* This needs to come before *(.text*) */
> -       .efi_runtime : {
> -                __efi_runtime_start = .;
> -               *(.text.efi_runtime*)
> -               *(.rodata.efi_runtime*)
> -               *(.data.efi_runtime*)
> -                __efi_runtime_stop = .;
> -       }
> -
> -       .text_rest :
> -       {
> -               *(.text*)
> -       }
> -
> -       . = ALIGN(8);
> -       .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> -
> -       . = ALIGN(8);
> -       .data : {
> -               *(.data*)
> -       }
> -
> -       . = ALIGN(8);
> -
> -       . = .;
> -
> -       . = ALIGN(8);
> -       __u_boot_list : {
> -               KEEP(*(SORT(__u_boot_list*)));
> -       }
> -
> -       . = ALIGN(8);
> -
> -       .efi_runtime_rel : {
> -                __efi_runtime_rel_start = .;
> -               *(.rel*.efi_runtime)
> -               *(.rel*.efi_runtime.*)
> -                __efi_runtime_rel_stop = .;
> -       }
> -
> -       . = ALIGN(8);
> -
> -       .image_copy_end :
> -       {
> -               *(.__image_copy_end)
> -       }
> -
> -       . = ALIGN(8);
> -
> -       .rel_dyn_start :
> -       {
> -               *(.__rel_dyn_start)
> -       }
> -
> -       .rela.dyn : {
> -               *(.rela*)
> -       }
> -
> -       .rel_dyn_end :
> -       {
> -               *(.__rel_dyn_end)
> -       }
> -
> -       _end = .;
> -
> -       . = ALIGN(8);
> -
> -       .bss_start : {
> -               KEEP(*(.__bss_start));
> -       }
> -
> -       .bss : {
> -               *(.bss*)
> -                . = ALIGN(8);
> -       }
> -
> -       .bss_end : {
> -               KEEP(*(.__bss_end));
> -       }
> -
> -       /DISCARD/ : { *(.dynsym) }
> -       /DISCARD/ : { *(.dynstr*) }
> -       /DISCARD/ : { *(.dynamic*) }
> -       /DISCARD/ : { *(.plt*) }
> -       /DISCARD/ : { *(.interp*) }
> -       /DISCARD/ : { *(.gnu*) }
> -}
>
> --
> 2.43.1
>

Re: [PATCH v4 20/39] mach-snapdragon: generalise board support

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot,
> in many cases to the specific SoC but also to the board itself (e.g.
> memory map). This has been largely resolved by modernising the Qualcomm
> drivers in U-Boot, however the board code still largely follows this
> model.
>
> This patch removes the board specific memory maps and duplicated board
> init code, replacing it with generic init code.
>
> The memory map is now built at runtime based on data read from DT, this
> allows for the memory map to be provided without having to recompile
> U-Boot. Support is also added for booting with appended DTBs, so that
> the first-stage bootloader can populate the memory map for us.
>
> The sdm845 specific init code is dropped entirely, it set an environment
> variable depending on if a button was pressed, but this variable wasn't
> used in U-Boot, and could be written to use the button command instead.
>
> The KASLR detection is also dropped as with appended dtb, the kaslr seed
> can be read directly from the DTB passed to U-Boot.
>
> A new qcom_defconfig is added, with the aim of providing a generic
> U-Boot configuration that will work on as many Qualcomm boards as
> possible. It replaces the defconfig files for the Dragonboard 845c,
> Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as
> they still have some board code left.
>
> Similarly, the config headers for db845c, starqltechn, and qcs404-evb
> are replaced by a single qcom header.
>
> The previously db410c-specific board_usb_init() function is made to be
> generic and is added to mach-snapdragon. While we lack proper modelling
> for USB configuration, using a well-known named pinctrl state is a
> reasonably generic middleground, and works using upstream DT. This
> function will do nothing unless the USB node has a pinctrl state named
> "device", in which case it will be set when entering USB peripheral
> mode.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/Kconfig                                 |   3 +
>  arch/arm/dts/Makefile                            |   9 +-
>  arch/arm/mach-snapdragon/Kconfig                 |  96 ++--------
>  arch/arm/mach-snapdragon/Makefile                |   6 +-
>  arch/arm/mach-snapdragon/board.c                 | 215 +++++++++++++++++++++++
>  arch/arm/mach-snapdragon/init_sdm845.c           |  73 --------
>  arch/arm/mach-snapdragon/sysmap-apq8016.c        |  31 ----
>  arch/arm/mach-snapdragon/sysmap-apq8096.c        |  31 ----
>  arch/arm/mach-snapdragon/sysmap-qcs404.c         |  43 -----
>  arch/arm/mach-snapdragon/sysmap-sdm845.c         |  31 ----
>  board/qualcomm/dragonboard410c/Kconfig           |  15 --
>  board/qualcomm/dragonboard410c/dragonboard410c.c |  41 -----
>  board/qualcomm/dragonboard820c/Kconfig           |  15 --
>  board/qualcomm/dragonboard820c/dragonboard820c.c |  39 +---
>  board/qualcomm/dragonboard845c/Kconfig           |  12 --
>  board/qualcomm/qcs404-evb/Kconfig                |  15 --
>  board/qualcomm/qcs404-evb/qcs404-evb.c           |  21 +--
>  configs/dragonboard410c_defconfig                |   6 +-
>  configs/dragonboard820c_defconfig                |   6 +-
>  configs/dragonboard845c_defconfig                |  29 ---
>  configs/qcom_defconfig                           |  67 +++++++
>  configs/qcs404evb_defconfig                      |   5 +-
>  configs/starqltechn_defconfig                    |  41 -----
>  include/configs/dragonboard845c.h                |  20 ---
>  include/configs/qcom.h                           |  21 +++
>  include/configs/qcs404-evb.h                     |  20 ---
>  include/configs/sdm845.h                         |  26 ---
>  27 files changed, 345 insertions(+), 592 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 6b072be24634..672577d0ddcc 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1095,6 +1095,9 @@ config ARCH_SNAPDRAGON
>         select OF_SEPARATE
>         select SMEM
>         select SPMI
> +       select OF_BOARD
> +       select SAVE_PREV_BL_FDT_ADDR
> +       select LINUX_KERNEL_IMAGE_HEADER
>         imply CMD_DM
>
>  config ARCH_SOCFPGA
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ce10d3dbb07d..751035a577f6 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -631,10 +631,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
>
>  dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
>
> -dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
> -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
> -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
> -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
> +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
> +       dragonboard820c.dtb \
> +       dragonboard845c.dtb \
> +       starqltechn.dtb \
> +       qcs404-evb.dtb
>
>  dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
>
> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
> index f897c393464f..96e44e2c5491 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -3,6 +3,9 @@ if ARCH_SNAPDRAGON
>  config SYS_SOC
>         default "snapdragon"
>
> +config SYS_VENDOR
> +       default "qualcomm"
> +
>  config SYS_MALLOC_F_LEN
>         default 0x2000
>
> @@ -12,91 +15,24 @@ config SPL_SYS_MALLOC_F
>  config SPL_SYS_MALLOC_F_LEN
>         default 0x2000
>
> -config SDM845
> -       bool "Qualcomm Snapdragon 845 SoC"
> -       select LINUX_KERNEL_IMAGE_HEADER
> -       imply CLK_QCOM_SDM845
> -       imply PINCTRL_QCOM_SDM845
> -       imply BUTTON_QCOM_PMIC
> -
>  config LNX_KRNL_IMG_TEXT_OFFSET_BASE
>         default 0x80000000
>
> -choice
> -       prompt "Snapdragon board select"
> -
> -config TARGET_DRAGONBOARD410C
> -       bool "96Boards Dragonboard 410C"
> -       select BOARD_LATE_INIT
> -       select ENABLE_ARM_SOC_BOOT0_HOOK
> -       imply CLK_QCOM_APQ8016
> -       imply PINCTRL_QCOM_APQ8016
> -       imply BUTTON_QCOM_PMIC
> +config SYS_BOARD
> +       string "Qualcomm custom board"
>         help
> -         Support for 96Boards Dragonboard 410C. This board complies with
> -         96Board Open Platform Specifications. Features:
> -         - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> -         - 1GiB RAM
> -         - 8GiB eMMC, uSD slot
> -         - WiFi, Bluetooth and GPS module
> -         - 2x Host, 1x Device USB port
> -         - HDMI
> -         - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
> +         The Dragonboard 410c and 820c have additional board init
> +         code that isn't shared with other Qualcomm boards.
> +         Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will
> +         be used.
>
> -config TARGET_DRAGONBOARD820C
> -       bool "96Boards Dragonboard 820C"
> -       select LINUX_KERNEL_IMAGE_HEADER
> -       imply CLK_QCOM_APQ8096
> -       imply PINCTRL_QCOM_APQ8096
> -       imply BUTTON_QCOM_PMIC
> +config SYS_CONFIG_NAME
> +       string "Board configuration name"
> +       default SYS_BOARD if SYS_BOARD != ""
> +       default "qcom"
>         help
> -         Support for 96Boards Dragonboard 820C. This board complies with
> -         96Board Open Platform Specifications. Features:
> -         - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
> -         - 3GiB RAM
> -         - 32GiB UFS drive
> -
> -config TARGET_DRAGONBOARD845C
> -       bool "96Boards Dragonboard 845C"
> -       help
> -         Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
> -         Platform. This board complies with 96Boards Open Platform
> -         Specifications. Features:
> -         - Qualcomm Snapdragon SDA845 SoC
> -         - 4GiB RAM
> -         - 64GiB UFS drive
> -       select MISC_INIT_R
> -       select SDM845
> -
> -config TARGET_STARQLTECHN
> -       bool "Samsung S9 SM-G9600(starqltechn)"
> -       help
> -         Support for Samsung S9 SM-G9600(starqltechn) board.
> -         Features:
> -         - Qualcomm Snapdragon SDM845 SoC
> -         - 4GiB RAM
> -         - 64GiB UFS drive
> -       select MISC_INIT_R
> -       select SDM845
> -
> -config TARGET_QCS404EVB
> -       bool "Qualcomm Technologies, Inc. QCS404 EVB"
> -       select LINUX_KERNEL_IMAGE_HEADER
> -       imply CLK_QCOM_QCS404
> -       imply PINCTRL_QCOM_QCS404
> -       help
> -         Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
> -         Features:
> -         - Qualcomm Snapdragon QCS404 SoC
> -         - 1GiB RAM
> -         - 8GiB eMMC, uSD slot
> -
> -endchoice
> -
> -source "board/qualcomm/dragonboard410c/Kconfig"
> -source "board/qualcomm/dragonboard820c/Kconfig"
> -source "board/qualcomm/dragonboard845c/Kconfig"
> -source "board/samsung/starqltechn/Kconfig"
> -source "board/qualcomm/qcs404-evb/Kconfig"
> +         This option contains information about board configuration name.
> +         Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
> +         will be used for board configuration.
>
>  endif
> diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
> index d02432df8b04..857171e593da 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -2,8 +2,4 @@
>  #
>  # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
>
> -obj-$(CONFIG_SDM845) += sysmap-sdm845.o
> -obj-$(CONFIG_SDM845) += init_sdm845.o
> -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
> -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
> -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
> +obj-y += board.o
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> new file mode 100644
> index 000000000000..a1867852bcca
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -0,0 +1,215 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Common initialisation for Qualcomm Snapdragon boards.
> + *
> + * Copyright (c) 2024 Linaro Ltd.
> + * Author: Caleb Connolly <caleb.connolly@linaro.org>
> + */
> +
> +#include "time.h"
> +#include <asm/armv8/mmu.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/psci.h>
> +#include <asm/system.h>
> +#include <dm/device.h>
> +#include <dm/pinctrl.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/read.h>
> +#include <env.h>
> +#include <init.h>
> +#include <linux/arm-smccc.h>
> +#include <linux/bug.h>
> +#include <linux/psci.h>
> +#include <linux/sizes.h>
> +#include <malloc.h>
> +#include <usb.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
> +
> +struct mm_region *mem_map = rbx_mem_map;
> +
> +int dram_init(void)
> +{
> +       return fdtdec_setup_mem_size_base();
> +}
> +
> +static int ddr_bank_cmp(const void *v1, const void *v2)
> +{
> +       const struct {
> +               phys_addr_t start;
> +               phys_size_t size;
> +       } *res1 = v1, *res2 = v2;
> +
> +       if (!res1->size)
> +               return 1;
> +       if (!res2->size)
> +               return -1;
> +
> +       return (res1->start >> 24) - (res2->start >> 24);
> +}
> +
> +int dram_init_banksize(void)
> +{
> +       int ret;
> +
> +       ret = fdtdec_setup_memory_banksize();
> +       if (ret < 0)
> +               return ret;
> +
> +       if (CONFIG_NR_DRAM_BANKS < 2)
> +               return 0;
> +
> +       /* Sort our RAM banks -_- */
> +       qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
> +
> +       return 0;
> +}
> +
> +static void show_psci_version(void)
> +{
> +       struct arm_smccc_res res;
> +
> +       arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> +
> +       debug("PSCI:  v%ld.%ld\n",
> +             PSCI_VERSION_MAJOR(res.a0),
> +             PSCI_VERSION_MINOR(res.a0));
> +}
> +
> +void *board_fdt_blob_setup(int *err)
> +{
> +       phys_addr_t fdt;
> +       /* Return DTB pointer passed by ABL */
> +       *err = 0;
> +       fdt = get_prev_bl_fdt_addr();
> +
> +       /*
> +        * If we bail then the board will simply not boot, instead let's
> +        * try and use the FDT built into U-Boot if there is one...
> +        * This avoids having a hard dependency on the previous stage bootloader
> +        */
> +       if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
> +               debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
> +               return (void *)gd->fdt_blob;
> +       }
> +
> +       return (void *)fdt;
> +}
> +
> +void reset_cpu(void)
> +{
> +       psci_system_reset();
> +}
> +
> +/*
> + * Some Qualcomm boards require GPIO configuration when switching USB modes.
> + * Support setting this configuration via pinctrl state.
> + */
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +       struct udevice *usb;
> +       int ret = 0;
> +
> +       /* USB device */
> +       ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb);
> +       if (ret) {
> +               printf("Cannot find USB device\n");
> +               return ret;
> +       }
> +
> +       ret = dev_read_stringlist_search(usb, "pinctrl-names",
> +                                        "device");
> +       /* No "device" pinctrl state, so just bail */
> +       if (ret < 0)
> +               return 0;
> +
> +       /* Select "default" or "device" pinctrl */
> +       switch (init) {
> +       case USB_INIT_HOST:
> +               pinctrl_select_state(usb, "default");
> +               break;
> +       case USB_INIT_DEVICE:
> +               pinctrl_select_state(usb, "device");
> +               break;
> +       default:
> +               debug("Unknown usb_init_type %d\n", init);
> +               break;
> +       }
> +
> +       return 0;
> +}
> +
> +/*
> + * Some boards still need board specific init code, they can implement that by
> + * overriding this function.
> + *
> + * FIXME: get rid of board specific init code
> + */
> +void __weak qcom_board_init(void)
> +{
> +}
> +
> +int board_init(void)
> +{
> +       show_psci_version();
> +       qcom_board_init();
> +       return 0;
> +}
> +
> +static void build_mem_map(void)
> +{
> +       int i;
> +
> +       /*
> +        * Ensure the peripheral block is sized to correctly cover the address range
> +        * up to the first memory bank.
> +        * Don't map the first page to ensure that we actually trigger an abort on a
> +        * null pointer access rather than just hanging.
> +        * FIXME: we should probably split this into more precise regions
> +        */
> +       mem_map[0].phys = 0x1000;
> +       mem_map[0].virt = mem_map[0].phys;
> +       mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
> +       mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +                        PTE_BLOCK_NON_SHARE |
> +                        PTE_BLOCK_PXN | PTE_BLOCK_UXN;
> +
> +       debug("Configured memory map:\n");
> +       debug("  0x%016llx - 0x%016llx: Peripheral block\n",
> +             mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
> +
> +       /*
> +        * Now add memory map entries for each DRAM bank, ensuring we don't
> +        * overwrite the list terminator
> +        */
> +       for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
> +               if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
> +                       log_warning("Too many DRAM banks!\n");
> +                       break;
> +               }
> +               mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
> +               mem_map[i + 1].virt = mem_map[i + 1].phys;
> +               mem_map[i + 1].size = gd->bd->bi_dram[i].size;
> +               mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +                                    PTE_BLOCK_INNER_SHARE;
> +
> +               debug("  0x%016llx - 0x%016llx: DDR bank %d\n",
> +                     mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
> +       }
> +}
> +
> +u64 get_page_table_size(void)
> +{
> +       return SZ_64K;
> +}
> +
> +void enable_caches(void)
> +{
> +       build_mem_map();
> +
> +       icache_enable();
> +       dcache_enable();
> +}
> diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c
> deleted file mode 100644
> index 067acc9a6f44..000000000000
> --- a/arch/arm/mach-snapdragon/init_sdm845.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Common init part for boards based on SDM845
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> - */
> -
> -#include <button.h>
> -#include <init.h>
> -#include <env.h>
> -#include <common.h>
> -#include <asm/system.h>
> -#include <asm/gpio.h>
> -#include <dm.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int dram_init(void)
> -{
> -       return fdtdec_setup_mem_size_base();
> -}
> -
> -void reset_cpu(void)
> -{
> -       psci_system_reset();
> -}
> -
> -__weak int board_init(void)
> -{
> -       return 0;
> -}
> -
> -/* Check for vol- and power buttons */
> -__weak int misc_init_r(void)
> -{
> -       struct udevice *btn;
> -       int ret;
> -       enum button_state_t state;
> -
> -       ret = button_get_by_label("pwrkey", &btn);
> -       if (ret < 0) {
> -               printf("Couldn't find power button!\n");
> -               return ret;
> -       }
> -
> -       state = button_get_state(btn);
> -       if (state == BUTTON_ON) {
> -               env_set("key_power", "1");
> -               printf("Power button pressed\n");
> -       } else {
> -               env_set("key_power", "0");
> -       }
> -
> -       /*
> -        * search for kaslr address, set by primary bootloader by searching first
> -        * 0x100 relocated bytes at u-boot's initial load address range
> -        */
> -       uintptr_t start = gd->ram_base;
> -       uintptr_t end = start + 0x800000;
> -       u8 *addr = (u8 *)start;
> -       phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
> -       u32 block_size = 0x1000;
> -
> -       while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
> -               addr += block_size;
> -
> -       if ((uintptr_t)addr >= end)
> -               printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
> -       else
> -               env_set_addr("KASLR", addr);
> -
> -       return 0;
> -}
> diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c
> deleted file mode 100644
> index ffa3f9aa3532..000000000000
> --- a/arch/arm/mach-snapdragon/sysmap-apq8016.c
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm APQ8016 memory map
> - *
> - * (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - */
> -
> -#include <common.h>
> -#include <asm/armv8/mmu.h>
> -
> -static struct mm_region apq8016_mem_map[] = {
> -       {
> -               .virt = 0x0UL, /* Peripheral block */
> -               .phys = 0x0UL, /* Peripheral block */
> -               .size = 0x8000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> -                        PTE_BLOCK_NON_SHARE |
> -                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
> -       }, {
> -               .virt = 0x80000000UL, /* DDR */
> -               .phys = 0x80000000UL, /* DDR */
> -               .size = 0x80000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               /* List terminator */
> -               0,
> -       }
> -};
> -
> -struct mm_region *mem_map = apq8016_mem_map;
> diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c
> deleted file mode 100644
> index 0614f8308d02..000000000000
> --- a/arch/arm/mach-snapdragon/sysmap-apq8096.c
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm APQ8096 memory map
> - *
> - * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
> - */
> -
> -#include <common.h>
> -#include <asm/armv8/mmu.h>
> -
> -static struct mm_region apq8096_mem_map[] = {
> -       {
> -               .virt = 0x0UL, /* Peripheral block */
> -               .phys = 0x0UL, /* Peripheral block */
> -               .size = 0x10000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> -                        PTE_BLOCK_NON_SHARE |
> -                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
> -       }, {
> -               .virt = 0x80000000UL, /* DDR */
> -               .phys = 0x80000000UL, /* DDR */
> -               .size = 0xC0000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               /* List terminator */
> -               0,
> -       }
> -};
> -
> -struct mm_region *mem_map = apq8096_mem_map;
> diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
> deleted file mode 100644
> index 64ca4adf1bd1..000000000000
> --- a/arch/arm/mach-snapdragon/sysmap-qcs404.c
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm QCS404 memory map
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -#include <common.h>
> -#include <asm/armv8/mmu.h>
> -
> -static struct mm_region qcs404_mem_map[] = {
> -       {
> -               .virt = 0x0UL, /* Peripheral block */
> -               .phys = 0x0UL, /* Peripheral block */
> -               .size = 0x8000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> -                        PTE_BLOCK_NON_SHARE |
> -                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
> -       }, {
> -               .virt = 0x80000000UL, /* DDR */
> -               .phys = 0x80000000UL, /* DDR */
> -               .size = 0x05900000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               .virt = 0x89600000UL, /* DDR */
> -               .phys = 0x89600000UL, /* DDR */
> -               .size = 0x162000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               .virt = 0xa0000000UL, /* DDR */
> -               .phys = 0xa0000000UL, /* DDR */
> -               .size = 0x20000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               /* List terminator */
> -               0,
> -       }
> -};
> -
> -struct mm_region *mem_map = qcs404_mem_map;
> diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c
> deleted file mode 100644
> index 721ac411665c..000000000000
> --- a/arch/arm/mach-snapdragon/sysmap-sdm845.c
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm SDM845 memory map
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
> - */
> -
> -#include <common.h>
> -#include <asm/armv8/mmu.h>
> -
> -static struct mm_region sdm845_mem_map[] = {
> -       {
> -               .virt = 0x0UL, /* Peripheral block */
> -               .phys = 0x0UL, /* Peripheral block */
> -               .size = 0x10000000UL,
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> -                        PTE_BLOCK_NON_SHARE |
> -                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
> -       }, {
> -               .virt = 0x80000000UL, /* DDR */
> -               .phys = 0x80000000UL, /* DDR */
> -               .size = 0x200000000UL, /* 8GiB - maximum allowed memory */
> -               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                        PTE_BLOCK_INNER_SHARE
> -       }, {
> -               /* List terminator */
> -               0,
> -       }
> -};
> -
> -struct mm_region *mem_map = sdm845_mem_map;
> diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig
> deleted file mode 100644
> index 03bd7ae309cd..000000000000
> --- a/board/qualcomm/dragonboard410c/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_DRAGONBOARD410C
> -
> -config SYS_BOARD
> -       default "dragonboard410c"
> -
> -config SYS_VENDOR
> -       default "qualcomm"
> -
> -config SYS_SOC
> -       default "apq8016"
> -
> -config SYS_CONFIG_NAME
> -       default "dragonboard410c"
> -
> -endif
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 40b5448c6ef1..0136cc2237de 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -23,37 +23,6 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -#define USB_HUB_RESET_GPIO 2
> -#define USB_SW_SELECT_GPIO 3
> -
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> -       struct udevice *usb;
> -       int ret = 0;
> -
> -       /* USB device */
> -       ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
> -       if (ret) {
> -               printf("Cannot find USB device\n");
> -               return ret;
> -       }
> -
> -       /* Select "default" or "device" pinctrl */
> -       switch (init) {
> -       case USB_INIT_HOST:
> -               pinctrl_select_state(usb, "default");
> -               break;
> -       case USB_INIT_DEVICE:
> -               pinctrl_select_state(usb, "device");
> -               break;
> -       default:
> -               debug("Unknown usb_init_type %d\n", init);
> -               break;
> -       }
> -
> -       return 0;
> -}
> -
>  /* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
>  #define UNSTUFF_BITS(resp, start, size) \
>         ({ \
> @@ -119,11 +88,6 @@ int misc_init_r(void)
>         return 0;
>  }
>
> -int board_init(void)
> -{
> -       return 0;
> -}
> -
>  int board_late_init(void)
>  {
>         char serial[16];
> @@ -166,8 +130,3 @@ int ft_board_setup(void *blob, struct bd_info *bd)
>                            "local-bd-address", mac, ARP_HLEN, 1);
>         return 0;
>  }
> -
> -void reset_cpu(void)
> -{
> -       psci_system_reset();
> -}
> diff --git a/board/qualcomm/dragonboard820c/Kconfig b/board/qualcomm/dragonboard820c/Kconfig
> deleted file mode 100644
> index aff9af527128..000000000000
> --- a/board/qualcomm/dragonboard820c/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_DRAGONBOARD820C
> -
> -config SYS_BOARD
> -       default "dragonboard820c"
> -
> -config SYS_VENDOR
> -       default "qualcomm"
> -
> -config SYS_SOC
> -       default "apq8096"
> -
> -config SYS_CONFIG_NAME
> -       default "dragonboard820c"
> -
> -endif
> diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c
> index 2f0db628368b..ac7de711c588 100644
> --- a/board/qualcomm/dragonboard820c/dragonboard820c.c
> +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c
> @@ -27,24 +27,6 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -int dram_init(void)
> -{
> -       gd->ram_size = PHYS_SDRAM_SIZE;
> -
> -       return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> -       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> -       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -
> -       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> -       gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
> -
> -       return 0;
> -}
> -
>  static void sdhci_power_init(void)
>  {
>         const u32 TLMM_PULL_MASK = 0x3;
> @@ -113,28 +95,9 @@ static void sdhci_power_init(void)
>                         rclk[i].val  << rclk[i].bit);
>  }
>
> -static void show_psci_version(void)
> -{
> -       struct arm_smccc_res res;
> -
> -       arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> -
> -       printf("PSCI:  v%ld.%ld\n",
> -              PSCI_VERSION_MAJOR(res.a0),
> -               PSCI_VERSION_MINOR(res.a0));
> -}
> -
> -int board_init(void)
> +void qcom_board_init(void)
>  {
>         sdhci_power_init();
> -       show_psci_version();
> -
> -       return 0;
> -}
> -
> -void reset_cpu(void)
> -{
> -       psci_system_reset();
>  }
>
>  /* Check for vol- button - if pressed - stop autoboot */
> diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig
> deleted file mode 100644
> index 52fdff288d59..000000000000
> --- a/board/qualcomm/dragonboard845c/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_DRAGONBOARD845C
> -
> -config SYS_BOARD
> -       default "dragonboard845c"
> -
> -config SYS_CONFIG_NAME
> -       default "dragonboard845c"
> -
> -config SYS_VENDOR
> -       default "qualcomm"
> -
> -endif
> diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig
> deleted file mode 100644
> index 32657c7d5e31..000000000000
> --- a/board/qualcomm/qcs404-evb/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_QCS404EVB
> -
> -config SYS_BOARD
> -       default "qcs404-evb"
> -
> -config SYS_VENDOR
> -       default "qualcomm"
> -
> -config SYS_SOC
> -       default "qcs404"
> -
> -config SYS_CONFIG_NAME
> -       default "qcs404-evb"
> -
> -endif
> diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
> index 249dca7e72f1..1a4b1f97a3ae 100644
> --- a/board/qualcomm/qcs404-evb/qcs404-evb.c
> +++ b/board/qualcomm/qcs404-evb/qcs404-evb.c
> @@ -14,16 +14,10 @@
>  #include <asm/gpio.h>
>  #include <asm/global_data.h>
>  #include <fdt_support.h>
> -#include <asm/arch/dram.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -int dram_init(void)
> -{
> -       return fdtdec_setup_mem_size_base();
> -}
> -
> -int board_init(void)
> +void qcom_board_init(void)
>  {
>         struct udevice *pmic_gpio;
>         struct gpio_desc usb_vbus_boost_pin;
> @@ -34,29 +28,22 @@ int board_init(void)
>                                         &pmic_gpio);
>         if (ret < 0) {
>                 printf("Failed to find pms405_gpios@c000 node.\n");
> -               return ret;
> +               return;
>         }
>
>         node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
>                                   "usb_vbus_boost_pin");
>         if (node < 0) {
>                 printf("Failed to find usb_hub_reset_pm dt node.\n");
> -               return node;
> +               return;
>         }
>         ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
>                                          &usb_vbus_boost_pin, 0);
>         if (ret < 0) {
>                 printf("Failed to request usb_hub_reset_pm gpio.\n");
> -               return ret;
> +               return;
>         }
>
>         dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
>                               GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
> -
> -       return 0;
> -}
> -
> -void reset_cpu(void)
> -{
> -       psci_system_reset();
>  }
> diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
> index 56a73893d3df..efdee8a40fa3 100644
> --- a/configs/dragonboard410c_defconfig
> +++ b/configs/dragonboard410c_defconfig
> @@ -1,9 +1,10 @@
>  CONFIG_ARM=y
> +CONFIG_SYS_BOARD="dragonboard410c"
>  CONFIG_COUNTER_FREQUENCY=19000000
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>  CONFIG_ARCH_SNAPDRAGON=y
>  CONFIG_TEXT_BASE=0x8f600000
>  CONFIG_SYS_MALLOC_LEN=0x802000
> -CONFIG_NR_DRAM_BANKS=1
>  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
>  CONFIG_ENV_SIZE=0x2000
> @@ -38,7 +39,9 @@ CONFIG_CMD_TIMER=y
>  CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>  CONFIG_SYS_MMC_ENV_PART=2
> +CONFIG_BUTTON_QCOM_PMIC=y
>  CONFIG_CLK=y
> +CONFIG_CLK_QCOM_APQ8016=y
>  CONFIG_USB_FUNCTION_FASTBOOT=y
>  CONFIG_FASTBOOT_BUF_ADDR=0x91000000
>  CONFIG_FASTBOOT_FLASH=y
> @@ -52,6 +55,7 @@ CONFIG_MMC_SDHCI_MSM=y
>  CONFIG_PHY=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCONF=y
> +CONFIG_PINCTRL_QCOM_APQ8016=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_QCOM=y
>  CONFIG_MSM_SERIAL=y
> diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
> index 7304ff97dd8e..89847ce0b307 100644
> --- a/configs/dragonboard820c_defconfig
> +++ b/configs/dragonboard820c_defconfig
> @@ -1,14 +1,13 @@
>  CONFIG_ARM=y
> +CONFIG_SYS_BOARD="dragonboard820c"
>  CONFIG_COUNTER_FREQUENCY=19000000
>  CONFIG_ARCH_SNAPDRAGON=y
>  CONFIG_TEXT_BASE=0x80080000
>  CONFIG_SYS_MALLOC_LEN=0x804000
> -CONFIG_NR_DRAM_BANKS=2
>  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
>  CONFIG_ENV_SIZE=0x4000
>  CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
> -CONFIG_TARGET_DRAGONBOARD820C=y
>  CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
>  CONFIG_SYS_LOAD_ADDR=0x80080000
>  CONFIG_DISTRO_DEFAULTS=y
> @@ -35,12 +34,15 @@ CONFIG_ENV_IS_IN_EXT4=y
>  CONFIG_ENV_EXT4_INTERFACE="mmc"
>  CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1"
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_BUTTON_QCOM_PMIC=y
>  CONFIG_CLK=y
> +CONFIG_CLK_QCOM_APQ8096=y
>  CONFIG_QCOM_PMIC_GPIO=y
>  CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_MSM=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCONF=y
> +CONFIG_PINCTRL_QCOM_APQ8096=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_QCOM=y
>  CONFIG_MSM_SERIAL=y
> diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig
> deleted file mode 100644
> index f29f11e342e7..000000000000
> --- a/configs/dragonboard845c_defconfig
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SKIP_LOWLEVEL_INIT=y
> -CONFIG_COUNTER_FREQUENCY=19000000
> -CONFIG_POSITION_INDEPENDENT=y
> -CONFIG_ARCH_SNAPDRAGON=y
> -CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
> -CONFIG_TARGET_DRAGONBOARD845C=y
> -CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
> -CONFIG_SYS_LOAD_ADDR=0x80000000
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_BOOTDELAY=5
> -CONFIG_SAVE_PREV_BL_FDT_ADDR=y
> -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
> -CONFIG_SYS_CBSIZE=512
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_MAXARGS=64
> -CONFIG_CMD_GPIO=y
> -# CONFIG_NET is not set
> -CONFIG_CLK=y
> -CONFIG_MSM_GPIO=y
> -CONFIG_QCOM_PMIC_GPIO=y
> -CONFIG_PINCTRL=y
> -CONFIG_DM_PMIC=y
> -CONFIG_PMIC_QCOM=y
> -CONFIG_MSM_GENI_SERIAL=y
> -CONFIG_SPMI_MSM=y
> -CONFIG_LMB_MAX_REGIONS=64
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> new file mode 100644
> index 000000000000..a84f5aee444e
> --- /dev/null
> +++ b/configs/qcom_defconfig
> @@ -0,0 +1,67 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_ARCH_SNAPDRAGON=y
> +CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
> +CONFIG_SYS_LOAD_ADDR=0x0
> +CONFIG_BUTTON_CMD=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_BOOTSTD_FULL=y
> +# CONFIG_BOOTMETH_VBE is not set
> +CONFIG_BOOTDELAY=1
> +CONFIG_USE_PREBOOT=y
> +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
> +CONFIG_SYS_CBSIZE=512
> +CONFIG_LOG_MAX_LEVEL=9
> +CONFIG_LOG_DEFAULT_LEVEL=4
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_CMD_BOOTMENU=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_UFS=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_CAT=y
> +CONFIG_CMD_BMP=y
> +CONFIG_CMD_LOG=y
> +# CONFIG_NET is not set
> +CONFIG_BUTTON_QCOM_PMIC=y
> +CONFIG_CLK=y
> +CONFIG_CLK_QCOM_QCS404=y
> +CONFIG_CLK_QCOM_SDM845=y
> +CONFIG_MSM_GPIO=y
> +CONFIG_QCOM_PMIC_GPIO=y
> +CONFIG_DM_KEYBOARD=y
> +CONFIG_BUTTON_KEYBOARD=y
> +CONFIG_MMC_HS200_SUPPORT=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ADMA=y
> +CONFIG_MMC_SDHCI_MSM=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_QCOM_QCS404=y
> +CONFIG_PINCTRL_QCOM_SDM845=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_QCOM=y
> +CONFIG_SCSI=y
> +CONFIG_MSM_SERIAL=y
> +CONFIG_MSM_GENI_SERIAL=y
> +CONFIG_SPMI_MSM=y
> +CONFIG_SYSINFO=y
> +CONFIG_SYSINFO_SMBIOS=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_DWC3=y
> +CONFIG_UFS=y
> +CONFIG_VIDEO=y
> +# CONFIG_VIDEO_FONT_8X16 is not set
> +CONFIG_VIDEO_FONT_16X32=y
> +CONFIG_SYS_WHITE_ON_BLACK=y
> +CONFIG_NO_FB_CLEAR=y
> +CONFIG_VIDEO_SIMPLE=y
> +CONFIG_HEXDUMP=y
> +# CONFIG_GENERATE_SMBIOS_TABLE is not set
> +CONFIG_LMB_MAX_REGIONS=64
> diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
> index 700c024e8b6a..d85d193895b0 100644
> --- a/configs/qcs404evb_defconfig
> +++ b/configs/qcs404evb_defconfig
> @@ -1,11 +1,10 @@
>  CONFIG_ARM=y
> +CONFIG_SYS_BOARD="qcs404-evb"
>  CONFIG_SKIP_LOWLEVEL_INIT=y
>  CONFIG_COUNTER_FREQUENCY=19000000
>  CONFIG_POSITION_INDEPENDENT=y
>  CONFIG_ARCH_SNAPDRAGON=y
>  CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
> -CONFIG_DM_RESET=y
> -CONFIG_TARGET_QCS404EVB=y
>  CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
>  CONFIG_SYS_LOAD_ADDR=0x80000000
>  CONFIG_FIT=y
> @@ -31,6 +30,7 @@ CONFIG_CMD_FAT=y
>  CONFIG_CMD_FS_GENERIC=y
>  # CONFIG_NET is not set
>  CONFIG_CLK=y
> +CONFIG_CLK_QCOM_QCS404=y
>  CONFIG_MSM_GPIO=y
>  CONFIG_QCOM_PMIC_GPIO=y
>  CONFIG_MISC=y
> @@ -42,6 +42,7 @@ CONFIG_PHY=y
>  CONFIG_PHY_QCOM_USB_HS_28NM=y
>  CONFIG_PHY_QCOM_USB_SS=y
>  CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_QCOM_QCS404=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_QCOM=y
>  CONFIG_MSM_SERIAL=y
> diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig
> deleted file mode 100644
> index 6980a8232667..000000000000
> --- a/configs/starqltechn_defconfig
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SKIP_LOWLEVEL_INIT=y
> -CONFIG_COUNTER_FREQUENCY=19000000
> -CONFIG_POSITION_INDEPENDENT=y
> -CONFIG_ARCH_SNAPDRAGON=y
> -CONFIG_DEFAULT_DEVICE_TREE="starqltechn"
> -CONFIG_TARGET_STARQLTECHN=y
> -CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600"
> -CONFIG_SYS_LOAD_ADDR=0x80000000
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_BOOTDELAY=0
> -CONFIG_SAVE_PREV_BL_FDT_ADDR=y
> -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
> -CONFIG_SYS_CBSIZE=512
> -CONFIG_SYS_PBSIZE=532
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_MAXARGS=64
> -CONFIG_CMD_BOOTMENU=y
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_BMP=y
> -# CONFIG_NET is not set
> -CONFIG_BUTTON=y
> -CONFIG_CLK=y
> -CONFIG_MSM_GPIO=y
> -CONFIG_QCOM_PMIC_GPIO=y
> -CONFIG_DM_KEYBOARD=y
> -CONFIG_BUTTON_KEYBOARD=y
> -CONFIG_PINCTRL=y
> -CONFIG_DM_PMIC=y
> -CONFIG_PMIC_QCOM=y
> -CONFIG_MSM_GENI_SERIAL=y
> -CONFIG_SPMI_MSM=y
> -CONFIG_VIDEO=y
> -# CONFIG_VIDEO_FONT_8X16 is not set
> -CONFIG_VIDEO_FONT_16X32=y
> -CONFIG_SYS_WHITE_ON_BLACK=y
> -CONFIG_VIDEO_SIMPLE=y
> -CONFIG_VIDEO_DT_SIMPLEFB=y
> -CONFIG_LMB_MAX_REGIONS=64
> diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
> deleted file mode 100644
> index 14a8a2ca049e..000000000000
> --- a/include/configs/dragonboard845c.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -#ifndef __CONFIGS_SDM845_H
> -#define __CONFIGS_SDM845_H
> -
> -#include <linux/sizes.h>
> -
> -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
> -
> -#define CFG_EXTRA_ENV_SETTINGS \
> -       "bootm_size=0x5000000\0"        \
> -       "bootm_low=0x80000000\0"        \
> -       "bootcmd=bootm $prevbl_initrd_start_addr\0"
> -
> -#endif
> diff --git a/include/configs/qcom.h b/include/configs/qcom.h
> new file mode 100644
> index 000000000000..e50b3bce5cdd
> --- /dev/null
> +++ b/include/configs/qcom.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration file for Qualcomm Snapdragon boards
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> + * (C) Copyright 2023 Linaro Ltd.
> + */
> +
> +#ifndef __CONFIGS_SNAPDRAGON_H
> +#define __CONFIGS_SNAPDRAGON_H
> +
> +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
> +
> +/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */
> +#define CFG_EXTRA_ENV_SETTINGS \
> +       "stdin=serial,button-kbd\0"     \
> +       "stdout=serial,vidconsole\0"    \
> +       "stderr=serial,vidconsole\0" \
> +       "bootcmd=bootm $prevbl_initrd_start_addr\0"
> +
> +#endif
> diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
> deleted file mode 100644
> index 9501d43665e9..000000000000
> --- a/include/configs/qcs404-evb.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Configuration file for QCS404 evaluation board
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -#ifndef __CONFIGS_QCS404EVB_H
> -#define __CONFIGS_QCS404EVB_H
> -
> -#include <linux/sizes.h>
> -
> -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
> -
> -#define CFG_EXTRA_ENV_SETTINGS \
> -       "bootm_size=0x5000000\0"        \
> -       "bootm_low=0x80000000\0"        \
> -       "bootcmd=bootm $prevbl_initrd_start_addr\0"
> -
> -#endif
> diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
> deleted file mode 100644
> index 5ad8569b2152..000000000000
> --- a/include/configs/sdm845.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Configuration file for boards, based on Qualcomm SDM845 chip
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> - */
> -
> -#ifndef __CONFIGS_SDM845_H
> -#define __CONFIGS_SDM845_H
> -
> -#include <linux/sizes.h>
> -
> -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
> -
> -#define CFG_EXTRA_ENV_SETTINGS \
> -       "bootm_size=0x4000000\0"        \
> -       "bootm_low=0x80000000\0"        \
> -       "stdin=serial,button-kbd\0"     \
> -       "stdout=serial,vidconsole\0"    \
> -       "stderr=serial,vidconsole\0"    \
> -       "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
> -       "bootcmd=source $prevbl_initrd_start_addr:bootscript\0"
> -
> -/* Size of malloc() pool */
> -
> -#endif
>
> --
> 2.43.1
>

Re: [PATCH v4 21/39] mach-snapdragon: dynamic load addresses

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Heavily inspired by Apple board code. Use the LMB allocator to configure
> load addresses at runtime, and implement a lookup table for selecting a
> devicetree.
>
> As some Qualcomm RBx boards have different RAM capacities and base
> addresses, it isn't possible to hardcode these regions.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/Kconfig                                 |  1 +
>  arch/arm/mach-snapdragon/board.c                 | 34 ++++++++++++++++++++++++
>  board/qualcomm/dragonboard410c/dragonboard410c.c |  2 +-
>  3 files changed, 36 insertions(+), 1 deletion(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 672577d0ddcc..0dba77f86b49 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1095,6 +1095,7 @@ config ARCH_SNAPDRAGON
>         select OF_SEPARATE
>         select SMEM
>         select SPMI
> +       select BOARD_LATE_INIT
>         select OF_BOARD
>         select SAVE_PREV_BL_FDT_ADDR
>         select LINUX_KERNEL_IMAGE_HEADER
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index a1867852bcca..f445bed3af00 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -22,6 +22,7 @@
>  #include <linux/bug.h>
>  #include <linux/psci.h>
>  #include <linux/sizes.h>
> +#include <lmb.h>
>  #include <malloc.h>
>  #include <usb.h>
>
> @@ -159,6 +160,39 @@ int board_init(void)
>         return 0;
>  }
>
> +void __weak qcom_late_init(void)
> +{
> +}
> +
> +#define KERNEL_COMP_SIZE       SZ_64M
> +
> +#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
> +
> +/* Stolen from arch/arm/mach-apple/board.c */
> +int board_late_init(void)
> +{
> +       struct lmb lmb;
> +       u32 status = 0;
> +
> +       lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
> +
> +       /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */
> +       status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
> +       status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
> +       status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE));
> +       status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
> +       status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
> +       status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
> +       status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
> +
> +       if (status)
> +               log_warning("%s: Failed to set run time variables\n", __func__);
> +
> +       qcom_late_init();
> +
> +       return 0;
> +}
> +
>  static void build_mem_map(void)
>  {
>         int i;
> diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
> index 0136cc2237de..fbbfc0e65e24 100644
> --- a/board/qualcomm/dragonboard410c/dragonboard410c.c
> +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
> @@ -88,7 +88,7 @@ int misc_init_r(void)
>         return 0;
>  }
>
> -int board_late_init(void)
> +int qcom_late_init(void)
>  {
>         char serial[16];
>
>
> --
> 2.43.1
>

Re: [PATCH v4 22/39] mach-snapdragon: generate fdtfile automatically

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> With just a few basic rules, we can generate the $fdtfile environment
> variable to match the format used in Linux. This uses the root
> compatible property inside u-boot, with specific handling for the
> Dragonboard845c which is a special case, and for the qrb robotics
> boards.
>
> This is known to work on supported platforms, and lets us avoid having a
> big lookup table.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/board.c | 101 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index f445bed3af00..5a859aabd5c4 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -160,6 +160,106 @@ int board_init(void)
>         return 0;
>  }
>
> +/* Sets up the "board", and "soc" environment variables as well as constructing the devicetree
> + * path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a
> + * comprehensive solution to automatically picking the DTB, but aims to be correct for the
> + * majority case. For most devices it should be possible to make this algorithm work by
> + * adjusting the root compatible property in the U-Boot DTS. Handling devices with multiple
> + * variants that are all supported by a single U-Boot image will require implementing device-
> + * specific detection.
> + */
> +static void configure_env(void)
> +{
> +       const char *first_compat, *last_compat;
> +       char *tmp;
> +       char buf[32] = { 0 };
> +       /*
> +        * Most DTB filenames follow the scheme: qcom/<soc>-[vendor]-<board>.dtb
> +        * The vendor is skipped when it's a Qualcomm reference board, or the
> +        * db845c.
> +        */
> +       char dt_path[64] = { 0 };
> +       int compat_count, ret;
> +       ofnode root;
> +
> +       root = ofnode_root();
> +       /* This is almost always 2, but be explicit that we want the first and last compatibles
> +        * not the first and second.
> +        */
> +       compat_count = ofnode_read_string_count(root, "compatible");
> +       if (compat_count < 2) {
> +               log_warning("%s: only one root compatible bailing!\n", __func__);
> +               return;
> +       }
> +
> +       /* The most specific device compatible (e.g. "thundercomm,db845c") */
> +       ret = ofnode_read_string_index(root, "compatible", 0, &first_compat);
> +       if (ret < 0) {
> +               log_warning("Can't read first compatible\n");
> +               return;
> +       }
> +
> +       /* The last compatible is always the SoC compatible */
> +       ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat);
> +       if (ret < 0) {
> +               log_warning("Can't read second compatible\n");
> +               return;
> +       }
> +
> +       /* Copy the second compat (e.g. "qcom,sdm845") into buf */
> +       strlcpy(buf, last_compat, sizeof(buf) - 1);
> +       tmp = buf;
> +
> +       /* strsep() is destructive, it replaces the comma with a \0 */
> +       if (!strsep(&tmp, ",")) {
> +               log_warning("second compatible '%s' has no ','\n", buf);
> +               return;
> +       }
> +
> +       /* tmp now points to just the "sdm845" part of the string */
> +       env_set("soc", tmp);
> +
> +       /* Now figure out the "board" part from the first compatible */
> +       memset(buf, 0, sizeof(buf));
> +       strlcpy(buf, first_compat, sizeof(buf) - 1);
> +       tmp = buf;
> +
> +       /* The Qualcomm reference boards (RBx, HDK, etc)  */
> +       if (!strncmp("qcom", buf, strlen("qcom"))) {
> +               /*
> +                * They all have the first compatible as "qcom,<soc>-<board>"
> +                * (e.g. "qcom,qrb5165-rb5"). We extract just the part after
> +                * the dash.
> +                */
> +               if (!strsep(&tmp, "-")) {
> +                       log_warning("compatible '%s' has no '-'\n", buf);
> +                       return;
> +               }
> +               /* tmp is now "rb5" */
> +               env_set("board", tmp);
> +       } else {
> +               if (!strsep(&tmp, ",")) {
> +                       log_warning("compatible '%s' has no ','\n", buf);
> +                       return;
> +               }
> +               /* for thundercomm we just want the bit after the comma (e.g. "db845c"),
> +                * for all other boards we replace the comma with a '-' and take both
> +                * (e.g. "oneplus-enchilada")
> +                */
> +               if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
> +                       env_set("board", tmp);
> +               } else {
> +                       *(tmp - 1) = '-';
> +                       env_set("board", buf);
> +               }
> +       }
> +
> +       /* Now build the full path name */
> +       snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
> +                env_get("soc"), env_get("board"));
> +       env_set("fdtfile", dt_path);
> +}
> +
>  void __weak qcom_late_init(void)
>  {
>  }
> @@ -188,6 +288,7 @@ int board_late_init(void)
>         if (status)
>                 log_warning("%s: Failed to set run time variables\n", __func__);
>
> +       configure_env();
>         qcom_late_init();
>
>         return 0;
>
> --
> 2.43.1
>

Re: [PATCH v4 23/39] mach-snapdragon: carve out no-map regions

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> On Qualcomm platforms, the TZ may already have certain memory regions
> under protection by the time U-Boot starts. There is a rare case on some
> platforms where the prefetcher might speculatively access one of these
> regions resulting in a board crash (TZ traps and then resets the board).
>
> We shouldn't be accessing these regions from within U-Boot anyway, so
> let's mark them all with PTE_TYPE_FAULT to prevent any speculative
> access and correctly trap in EL1 rather than EL3.
>
> This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
> with caches on). So to minimise the impact this is only enabled on
> QCS404 for now (where the issue is known to occur).
>
> In the future, we should try to find a more efficient way to handle
> this, perhaps by turning on the MMU in stages.
>

I suppose you forgot to update the commit message since we already
found more or less an efficient way.

> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/mach-snapdragon/board.c | 162 +++++++++++++++++++++++++++++++++------
>  1 file changed, 140 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index 5a859aabd5c4..f12f5791a136 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -25,6 +25,7 @@
>  #include <lmb.h>
>  #include <malloc.h>
>  #include <usb.h>
> +#include <sort.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -296,7 +297,7 @@ int board_late_init(void)
>
>  static void build_mem_map(void)
>  {
> -       int i;
> +       int i, j;
>
>         /*
>          * Ensure the peripheral block is sized to correctly cover the address range
> @@ -312,28 +313,23 @@ static void build_mem_map(void)
>                          PTE_BLOCK_NON_SHARE |
>                          PTE_BLOCK_PXN | PTE_BLOCK_UXN;
>
> -       debug("Configured memory map:\n");
> -       debug("  0x%016llx - 0x%016llx: Peripheral block\n",
> -             mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
> -
> -       /*
> -        * Now add memory map entries for each DRAM bank, ensuring we don't
> -        * overwrite the list terminator
> -        */
> -       for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
> -               if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
> -                       log_warning("Too many DRAM banks!\n");
> -                       break;
> -               }
> -               mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
> -               mem_map[i + 1].virt = mem_map[i + 1].phys;
> -               mem_map[i + 1].size = gd->bd->bi_dram[i].size;
> -               mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -                                    PTE_BLOCK_INNER_SHARE;
> -
> -               debug("  0x%016llx - 0x%016llx: DDR bank %d\n",
> -                     mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
> +       for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
> +               mem_map[i].phys = gd->bd->bi_dram[j].start;
> +               mem_map[i].virt = mem_map[i].phys;
> +               mem_map[i].size = gd->bd->bi_dram[j].size;
> +               mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
> +                                  PTE_BLOCK_INNER_SHARE;
>         }
> +
> +       mem_map[i].phys = UINT64_MAX;
> +       mem_map[i].size = 0;
> +
> +#ifdef DEBUG
> +       debug("Configured memory map:\n");
> +       for (i = 0; mem_map[i].size; i++)
> +               debug("  0x%016llx - 0x%016llx: entry %d\n",
> +                     mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
> +#endif
>  }
>
>  u64 get_page_table_size(void)
> @@ -341,10 +337,132 @@ u64 get_page_table_size(void)
>         return SZ_64K;
>  }
>
> +static int fdt_cmp_res(const void *v1, const void *v2)
> +{
> +       const struct fdt_resource *res1 = v1, *res2 = v2;
> +
> +       return res1->start - res2->start;
> +}
> +
> +#define N_RESERVED_REGIONS 32
> +
> +/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
> + * On some platforms this is enough to trigger a security violation and trap
> + * to EL3.
> + */
> +static void carve_out_reserved_memory(void)
> +{
> +       static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
> +       int parent, rmem, count, i = 0;
> +       phys_addr_t start;
> +       size_t size;
> +
> +       /* Some reserved nodes must be carved out, as the cache-prefetcher may otherwise
> +        * attempt to access them, causing a security exception.
> +        */
> +       parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
> +       if (parent <= 0) {
> +               log_err("No reserved memory regions found\n");
> +               return;
> +       }
> +
> +       /* Collect the reserved memory regions */
> +       fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
> +               const fdt32_t *ptr;
> +               int len;
> +               if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL))
> +                       continue;
> +
> +               if (i == N_RESERVED_REGIONS) {
> +                       log_err("Too many reserved regions!\n");
> +                       break;
> +               }
> +
> +               /* Read the address and size out from the reg property. Doing this "properly" with
> +                * fdt_get_resource() takes ~70ms on SDM845, but open-coding the happy path here
> +                * takes <1ms... Oh the woes of no dcache.
> +                */

Nice optimization.

> +               ptr = fdt_getprop(gd->fdt_blob, rmem, "reg", &len);
> +               if (ptr) {
> +                       /* Qualcomm devices use #address/size-cells = <2> but all reserved regions are within
> +                        * the 32-bit address space. So we can cheat here for speed.
> +                        */
> +                       res[i].start = fdt32_to_cpu(ptr[1]);
> +                       res[i].end = res[i].start + fdt32_to_cpu(ptr[3]);
> +                       i++;
> +               }
> +       }
> +
> +       /* Sort the reserved memory regions by address */
> +       count = i;
> +       qsort(res, count, sizeof(struct fdt_resource), fdt_cmp_res);
> +
> +       /* Now set the right attributes for them. Often a lot of the regions are tightly packed together
> +        * so we can optimise the number of calls to mmu_change_region_attr() by combining adjacent
> +        * regions.
> +        */
> +       start = ALIGN_DOWN(res[0].start, SZ_2M);
> +       size = ALIGN(res[0].end - start, SZ_2M);
> +       for (i = 1; i <= count; i++) {
> +               /* We ideally want to 2M align everything for more efficient pagetables, but we must avoid
> +                * overwriting reserved memory regions which shouldn't be mapped as FAULT (like those with
> +                * compatible properties).

This comment requires an update too.

With above incorporated, feel free to add:

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> +                * If within 2M of the previous region, bump the size to include this region. Otherwise
> +                * start a new region.
> +                */
> +               if (i == count || start + size < res[i].start - SZ_2M) {
> +                       debug("  0x%016llx - 0x%016llx: reserved\n",
> +                             start, start + size);
> +                       mmu_change_region_attr(start, size, PTE_TYPE_FAULT);
> +                       /* If this is the final region then quit here before we index
> +                        * out of bounds...
> +                        */
> +                       if (i == count)
> +                               break;
> +                       start = ALIGN_DOWN(res[i].start, SZ_2M);
> +                       size = ALIGN(res[i].end - start, SZ_2M);
> +               } else {
> +                       /* Bump size if this region is immediately after the previous one */
> +                       size = ALIGN(res[i].end - start, SZ_2M);
> +               }
> +       }
> +}
> +
> +/* This function open-codes setup_all_pgtables() so that we can
> + * insert additional mappings *before* turning on the MMU.
> + */
>  void enable_caches(void)
>  {
> +       u64 tlb_addr = gd->arch.tlb_addr;
> +       u64 tlb_size = gd->arch.tlb_size;
> +       u64 pt_size;
> +       ulong carveout_start;
> +
> +       gd->arch.tlb_fillptr = tlb_addr;
> +
>         build_mem_map();
>
>         icache_enable();
> +
> +       /* Create normal system page tables */
> +       setup_pgtables();
> +
> +       pt_size = (uintptr_t)gd->arch.tlb_fillptr -
> +                 (uintptr_t)gd->arch.tlb_addr;
> +       debug("Primary pagetable size: %lluKiB\n", pt_size / 1024);
> +
> +       /* Create emergency page tables */
> +       gd->arch.tlb_size -= pt_size;
> +       gd->arch.tlb_addr = gd->arch.tlb_fillptr;
> +       setup_pgtables();
> +       gd->arch.tlb_emerg = gd->arch.tlb_addr;
> +       gd->arch.tlb_addr = tlb_addr;
> +       gd->arch.tlb_size = tlb_size;
> +
> +       carveout_start = get_timer(0);
> +       /* Takes ~20-50ms on SDM845 */
> +       carve_out_reserved_memory();
> +       debug("carveout time: %lums\n", get_timer(carveout_start));
> +
>         dcache_enable();
>  }
>
> --
> 2.43.1
>

Re: [PATCH v4 24/39] board: qcs404-evb: drop board code

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> This board is entirely supported by the generic arch code and DTS. The
> board code used to handle turning on the vbus regulator, however this is
> now handled via DT.
>
> With this, the board specific defconfig is also no longer needed, so
> drop it as well.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  board/qualcomm/qcs404-evb/Makefile     |  6 ----
>  board/qualcomm/qcs404-evb/qcs404-evb.c | 49 -----------------------------
>  configs/qcs404evb_defconfig            | 56 ----------------------------------
>  3 files changed, 111 deletions(-)
>

Glad to see qcs404 being supported by generic defconfig.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/board/qualcomm/qcs404-evb/Makefile b/board/qualcomm/qcs404-evb/Makefile
> deleted file mode 100644
> index 4665827e0859..000000000000
> --- a/board/qualcomm/qcs404-evb/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> -#
> -
> -obj-y += qcs404-evb.o
> diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
> deleted file mode 100644
> index 1a4b1f97a3ae..000000000000
> --- a/board/qualcomm/qcs404-evb/qcs404-evb.c
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Board init file for QCS404-EVB
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -#include <common.h>
> -#include <cpu_func.h>
> -#include <dm.h>
> -#include <env.h>
> -#include <init.h>
> -#include <asm/cache.h>
> -#include <asm/gpio.h>
> -#include <asm/global_data.h>
> -#include <fdt_support.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -void qcom_board_init(void)
> -{
> -       struct udevice *pmic_gpio;
> -       struct gpio_desc usb_vbus_boost_pin;
> -       int ret, node;
> -
> -       ret = uclass_get_device_by_name(UCLASS_GPIO,
> -                                       "pms405_gpios@c000",
> -                                       &pmic_gpio);
> -       if (ret < 0) {
> -               printf("Failed to find pms405_gpios@c000 node.\n");
> -               return;
> -       }
> -
> -       node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
> -                                 "usb_vbus_boost_pin");
> -       if (node < 0) {
> -               printf("Failed to find usb_hub_reset_pm dt node.\n");
> -               return;
> -       }
> -       ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
> -                                        &usb_vbus_boost_pin, 0);
> -       if (ret < 0) {
> -               printf("Failed to request usb_hub_reset_pm gpio.\n");
> -               return;
> -       }
> -
> -       dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
> -                             GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
> -}
> diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
> deleted file mode 100644
> index d85d193895b0..000000000000
> --- a/configs/qcs404evb_defconfig
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_BOARD="qcs404-evb"
> -CONFIG_SKIP_LOWLEVEL_INIT=y
> -CONFIG_COUNTER_FREQUENCY=19000000
> -CONFIG_POSITION_INDEPENDENT=y
> -CONFIG_ARCH_SNAPDRAGON=y
> -CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
> -CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
> -CONFIG_SYS_LOAD_ADDR=0x80000000
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_BOOTDELAY=5
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
> -CONFIG_SAVE_PREV_BL_FDT_ADDR=y
> -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
> -CONFIG_SYS_CBSIZE=512
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_MAXARGS=64
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_GPT=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_PART=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -# CONFIG_NET is not set
> -CONFIG_CLK=y
> -CONFIG_CLK_QCOM_QCS404=y
> -CONFIG_MSM_GPIO=y
> -CONFIG_QCOM_PMIC_GPIO=y
> -CONFIG_MISC=y
> -CONFIG_MMC_HS400_SUPPORT=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_ADMA=y
> -CONFIG_MMC_SDHCI_MSM=y
> -CONFIG_PHY=y
> -CONFIG_PHY_QCOM_USB_HS_28NM=y
> -CONFIG_PHY_QCOM_USB_SS=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_QCOM_QCS404=y
> -CONFIG_DM_PMIC=y
> -CONFIG_PMIC_QCOM=y
> -CONFIG_MSM_SERIAL=y
> -CONFIG_SPMI_MSM=y
> -CONFIG_USB=y
> -CONFIG_USB_XHCI_HCD=y
> -CONFIG_USB_XHCI_DWC3=y
> -CONFIG_USB_DWC3=y
> -CONFIG_USB_DWC3_GENERIC=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_LMB_MAX_REGIONS=64
>
> --
> 2.43.1
>

Re: [PATCH v4 25/39] doc: board/qualcomm: document generic targets

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Replace the board specific docs with a generic board.rst file which
> documents the build/boot process for the sdm845 and qcs404 boards now
> that the only differences are the DTB in use.
>
> At the same time, create a debugging page to document some useful
> snippets and tips for working with Qualcomm platforms.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  doc/board/qualcomm/board.rst     | 125 +++++++++++++++++++++++++++++
>  doc/board/qualcomm/debugging.rst |  61 ++++++++++++++
>  doc/board/qualcomm/index.rst     |   4 +-
>  doc/board/qualcomm/qcs404.rst    |  79 ------------------
>  doc/board/qualcomm/sdm845.rst    | 167 ---------------------------------------
>  5 files changed, 188 insertions(+), 248 deletions(-)
>

Apart from minor nits below, feel free to add:

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst
> new file mode 100644
> index 000000000000..4d793209f9e3
> --- /dev/null
> +++ b/doc/board/qualcomm/board.rst
> @@ -0,0 +1,125 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
> +
> +Qualcomm generic boards
> +=======================
> +
> +About this
> +----------
> +This document describes how to build and run U-Boot for Qualcomm generic
> +boards. Right now the generic target supports the Snapdragon 845 SoC, however
> +it's expected to support more SoCs going forward.
> +
> +SDM845 - high-end qualcomm chip, introduced in late 2017.
> +Mostly used in flagship phones and tablets of 2018.
> +
> +The current boot flow support loading u-boot as an Android boot image via

s/support/supports/

> +Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will
> +be appended to the U-Boot image the same way as when booting Linux. U-Boot
> +will then retrieve the DTB during init. This way the memory layout and KASLR
> +offset will be populated by ABL.
> +
> +Installation
> +------------
> +Build
> +^^^^^
> +
> +       $ ./tools/buildman/buildman -o .output qcom
> +
> +This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``.
> +
> +Generate FIT image (optional)
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +See doc/uImage.FIT for more details
> +
> +Pack android boot image
> +^^^^^^^^^^^^^^^^^^^^^^^
> +We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux kernel,
> +and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel

s/expect/expects/

> +with appended dtb, so let's mimic linux to satisfy stock bootloader.
> +
> +Boards
> +------
> +
> +starqlte
> +^^^^^^^^
> +
> +The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
> +based on the Qualcomm SDM845 SoC.
> +
> +This device is supported by the common qcom_defconfig.
> +
> +The DTB is called "sdm845-samsung-starqltechn.dtb"
> +
> +More information can be found on the `Samsung S9 page`_.
> +
> +dragonboard845c
> +^^^^^^^^^^^^^^^
> +
> +The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
> +the Qualcomm SDM845 SoC.
> +
> +This device is supported by the common qcom_defconfig
> +
> +The DTB is called "sdm845-db845c.dtb"
> +
> +More information can be found on the `DragonBoard 845c page`_.
> +
> +qcs404-evb
> +^^^^^^^^^^
> +
> +The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm QCS404 SoC.
> +
> +This device is supported by the common qcom_defconfig
> +
> +The DTB is called "qcs404-evb-4000.dtb"
> +
> +Building steps
> +--------------
> +
> +Steps:
> +
> +- Build u-boot
> +
> +As above::
> +
> +       ./tools/buildman/buildman -o .output qcom
> +
> +Or for db410c (and other boards not supported by the generic target)::
> +
> +       make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig
> +       make O=.output -j$(nproc)
> +
> +- gzip u-boot::
> +
> +       gzip u-boot-nodtb.bin
> +
> +- Append dtb to gzipped u-boot::
> +
> +       cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > u-boot-nodtb.bin.gz-dtb
> +
> +- If you chose to build a FIT image, A ``qcom.its`` file can be found in ``board/qualcomm/generic/``

s/chose/choose/


> +  directory. It expects a folder as ``qcom_imgs/`` in the main directory containing pre-built kernel,
> +  dts and ramdisk images. See ``qcom.its`` for full path to images::
> +
> +       mkimage -f qcom.its qcom.itb
> +
> +- Now we've got everything to build android boot image::
> +
> +       mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \
> +       --output boot.img --pagesize 4096 --base 0x80000000
> +
> +Or with no FIT image::
> +
> +       mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \
> +       --output boot.img --pagesize 4096 --base 0x80000000
> +
> +- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB:
> +
> +  .. code-block:: bash
> +
> +       fastboot flash boot boot.img
> +       fastboot erase dtbo
> +
> +.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
> +.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/
> diff --git a/doc/board/qualcomm/debugging.rst b/doc/board/qualcomm/debugging.rst
> new file mode 100644
> index 000000000000..1c35d1909d12
> --- /dev/null
> +++ b/doc/board/qualcomm/debugging.rst
> @@ -0,0 +1,61 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org>
> +
> +Qualcomm debugging
> +==================
> +
> +About this
> +----------
> +
> +This page describes how to enable early UART and other debugging techniques
> +for Qualcomm boards.
> +
> +Enable debug UART
> +-----------------
> +
> +Newer boards (SDM845 and newer, those with GENI SE UART)
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +Open ``configs/qcom_defconfig`` and add the following snippet to the bottom:
> +
> +       CONFIG_BAUDRATE=115200
> +
> +       # Uncomment to enable UART pre-relocation
> +       CONFIG_DEBUG_UART=y
> +       CONFIG_DEBUG_UART_ANNOUNCE=y
> +       # This is the address of the debug-uart peripheral
> +       # The value here is for SDM845, other platforms will vary
> +       CONFIG_DEBUG_UART_BASE=0xa84000
> +       # Boards older than ~2018 pre-date the GENI driver and unfortunately
> +       # aren't supported here
> +       CONFIG_DEBUG_UART_MSM_GENI=y
> +       # For sdm845 this is the UART clock rate
> +       CONFIG_DEBUG_UART_CLOCK=7372800
> +       # Most newer boards have an oversampling value of 16 instead
> +       # of 32, they need the clock rate to be doubled
> +       #CONFIG_DEBUG_UART_CLOCK=14745600
> +
> +Then build as normal (don't forget to ``make qcom_defconfig``` again).
> +
> +Older boards (db410c and db820c)
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +Open ``configs/dragonboard<BOARD>_defconfig``
> +

In case you don't plan to enable debug UART when U-Boot is the first
stage bootloader then it should atleast be documented here that only
chainloaded configuration supports it.

-Sumit

> +       CONFIG_BAUDRATE=115200
> +       CONFIG_DEBUG_UART=y
> +       CONFIG_DEBUG_UART_ANNOUNCE=y
> +       # db410c - 0x78b0000
> +       # db820c - 0x75b0000
> +       CONFIG_DEBUG_UART_BASE=0x75b0000
> +       CONFIG_DEBUG_UART_MSM=y
> +       CONFIG_DEBUG_UART_CLOCK=7372800
> +       #CONFIG_DEBUG_UART_SKIP_INIT=y
> +
> +       CONFIG_LOG=y
> +       CONFIG_HEXDUMP=y
> +       CONFIG_CMD_LOG=y
> +       CONFIG_LOG_MAX_LEVEL=9
> +       CONFIG_LOG_DEFAULT_LEVEL=9
> +       CONFIG_LOGLEVEL=9
> +
> diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
> index 0f9c4299569a..4955274a39bc 100644
> --- a/doc/board/qualcomm/index.rst
> +++ b/doc/board/qualcomm/index.rst
> @@ -7,5 +7,5 @@ Qualcomm
>     :maxdepth: 2
>
>     dragonboard410c
> -   sdm845
> -   qcs404
> +   board
> +   debugging
> diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
> deleted file mode 100644
> index 0cb71d97c987..000000000000
> --- a/doc/board/qualcomm/qcs404.rst
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0+
> -.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
> -
> -QCS404 EVB
> -==========
> -
> -About this
> -----------
> -This document describes the information about Qualcomm QCS404 evaluation board
> -and it's usage steps.
> -
> -The current boot flow support loading u-boot as an Android boot image via
> -Qualcomm's UEFI-based ABL (Android) Bootloader.
> -
> -Installation
> -------------
> -Build
> -^^^^^
> -Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
> -
> -       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
> -       $ make qcs404evb_defconfig
> -       $ make
> -
> -This will build ``u-boot.bin`` in the configured output directory.
> -
> -Generate FIT image
> -^^^^^^^^^^^^^^^^^^
> -A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
> -It expects a folder as ``qcs404_imgs/`` in the main directory containing
> -pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
> -images.
> -
> -- Build FIT image::
> -
> -       mkimage -f qcs404-evb.its qcs404-evb.itb
> -
> -Pack android boot image
> -^^^^^^^^^^^^^^^^^^^^^^^
> -We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
> -and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
> -with appended dtb, so let's mimic linux to satisfy stock bootloader:
> -
> -- create dump dtb::
> -
> -       workdir=/tmp/prepare_payload
> -       mkdir -p "$workdir"
> -       cd "$workdir"
> -       mock_dtb="$workdir"/payload_mock.dtb
> -
> -       dtc -I dts -O dtb -o "$mock_dtb" << EOF
> -       /dts-v1/;
> -       / {
> -               model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
> -               compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
> -
> -               #address-cells = <2>;
> -               #size-cells = <2>;
> -
> -               memory@80000000 {
> -                       device_type = "memory";
> -                       /* We expect the bootloader to fill in the size */
> -                       reg = <0 0x80000000 0 0>;
> -               };
> -
> -               chosen { };
> -       };
> -       EOF
> -
> -- gzip u-boot ``gzip u-boot.bin``
> -- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
> -
> -Now we've got everything to build android boot image:::
> -
> -       mkbootimg --kernel u-boot.bin.gz-dtb \
> -       --ramdisk qcs404-evb.itb --pagesize 4096 \
> -       --base 0x80000000 --output boot.img
> -
> -Flash image on qcs404-evb using fastboot method.
> diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
> deleted file mode 100644
> index a65f00df39f5..000000000000
> --- a/doc/board/qualcomm/sdm845.rst
> +++ /dev/null
> @@ -1,167 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0+
> -.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
> -
> -Snapdragon 845
> -==============
> -
> -About this
> -----------
> -
> -This document describes the information about Qualcomm Snapdragon 845
> -supported boards and it's usage steps.
> -
> -SDM845 - hi-end qualcomm chip, introduced in late 2017.
> -Mostly used in flagship phones and tablets of 2018.
> -
> -The current boot flow support loading u-boot as an Android boot image via
> -Qualcomm's UEFI-based ABL (Android) Bootloader.
> -
> -Installation
> -------------
> -
> -Build
> -^^^^^
> -
> -Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
> -
> -       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
> -       $ make <your board name here, see Boards section>_defconfig
> -       $ make
> -
> -This will build ``u-boot.bin`` in the configured output directory.
> -
> -Generate FIT image
> -^^^^^^^^^^^^^^^^^^
> -
> -See doc/uImage.FIT for more details
> -
> -Pack android boot image
> -^^^^^^^^^^^^^^^^^^^^^^^
> -
> -We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
> -and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
> -with appended dtb, so let's mimic linux to satisfy stock bootloader.
> -
> -Boards
> -------
> -
> -starqlte
> -^^^^^^^^
> -
> -The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
> -based on the Qualcomm SDM845 SoC.
> -
> -Steps:
> -
> -- Build u-boot::
> -
> -       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
> -       $ make starqltechn_defconfig
> -       $ make
> -
> -- Create dump dtb::
> -
> -       workdir=/tmp/prepare_payload
> -       mkdir -p "$workdir"
> -       cd "$workdir"
> -       mock_dtb="$workdir"/payload_mock.dtb
> -
> -       dtc -I dts -O dtb -o "$mock_dtb" << EOF
> -       /dts-v1/;
> -       / {
> -               memory {
> -                       /* We expect the bootloader to fill in the size */
> -                       reg = <0 0 0 0>;
> -               };
> -
> -               chosen { };
> -       };
> -       EOF
> -
> -- gzip u-boot::
> -
> -       gzip u-boot.bin
> -
> -- Append dtb to gzipped u-boot::
> -
> -       cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
> -
> -- Now we've got everything to build android boot image::
> -
> -       mkbootimg --base 0x0 --kernel_offset 0x00008000 \
> -       --ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
> -       --pagesize 4096 --second_offset 0x00f00000 \
> -       --ramdisk "$fit_image" \
> -       --kernel u-boot.bin.gz-dtb \
> -       -o boot.img
> -
> -- Flash image with your phone's flashing method.
> -
> -More information can be found on the `Samsung S9 page`_.
> -
> -dragonboard845c
> -^^^^^^^^^^^^^^^
> -
> -The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
> -the Qualcomm SDM845 SoC.
> -
> -Steps:
> -
> -- Build u-boot::
> -
> -       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
> -       $ make dragonboard845c_defconfig
> -       $ make
> -
> -- Create dummy dtb::
> -
> -       workdir=/tmp/prepare_payload
> -       mkdir -p "$workdir"
> -       mock_dtb="$workdir"/payload_mock.dtb
> -
> -       dtc -I dts -O dtb -o "$mock_dtb" << EOF
> -       /dts-v1/;
> -       / {
> -               #address-cells = <2>;
> -               #size-cells = <2>;
> -
> -               memory@80000000 {
> -                       device_type = "memory";
> -                       /* We expect the bootloader to fill in the size */
> -                       reg = <0 0x80000000 0 0>;
> -               };
> -
> -               chosen { };
> -       };
> -       EOF
> -
> -- gzip u-boot::
> -
> -       gzip u-boot.bin
> -
> -- Append dtb to gzipped u-boot::
> -
> -        cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
> -
> -- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
> -  directory. It expects a folder as ``db845c_imgs/`` in the main directory
> -  containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
> -  for full path to images::
> -
> -       mkimage -f db845c.its db845c.itb
> -
> -- Now we've got everything to build android boot image::
> -
> -       mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
> -       --output boot.img --pagesize 4096 --base 0x80000000
> -
> -- Flash boot.img using db845c fastboot method:
> -
> -  .. code-block:: bash
> -
> -      sudo fastboot flash boot boot.img
> -
> -More information can be found on the `DragonBoard 845c page`_.
> -
> -.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
> -.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/
>
> --
> 2.43.1
>

Re: [PATCH v4 07/39] serial: msm: add debug UART

[Sumit Garg]

On Tue, 20 Feb 2024 at 17:09, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
>
>
> On 20/02/2024 06:08, Sumit Garg wrote:
> > On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
> >>
> >> Introduce support for early debugging. This relies on the previous stage
> >> bootloader to initialise the UART clocks, when running with U-Boot as
> >> the primary bootloader this feature doesn't work. It will require a way
> >> to configure the clocks before the driver model is available.
> >>
> >> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> >> ---
> >>  drivers/serial/Kconfig      |  8 ++++++++
> >>  drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++
> >>  2 files changed, 45 insertions(+)
> >>
> >> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> >> index 26460c4e0cab..fbd351a47859 100644
> >> --- a/drivers/serial/Kconfig
> >> +++ b/drivers/serial/Kconfig
> >> @@ -319,6 +319,14 @@ config DEBUG_UART_S5P
> >>           will need to provide parameters to make this work. The driver will
> >>           be available until the real driver-model serial is running.
> >>
> >> +config DEBUG_UART_MSM
> >> +       bool "Qualcomm QUP UART debug"
> >> +       depends on ARCH_SNAPDRAGON
> >
> > Since this debug UART only works for chainloaded configuration, can we
> > somehow add explicit dependency here? Something like !REMAKE_ELF?
>
> With a small patch (which didn't make it into v4 apparently) the
> apq8016_clk_init_uart() function from clock-apq8016 can be adjusted to
> just take a base address rather than "struct msm_clk_priv". It can then
> be called from debug_uart_init() and allows for debug UART to be used
> when U-Boot is running as the first stage.
>
> This is definitely not ideal (although fwiw if the GPLLs were configured
> right then this same function could maybe work on QCS404 as well

QCS404 is chainloaded config too, so the debug UART should work there.

> - the
> RCGs are at the same physical addresses), but I don't think gating it
> behind REMAKE_ELF or something is a great solution here.

I don't have a strong opinion here and I could live with just a
documentation update for debug UART too.

-Sumit

Re: [PATCH v4 26/39] doc: board/qualcomm: link to APQ8016 TRM

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> The MSM8916/APQ8016 Technical Reference Manual is publicly available and
> contains a lot of useful register maps for many core parts of the SoC.
> Include an archive.org link to it in the dragonboard410c documentation.
>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  doc/board/qualcomm/dragonboard410c.rst | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/doc/board/qualcomm/dragonboard410c.rst b/doc/board/qualcomm/dragonboard410c.rst
> index d0de9dbcbc9a..34629241110c 100644
> --- a/doc/board/qualcomm/dragonboard410c.rst
> +++ b/doc/board/qualcomm/dragonboard410c.rst
> @@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can replace LK entirely.
>
>  .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/
>
> +.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf
> +
>  Installation
>  ------------
>  First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``::
>
> --
> 2.43.1
>

Re: [PATCH v4 27/39] dt-bindings: import headers for SDM845

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import the DT bindings headers that are used by SDM845 from Linux.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  include/dt-bindings/clock/qcom,camcc-sdm845.h      | 116 ++++++
>  include/dt-bindings/clock/qcom,dispcc-sdm845.h     |  56 +++
>  include/dt-bindings/clock/qcom,gpucc-sdm845.h      |  24 ++
>  include/dt-bindings/clock/qcom,lpass-sdm845.h      |  15 +
>  include/dt-bindings/clock/qcom,rpmh.h              |  37 ++
>  include/dt-bindings/clock/qcom,videocc-sdm845.h    |  35 ++
>  include/dt-bindings/dma/qcom-gpi.h                 |  11 +
>  include/dt-bindings/firmware/qcom,scm.h            |  39 ++
>  include/dt-bindings/iio/qcom,spmi-vadc.h           | 300 +++++++++++++++
>  include/dt-bindings/interconnect/qcom,osm-l3.h     |  15 +
>  include/dt-bindings/interconnect/qcom,sdm845.h     | 150 ++++++++
>  include/dt-bindings/phy/phy-qcom-qmp.h             |  20 +
>  include/dt-bindings/phy/phy-qcom-qusb2.h           |  37 ++
>  include/dt-bindings/pinctrl/qcom,pmic-gpio.h       | 164 ++++++++
>  include/dt-bindings/power/qcom-rpmpd.h             | 412 +++++++++++++++++++++
>  .../dt-bindings/regulator/qcom,rpmh-regulator.h    |  36 ++
>  include/dt-bindings/reset/qcom,sdm845-aoss.h       |  17 +
>  include/dt-bindings/reset/qcom,sdm845-pdc.h        |  22 ++
>  include/dt-bindings/soc/qcom,apr.h                 |  28 ++
>  include/dt-bindings/soc/qcom,rpmh-rsc.h            |  14 +
>  include/dt-bindings/sound/qcom,q6afe.h             |   9 +
>  include/dt-bindings/sound/qcom,q6asm.h             |  26 ++
>  include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 234 ++++++++++++
>  23 files changed, 1817 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
> new file mode 100644
> index 000000000000..4f7a2d2320bf
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
> +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
> +
> +/* CAM_CC clock registers */
> +#define CAM_CC_BPS_AHB_CLK                             0
> +#define CAM_CC_BPS_AREG_CLK                            1
> +#define CAM_CC_BPS_AXI_CLK                             2
> +#define CAM_CC_BPS_CLK                                 3
> +#define CAM_CC_BPS_CLK_SRC                             4
> +#define CAM_CC_CAMNOC_ATB_CLK                          5
> +#define CAM_CC_CAMNOC_AXI_CLK                          6
> +#define CAM_CC_CCI_CLK                                 7
> +#define CAM_CC_CCI_CLK_SRC                             8
> +#define CAM_CC_CPAS_AHB_CLK                            9
> +#define CAM_CC_CPHY_RX_CLK_SRC                         10
> +#define CAM_CC_CSI0PHYTIMER_CLK                                11
> +#define CAM_CC_CSI0PHYTIMER_CLK_SRC                    12
> +#define CAM_CC_CSI1PHYTIMER_CLK                                13
> +#define CAM_CC_CSI1PHYTIMER_CLK_SRC                    14
> +#define CAM_CC_CSI2PHYTIMER_CLK                                15
> +#define CAM_CC_CSI2PHYTIMER_CLK_SRC                    16
> +#define CAM_CC_CSI3PHYTIMER_CLK                                17
> +#define CAM_CC_CSI3PHYTIMER_CLK_SRC                    18
> +#define CAM_CC_CSIPHY0_CLK                             19
> +#define CAM_CC_CSIPHY1_CLK                             20
> +#define CAM_CC_CSIPHY2_CLK                             21
> +#define CAM_CC_CSIPHY3_CLK                             22
> +#define CAM_CC_FAST_AHB_CLK_SRC                                23
> +#define CAM_CC_FD_CORE_CLK                             24
> +#define CAM_CC_FD_CORE_CLK_SRC                         25
> +#define CAM_CC_FD_CORE_UAR_CLK                         26
> +#define CAM_CC_ICP_APB_CLK                             27
> +#define CAM_CC_ICP_ATB_CLK                             28
> +#define CAM_CC_ICP_CLK                                 29
> +#define CAM_CC_ICP_CLK_SRC                             30
> +#define CAM_CC_ICP_CTI_CLK                             31
> +#define CAM_CC_ICP_TS_CLK                              32
> +#define CAM_CC_IFE_0_AXI_CLK                           33
> +#define CAM_CC_IFE_0_CLK                               34
> +#define CAM_CC_IFE_0_CLK_SRC                           35
> +#define CAM_CC_IFE_0_CPHY_RX_CLK                       36
> +#define CAM_CC_IFE_0_CSID_CLK                          37
> +#define CAM_CC_IFE_0_CSID_CLK_SRC                      38
> +#define CAM_CC_IFE_0_DSP_CLK                           39
> +#define CAM_CC_IFE_1_AXI_CLK                           40
> +#define CAM_CC_IFE_1_CLK                               41
> +#define CAM_CC_IFE_1_CLK_SRC                           42
> +#define CAM_CC_IFE_1_CPHY_RX_CLK                       43
> +#define CAM_CC_IFE_1_CSID_CLK                          44
> +#define CAM_CC_IFE_1_CSID_CLK_SRC                      45
> +#define CAM_CC_IFE_1_DSP_CLK                           46
> +#define CAM_CC_IFE_LITE_CLK                            47
> +#define CAM_CC_IFE_LITE_CLK_SRC                                48
> +#define CAM_CC_IFE_LITE_CPHY_RX_CLK                    49
> +#define CAM_CC_IFE_LITE_CSID_CLK                       50
> +#define CAM_CC_IFE_LITE_CSID_CLK_SRC                   51
> +#define CAM_CC_IPE_0_AHB_CLK                           52
> +#define CAM_CC_IPE_0_AREG_CLK                          53
> +#define CAM_CC_IPE_0_AXI_CLK                           54
> +#define CAM_CC_IPE_0_CLK                               55
> +#define CAM_CC_IPE_0_CLK_SRC                           56
> +#define CAM_CC_IPE_1_AHB_CLK                           57
> +#define CAM_CC_IPE_1_AREG_CLK                          58
> +#define CAM_CC_IPE_1_AXI_CLK                           59
> +#define CAM_CC_IPE_1_CLK                               60
> +#define CAM_CC_IPE_1_CLK_SRC                           61
> +#define CAM_CC_JPEG_CLK                                        62
> +#define CAM_CC_JPEG_CLK_SRC                            63
> +#define CAM_CC_LRME_CLK                                        64
> +#define CAM_CC_LRME_CLK_SRC                            65
> +#define CAM_CC_MCLK0_CLK                               66
> +#define CAM_CC_MCLK0_CLK_SRC                           67
> +#define CAM_CC_MCLK1_CLK                               68
> +#define CAM_CC_MCLK1_CLK_SRC                           69
> +#define CAM_CC_MCLK2_CLK                               70
> +#define CAM_CC_MCLK2_CLK_SRC                           71
> +#define CAM_CC_MCLK3_CLK                               72
> +#define CAM_CC_MCLK3_CLK_SRC                           73
> +#define CAM_CC_PLL0                                    74
> +#define CAM_CC_PLL0_OUT_EVEN                           75
> +#define CAM_CC_PLL1                                    76
> +#define CAM_CC_PLL1_OUT_EVEN                           77
> +#define CAM_CC_PLL2                                    78
> +#define CAM_CC_PLL2_OUT_EVEN                           79
> +#define CAM_CC_PLL3                                    80
> +#define CAM_CC_PLL3_OUT_EVEN                           81
> +#define CAM_CC_SLOW_AHB_CLK_SRC                                82
> +#define CAM_CC_SOC_AHB_CLK                             83
> +#define CAM_CC_SYS_TMR_CLK                             84
> +
> +/* CAM_CC Resets */
> +#define TITAN_CAM_CC_CCI_BCR                           0
> +#define TITAN_CAM_CC_CPAS_BCR                          1
> +#define TITAN_CAM_CC_CSI0PHY_BCR                       2
> +#define TITAN_CAM_CC_CSI1PHY_BCR                       3
> +#define TITAN_CAM_CC_CSI2PHY_BCR                       4
> +#define TITAN_CAM_CC_MCLK0_BCR                         5
> +#define TITAN_CAM_CC_MCLK1_BCR                         6
> +#define TITAN_CAM_CC_MCLK2_BCR                         7
> +#define TITAN_CAM_CC_MCLK3_BCR                         8
> +#define TITAN_CAM_CC_TITAN_TOP_BCR                     9
> +
> +/* CAM_CC GDSCRs */
> +#define BPS_GDSC                                       0
> +#define IPE_0_GDSC                                     1
> +#define IPE_1_GDSC                                     2
> +#define IFE_0_GDSC                                     3
> +#define IFE_1_GDSC                                     4
> +#define TITAN_TOP_GDSC                                 5
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
> new file mode 100644
> index 000000000000..4016fd1d5b46
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
> +#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
> +
> +/* DISP_CC clock registers */
> +#define DISP_CC_MDSS_AHB_CLK                                   0
> +#define DISP_CC_MDSS_AXI_CLK                                   1
> +#define DISP_CC_MDSS_BYTE0_CLK                                 2
> +#define DISP_CC_MDSS_BYTE0_CLK_SRC                             3
> +#define DISP_CC_MDSS_BYTE0_INTF_CLK                            4
> +#define DISP_CC_MDSS_BYTE1_CLK                                 5
> +#define DISP_CC_MDSS_BYTE1_CLK_SRC                             6
> +#define DISP_CC_MDSS_BYTE1_INTF_CLK                            7
> +#define DISP_CC_MDSS_ESC0_CLK                                  8
> +#define DISP_CC_MDSS_ESC0_CLK_SRC                              9
> +#define DISP_CC_MDSS_ESC1_CLK                                  10
> +#define DISP_CC_MDSS_ESC1_CLK_SRC                              11
> +#define DISP_CC_MDSS_MDP_CLK                                   12
> +#define DISP_CC_MDSS_MDP_CLK_SRC                               13
> +#define DISP_CC_MDSS_MDP_LUT_CLK                               14
> +#define DISP_CC_MDSS_PCLK0_CLK                                 15
> +#define DISP_CC_MDSS_PCLK0_CLK_SRC                             16
> +#define DISP_CC_MDSS_PCLK1_CLK                                 17
> +#define DISP_CC_MDSS_PCLK1_CLK_SRC                             18
> +#define DISP_CC_MDSS_ROT_CLK                                   19
> +#define DISP_CC_MDSS_ROT_CLK_SRC                               20
> +#define DISP_CC_MDSS_RSCC_AHB_CLK                              21
> +#define DISP_CC_MDSS_RSCC_VSYNC_CLK                            22
> +#define DISP_CC_MDSS_VSYNC_CLK                                 23
> +#define DISP_CC_MDSS_VSYNC_CLK_SRC                             24
> +#define DISP_CC_PLL0                                           25
> +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                         26
> +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC                         27
> +#define DISP_CC_MDSS_DP_AUX_CLK                                        28
> +#define DISP_CC_MDSS_DP_AUX_CLK_SRC                            29
> +#define DISP_CC_MDSS_DP_CRYPTO_CLK                             30
> +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC                         31
> +#define DISP_CC_MDSS_DP_LINK_CLK                               32
> +#define DISP_CC_MDSS_DP_LINK_CLK_SRC                           33
> +#define DISP_CC_MDSS_DP_LINK_INTF_CLK                          34
> +#define DISP_CC_MDSS_DP_PIXEL1_CLK                             35
> +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC                         36
> +#define DISP_CC_MDSS_DP_PIXEL_CLK                              37
> +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC                          38
> +
> +/* DISP_CC Reset */
> +#define DISP_CC_MDSS_RSCC_BCR                                  0
> +
> +/* DISP_CC GDSCR */
> +#define MDSS_GDSC                                              0
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
> new file mode 100644
> index 000000000000..9690d901b50a
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
> +#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
> +
> +/* GPU_CC clock registers */
> +#define GPU_CC_CX_GMU_CLK                      0
> +#define GPU_CC_CXO_CLK                         1
> +#define GPU_CC_GMU_CLK_SRC                     2
> +#define GPU_CC_PLL1                            3
> +
> +/* GPU_CC Resets */
> +#define GPUCC_GPU_CC_CX_BCR                    0
> +#define GPUCC_GPU_CC_GMU_BCR                   1
> +#define GPUCC_GPU_CC_XO_BCR                    2
> +
> +/* GPU_CC GDSCRs */
> +#define GPU_CX_GDSC                            0
> +#define GPU_GX_GDSC                            1
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h
> new file mode 100644
> index 000000000000..659050846f61
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,lpass-sdm845.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
> +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
> +
> +#define LPASS_Q6SS_AHBM_AON_CLK                                0
> +#define LPASS_Q6SS_AHBS_AON_CLK                                1
> +#define LPASS_QDSP6SS_XO_CLK                           2
> +#define LPASS_QDSP6SS_SLEEP_CLK                                3
> +#define LPASS_QDSP6SS_CORE_CLK                         4
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
> new file mode 100644
> index 000000000000..0a7d1be0d124
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,rpmh.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
> +
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
> +#define _DT_BINDINGS_CLK_MSM_RPMH_H
> +
> +/* RPMh controlled clocks */
> +#define RPMH_CXO_CLK                           0
> +#define RPMH_CXO_CLK_A                         1
> +#define RPMH_LN_BB_CLK2                                2
> +#define RPMH_LN_BB_CLK2_A                      3
> +#define RPMH_LN_BB_CLK3                                4
> +#define RPMH_LN_BB_CLK3_A                      5
> +#define RPMH_RF_CLK1                           6
> +#define RPMH_RF_CLK1_A                         7
> +#define RPMH_RF_CLK2                           8
> +#define RPMH_RF_CLK2_A                         9
> +#define RPMH_RF_CLK3                           10
> +#define RPMH_RF_CLK3_A                         11
> +#define RPMH_IPA_CLK                           12
> +#define RPMH_LN_BB_CLK1                                13
> +#define RPMH_LN_BB_CLK1_A                      14
> +#define RPMH_CE_CLK                            15
> +#define RPMH_QPIC_CLK                          16
> +#define RPMH_DIV_CLK1                          17
> +#define RPMH_DIV_CLK1_A                                18
> +#define RPMH_RF_CLK4                           19
> +#define RPMH_RF_CLK4_A                         20
> +#define RPMH_RF_CLK5                           21
> +#define RPMH_RF_CLK5_A                         22
> +#define RPMH_PKA_CLK                           23
> +#define RPMH_HWKM_CLK                          24
> +#define RPMH_QLINK_CLK                         25
> +#define RPMH_QLINK_CLK_A                       26
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
> new file mode 100644
> index 000000000000..1b868165e8ce
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
> +#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
> +
> +/* VIDEO_CC clock registers */
> +#define VIDEO_CC_APB_CLK               0
> +#define VIDEO_CC_AT_CLK                        1
> +#define VIDEO_CC_QDSS_TRIG_CLK         2
> +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK   3
> +#define VIDEO_CC_VCODEC0_AXI_CLK       4
> +#define VIDEO_CC_VCODEC0_CORE_CLK      5
> +#define VIDEO_CC_VCODEC1_AXI_CLK       6
> +#define VIDEO_CC_VCODEC1_CORE_CLK      7
> +#define VIDEO_CC_VENUS_AHB_CLK         8
> +#define VIDEO_CC_VENUS_CLK_SRC         9
> +#define VIDEO_CC_VENUS_CTL_AXI_CLK     10
> +#define VIDEO_CC_VENUS_CTL_CORE_CLK    11
> +#define VIDEO_PLL0                     12
> +
> +/* VIDEO_CC Resets */
> +#define VIDEO_CC_VENUS_BCR             0
> +#define VIDEO_CC_VCODEC0_BCR           1
> +#define VIDEO_CC_VCODEC1_BCR           2
> +#define VIDEO_CC_INTERFACE_BCR         3
> +
> +/* VIDEO_CC GDSCRs */
> +#define VENUS_GDSC                     0
> +#define VCODEC0_GDSC                   1
> +#define VCODEC1_GDSC                   2
> +
> +#endif
> diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h
> new file mode 100644
> index 000000000000..ebda2a37f52a
> --- /dev/null
> +++ b/include/dt-bindings/dma/qcom-gpi.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Copyright (c) 2020, Linaro Ltd.  */
> +
> +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
> +#define __DT_BINDINGS_DMA_QCOM_GPI_H__
> +
> +#define QCOM_GPI_SPI           1
> +#define QCOM_GPI_UART          2
> +#define QCOM_GPI_I2C           3
> +
> +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */
> diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h
> new file mode 100644
> index 000000000000..6de8b08e1e79
> --- /dev/null
> +++ b/include/dt-bindings/firmware/qcom,scm.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
> +#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
> +
> +#define QCOM_SCM_VMID_TZ               0x1
> +#define QCOM_SCM_VMID_HLOS             0x3
> +#define QCOM_SCM_VMID_SSC_Q6           0x5
> +#define QCOM_SCM_VMID_ADSP_Q6          0x6
> +#define QCOM_SCM_VMID_CP_TOUCH         0x8
> +#define QCOM_SCM_VMID_CP_BITSTREAM     0x9
> +#define QCOM_SCM_VMID_CP_PIXEL         0xA
> +#define QCOM_SCM_VMID_CP_NON_PIXEL     0xB
> +#define QCOM_SCM_VMID_CP_CAMERA                0xD
> +#define QCOM_SCM_VMID_HLOS_FREE                0xE
> +#define QCOM_SCM_VMID_MSS_MSA          0xF
> +#define QCOM_SCM_VMID_MSS_NONMSA       0x10
> +#define QCOM_SCM_VMID_CP_SEC_DISPLAY   0x11
> +#define QCOM_SCM_VMID_CP_APP           0x12
> +#define QCOM_SCM_VMID_LPASS            0x16
> +#define QCOM_SCM_VMID_WLAN             0x18
> +#define QCOM_SCM_VMID_WLAN_CE          0x19
> +#define QCOM_SCM_VMID_CP_SPSS_SP       0x1A
> +#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D
> +#define QCOM_SCM_VMID_CDSP             0x1E
> +#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22
> +#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24
> +#define QCOM_SCM_VMID_ADSP_HEAP                0x25
> +#define QCOM_SCM_VMID_CP_CDSP          0x2A
> +#define QCOM_SCM_VMID_NAV              0x2B
> +#define QCOM_SCM_VMID_TVM              0x2D
> +#define QCOM_SCM_VMID_OEMVM            0x31
> +
> +#endif
> diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
> new file mode 100644
> index 000000000000..08adfe25964c
> --- /dev/null
> +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
> @@ -0,0 +1,300 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_H
> +
> +/* Voltage ADC channels */
> +#define VADC_USBIN                             0x00
> +#define VADC_DCIN                              0x01
> +#define VADC_VCHG_SNS                          0x02
> +#define VADC_SPARE1_03                         0x03
> +#define VADC_USB_ID_MV                         0x04
> +#define VADC_VCOIN                             0x05
> +#define VADC_VBAT_SNS                          0x06
> +#define VADC_VSYS                              0x07
> +#define VADC_DIE_TEMP                          0x08
> +#define VADC_REF_625MV                         0x09
> +#define VADC_REF_1250MV                                0x0a
> +#define VADC_CHG_TEMP                          0x0b
> +#define VADC_SPARE1                            0x0c
> +#define VADC_SPARE2                            0x0d
> +#define VADC_GND_REF                           0x0e
> +#define VADC_VDD_VADC                          0x0f
> +
> +#define VADC_P_MUX1_1_1                                0x10
> +#define VADC_P_MUX2_1_1                                0x11
> +#define VADC_P_MUX3_1_1                                0x12
> +#define VADC_P_MUX4_1_1                                0x13
> +#define VADC_P_MUX5_1_1                                0x14
> +#define VADC_P_MUX6_1_1                                0x15
> +#define VADC_P_MUX7_1_1                                0x16
> +#define VADC_P_MUX8_1_1                                0x17
> +#define VADC_P_MUX9_1_1                                0x18
> +#define VADC_P_MUX10_1_1                       0x19
> +#define VADC_P_MUX11_1_1                       0x1a
> +#define VADC_P_MUX12_1_1                       0x1b
> +#define VADC_P_MUX13_1_1                       0x1c
> +#define VADC_P_MUX14_1_1                       0x1d
> +#define VADC_P_MUX15_1_1                       0x1e
> +#define VADC_P_MUX16_1_1                       0x1f
> +
> +#define VADC_P_MUX1_1_3                                0x20
> +#define VADC_P_MUX2_1_3                                0x21
> +#define VADC_P_MUX3_1_3                                0x22
> +#define VADC_P_MUX4_1_3                                0x23
> +#define VADC_P_MUX5_1_3                                0x24
> +#define VADC_P_MUX6_1_3                                0x25
> +#define VADC_P_MUX7_1_3                                0x26
> +#define VADC_P_MUX8_1_3                                0x27
> +#define VADC_P_MUX9_1_3                                0x28
> +#define VADC_P_MUX10_1_3                       0x29
> +#define VADC_P_MUX11_1_3                       0x2a
> +#define VADC_P_MUX12_1_3                       0x2b
> +#define VADC_P_MUX13_1_3                       0x2c
> +#define VADC_P_MUX14_1_3                       0x2d
> +#define VADC_P_MUX15_1_3                       0x2e
> +#define VADC_P_MUX16_1_3                       0x2f
> +
> +#define VADC_LR_MUX1_BAT_THERM                 0x30
> +#define VADC_LR_MUX2_BAT_ID                    0x31
> +#define VADC_LR_MUX3_XO_THERM                  0x32
> +#define VADC_LR_MUX4_AMUX_THM1                 0x33
> +#define VADC_LR_MUX5_AMUX_THM2                 0x34
> +#define VADC_LR_MUX6_AMUX_THM3                 0x35
> +#define VADC_LR_MUX7_HW_ID                     0x36
> +#define VADC_LR_MUX8_AMUX_THM4                 0x37
> +#define VADC_LR_MUX9_AMUX_THM5                 0x38
> +#define VADC_LR_MUX10_USB_ID                   0x39
> +#define VADC_AMUX_PU1                          0x3a
> +#define VADC_AMUX_PU2                          0x3b
> +#define VADC_LR_MUX3_BUF_XO_THERM              0x3c
> +
> +#define VADC_LR_MUX1_PU1_BAT_THERM             0x70
> +#define VADC_LR_MUX2_PU1_BAT_ID                        0x71
> +#define VADC_LR_MUX3_PU1_XO_THERM              0x72
> +#define VADC_LR_MUX4_PU1_AMUX_THM1             0x73
> +#define VADC_LR_MUX5_PU1_AMUX_THM2             0x74
> +#define VADC_LR_MUX6_PU1_AMUX_THM3             0x75
> +#define VADC_LR_MUX7_PU1_AMUX_HW_ID            0x76
> +#define VADC_LR_MUX8_PU1_AMUX_THM4             0x77
> +#define VADC_LR_MUX9_PU1_AMUX_THM5             0x78
> +#define VADC_LR_MUX10_PU1_AMUX_USB_ID          0x79
> +#define VADC_LR_MUX3_BUF_PU1_XO_THERM          0x7c
> +
> +#define VADC_LR_MUX1_PU2_BAT_THERM             0xb0
> +#define VADC_LR_MUX2_PU2_BAT_ID                        0xb1
> +#define VADC_LR_MUX3_PU2_XO_THERM              0xb2
> +#define VADC_LR_MUX4_PU2_AMUX_THM1             0xb3
> +#define VADC_LR_MUX5_PU2_AMUX_THM2             0xb4
> +#define VADC_LR_MUX6_PU2_AMUX_THM3             0xb5
> +#define VADC_LR_MUX7_PU2_AMUX_HW_ID            0xb6
> +#define VADC_LR_MUX8_PU2_AMUX_THM4             0xb7
> +#define VADC_LR_MUX9_PU2_AMUX_THM5             0xb8
> +#define VADC_LR_MUX10_PU2_AMUX_USB_ID          0xb9
> +#define VADC_LR_MUX3_BUF_PU2_XO_THERM          0xbc
> +
> +#define VADC_LR_MUX1_PU1_PU2_BAT_THERM         0xf0
> +#define VADC_LR_MUX2_PU1_PU2_BAT_ID            0xf1
> +#define VADC_LR_MUX3_PU1_PU2_XO_THERM          0xf2
> +#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1         0xf3
> +#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2         0xf4
> +#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3         0xf5
> +#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID                0xf6
> +#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4         0xf7
> +#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5         0xf8
> +#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID      0xf9
> +#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM      0xfc
> +
> +/* ADC channels for SPMI PMIC5 */
> +
> +#define ADC5_REF_GND                           0x00
> +#define ADC5_1P25VREF                          0x01
> +#define ADC5_VREF_VADC                         0x02
> +#define ADC5_VREF_VADC5_DIV_3                  0x82
> +#define ADC5_VPH_PWR                           0x83
> +#define ADC5_VBAT_SNS                          0x84
> +#define ADC5_VCOIN                             0x85
> +#define ADC5_DIE_TEMP                          0x06
> +#define ADC5_USB_IN_I                          0x07
> +#define ADC5_USB_IN_V_16                       0x08
> +#define ADC5_CHG_TEMP                          0x09
> +#define ADC5_BAT_THERM                         0x0a
> +#define ADC5_BAT_ID                            0x0b
> +#define ADC5_XO_THERM                          0x0c
> +#define ADC5_AMUX_THM1                         0x0d
> +#define ADC5_AMUX_THM2                         0x0e
> +#define ADC5_AMUX_THM3                         0x0f
> +#define ADC5_AMUX_THM4                         0x10
> +#define ADC5_AMUX_THM5                         0x11
> +#define ADC5_GPIO1                             0x12
> +#define ADC5_GPIO2                             0x13
> +#define ADC5_GPIO3                             0x14
> +#define ADC5_GPIO4                             0x15
> +#define ADC5_GPIO5                             0x16
> +#define ADC5_GPIO6                             0x17
> +#define ADC5_GPIO7                             0x18
> +#define ADC5_SBUx                              0x99
> +#define ADC5_MID_CHG_DIV6                      0x1e
> +#define ADC5_OFF                               0xff
> +
> +/* 30k pull-up1 */
> +#define ADC5_BAT_THERM_30K_PU                  0x2a
> +#define ADC5_BAT_ID_30K_PU                     0x2b
> +#define ADC5_XO_THERM_30K_PU                   0x2c
> +#define ADC5_AMUX_THM1_30K_PU                  0x2d
> +#define ADC5_AMUX_THM2_30K_PU                  0x2e
> +#define ADC5_AMUX_THM3_30K_PU                  0x2f
> +#define ADC5_AMUX_THM4_30K_PU                  0x30
> +#define ADC5_AMUX_THM5_30K_PU                  0x31
> +#define ADC5_GPIO1_30K_PU                      0x32
> +#define ADC5_GPIO2_30K_PU                      0x33
> +#define ADC5_GPIO3_30K_PU                      0x34
> +#define ADC5_GPIO4_30K_PU                      0x35
> +#define ADC5_GPIO5_30K_PU                      0x36
> +#define ADC5_GPIO6_30K_PU                      0x37
> +#define ADC5_GPIO7_30K_PU                      0x38
> +#define ADC5_SBUx_30K_PU                       0x39
> +
> +/* 100k pull-up2 */
> +#define ADC5_BAT_THERM_100K_PU                 0x4a
> +#define ADC5_BAT_ID_100K_PU                    0x4b
> +#define ADC5_XO_THERM_100K_PU                  0x4c
> +#define ADC5_AMUX_THM1_100K_PU                 0x4d
> +#define ADC5_AMUX_THM2_100K_PU                 0x4e
> +#define ADC5_AMUX_THM3_100K_PU                 0x4f
> +#define ADC5_AMUX_THM4_100K_PU                 0x50
> +#define ADC5_AMUX_THM5_100K_PU                 0x51
> +#define ADC5_GPIO1_100K_PU                     0x52
> +#define ADC5_GPIO2_100K_PU                     0x53
> +#define ADC5_GPIO3_100K_PU                     0x54
> +#define ADC5_GPIO4_100K_PU                     0x55
> +#define ADC5_GPIO5_100K_PU                     0x56
> +#define ADC5_GPIO6_100K_PU                     0x57
> +#define ADC5_GPIO7_100K_PU                     0x58
> +#define ADC5_SBUx_100K_PU                      0x59
> +
> +/* 400k pull-up3 */
> +#define ADC5_BAT_THERM_400K_PU                 0x6a
> +#define ADC5_BAT_ID_400K_PU                    0x6b
> +#define ADC5_XO_THERM_400K_PU                  0x6c
> +#define ADC5_AMUX_THM1_400K_PU                 0x6d
> +#define ADC5_AMUX_THM2_400K_PU                 0x6e
> +#define ADC5_AMUX_THM3_400K_PU                 0x6f
> +#define ADC5_AMUX_THM4_400K_PU                 0x70
> +#define ADC5_AMUX_THM5_400K_PU                 0x71
> +#define ADC5_GPIO1_400K_PU                     0x72
> +#define ADC5_GPIO2_400K_PU                     0x73
> +#define ADC5_GPIO3_400K_PU                     0x74
> +#define ADC5_GPIO4_400K_PU                     0x75
> +#define ADC5_GPIO5_400K_PU                     0x76
> +#define ADC5_GPIO6_400K_PU                     0x77
> +#define ADC5_GPIO7_400K_PU                     0x78
> +#define ADC5_SBUx_400K_PU                      0x79
> +
> +/* 1/3 Divider */
> +#define ADC5_GPIO1_DIV3                                0x92
> +#define ADC5_GPIO2_DIV3                                0x93
> +#define ADC5_GPIO3_DIV3                                0x94
> +#define ADC5_GPIO4_DIV3                                0x95
> +#define ADC5_GPIO5_DIV3                                0x96
> +#define ADC5_GPIO6_DIV3                                0x97
> +#define ADC5_GPIO7_DIV3                                0x98
> +#define ADC5_SBUx_DIV3                         0x99
> +
> +/* Current and combined current/voltage channels */
> +#define ADC5_INT_EXT_ISENSE                    0xa1
> +#define ADC5_PARALLEL_ISENSE                   0xa5
> +#define ADC5_CUR_REPLICA_VDS                   0xa7
> +#define ADC5_CUR_SENS_BATFET_VDS_OFFSET                0xa9
> +#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET       0xab
> +#define ADC5_EXT_SENS_OFFSET                   0xad
> +
> +#define ADC5_INT_EXT_ISENSE_VBAT_VDATA         0xb0
> +#define ADC5_INT_EXT_ISENSE_VBAT_IDATA         0xb1
> +#define ADC5_EXT_ISENSE_VBAT_VDATA             0xb2
> +#define ADC5_EXT_ISENSE_VBAT_IDATA             0xb3
> +#define ADC5_PARALLEL_ISENSE_VBAT_VDATA                0xb4
> +#define ADC5_PARALLEL_ISENSE_VBAT_IDATA                0xb5
> +
> +#define ADC5_MAX_CHANNEL                       0xc0
> +
> +/* ADC channels for ADC for PMIC7 */
> +
> +#define ADC7_REF_GND                           0x00
> +#define ADC7_1P25VREF                          0x01
> +#define ADC7_VREF_VADC                         0x02
> +#define ADC7_DIE_TEMP                          0x03
> +
> +#define ADC7_AMUX_THM1                         0x04
> +#define ADC7_AMUX_THM2                         0x05
> +#define ADC7_AMUX_THM3                         0x06
> +#define ADC7_AMUX_THM4                         0x07
> +#define ADC7_AMUX_THM5                         0x08
> +#define ADC7_AMUX_THM6                         0x09
> +#define ADC7_GPIO1                             0x0a
> +#define ADC7_GPIO2                             0x0b
> +#define ADC7_GPIO3                             0x0c
> +#define ADC7_GPIO4                             0x0d
> +
> +#define ADC7_CHG_TEMP                          0x10
> +#define ADC7_USB_IN_V_16                       0x11
> +#define ADC7_VDC_16                            0x12
> +#define ADC7_CC1_ID                            0x13
> +#define ADC7_VREF_BAT_THERM                    0x15
> +#define ADC7_IIN_FB                            0x17
> +
> +/* 30k pull-up1 */
> +#define ADC7_AMUX_THM1_30K_PU                  0x24
> +#define ADC7_AMUX_THM2_30K_PU                  0x25
> +#define ADC7_AMUX_THM3_30K_PU                  0x26
> +#define ADC7_AMUX_THM4_30K_PU                  0x27
> +#define ADC7_AMUX_THM5_30K_PU                  0x28
> +#define ADC7_AMUX_THM6_30K_PU                  0x29
> +#define ADC7_GPIO1_30K_PU                      0x2a
> +#define ADC7_GPIO2_30K_PU                      0x2b
> +#define ADC7_GPIO3_30K_PU                      0x2c
> +#define ADC7_GPIO4_30K_PU                      0x2d
> +#define ADC7_CC1_ID_30K_PU                     0x33
> +
> +/* 100k pull-up2 */
> +#define ADC7_AMUX_THM1_100K_PU                 0x44
> +#define ADC7_AMUX_THM2_100K_PU                 0x45
> +#define ADC7_AMUX_THM3_100K_PU                 0x46
> +#define ADC7_AMUX_THM4_100K_PU                 0x47
> +#define ADC7_AMUX_THM5_100K_PU                 0x48
> +#define ADC7_AMUX_THM6_100K_PU                 0x49
> +#define ADC7_GPIO1_100K_PU                     0x4a
> +#define ADC7_GPIO2_100K_PU                     0x4b
> +#define ADC7_GPIO3_100K_PU                     0x4c
> +#define ADC7_GPIO4_100K_PU                     0x4d
> +#define ADC7_CC1_ID_100K_PU                    0x53
> +
> +/* 400k pull-up3 */
> +#define ADC7_AMUX_THM1_400K_PU                 0x64
> +#define ADC7_AMUX_THM2_400K_PU                 0x65
> +#define ADC7_AMUX_THM3_400K_PU                 0x66
> +#define ADC7_AMUX_THM4_400K_PU                 0x67
> +#define ADC7_AMUX_THM5_400K_PU                 0x68
> +#define ADC7_AMUX_THM6_400K_PU                 0x69
> +#define ADC7_GPIO1_400K_PU                     0x6a
> +#define ADC7_GPIO2_400K_PU                     0x6b
> +#define ADC7_GPIO3_400K_PU                     0x6c
> +#define ADC7_GPIO4_400K_PU                     0x6d
> +#define ADC7_CC1_ID_400K_PU                    0x73
> +
> +/* 1/3 Divider */
> +#define ADC7_GPIO1_DIV3                                0x8a
> +#define ADC7_GPIO2_DIV3                                0x8b
> +#define ADC7_GPIO3_DIV3                                0x8c
> +#define ADC7_GPIO4_DIV3                                0x8d
> +
> +#define ADC7_VPH_PWR                           0x8e
> +#define ADC7_VBAT_SNS                          0x8f
> +
> +#define ADC7_SBUx                              0x94
> +#define ADC7_VBAT_2S_MID                       0x96
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
> diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
> new file mode 100644
> index 000000000000..61ef649ae565
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> +
> +#define MASTER_OSM_L3_APPS     0
> +#define SLAVE_OSM_L3           1
> +
> +#define MASTER_EPSS_L3_APPS    0
> +#define SLAVE_EPSS_L3_SHARED   1
> +
> +#endif
> diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
> new file mode 100644
> index 000000000000..67b500e24915
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,sdm845.h
> @@ -0,0 +1,150 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Qualcomm SDM845 interconnect IDs
> + *
> + * Copyright (c) 2018, Linaro Ltd.
> + * Author: Georgi Djakov <georgi.djakov@linaro.org>
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
> +
> +#define MASTER_A1NOC_CFG               0
> +#define MASTER_TSIF                    1
> +#define MASTER_SDCC_2                  2
> +#define MASTER_SDCC_4                  3
> +#define MASTER_UFS_CARD                        4
> +#define MASTER_UFS_MEM                 5
> +#define MASTER_PCIE_0                  6
> +#define SLAVE_A1NOC_SNOC               7
> +#define SLAVE_SERVICE_A1NOC            8
> +#define SLAVE_ANOC_PCIE_A1NOC_SNOC     9
> +#define MASTER_QUP_1                   10
> +
> +#define MASTER_A2NOC_CFG               0
> +#define MASTER_QDSS_BAM                        1
> +#define MASTER_CNOC_A2NOC              2
> +#define MASTER_CRYPTO                  3
> +#define MASTER_IPA                     4
> +#define MASTER_PCIE_1                  5
> +#define MASTER_QDSS_ETR                        6
> +#define MASTER_USB3_0                  7
> +#define MASTER_USB3_1                  8
> +#define SLAVE_A2NOC_SNOC               9
> +#define SLAVE_ANOC_PCIE_SNOC           10
> +#define SLAVE_SERVICE_A2NOC            11
> +#define MASTER_QUP_2                   12
> +
> +#define MASTER_SPDM                    0
> +#define MASTER_TIC                     1
> +#define MASTER_SNOC_CNOC               2
> +#define MASTER_QDSS_DAP                        3
> +#define SLAVE_A1NOC_CFG                        4
> +#define SLAVE_A2NOC_CFG                        5
> +#define SLAVE_AOP                      6
> +#define SLAVE_AOSS                     7
> +#define SLAVE_CAMERA_CFG               8
> +#define SLAVE_CLK_CTL                  9
> +#define SLAVE_CDSP_CFG                 10
> +#define SLAVE_RBCPR_CX_CFG             11
> +#define SLAVE_CRYPTO_0_CFG             12
> +#define SLAVE_DCC_CFG                  13
> +#define SLAVE_CNOC_DDRSS               14
> +#define SLAVE_DISPLAY_CFG              15
> +#define SLAVE_GLM                      16
> +#define SLAVE_GFX3D_CFG                        17
> +#define SLAVE_IMEM_CFG                 18
> +#define SLAVE_IPA_CFG                  19
> +#define SLAVE_CNOC_MNOC_CFG            20
> +#define SLAVE_PCIE_0_CFG               21
> +#define SLAVE_PCIE_1_CFG               22
> +#define SLAVE_PDM                      23
> +#define SLAVE_SOUTH_PHY_CFG            24
> +#define SLAVE_PIMEM_CFG                        25
> +#define SLAVE_PRNG                     26
> +#define SLAVE_QDSS_CFG                 27
> +#define SLAVE_BLSP_2                   28
> +#define SLAVE_BLSP_1                   29
> +#define SLAVE_SDCC_2                   30
> +#define SLAVE_SDCC_4                   31
> +#define SLAVE_SNOC_CFG                 32
> +#define SLAVE_SPDM_WRAPPER             33
> +#define SLAVE_SPSS_CFG                 34
> +#define SLAVE_TCSR                     35
> +#define SLAVE_TLMM_NORTH               36
> +#define SLAVE_TLMM_SOUTH               37
> +#define SLAVE_TSIF                     38
> +#define SLAVE_UFS_CARD_CFG             39
> +#define SLAVE_UFS_MEM_CFG              40
> +#define SLAVE_USB3_0                   41
> +#define SLAVE_USB3_1                   42
> +#define SLAVE_VENUS_CFG                        43
> +#define SLAVE_VSENSE_CTRL_CFG          44
> +#define SLAVE_CNOC_A2NOC               45
> +#define SLAVE_SERVICE_CNOC             46
> +
> +#define MASTER_CNOC_DC_NOC             0
> +#define SLAVE_LLCC_CFG                 1
> +#define SLAVE_MEM_NOC_CFG              2
> +
> +#define MASTER_APPSS_PROC              0
> +#define MASTER_GNOC_CFG                        1
> +#define SLAVE_GNOC_SNOC                        2
> +#define SLAVE_GNOC_MEM_NOC             3
> +#define SLAVE_SERVICE_GNOC             4
> +
> +#define MASTER_TCU_0                   0
> +#define MASTER_MEM_NOC_CFG             1
> +#define MASTER_GNOC_MEM_NOC            2
> +#define MASTER_MNOC_HF_MEM_NOC         3
> +#define MASTER_MNOC_SF_MEM_NOC         4
> +#define MASTER_SNOC_GC_MEM_NOC         5
> +#define MASTER_SNOC_SF_MEM_NOC         6
> +#define MASTER_GFX3D                   7
> +#define SLAVE_MSS_PROC_MS_MPU_CFG      8
> +#define SLAVE_MEM_NOC_GNOC             9
> +#define SLAVE_LLCC                     10
> +#define SLAVE_MEM_NOC_SNOC             11
> +#define SLAVE_SERVICE_MEM_NOC          12
> +#define MASTER_LLCC                    13
> +#define SLAVE_EBI1                     14
> +
> +#define MASTER_CNOC_MNOC_CFG           0
> +#define MASTER_CAMNOC_HF0              1
> +#define MASTER_CAMNOC_HF1              2
> +#define MASTER_CAMNOC_SF               3
> +#define MASTER_MDP0                    4
> +#define MASTER_MDP1                    5
> +#define MASTER_ROTATOR                 6
> +#define MASTER_VIDEO_P0                        7
> +#define MASTER_VIDEO_P1                        8
> +#define MASTER_VIDEO_PROC              9
> +#define SLAVE_MNOC_SF_MEM_NOC          10
> +#define SLAVE_MNOC_HF_MEM_NOC          11
> +#define SLAVE_SERVICE_MNOC             12
> +#define MASTER_CAMNOC_HF0_UNCOMP       13
> +#define MASTER_CAMNOC_HF1_UNCOMP       14
> +#define MASTER_CAMNOC_SF_UNCOMP                15
> +#define SLAVE_CAMNOC_UNCOMP            16
> +
> +#define MASTER_SNOC_CFG                        0
> +#define MASTER_A1NOC_SNOC              1
> +#define MASTER_A2NOC_SNOC              2
> +#define MASTER_GNOC_SNOC               3
> +#define MASTER_MEM_NOC_SNOC            4
> +#define MASTER_ANOC_PCIE_SNOC          5
> +#define MASTER_PIMEM                   6
> +#define MASTER_GIC                     7
> +#define SLAVE_APPSS                    8
> +#define SLAVE_SNOC_CNOC                        9
> +#define SLAVE_SNOC_MEM_NOC_GC          10
> +#define SLAVE_SNOC_MEM_NOC_SF          11
> +#define SLAVE_IMEM                     12
> +#define SLAVE_PCIE_0                   13
> +#define SLAVE_PCIE_1                   14
> +#define SLAVE_PIMEM                    15
> +#define SLAVE_SERVICE_SNOC             16
> +#define SLAVE_QDSS_STM                 17
> +#define SLAVE_TCU                      18
> +
> +#endif
> diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
> new file mode 100644
> index 000000000000..4edec4c5b224
> --- /dev/null
> +++ b/include/dt-bindings/phy/phy-qcom-qmp.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
> +/*
> + * Qualcomm QMP PHY constants
> + *
> + * Copyright (C) 2022 Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_PHY_QMP
> +#define _DT_BINDINGS_PHY_QMP
> +
> +/* QMP USB4-USB3-DP clocks */
> +#define QMP_USB43DP_USB3_PIPE_CLK      0
> +#define QMP_USB43DP_DP_LINK_CLK                1
> +#define QMP_USB43DP_DP_VCO_DIV_CLK     2
> +
> +/* QMP USB4-USB3-DP PHYs */
> +#define QMP_USB43DP_USB3_PHY           0
> +#define QMP_USB43DP_DP_PHY             1
> +
> +#endif /* _DT_BINDINGS_PHY_QMP */
> diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h
> new file mode 100644
> index 000000000000..5c5e4d800cac
> --- /dev/null
> +++ b/include/dt-bindings/phy/phy-qcom-qusb2.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_
> +#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_
> +
> +/* PHY HSTX TRIM bit values (24mA to 15mA) */
> +#define QUSB2_V2_HSTX_TRIM_24_0_MA             0x0
> +#define QUSB2_V2_HSTX_TRIM_23_4_MA             0x1
> +#define QUSB2_V2_HSTX_TRIM_22_8_MA             0x2
> +#define QUSB2_V2_HSTX_TRIM_22_2_MA             0x3
> +#define QUSB2_V2_HSTX_TRIM_21_6_MA             0x4
> +#define QUSB2_V2_HSTX_TRIM_21_0_MA             0x5
> +#define QUSB2_V2_HSTX_TRIM_20_4_MA             0x6
> +#define QUSB2_V2_HSTX_TRIM_19_8_MA             0x7
> +#define QUSB2_V2_HSTX_TRIM_19_2_MA             0x8
> +#define QUSB2_V2_HSTX_TRIM_18_6_MA             0x9
> +#define QUSB2_V2_HSTX_TRIM_18_0_MA             0xa
> +#define QUSB2_V2_HSTX_TRIM_17_4_MA             0xb
> +#define QUSB2_V2_HSTX_TRIM_16_8_MA             0xc
> +#define QUSB2_V2_HSTX_TRIM_16_2_MA             0xd
> +#define QUSB2_V2_HSTX_TRIM_15_6_MA             0xe
> +#define QUSB2_V2_HSTX_TRIM_15_0_MA             0xf
> +
> +/* PHY PREEMPHASIS bit values */
> +#define QUSB2_V2_PREEMPHASIS_NONE              0
> +#define QUSB2_V2_PREEMPHASIS_5_PERCENT         1
> +#define QUSB2_V2_PREEMPHASIS_10_PERCENT                2
> +#define QUSB2_V2_PREEMPHASIS_15_PERCENT                3
> +
> +/* PHY PREEMPHASIS-WIDTH bit values */
> +#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT    0
> +#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT    1
> +
> +#endif
> diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
> new file mode 100644
> index 000000000000..e5df5ce45a0f
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for the Qualcomm PMIC GPIO binding.
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
> +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
> +
> +#define PMIC_GPIO_PULL_UP_30           0
> +#define PMIC_GPIO_PULL_UP_1P5          1
> +#define PMIC_GPIO_PULL_UP_31P5         2
> +#define PMIC_GPIO_PULL_UP_1P5_30       3
> +
> +#define PMIC_GPIO_STRENGTH_NO          0
> +#define PMIC_GPIO_STRENGTH_HIGH                1
> +#define PMIC_GPIO_STRENGTH_MED         2
> +#define PMIC_GPIO_STRENGTH_LOW         3
> +
> +/*
> + * Note: PM8018 GPIO3 and GPIO4 are supporting
> + * only S3 and L2 options (1.8V)
> + */
> +#define PM8018_GPIO_L6                 0
> +#define PM8018_GPIO_L5                 1
> +#define PM8018_GPIO_S3                 2
> +#define PM8018_GPIO_L14                        3
> +#define PM8018_GPIO_L2                 4
> +#define PM8018_GPIO_L4                 5
> +#define PM8018_GPIO_VDD                        6
> +
> +/*
> + * Note: PM8038 GPIO7 and GPIO8 are supporting
> + * only L11 and L4 options (1.8V)
> + */
> +#define PM8038_GPIO_VPH                        0
> +#define PM8038_GPIO_BB                 1
> +#define PM8038_GPIO_L11                        2
> +#define PM8038_GPIO_L15                        3
> +#define PM8038_GPIO_L4                 4
> +#define PM8038_GPIO_L3                 5
> +#define PM8038_GPIO_L17                        6
> +
> +#define PM8058_GPIO_VPH                        0
> +#define PM8058_GPIO_BB                 1
> +#define PM8058_GPIO_S3                 2
> +#define PM8058_GPIO_L3                 3
> +#define PM8058_GPIO_L7                 4
> +#define PM8058_GPIO_L6                 5
> +#define PM8058_GPIO_L5                 6
> +#define PM8058_GPIO_L2                 7
> +
> +/*
> + * Note: PM8916 GPIO1 and GPIO2 are supporting
> + * only L2(1.15V) and L5(1.8V) options
> + */
> +#define PM8916_GPIO_VPH                        0
> +#define PM8916_GPIO_L2                 2
> +#define PM8916_GPIO_L5                 3
> +
> +#define PM8917_GPIO_VPH                        0
> +#define PM8917_GPIO_S4                 2
> +#define PM8917_GPIO_L15                        3
> +#define PM8917_GPIO_L4                 4
> +#define PM8917_GPIO_L3                 5
> +#define PM8917_GPIO_L17                        6
> +
> +#define PM8921_GPIO_VPH                        0
> +#define PM8921_GPIO_BB                 1
> +#define PM8921_GPIO_S4                 2
> +#define PM8921_GPIO_L15                        3
> +#define PM8921_GPIO_L4                 4
> +#define PM8921_GPIO_L3                 5
> +#define PM8921_GPIO_L17                        6
> +
> +/*
> + * Note: PM8941 gpios from 15 to 18 are supporting
> + * only S3 and L6 options (1.8V)
> + */
> +#define PM8941_GPIO_VPH                        0
> +#define PM8941_GPIO_L1                 1
> +#define PM8941_GPIO_S3                 2
> +#define PM8941_GPIO_L6                 3
> +
> +/*
> + * Note: PMA8084 gpios from 15 to 18 are supporting
> + * only S4 and L6 options (1.8V)
> + */
> +#define PMA8084_GPIO_VPH               0
> +#define PMA8084_GPIO_L1                        1
> +#define PMA8084_GPIO_S4                        2
> +#define PMA8084_GPIO_L6                        3
> +
> +#define PM8994_GPIO_VPH                        0
> +#define PM8994_GPIO_S4                 2
> +#define PM8994_GPIO_L12                        3
> +
> +/* To be used with "function" */
> +#define PMIC_GPIO_FUNC_NORMAL          "normal"
> +#define PMIC_GPIO_FUNC_PAIRED          "paired"
> +#define PMIC_GPIO_FUNC_FUNC1           "func1"
> +#define PMIC_GPIO_FUNC_FUNC2           "func2"
> +#define PMIC_GPIO_FUNC_FUNC3           "func3"
> +#define PMIC_GPIO_FUNC_FUNC4           "func4"
> +#define PMIC_GPIO_FUNC_DTEST1          "dtest1"
> +#define PMIC_GPIO_FUNC_DTEST2          "dtest2"
> +#define PMIC_GPIO_FUNC_DTEST3          "dtest3"
> +#define PMIC_GPIO_FUNC_DTEST4          "dtest4"
> +
> +#define PM8038_GPIO1_2_LPG_DRV         PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO3_5V_BOOST_EN       PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO4_SSBI_ALT_CLK      PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO5_6_EXT_REG_EN      PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO10_11_EXT_REG_EN    PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO6_7_CLK             PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO9_BAT_ALRM_OUT      PMIC_GPIO_FUNC_FUNC1
> +#define PM8038_GPIO6_12_KYPD_DRV       PMIC_GPIO_FUNC_FUNC2
> +
> +#define PM8058_GPIO7_8_MP3_CLK         PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO7_8_BCLK_19P2MHZ    PMIC_GPIO_FUNC_FUNC2
> +#define PM8058_GPIO9_26_KYPD_DRV       PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO21_23_UART_TX       PMIC_GPIO_FUNC_FUNC2
> +#define PM8058_GPIO24_26_LPG_DRV       PMIC_GPIO_FUNC_FUNC2
> +#define PM8058_GPIO33_BCLK_19P2MHZ     PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO34_35_MP3_CLK       PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO36_BCLK_19P2MHZ     PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO37_UPL_OUT          PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO37_UART_M_RX                PMIC_GPIO_FUNC_FUNC2
> +#define PM8058_GPIO38_XO_SLEEP_CLK     PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO38_39_CLK_32KHZ     PMIC_GPIO_FUNC_FUNC2
> +#define PM8058_GPIO39_MP3_CLK          PMIC_GPIO_FUNC_FUNC1
> +#define PM8058_GPIO40_EXT_BB_EN                PMIC_GPIO_FUNC_FUNC1
> +
> +#define PM8916_GPIO1_BAT_ALRM_OUT      PMIC_GPIO_FUNC_FUNC1
> +#define PM8916_GPIO1_KEYP_DRV          PMIC_GPIO_FUNC_FUNC2
> +#define PM8916_GPIO2_DIV_CLK           PMIC_GPIO_FUNC_FUNC1
> +#define PM8916_GPIO2_SLEEP_CLK         PMIC_GPIO_FUNC_FUNC2
> +#define PM8916_GPIO3_KEYP_DRV          PMIC_GPIO_FUNC_FUNC1
> +#define PM8916_GPIO4_KEYP_DRV          PMIC_GPIO_FUNC_FUNC2
> +
> +#define PM8917_GPIO9_18_KEYP_DRV       PMIC_GPIO_FUNC_FUNC1
> +#define PM8917_GPIO20_BAT_ALRM_OUT     PMIC_GPIO_FUNC_FUNC1
> +#define PM8917_GPIO21_23_UART_TX       PMIC_GPIO_FUNC_FUNC2
> +#define PM8917_GPIO25_26_EXT_REG_EN    PMIC_GPIO_FUNC_FUNC1
> +#define PM8917_GPIO37_38_XO_SLEEP_CLK  PMIC_GPIO_FUNC_FUNC1
> +#define PM8917_GPIO37_38_MP3_CLK       PMIC_GPIO_FUNC_FUNC2
> +
> +#define PM8941_GPIO9_14_KYPD_DRV       PMIC_GPIO_FUNC_FUNC1
> +#define PM8941_GPIO15_18_DIV_CLK       PMIC_GPIO_FUNC_FUNC1
> +#define PM8941_GPIO15_18_SLEEP_CLK     PMIC_GPIO_FUNC_FUNC2
> +#define PM8941_GPIO23_26_KYPD_DRV      PMIC_GPIO_FUNC_FUNC1
> +#define PM8941_GPIO23_26_LPG_DRV_HI    PMIC_GPIO_FUNC_FUNC2
> +#define PM8941_GPIO31_BAT_ALRM_OUT     PMIC_GPIO_FUNC_FUNC1
> +#define PM8941_GPIO33_36_LPG_DRV_3D    PMIC_GPIO_FUNC_FUNC1
> +#define PM8941_GPIO33_36_LPG_DRV_HI    PMIC_GPIO_FUNC_FUNC2
> +
> +#define PMA8084_GPIO4_5_LPG_DRV                PMIC_GPIO_FUNC_FUNC1
> +#define PMA8084_GPIO7_10_LPG_DRV       PMIC_GPIO_FUNC_FUNC1
> +#define PMA8084_GPIO5_14_KEYP_DRV      PMIC_GPIO_FUNC_FUNC2
> +#define PMA8084_GPIO19_21_KEYP_DRV     PMIC_GPIO_FUNC_FUNC2
> +#define PMA8084_GPIO15_18_DIV_CLK      PMIC_GPIO_FUNC_FUNC1
> +#define PMA8084_GPIO15_18_SLEEP_CLK    PMIC_GPIO_FUNC_FUNC2
> +#define PMA8084_GPIO22_BAT_ALRM_OUT    PMIC_GPIO_FUNC_FUNC1
> +
> +#endif
> diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
> new file mode 100644
> index 000000000000..7f4e2983a4c5
> --- /dev/null
> +++ b/include/dt-bindings/power/qcom-rpmpd.h
> @@ -0,0 +1,412 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
> +
> +#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
> +#define _DT_BINDINGS_POWER_QCOM_RPMPD_H
> +
> +/* SA8775P Power Domain Indexes */
> +#define SA8775P_CX     0
> +#define SA8775P_CX_AO  1
> +#define SA8775P_DDR    2
> +#define SA8775P_EBI    3
> +#define SA8775P_GFX    4
> +#define SA8775P_LCX    5
> +#define SA8775P_LMX    6
> +#define SA8775P_MMCX   7
> +#define SA8775P_MMCX_AO        8
> +#define SA8775P_MSS    9
> +#define SA8775P_MX     10
> +#define SA8775P_MX_AO  11
> +#define SA8775P_MXC    12
> +#define SA8775P_MXC_AO 13
> +#define SA8775P_NSP0   14
> +#define SA8775P_NSP1   15
> +#define SA8775P_XO     16
> +
> +/* SDM670 Power Domain Indexes */
> +#define SDM670_MX      0
> +#define SDM670_MX_AO   1
> +#define SDM670_CX      2
> +#define SDM670_CX_AO   3
> +#define SDM670_LMX     4
> +#define SDM670_LCX     5
> +#define SDM670_GFX     6
> +#define SDM670_MSS     7
> +
> +/* SDM845 Power Domain Indexes */
> +#define SDM845_EBI     0
> +#define SDM845_MX      1
> +#define SDM845_MX_AO   2
> +#define SDM845_CX      3
> +#define SDM845_CX_AO   4
> +#define SDM845_LMX     5
> +#define SDM845_LCX     6
> +#define SDM845_GFX     7
> +#define SDM845_MSS     8
> +
> +/* SDX55 Power Domain Indexes */
> +#define SDX55_MSS      0
> +#define SDX55_MX       1
> +#define SDX55_CX       2
> +
> +/* SDX65 Power Domain Indexes */
> +#define SDX65_MSS      0
> +#define SDX65_MX       1
> +#define SDX65_MX_AO    2
> +#define SDX65_CX       3
> +#define SDX65_CX_AO    4
> +#define SDX65_MXC      5
> +
> +/* SM6350 Power Domain Indexes */
> +#define SM6350_CX      0
> +#define SM6350_GFX     1
> +#define SM6350_LCX     2
> +#define SM6350_LMX     3
> +#define SM6350_MSS     4
> +#define SM6350_MX      5
> +
> +/* SM6350 Power Domain Indexes */
> +#define SM6375_VDDCX           0
> +#define SM6375_VDDCX_AO        1
> +#define SM6375_VDDCX_VFL       2
> +#define SM6375_VDDMX           3
> +#define SM6375_VDDMX_AO        4
> +#define SM6375_VDDMX_VFL       5
> +#define SM6375_VDDGX           6
> +#define SM6375_VDDGX_AO        7
> +#define SM6375_VDD_LPI_CX      8
> +#define SM6375_VDD_LPI_MX      9
> +
> +/* SM8150 Power Domain Indexes */
> +#define SM8150_MSS     0
> +#define SM8150_EBI     1
> +#define SM8150_LMX     2
> +#define SM8150_LCX     3
> +#define SM8150_GFX     4
> +#define SM8150_MX      5
> +#define SM8150_MX_AO   6
> +#define SM8150_CX      7
> +#define SM8150_CX_AO   8
> +#define SM8150_MMCX    9
> +#define SM8150_MMCX_AO 10
> +
> +/* SA8155P is a special case, kept for backwards compatibility */
> +#define SA8155P_CX     SM8150_CX
> +#define SA8155P_CX_AO  SM8150_CX_AO
> +#define SA8155P_EBI    SM8150_EBI
> +#define SA8155P_GFX    SM8150_GFX
> +#define SA8155P_MSS    SM8150_MSS
> +#define SA8155P_MX     SM8150_MX
> +#define SA8155P_MX_AO  SM8150_MX_AO
> +
> +/* SM8250 Power Domain Indexes */
> +#define SM8250_CX      0
> +#define SM8250_CX_AO   1
> +#define SM8250_EBI     2
> +#define SM8250_GFX     3
> +#define SM8250_LCX     4
> +#define SM8250_LMX     5
> +#define SM8250_MMCX    6
> +#define SM8250_MMCX_AO 7
> +#define SM8250_MX      8
> +#define SM8250_MX_AO   9
> +
> +/* SM8350 Power Domain Indexes */
> +#define SM8350_CX      0
> +#define SM8350_CX_AO   1
> +#define SM8350_EBI     2
> +#define SM8350_GFX     3
> +#define SM8350_LCX     4
> +#define SM8350_LMX     5
> +#define SM8350_MMCX    6
> +#define SM8350_MMCX_AO 7
> +#define SM8350_MX      8
> +#define SM8350_MX_AO   9
> +#define SM8350_MXC     10
> +#define SM8350_MXC_AO  11
> +#define SM8350_MSS     12
> +
> +/* SM8450 Power Domain Indexes */
> +#define SM8450_CX      0
> +#define SM8450_CX_AO   1
> +#define SM8450_EBI     2
> +#define SM8450_GFX     3
> +#define SM8450_LCX     4
> +#define SM8450_LMX     5
> +#define SM8450_MMCX    6
> +#define SM8450_MMCX_AO 7
> +#define SM8450_MX      8
> +#define SM8450_MX_AO   9
> +#define SM8450_MXC     10
> +#define SM8450_MXC_AO  11
> +#define SM8450_MSS     12
> +
> +/* SM8550 Power Domain Indexes */
> +#define SM8550_CX      0
> +#define SM8550_CX_AO   1
> +#define SM8550_EBI     2
> +#define SM8550_GFX     3
> +#define SM8550_LCX     4
> +#define SM8550_LMX     5
> +#define SM8550_MMCX    6
> +#define SM8550_MMCX_AO 7
> +#define SM8550_MX      8
> +#define SM8550_MX_AO   9
> +#define SM8550_MXC     10
> +#define SM8550_MXC_AO  11
> +#define SM8550_MSS     12
> +#define SM8550_NSP     13
> +
> +/* QDU1000/QRU1000 Power Domain Indexes */
> +#define QDU1000_EBI    0
> +#define QDU1000_MSS    1
> +#define QDU1000_CX     2
> +#define QDU1000_MX     3
> +
> +/* SC7180 Power Domain Indexes */
> +#define SC7180_CX      0
> +#define SC7180_CX_AO   1
> +#define SC7180_GFX     2
> +#define SC7180_MX      3
> +#define SC7180_MX_AO   4
> +#define SC7180_LMX     5
> +#define SC7180_LCX     6
> +#define SC7180_MSS     7
> +
> +/* SC7280 Power Domain Indexes */
> +#define SC7280_CX      0
> +#define SC7280_CX_AO   1
> +#define SC7280_EBI     2
> +#define SC7280_GFX     3
> +#define SC7280_MX      4
> +#define SC7280_MX_AO   5
> +#define SC7280_LMX     6
> +#define SC7280_LCX     7
> +#define SC7280_MSS     8
> +
> +/* SC8180X Power Domain Indexes */
> +#define SC8180X_CX     0
> +#define SC8180X_CX_AO  1
> +#define SC8180X_EBI    2
> +#define SC8180X_GFX    3
> +#define SC8180X_LCX    4
> +#define SC8180X_LMX    5
> +#define SC8180X_MMCX   6
> +#define SC8180X_MMCX_AO        7
> +#define SC8180X_MSS    8
> +#define SC8180X_MX     9
> +#define SC8180X_MX_AO  10
> +
> +/* SC8280XP Power Domain Indexes */
> +#define SC8280XP_CX            0
> +#define SC8280XP_CX_AO         1
> +#define SC8280XP_DDR           2
> +#define SC8280XP_EBI           3
> +#define SC8280XP_GFX           4
> +#define SC8280XP_LCX           5
> +#define SC8280XP_LMX           6
> +#define SC8280XP_MMCX          7
> +#define SC8280XP_MMCX_AO       8
> +#define SC8280XP_MSS           9
> +#define SC8280XP_MX            10
> +#define SC8280XP_MXC           12
> +#define SC8280XP_MX_AO         11
> +#define SC8280XP_NSP           13
> +#define SC8280XP_QPHY          14
> +#define SC8280XP_XO            15
> +
> +/* SDM845 Power Domain performance levels */
> +#define RPMH_REGULATOR_LEVEL_RETENTION         16
> +#define RPMH_REGULATOR_LEVEL_MIN_SVS           48
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2                52
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1                56
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0                60
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS           64
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1                72
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1                80
> +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2                96
> +#define RPMH_REGULATOR_LEVEL_SVS               128
> +#define RPMH_REGULATOR_LEVEL_SVS_L0            144
> +#define RPMH_REGULATOR_LEVEL_SVS_L1            192
> +#define RPMH_REGULATOR_LEVEL_SVS_L2            224
> +#define RPMH_REGULATOR_LEVEL_NOM               256
> +#define RPMH_REGULATOR_LEVEL_NOM_L0            288
> +#define RPMH_REGULATOR_LEVEL_NOM_L1            320
> +#define RPMH_REGULATOR_LEVEL_NOM_L2            336
> +#define RPMH_REGULATOR_LEVEL_TURBO             384
> +#define RPMH_REGULATOR_LEVEL_TURBO_L0          400
> +#define RPMH_REGULATOR_LEVEL_TURBO_L1          416
> +#define RPMH_REGULATOR_LEVEL_TURBO_L2          432
> +#define RPMH_REGULATOR_LEVEL_TURBO_L3          448
> +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO       464
> +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR        480
> +
> +/* MDM9607 Power Domains */
> +#define MDM9607_VDDCX          0
> +#define MDM9607_VDDCX_AO       1
> +#define MDM9607_VDDCX_VFL      2
> +#define MDM9607_VDDMX          3
> +#define MDM9607_VDDMX_AO       4
> +#define MDM9607_VDDMX_VFL      5
> +
> +/* MSM8226 Power Domain Indexes */
> +#define MSM8226_VDDCX          0
> +#define MSM8226_VDDCX_AO       1
> +#define MSM8226_VDDCX_VFC      2
> +
> +/* MSM8939 Power Domains */
> +#define MSM8939_VDDMDCX                0
> +#define MSM8939_VDDMDCX_AO     1
> +#define MSM8939_VDDMDCX_VFC    2
> +#define MSM8939_VDDCX          3
> +#define MSM8939_VDDCX_AO       4
> +#define MSM8939_VDDCX_VFC      5
> +#define MSM8939_VDDMX          6
> +#define MSM8939_VDDMX_AO       7
> +
> +/* MSM8916 Power Domain Indexes */
> +#define MSM8916_VDDCX          0
> +#define MSM8916_VDDCX_AO       1
> +#define MSM8916_VDDCX_VFC      2
> +#define MSM8916_VDDMX          3
> +#define MSM8916_VDDMX_AO       4
> +
> +/* MSM8909 Power Domain Indexes */
> +#define MSM8909_VDDCX          MSM8916_VDDCX
> +#define MSM8909_VDDCX_AO       MSM8916_VDDCX_AO
> +#define MSM8909_VDDCX_VFC      MSM8916_VDDCX_VFC
> +#define MSM8909_VDDMX          MSM8916_VDDMX
> +#define MSM8909_VDDMX_AO       MSM8916_VDDMX_AO
> +
> +/* MSM8917 Power Domain Indexes */
> +#define MSM8917_VDDCX          0
> +#define MSM8917_VDDCX_AO       1
> +#define MSM8917_VDDCX_VFL      2
> +#define MSM8917_VDDMX          3
> +#define MSM8917_VDDMX_AO       4
> +
> +/* MSM8937 Power Domain Indexes */
> +#define MSM8937_VDDCX          MSM8917_VDDCX
> +#define MSM8937_VDDCX_AO       MSM8917_VDDCX_AO
> +#define MSM8937_VDDCX_VFL      MSM8917_VDDCX_VFL
> +#define MSM8937_VDDMX          MSM8917_VDDMX
> +#define MSM8937_VDDMX_AO       MSM8917_VDDMX_AO
> +
> +/* QM215 Power Domain Indexes */
> +#define QM215_VDDCX            MSM8917_VDDCX
> +#define QM215_VDDCX_AO         MSM8917_VDDCX_AO
> +#define QM215_VDDCX_VFL                MSM8917_VDDCX_VFL
> +#define QM215_VDDMX            MSM8917_VDDMX
> +#define QM215_VDDMX_AO         MSM8917_VDDMX_AO
> +
> +/* MSM8953 Power Domain Indexes */
> +#define MSM8953_VDDMD          0
> +#define MSM8953_VDDMD_AO       1
> +#define MSM8953_VDDCX          2
> +#define MSM8953_VDDCX_AO       3
> +#define MSM8953_VDDCX_VFL      4
> +#define MSM8953_VDDMX          5
> +#define MSM8953_VDDMX_AO       6
> +
> +/* MSM8976 Power Domain Indexes */
> +#define MSM8976_VDDCX          0
> +#define MSM8976_VDDCX_AO       1
> +#define MSM8976_VDDCX_VFL      2
> +#define MSM8976_VDDMX          3
> +#define MSM8976_VDDMX_AO       4
> +#define MSM8976_VDDMX_VFL      5
> +
> +/* MSM8994 Power Domain Indexes */
> +#define MSM8994_VDDCX          0
> +#define MSM8994_VDDCX_AO       1
> +#define MSM8994_VDDCX_VFC      2
> +#define MSM8994_VDDMX          3
> +#define MSM8994_VDDMX_AO       4
> +#define MSM8994_VDDGFX         5
> +#define MSM8994_VDDGFX_VFC     6
> +
> +/* MSM8996 Power Domain Indexes */
> +#define MSM8996_VDDCX          0
> +#define MSM8996_VDDCX_AO       1
> +#define MSM8996_VDDCX_VFC      2
> +#define MSM8996_VDDMX          3
> +#define MSM8996_VDDMX_AO       4
> +#define MSM8996_VDDSSCX                5
> +#define MSM8996_VDDSSCX_VFC    6
> +
> +/* MSM8998 Power Domain Indexes */
> +#define MSM8998_VDDCX          0
> +#define MSM8998_VDDCX_AO       1
> +#define MSM8998_VDDCX_VFL      2
> +#define MSM8998_VDDMX          3
> +#define MSM8998_VDDMX_AO       4
> +#define MSM8998_VDDMX_VFL      5
> +#define MSM8998_SSCCX          6
> +#define MSM8998_SSCCX_VFL      7
> +#define MSM8998_SSCMX          8
> +#define MSM8998_SSCMX_VFL      9
> +
> +/* QCS404 Power Domains */
> +#define QCS404_VDDMX           0
> +#define QCS404_VDDMX_AO                1
> +#define QCS404_VDDMX_VFL       2
> +#define QCS404_LPICX           3
> +#define QCS404_LPICX_VFL       4
> +#define QCS404_LPIMX           5
> +#define QCS404_LPIMX_VFL       6
> +
> +/* SDM660 Power Domains */
> +#define SDM660_VDDCX           0
> +#define SDM660_VDDCX_AO                1
> +#define SDM660_VDDCX_VFL       2
> +#define SDM660_VDDMX           3
> +#define SDM660_VDDMX_AO                4
> +#define SDM660_VDDMX_VFL       5
> +#define SDM660_SSCCX           6
> +#define SDM660_SSCCX_VFL       7
> +#define SDM660_SSCMX           8
> +#define SDM660_SSCMX_VFL       9
> +
> +/* SM6115 Power Domains */
> +#define SM6115_VDDCX           0
> +#define SM6115_VDDCX_AO                1
> +#define SM6115_VDDCX_VFL       2
> +#define SM6115_VDDMX           3
> +#define SM6115_VDDMX_AO                4
> +#define SM6115_VDDMX_VFL       5
> +#define SM6115_VDD_LPI_CX      6
> +#define SM6115_VDD_LPI_MX      7
> +
> +/* SM6125 Power Domains */
> +#define SM6125_VDDCX           0
> +#define SM6125_VDDCX_AO                1
> +#define SM6125_VDDCX_VFL       2
> +#define SM6125_VDDMX           3
> +#define SM6125_VDDMX_AO                4
> +#define SM6125_VDDMX_VFL       5
> +
> +/* QCM2290 Power Domains */
> +#define QCM2290_VDDCX          0
> +#define QCM2290_VDDCX_AO       1
> +#define QCM2290_VDDCX_VFL      2
> +#define QCM2290_VDDMX          3
> +#define QCM2290_VDDMX_AO       4
> +#define QCM2290_VDDMX_VFL      5
> +#define QCM2290_VDD_LPI_CX     6
> +#define QCM2290_VDD_LPI_MX     7
> +
> +/* RPM SMD Power Domain performance levels */
> +#define RPM_SMD_LEVEL_RETENTION       16
> +#define RPM_SMD_LEVEL_RETENTION_PLUS  32
> +#define RPM_SMD_LEVEL_MIN_SVS         48
> +#define RPM_SMD_LEVEL_LOW_SVS         64
> +#define RPM_SMD_LEVEL_SVS             128
> +#define RPM_SMD_LEVEL_SVS_PLUS        192
> +#define RPM_SMD_LEVEL_NOM             256
> +#define RPM_SMD_LEVEL_NOM_PLUS        320
> +#define RPM_SMD_LEVEL_TURBO           384
> +#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
> +#define RPM_SMD_LEVEL_TURBO_HIGH      448
> +#define RPM_SMD_LEVEL_BINNING         512
> +
> +#endif
> diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
> new file mode 100644
> index 000000000000..86713dcf9e02
> --- /dev/null
> +++ b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
> +
> +#ifndef __QCOM_RPMH_REGULATOR_H
> +#define __QCOM_RPMH_REGULATOR_H
> +
> +/*
> + * These mode constants may be used to specify modes for various RPMh regulator
> + * device tree properties (e.g. regulator-initial-mode).  Each type of regulator
> + * supports a subset of the possible modes.
> + *
> + * %RPMH_REGULATOR_MODE_RET:   Retention mode in which only an extremely small
> + *                             load current is allowed.  This mode is supported
> + *                             by LDO and SMPS type regulators.
> + * %RPMH_REGULATOR_MODE_LPM:   Low power mode in which a small load current is
> + *                             allowed.  This mode corresponds to PFM for SMPS
> + *                             and BOB type regulators.  This mode is supported
> + *                             by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
> + *                             regulators.
> + * %RPMH_REGULATOR_MODE_AUTO:  Auto mode in which the regulator hardware
> + *                             automatically switches between LPM and HPM based
> + *                             upon the real-time load current.  This mode is
> + *                             supported by HFSMPS, BOB, and PMIC4 FTSMPS type
> + *                             regulators.
> + * %RPMH_REGULATOR_MODE_HPM:   High power mode in which the full rated current
> + *                             of the regulator is allowed.  This mode
> + *                             corresponds to PWM for SMPS and BOB type
> + *                             regulators.  This mode is supported by all types
> + *                             of regulators.
> + */
> +#define RPMH_REGULATOR_MODE_RET                0
> +#define RPMH_REGULATOR_MODE_LPM                1
> +#define RPMH_REGULATOR_MODE_AUTO       2
> +#define RPMH_REGULATOR_MODE_HPM                3
> +
> +#endif
> diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
> new file mode 100644
> index 000000000000..476c5fc873b6
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +
> +#define AOSS_CC_MSS_RESTART    0
> +#define AOSS_CC_CAMSS_RESTART  1
> +#define AOSS_CC_VENUS_RESTART  2
> +#define AOSS_CC_GPU_RESTART    3
> +#define AOSS_CC_DISPSS_RESTART 4
> +#define AOSS_CC_WCSS_RESTART   5
> +#define AOSS_CC_LPASS_RESTART  6
> +
> +#endif
> diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> new file mode 100644
> index 000000000000..03a0c0eb8147
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
> +#define _DT_BINDINGS_RESET_PDC_SDM_845_H
> +
> +#define PDC_APPS_SYNC_RESET    0
> +#define PDC_SP_SYNC_RESET      1
> +#define PDC_AUDIO_SYNC_RESET   2
> +#define PDC_SENSORS_SYNC_RESET 3
> +#define PDC_AOP_SYNC_RESET     4
> +#define PDC_DEBUG_SYNC_RESET   5
> +#define PDC_GPU_SYNC_RESET     6
> +#define PDC_DISPLAY_SYNC_RESET 7
> +#define PDC_COMPUTE_SYNC_RESET 8
> +#define PDC_MODEM_SYNC_RESET   9
> +#define PDC_WLAN_RF_SYNC_RESET 10
> +#define PDC_WPSS_SYNC_RESET    11
> +
> +#endif
> diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h
> new file mode 100644
> index 000000000000..006362400c0f
> --- /dev/null
> +++ b/include/dt-bindings/soc/qcom,apr.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_BINDINGS_QCOM_APR_H
> +#define __DT_BINDINGS_QCOM_APR_H
> +
> +/* Domain IDs */
> +#define APR_DOMAIN_SIM         0x1
> +#define APR_DOMAIN_PC          0x2
> +#define APR_DOMAIN_MODEM       0x3
> +#define APR_DOMAIN_ADSP                0x4
> +#define APR_DOMAIN_APPS                0x5
> +#define APR_DOMAIN_MAX         0x6
> +
> +/* ADSP service IDs */
> +#define APR_SVC_ADSP_CORE      0x3
> +#define APR_SVC_AFE            0x4
> +#define APR_SVC_VSM            0x5
> +#define APR_SVC_VPM            0x6
> +#define APR_SVC_ASM            0x7
> +#define APR_SVC_ADM            0x8
> +#define APR_SVC_ADSP_MVM       0x09
> +#define APR_SVC_ADSP_CVS       0x0A
> +#define APR_SVC_ADSP_CVP       0x0B
> +#define APR_SVC_USM            0x0C
> +#define APR_SVC_LSM            0x0D
> +#define APR_SVC_VIDC           0x16
> +#define APR_SVC_MAX            0x17
> +
> +#endif /* __DT_BINDINGS_QCOM_APR_H */
> diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h
> new file mode 100644
> index 000000000000..868f998ea998
> --- /dev/null
> +++ b/include/dt-bindings/soc/qcom,rpmh-rsc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef __DT_QCOM_RPMH_RSC_H__
> +#define __DT_QCOM_RPMH_RSC_H__
> +
> +#define SLEEP_TCS      0
> +#define WAKE_TCS       1
> +#define ACTIVE_TCS     2
> +#define CONTROL_TCS    3
> +
> +#endif /* __DT_QCOM_RPMH_RSC_H__ */
> diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
> new file mode 100644
> index 000000000000..9d5d89cfabcf
> --- /dev/null
> +++ b/include/dt-bindings/sound/qcom,q6afe.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_BINDINGS_Q6_AFE_H__
> +#define __DT_BINDINGS_Q6_AFE_H__
> +
> +/* This file exists due to backward compatibility reasons, Please do not DELETE! */
> +
> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
> +
> +#endif /* __DT_BINDINGS_Q6_AFE_H__ */
> diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h
> new file mode 100644
> index 000000000000..f59d74f14395
> --- /dev/null
> +++ b/include/dt-bindings/sound/qcom,q6asm.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_BINDINGS_Q6_ASM_H__
> +#define __DT_BINDINGS_Q6_ASM_H__
> +
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA1    0
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA2    1
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA3    2
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA4    3
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA5    4
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA6    5
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA7    6
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA8    7
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA9    8
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA10   9
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA11   10
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA12   11
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA13   12
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA14   13
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA15   14
> +#define        MSM_FRONTEND_DAI_MULTIMEDIA16   15
> +
> +#define Q6ASM_DAI_TX_RX        0
> +#define Q6ASM_DAI_TX   1
> +#define Q6ASM_DAI_RX   2
> +
> +#endif /* __DT_BINDINGS_Q6_ASM_H__ */
> diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
> new file mode 100644
> index 000000000000..39f203256c4f
> --- /dev/null
> +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
> @@ -0,0 +1,234 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
> +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
> +
> +/* LPASS Audio virtual ports IDs */
> +#define HDMI_RX                1
> +#define SLIMBUS_0_RX    2
> +#define SLIMBUS_0_TX    3
> +#define SLIMBUS_1_RX    4
> +#define SLIMBUS_1_TX    5
> +#define SLIMBUS_2_RX    6
> +#define SLIMBUS_2_TX    7
> +#define SLIMBUS_3_RX    8
> +#define SLIMBUS_3_TX    9
> +#define SLIMBUS_4_RX    10
> +#define SLIMBUS_4_TX    11
> +#define SLIMBUS_5_RX    12
> +#define SLIMBUS_5_TX    13
> +#define SLIMBUS_6_RX    14
> +#define SLIMBUS_6_TX    15
> +#define PRIMARY_MI2S_RX                16
> +#define PRIMARY_MI2S_TX                17
> +#define SECONDARY_MI2S_RX      18
> +#define SECONDARY_MI2S_TX      19
> +#define TERTIARY_MI2S_RX       20
> +#define TERTIARY_MI2S_TX       21
> +#define QUATERNARY_MI2S_RX     22
> +#define QUATERNARY_MI2S_TX     23
> +#define PRIMARY_TDM_RX_0       24
> +#define PRIMARY_TDM_TX_0       25
> +#define PRIMARY_TDM_RX_1       26
> +#define PRIMARY_TDM_TX_1       27
> +#define PRIMARY_TDM_RX_2       28
> +#define PRIMARY_TDM_TX_2       29
> +#define PRIMARY_TDM_RX_3       30
> +#define PRIMARY_TDM_TX_3       31
> +#define PRIMARY_TDM_RX_4       32
> +#define PRIMARY_TDM_TX_4       33
> +#define PRIMARY_TDM_RX_5       34
> +#define PRIMARY_TDM_TX_5       35
> +#define PRIMARY_TDM_RX_6       36
> +#define PRIMARY_TDM_TX_6       37
> +#define PRIMARY_TDM_RX_7       38
> +#define PRIMARY_TDM_TX_7       39
> +#define SECONDARY_TDM_RX_0     40
> +#define SECONDARY_TDM_TX_0     41
> +#define SECONDARY_TDM_RX_1     42
> +#define SECONDARY_TDM_TX_1     43
> +#define SECONDARY_TDM_RX_2     44
> +#define SECONDARY_TDM_TX_2     45
> +#define SECONDARY_TDM_RX_3     46
> +#define SECONDARY_TDM_TX_3     47
> +#define SECONDARY_TDM_RX_4     48
> +#define SECONDARY_TDM_TX_4     49
> +#define SECONDARY_TDM_RX_5     50
> +#define SECONDARY_TDM_TX_5     51
> +#define SECONDARY_TDM_RX_6     52
> +#define SECONDARY_TDM_TX_6     53
> +#define SECONDARY_TDM_RX_7     54
> +#define SECONDARY_TDM_TX_7     55
> +#define TERTIARY_TDM_RX_0      56
> +#define TERTIARY_TDM_TX_0      57
> +#define TERTIARY_TDM_RX_1      58
> +#define TERTIARY_TDM_TX_1      59
> +#define TERTIARY_TDM_RX_2      60
> +#define TERTIARY_TDM_TX_2      61
> +#define TERTIARY_TDM_RX_3      62
> +#define TERTIARY_TDM_TX_3      63
> +#define TERTIARY_TDM_RX_4      64
> +#define TERTIARY_TDM_TX_4      65
> +#define TERTIARY_TDM_RX_5      66
> +#define TERTIARY_TDM_TX_5      67
> +#define TERTIARY_TDM_RX_6      68
> +#define TERTIARY_TDM_TX_6      69
> +#define TERTIARY_TDM_RX_7      70
> +#define TERTIARY_TDM_TX_7      71
> +#define QUATERNARY_TDM_RX_0    72
> +#define QUATERNARY_TDM_TX_0    73
> +#define QUATERNARY_TDM_RX_1    74
> +#define QUATERNARY_TDM_TX_1    75
> +#define QUATERNARY_TDM_RX_2    76
> +#define QUATERNARY_TDM_TX_2    77
> +#define QUATERNARY_TDM_RX_3    78
> +#define QUATERNARY_TDM_TX_3    79
> +#define QUATERNARY_TDM_RX_4    80
> +#define QUATERNARY_TDM_TX_4    81
> +#define QUATERNARY_TDM_RX_5    82
> +#define QUATERNARY_TDM_TX_5    83
> +#define QUATERNARY_TDM_RX_6    84
> +#define QUATERNARY_TDM_TX_6    85
> +#define QUATERNARY_TDM_RX_7    86
> +#define QUATERNARY_TDM_TX_7    87
> +#define QUINARY_TDM_RX_0       88
> +#define QUINARY_TDM_TX_0       89
> +#define QUINARY_TDM_RX_1       90
> +#define QUINARY_TDM_TX_1       91
> +#define QUINARY_TDM_RX_2       92
> +#define QUINARY_TDM_TX_2       93
> +#define QUINARY_TDM_RX_3       94
> +#define QUINARY_TDM_TX_3       95
> +#define QUINARY_TDM_RX_4       96
> +#define QUINARY_TDM_TX_4       97
> +#define QUINARY_TDM_RX_5       98
> +#define QUINARY_TDM_TX_5       99
> +#define QUINARY_TDM_RX_6       100
> +#define QUINARY_TDM_TX_6       101
> +#define QUINARY_TDM_RX_7       102
> +#define QUINARY_TDM_TX_7       103
> +#define DISPLAY_PORT_RX                104
> +#define WSA_CODEC_DMA_RX_0     105
> +#define WSA_CODEC_DMA_TX_0     106
> +#define WSA_CODEC_DMA_RX_1     107
> +#define WSA_CODEC_DMA_TX_1     108
> +#define WSA_CODEC_DMA_TX_2     109
> +#define VA_CODEC_DMA_TX_0      110
> +#define VA_CODEC_DMA_TX_1      111
> +#define VA_CODEC_DMA_TX_2      112
> +#define RX_CODEC_DMA_RX_0      113
> +#define TX_CODEC_DMA_TX_0      114
> +#define RX_CODEC_DMA_RX_1      115
> +#define TX_CODEC_DMA_TX_1      116
> +#define RX_CODEC_DMA_RX_2      117
> +#define TX_CODEC_DMA_TX_2      118
> +#define RX_CODEC_DMA_RX_3      119
> +#define TX_CODEC_DMA_TX_3      120
> +#define RX_CODEC_DMA_RX_4      121
> +#define TX_CODEC_DMA_TX_4      122
> +#define RX_CODEC_DMA_RX_5      123
> +#define TX_CODEC_DMA_TX_5      124
> +#define RX_CODEC_DMA_RX_6      125
> +#define RX_CODEC_DMA_RX_7      126
> +#define QUINARY_MI2S_RX                127
> +#define QUINARY_MI2S_TX                128
> +#define DISPLAY_PORT_RX_0      DISPLAY_PORT_RX
> +#define DISPLAY_PORT_RX_1      129
> +#define DISPLAY_PORT_RX_2      130
> +#define DISPLAY_PORT_RX_3      131
> +#define DISPLAY_PORT_RX_4      132
> +#define DISPLAY_PORT_RX_5      133
> +#define DISPLAY_PORT_RX_6      134
> +#define DISPLAY_PORT_RX_7      135
> +
> +#define LPASS_CLK_ID_PRI_MI2S_IBIT     1
> +#define LPASS_CLK_ID_PRI_MI2S_EBIT     2
> +#define LPASS_CLK_ID_SEC_MI2S_IBIT     3
> +#define LPASS_CLK_ID_SEC_MI2S_EBIT     4
> +#define LPASS_CLK_ID_TER_MI2S_IBIT     5
> +#define LPASS_CLK_ID_TER_MI2S_EBIT     6
> +#define LPASS_CLK_ID_QUAD_MI2S_IBIT    7
> +#define LPASS_CLK_ID_QUAD_MI2S_EBIT    8
> +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT  9
> +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT  10
> +#define LPASS_CLK_ID_SPEAKER_I2S_OSR   11
> +#define LPASS_CLK_ID_QUI_MI2S_IBIT     12
> +#define LPASS_CLK_ID_QUI_MI2S_EBIT     13
> +#define LPASS_CLK_ID_SEN_MI2S_IBIT     14
> +#define LPASS_CLK_ID_SEN_MI2S_EBIT     15
> +#define LPASS_CLK_ID_INT0_MI2S_IBIT    16
> +#define LPASS_CLK_ID_INT1_MI2S_IBIT    17
> +#define LPASS_CLK_ID_INT2_MI2S_IBIT    18
> +#define LPASS_CLK_ID_INT3_MI2S_IBIT    19
> +#define LPASS_CLK_ID_INT4_MI2S_IBIT    20
> +#define LPASS_CLK_ID_INT5_MI2S_IBIT    21
> +#define LPASS_CLK_ID_INT6_MI2S_IBIT    22
> +#define LPASS_CLK_ID_QUI_MI2S_OSR      23
> +#define LPASS_CLK_ID_PRI_PCM_IBIT      24
> +#define LPASS_CLK_ID_PRI_PCM_EBIT      25
> +#define LPASS_CLK_ID_SEC_PCM_IBIT      26
> +#define LPASS_CLK_ID_SEC_PCM_EBIT      27
> +#define LPASS_CLK_ID_TER_PCM_IBIT      28
> +#define LPASS_CLK_ID_TER_PCM_EBIT      29
> +#define LPASS_CLK_ID_QUAD_PCM_IBIT     30
> +#define LPASS_CLK_ID_QUAD_PCM_EBIT     31
> +#define LPASS_CLK_ID_QUIN_PCM_IBIT     32
> +#define LPASS_CLK_ID_QUIN_PCM_EBIT     33
> +#define LPASS_CLK_ID_QUI_PCM_OSR       34
> +#define LPASS_CLK_ID_PRI_TDM_IBIT      35
> +#define LPASS_CLK_ID_PRI_TDM_EBIT      36
> +#define LPASS_CLK_ID_SEC_TDM_IBIT      37
> +#define LPASS_CLK_ID_SEC_TDM_EBIT      38
> +#define LPASS_CLK_ID_TER_TDM_IBIT      39
> +#define LPASS_CLK_ID_TER_TDM_EBIT      40
> +#define LPASS_CLK_ID_QUAD_TDM_IBIT     41
> +#define LPASS_CLK_ID_QUAD_TDM_EBIT     42
> +#define LPASS_CLK_ID_QUIN_TDM_IBIT     43
> +#define LPASS_CLK_ID_QUIN_TDM_EBIT     44
> +#define LPASS_CLK_ID_QUIN_TDM_OSR      45
> +#define LPASS_CLK_ID_MCLK_1            46
> +#define LPASS_CLK_ID_MCLK_2            47
> +#define LPASS_CLK_ID_MCLK_3            48
> +#define LPASS_CLK_ID_MCLK_4            49
> +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE       50
> +#define LPASS_CLK_ID_INT_MCLK_0                51
> +#define LPASS_CLK_ID_INT_MCLK_1                52
> +#define LPASS_CLK_ID_MCLK_5            53
> +#define LPASS_CLK_ID_WSA_CORE_MCLK     54
> +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
> +#define LPASS_CLK_ID_VA_CORE_MCLK      56
> +#define LPASS_CLK_ID_TX_CORE_MCLK      57
> +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK  58
> +#define LPASS_CLK_ID_RX_CORE_MCLK      59
> +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK  60
> +#define LPASS_CLK_ID_VA_CORE_2X_MCLK   61
> +/* Clock ID for MCLK for WSA2 core */
> +#define LPASS_CLK_ID_WSA2_CORE_MCLK    62
> +/* Clock ID for NPL MCLK for WSA2 core */
> +#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63
> +/* Clock ID for RX Core TX MCLK */
> +#define LPASS_CLK_ID_RX_CORE_TX_MCLK   64
> +/* Clock ID for RX CORE TX 2X MCLK */
> +#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK        65
> +/* Clock ID for WSA core TX MCLK */
> +#define LPASS_CLK_ID_WSA_CORE_TX_MCLK  66
> +/* Clock ID for WSA core TX 2X MCLK */
> +#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK       67
> +/* Clock ID for WSA2 core TX MCLK */
> +#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68
> +/* Clock ID for WSA2 core TX 2X MCLK */
> +#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK      69
> +/* Clock ID for RX CORE MCLK2 2X  MCLK */
> +#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK     70
> +
> +#define LPASS_HW_AVTIMER_VOTE          101
> +#define LPASS_HW_MACRO_VOTE            102
> +#define LPASS_HW_DCODEC_VOTE           103
> +
> +#define Q6AFE_MAX_CLK_ID                       104
> +
> +#define LPASS_CLK_ATTRIBUTE_INVALID            0x0
> +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO          0x1
> +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND    0x2
> +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR     0x3
> +
> +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */
>
> --
> 2.43.1
>

Re: [PATCH v4 28/39] dts: sdm845: import supporting dtsi files

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import the PM8998 and PMI8998 PMIC DTSI files from Linux as well
> as the common audio codec in preperation for replacing board DTS files

s/preperation/preparation/

> with upstream.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/pm8998.dtsi         | 130 +++++++++++++++++++++++++++++++++++++++
>  arch/arm/dts/pmi8998.dtsi        |  98 +++++++++++++++++++++++++++++
>  arch/arm/dts/sdm845-wcd9340.dtsi |  86 ++++++++++++++++++++++++++
>  3 files changed, 314 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi
> new file mode 100644
> index 000000000000..3f82715392c6
> --- /dev/null
> +++ b/arch/arm/dts/pm8998.dtsi
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/* Copyright 2018 Google LLC. */
> +
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       thermal-zones {
> +               pm8998-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&pm8998_temp>;
> +
> +                       trips {
> +                               pm8998_alert0: pm8998-alert0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               pm8998_crit: pm8998-crit {
> +                                       temperature = <125000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&spmi_bus {
> +       pm8998_lsid0: pmic@0 {
> +               compatible = "qcom,pm8998", "qcom,spmi-pmic";
> +               reg = <0x0 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pm8998_pon: pon@800 {
> +                       compatible = "qcom,pm8998-pon";
> +
> +                       reg = <0x800>;
> +                       mode-bootloader = <0x2>;
> +                       mode-recovery = <0x1>;
> +
> +                       pm8998_pwrkey: pwrkey {
> +                               compatible = "qcom,pm8941-pwrkey";
> +                               interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               linux,code = <KEY_POWER>;
> +                       };
> +
> +                       pm8998_resin: resin {
> +                               compatible = "qcom,pm8941-resin";
> +                               interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               pm8998_temp: temp-alarm@2400 {
> +                       compatible = "qcom,spmi-temp-alarm";
> +                       reg = <0x2400>;
> +                       interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
> +                       io-channel-names = "thermal";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
> +               pm8998_coincell: charger@2800 {
> +                       compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell";
> +                       reg = <0x2800>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pm8998_adc: adc@3100 {
> +                       compatible = "qcom,spmi-adc-rev2";
> +                       reg = <0x3100>;
> +                       interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #io-channel-cells = <1>;
> +
> +                       channel@6 {
> +                               reg = <ADC5_DIE_TEMP>;
> +                               label = "die_temp";
> +                       };
> +               };
> +
> +               pm8998_adc_tm: adc-tm@3400 {
> +                       compatible = "qcom,spmi-adc-tm-hc";
> +                       reg = <0x3400>;
> +                       interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #thermal-sensor-cells = <1>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               rtc@6000 {
> +                       compatible = "qcom,pm8941-rtc";
> +                       reg = <0x6000>, <0x6100>;
> +                       reg-names = "rtc", "alarm";
> +                       interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
> +               };
> +
> +               pm8998_gpios: gpio@c000 {
> +                       compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pm8998_gpios 0 0 26>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +       };
> +
> +       pm8998_lsid1: pmic@1 {
> +               compatible = "qcom,pm8998", "qcom,spmi-pmic";
> +               reg = <0x1 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +};
> diff --git a/arch/arm/dts/pmi8998.dtsi b/arch/arm/dts/pmi8998.dtsi
> new file mode 100644
> index 000000000000..cd3f0790fd42
> --- /dev/null
> +++ b/arch/arm/dts/pmi8998.dtsi
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> +       pmi8998_lsid0: pmic@2 {
> +               compatible = "qcom,pmi8998", "qcom,spmi-pmic";
> +               reg = <0x2 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pmi8998_charger: charger@1000 {
> +                       compatible = "qcom,pmi8998-charger";
> +                       reg = <0x1000>;
> +
> +                       interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
> +                                    <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
> +                                    <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
> +                                    <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "usb-plugin",
> +                                         "bat-ov",
> +                                         "wdog-bark",
> +                                         "usbin-icl-change";
> +
> +                       io-channels = <&pmi8998_rradc 3>,
> +                                     <&pmi8998_rradc 4>;
> +                       io-channel-names = "usbin_i", "usbin_v";
> +
> +                       status = "disabled";
> +               };
> +
> +               pmi8998_gpios: gpio@c000 {
> +                       compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pmi8998_gpios 0 0 14>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               pmi8998_rradc: adc@4500 {
> +                       compatible = "qcom,pmi8998-rradc";
> +                       reg = <0x4500>;
> +                       #io-channel-cells = <1>;
> +               };
> +       };
> +
> +       pmi8998_lsid1: pmic@3 {
> +               compatible = "qcom,pmi8998", "qcom,spmi-pmic";
> +               reg = <0x3 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               labibb {
> +                       compatible = "qcom,pmi8998-lab-ibb";
> +
> +                       ibb: ibb {
> +                               interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
> +                                            <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupt-names = "sc-err", "ocp";
> +                       };
> +
> +                       lab: lab {
> +                               interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
> +                                            <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
> +                               interrupt-names = "sc-err", "ocp";
> +                       };
> +               };
> +
> +               pmi8998_lpg: pwm {
> +                       compatible = "qcom,pmi8998-lpg";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #pwm-cells = <2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pmi8998_flash: led-controller@d300 {
> +                       compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led";
> +                       reg = <0xd300>;
> +                       status = "disabled";
> +               };
> +
> +               pmi8998_wled: leds@d800 {
> +                       compatible = "qcom,pmi8998-wled";
> +                       reg = <0xd800>, <0xd900>;
> +                       interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
> +                                    <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "ovp", "short";
> +                       label = "backlight";
> +
> +                       status = "disabled";
> +               };
> +       };
> +};
> diff --git a/arch/arm/dts/sdm845-wcd9340.dtsi b/arch/arm/dts/sdm845-wcd9340.dtsi
> new file mode 100644
> index 000000000000..c15d48860646
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-wcd9340.dtsi
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 SoC device tree source
> + *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +&slim {
> +       status = "okay";
> +
> +       slim@1 {
> +               reg = <1>;
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               wcd9340_ifd: ifd@0,0 {
> +                       compatible = "slim217,250";
> +                       reg = <0 0>;
> +               };
> +
> +               wcd9340: codec@1,0 {
> +                       compatible = "slim217,250";
> +                       reg = <1 0>;
> +                       slim-ifc-dev = <&wcd9340_ifd>;
> +
> +                       #sound-dai-cells = <1>;
> +
> +                       interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       clock-names = "extclk";
> +                       clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
> +
> +                       #clock-cells = <0>;
> +                       clock-frequency = <9600000>;
> +                       clock-output-names = "mclk";
> +
> +                       pinctrl-0 = <&wcd_intr_default>;
> +                       pinctrl-names = "default";
> +
> +                       qcom,micbias1-microvolt = <1800000>;
> +                       qcom,micbias2-microvolt = <1800000>;
> +                       qcom,micbias3-microvolt = <1800000>;
> +                       qcom,micbias4-microvolt = <1800000>;
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       wcdgpio: gpio-controller@42 {
> +                               compatible = "qcom,wcd9340-gpio";
> +                               gpio-controller;
> +                               #gpio-cells = <2>;
> +                               reg = <0x42 0x2>;
> +                       };
> +
> +                       swm: swm@c85 {
> +                               compatible = "qcom,soundwire-v1.3.0";
> +                               reg = <0xc85 0x40>;
> +                               interrupts-extended = <&wcd9340 20>;
> +
> +                               qcom,dout-ports = <6>;
> +                               qcom,din-ports = <2>;
> +                               qcom,ports-sinterval-low = /bits/ 8  <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>;
> +                               qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>;
> +                               qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>;
> +
> +                               #sound-dai-cells = <1>;
> +                               clocks = <&wcd9340>;
> +                               clock-names = "iface";
> +                               #address-cells = <2>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +       };
> +};
> +
> +&tlmm {
> +       wcd_intr_default: wcd-intr-default-state {
> +               pins = "gpio54";
> +               function = "gpio";
> +
> +               bias-pull-down;
> +               drive-strength = <2>;
> +       };
> +};
>
> --
> 2.43.1
>

Re: [PATCH v4 29/39] dts: sdm845: replace with upstream DTS

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import sdm845.dtsi from upstream, as well as the upstream DTS files for
> the db845c and Samsung starqltechn. Delete the old board files.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/Makefile                              |    4 +-
>  arch/arm/dts/dragonboard845c-uboot.dtsi            |   26 -
>  arch/arm/dts/dragonboard845c.dts                   |   48 -
>  arch/arm/dts/sdm845-db845c.dts                     | 1190 ++++
>  .../arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi |   16 +
>  arch/arm/dts/sdm845-samsung-starqltechn.dts        |  460 ++
>  arch/arm/dts/sdm845.dtsi                           | 5801 +++++++++++++++++++-
>  arch/arm/dts/starqltechn-uboot.dtsi                |   27 -
>  arch/arm/dts/starqltechn.dts                       |   68 -
>  configs/qcom_defconfig                             |    2 +-
>  10 files changed, 7386 insertions(+), 256 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 751035a577f6..3f4e49b3e445 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -633,8 +633,8 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
>
>  dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
>         dragonboard820c.dtb \
> -       dragonboard845c.dtb \
> -       starqltechn.dtb \
> +       sdm845-db845c.dtb \
> +       sdm845-samsung-starqltechn.dtb \
>         qcs404-evb.dtb
>
>  dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
> diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
> deleted file mode 100644
> index 775f45c0149f..000000000000
> --- a/arch/arm/dts/dragonboard845c-uboot.dtsi
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
> - * (dragonboard845c) pins
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -/
> -{
> -       soc {
> -               bootph-all;
> -
> -               serial@a84000 {
> -                       bootph-all;
> -               };
> -
> -               clock-controller@100000 {
> -                       bootph-all;
> -               };
> -
> -               pinctrl@3400000 {
> -                       bootph-all;
> -               };
> -       };
> -};
> diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
> deleted file mode 100644
> index 054f253eb32a..000000000000
> --- a/arch/arm/dts/dragonboard845c.dts
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm Robotics RB3 Development (dragonboard845c) board device
> - * tree source
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -/dts-v1/;
> -
> -#include "sdm845.dtsi"
> -
> -/ {
> -       model = "Thundercomm Dragonboard 845c";
> -       compatible = "thundercomm,db845c", "qcom,sdm845";
> -       #address-cells = <2>;
> -       #size-cells = <2>;
> -
> -       chosen {
> -               stdout-path = "serial0:115200n8";
> -       };
> -
> -       aliases {
> -               serial0 = &uart9;
> -       };
> -
> -       memory {
> -               device_type = "memory";
> -               reg = <0 0x80000000 0 0xfdfa0000>;
> -       };
> -
> -       psci {
> -               compatible = "arm,psci-1.0";
> -               method = "smc";
> -       };
> -
> -       soc: soc {
> -               serial@a84000 {
> -                       status = "okay";
> -               };
> -       };
> -};
> -
> -&pm8998_resin {
> -       status = "okay";
> -};
> -
> -#include "dragonboard845c-uboot.dtsi"
> diff --git a/arch/arm/dts/sdm845-db845c.dts b/arch/arm/dts/sdm845-db845c.dts
> new file mode 100644
> index 000000000000..c7eba6c491be
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-db845c.dts
> @@ -0,0 +1,1190 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, Linaro Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/sound/qcom,q6afe.h>
> +#include <dt-bindings/sound/qcom,q6asm.h>
> +#include "sdm845.dtsi"
> +#include "sdm845-wcd9340.dtsi"
> +#include "pm8998.dtsi"
> +#include "pmi8998.dtsi"
> +
> +/ {
> +       model = "Thundercomm Dragonboard 845c";
> +       compatible = "thundercomm,db845c", "qcom,sdm845";
> +       qcom,msm-id = <341 0x20001>;
> +       qcom,board-id = <8 0>;
> +
> +       aliases {
> +               serial0 = &uart9;
> +               serial1 = &uart6;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       /* Fixed crystal oscillator dedicated to MCP2517FD */
> +       clk40M: can-clock {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <40000000>;
> +       };
> +
> +       dc12v: dc12v-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "DC12V";
> +               regulator-min-microvolt = <12000000>;
> +               regulator-max-microvolt = <12000000>;
> +               regulator-always-on;
> +       };
> +
> +       gpio-keys {
> +               compatible = "gpio-keys";
> +               autorepeat;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&vol_up_pin_a>;
> +
> +               key-vol-up {
> +                       label = "Volume Up";
> +                       linux,code = <KEY_VOLUMEUP>;
> +                       gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> +               };
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led-0 {
> +                       label = "green:user4";
> +                       function = LED_FUNCTION_INDICATOR;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "panic-indicator";
> +                       default-state = "off";
> +               };
> +
> +               led-1 {
> +                       label = "yellow:wlan";
> +                       function = LED_FUNCTION_WLAN;
> +                       color = <LED_COLOR_ID_YELLOW>;
> +                       gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "phy0tx";
> +                       default-state = "off";
> +               };
> +
> +               led-2 {
> +                       label = "blue:bt";
> +                       function = LED_FUNCTION_BLUETOOTH;
> +                       color = <LED_COLOR_ID_BLUE>;
> +                       gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "bluetooth-power";
> +                       default-state = "off";
> +               };
> +       };
> +
> +       hdmi-out {
> +               compatible = "hdmi-connector";
> +               type = "a";
> +
> +               port {
> +                       hdmi_con: endpoint {
> +                               remote-endpoint = <&lt9611_out>;
> +                       };
> +               };
> +       };
> +
> +       reserved-memory {
> +               /* Cont splash region set up by the bootloader */
> +               cont_splash_mem: framebuffer@9d400000 {
> +                       reg = <0x0 0x9d400000 0x0 0x2400000>;
> +                       no-map;
> +               };
> +       };
> +
> +       lt9611_1v8: lt9611-vdd18-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "LT9611_1V8";
> +
> +               vin-supply = <&vdc_5v>;
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +
> +               gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +       };
> +
> +       lt9611_3v3: lt9611-3v3 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "LT9611_3V3";
> +
> +               vin-supply = <&vdc_3v3>;
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +
> +               /*
> +                * TODO: make it possible to drive same GPIO from two clients
> +                * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
> +                * enable-active-high;
> +                */
> +       };
> +
> +       pcie0_1p05v: pcie-0-1p05v-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "PCIE0_1.05V";
> +
> +               vin-supply = <&vbat>;
> +               regulator-min-microvolt = <1050000>;
> +               regulator-max-microvolt = <1050000>;
> +
> +               /*
> +                * TODO: make it possible to drive same GPIO from two clients
> +                * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
> +                * enable-active-high;
> +                */
> +       };
> +
> +       cam0_dvdd_1v2: cam0-dvdd-1v2-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "CAM0_DVDD_1V2";
> +               regulator-min-microvolt = <1200000>;
> +               regulator-max-microvolt = <1200000>;
> +               enable-active-high;
> +               gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&cam0_dvdd_1v2_en_default>;
> +               vin-supply = <&vbat>;
> +       };
> +
> +       cam0_avdd_2v8: cam0-avdd-2v8-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "CAM0_AVDD_2V8";
> +               regulator-min-microvolt = <2800000>;
> +               regulator-max-microvolt = <2800000>;
> +               enable-active-high;
> +               gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&cam0_avdd_2v8_en_default>;
> +               vin-supply = <&vbat>;
> +       };
> +
> +       /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */
> +       cam3_avdd_2v8: cam3-avdd-2v8-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "CAM3_AVDD_2V8";
> +               regulator-min-microvolt = <2800000>;
> +               regulator-max-microvolt = <2800000>;
> +               regulator-always-on;
> +               vin-supply = <&vbat>;
> +       };
> +
> +       pcie0_3p3v_dual: vldo-3v3-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VLDO_3V3";
> +
> +               vin-supply = <&vbat>;
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +
> +               gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pcie0_pwren_state>;
> +       };
> +
> +       v5p0_hdmiout: v5p0-hdmiout-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "V5P0_HDMIOUT";
> +
> +               vin-supply = <&vdc_5v>;
> +               regulator-min-microvolt = <500000>;
> +               regulator-max-microvolt = <500000>;
> +
> +               /*
> +                * TODO: make it possible to drive same GPIO from two clients
> +                * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
> +                * enable-active-high;
> +                */
> +       };
> +
> +       vbat: vbat-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VBAT";
> +
> +               vin-supply = <&dc12v>;
> +               regulator-min-microvolt = <4200000>;
> +               regulator-max-microvolt = <4200000>;
> +               regulator-always-on;
> +       };
> +
> +       vbat_som: vbat-som-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VBAT_SOM";
> +
> +               vin-supply = <&dc12v>;
> +               regulator-min-microvolt = <4200000>;
> +               regulator-max-microvolt = <4200000>;
> +               regulator-always-on;
> +       };
> +
> +       vdc_3v3: vdc-3v3-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VDC_3V3";
> +               vin-supply = <&dc12v>;
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +               regulator-always-on;
> +       };
> +
> +       vdc_5v: vdc-5v-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VDC_5V";
> +
> +               vin-supply = <&dc12v>;
> +               regulator-min-microvolt = <500000>;
> +               regulator-max-microvolt = <500000>;
> +               regulator-always-on;
> +       };
> +
> +       vreg_s4a_1p8: vreg-s4a-1p8 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vreg_s4a_1p8";
> +
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +               regulator-always-on;
> +       };
> +
> +       vph_pwr: vph-pwr-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vph_pwr";
> +
> +               vin-supply = <&vbat_som>;
> +       };
> +};
> +
> +&adsp_pas {
> +       status = "okay";
> +
> +       firmware-name = "qcom/sdm845/adsp.mbn";
> +};
> +
> +&apps_rsc {
> +       regulators-0 {
> +               compatible = "qcom,pm8998-rpmh-regulators";
> +               qcom,pmic-id = "a";
> +               vdd-s1-supply = <&vph_pwr>;
> +               vdd-s2-supply = <&vph_pwr>;
> +               vdd-s3-supply = <&vph_pwr>;
> +               vdd-s4-supply = <&vph_pwr>;
> +               vdd-s5-supply = <&vph_pwr>;
> +               vdd-s6-supply = <&vph_pwr>;
> +               vdd-s7-supply = <&vph_pwr>;
> +               vdd-s8-supply = <&vph_pwr>;
> +               vdd-s9-supply = <&vph_pwr>;
> +               vdd-s10-supply = <&vph_pwr>;
> +               vdd-s11-supply = <&vph_pwr>;
> +               vdd-s12-supply = <&vph_pwr>;
> +               vdd-s13-supply = <&vph_pwr>;
> +               vdd-l1-l27-supply = <&vreg_s7a_1p025>;
> +               vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
> +               vdd-l3-l11-supply = <&vreg_s7a_1p025>;
> +               vdd-l4-l5-supply = <&vreg_s7a_1p025>;
> +               vdd-l6-supply = <&vph_pwr>;
> +               vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
> +               vdd-l9-supply = <&vreg_bob>;
> +               vdd-l10-l23-l25-supply = <&vreg_bob>;
> +               vdd-l13-l19-l21-supply = <&vreg_bob>;
> +               vdd-l16-l28-supply = <&vreg_bob>;
> +               vdd-l18-l22-supply = <&vreg_bob>;
> +               vdd-l20-l24-supply = <&vreg_bob>;
> +               vdd-l26-supply = <&vreg_s3a_1p35>;
> +               vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
> +
> +               vreg_s3a_1p35: smps3 {
> +                       regulator-min-microvolt = <1352000>;
> +                       regulator-max-microvolt = <1352000>;
> +               };
> +
> +               vreg_s5a_2p04: smps5 {
> +                       regulator-min-microvolt = <1904000>;
> +                       regulator-max-microvolt = <2040000>;
> +               };
> +
> +               vreg_s7a_1p025: smps7 {
> +                       regulator-min-microvolt = <900000>;
> +                       regulator-max-microvolt = <1028000>;
> +               };
> +
> +               vreg_l1a_0p875: ldo1 {
> +                       regulator-min-microvolt = <880000>;
> +                       regulator-max-microvolt = <880000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l5a_0p8: ldo5 {
> +                       regulator-min-microvolt = <800000>;
> +                       regulator-max-microvolt = <800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l12a_1p8: ldo12 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l7a_1p8: ldo7 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l13a_2p95: ldo13 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <2960000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l17a_1p3: ldo17 {
> +                       regulator-min-microvolt = <1304000>;
> +                       regulator-max-microvolt = <1304000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l20a_2p95: ldo20 {
> +                       regulator-min-microvolt = <2960000>;
> +                       regulator-max-microvolt = <2968000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l21a_2p95: ldo21 {
> +                       regulator-min-microvolt = <2960000>;
> +                       regulator-max-microvolt = <2968000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l24a_3p075: ldo24 {
> +                       regulator-min-microvolt = <3088000>;
> +                       regulator-max-microvolt = <3088000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l25a_3p3: ldo25 {
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3312000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l26a_1p2: ldo26 {
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_lvs1a_1p8: lvs1 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on;
> +               };
> +
> +               vreg_lvs2a_1p8: lvs2 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on;
> +               };
> +       };
> +
> +       regulators-1 {
> +               compatible = "qcom,pmi8998-rpmh-regulators";
> +               qcom,pmic-id = "b";
> +
> +               vdd-bob-supply = <&vph_pwr>;
> +
> +               vreg_bob: bob {
> +                       regulator-min-microvolt = <3312000>;
> +                       regulator-max-microvolt = <3600000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> +                       regulator-allow-bypass;
> +               };
> +       };
> +};
> +
> +&camss {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l26a_1p2>;
> +};
> +
> +&cdsp_pas {
> +       status = "okay";
> +       firmware-name = "qcom/sdm845/cdsp.mbn";
> +};
> +
> +&gcc {
> +       protected-clocks = <GCC_QSPI_CORE_CLK>,
> +                          <GCC_QSPI_CORE_CLK_SRC>,
> +                          <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> +                          <GCC_LPASS_Q6_AXI_CLK>,
> +                          <GCC_LPASS_SWAY_CLK>;
> +};
> +
> +&gmu {
> +       status = "okay";
> +};
> +
> +&gpi_dma0 {
> +       status = "okay";
> +};
> +
> +&gpi_dma1 {
> +       status = "okay";
> +};
> +
> +&gpu {
> +       status = "okay";
> +       zap-shader {
> +               memory-region = <&gpu_mem>;
> +               firmware-name = "qcom/sdm845/a630_zap.mbn";
> +       };
> +};
> +
> +&i2c10 {
> +       status = "okay";
> +       clock-frequency = <400000>;
> +
> +       lt9611_codec: hdmi-bridge@3b {
> +               compatible = "lontium,lt9611";
> +               reg = <0x3b>;
> +               #sound-dai-cells = <1>;
> +
> +               interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
> +
> +               reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
> +
> +               vdd-supply = <&lt9611_1v8>;
> +               vcc-supply = <&lt9611_3v3>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&lt9611_irq_pin>, <&dsi_sw_sel>;
> +
> +               ports {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       port@0 {
> +                               reg = <0>;
> +
> +                               lt9611_a: endpoint {
> +                                       remote-endpoint = <&mdss_dsi0_out>;
> +                               };
> +                       };
> +
> +                       port@1 {
> +                               reg = <1>;
> +
> +                               lt9611_b: endpoint {
> +                                       remote-endpoint = <&mdss_dsi1_out>;
> +                               };
> +                       };
> +
> +                       port@2 {
> +                               reg = <2>;
> +
> +                               lt9611_out: endpoint {
> +                                       remote-endpoint = <&hdmi_con>;
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&i2c11 {
> +       /* On Low speed expansion */
> +       clock-frequency = <100000>;
> +       status = "okay";
> +};
> +
> +&i2c14 {
> +       /* On Low speed expansion */
> +       clock-frequency = <100000>;
> +       status = "okay";
> +};
> +
> +&mdss {
> +       memory-region = <&cont_splash_mem>;
> +       status = "okay";
> +};
> +
> +&mdss_dsi0 {
> +       status = "okay";
> +       vdda-supply = <&vreg_l26a_1p2>;
> +
> +       qcom,dual-dsi-mode;
> +       qcom,master-dsi;
> +
> +       ports {
> +               port@1 {
> +                       endpoint {
> +                               remote-endpoint = <&lt9611_a>;
> +                               data-lanes = <0 1 2 3>;
> +                       };
> +               };
> +       };
> +};
> +
> +&mdss_dsi0_phy {
> +       status = "okay";
> +       vdds-supply = <&vreg_l1a_0p875>;
> +};
> +
> +&mdss_dsi1 {
> +       vdda-supply = <&vreg_l26a_1p2>;
> +
> +       qcom,dual-dsi-mode;
> +
> +       /* DSI1 is slave, so use DSI0 clocks */
> +       assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> +       status = "okay";
> +
> +       ports {
> +               port@1 {
> +                       endpoint {
> +                               remote-endpoint = <&lt9611_b>;
> +                               data-lanes = <0 1 2 3>;
> +                       };
> +               };
> +       };
> +};
> +
> +&mdss_dsi1_phy {
> +       vdds-supply = <&vreg_l1a_0p875>;
> +       status = "okay";
> +};
> +
> +&mss_pil {
> +       status = "okay";
> +       firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
> +};
> +
> +&pcie0 {
> +       status = "okay";
> +       perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
> +       enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
> +
> +       vddpe-3v3-supply = <&pcie0_3p3v_dual>;
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pcie0_default_state>;
> +};
> +
> +&pcie0_phy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l26a_1p2>;
> +};
> +
> +&pcie1 {
> +       status = "okay";
> +       perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pcie1_default_state>;
> +};
> +
> +&pcie1_phy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l26a_1p2>;
> +};
> +
> +&pm8998_gpios {
> +       gpio-line-names =
> +               "NC",
> +               "NC",
> +               "WLAN_SW_CTRL",
> +               "NC",
> +               "PM_GPIO5_BLUE_BT_LED",
> +               "VOL_UP_N",
> +               "NC",
> +               "ADC_IN1",
> +               "PM_GPIO9_YEL_WIFI_LED",
> +               "CAM0_AVDD_EN",
> +               "NC",
> +               "CAM0_DVDD_EN",
> +               "PM_GPIO13_GREEN_U4_LED",
> +               "DIV_CLK2",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "SMB_STAT",
> +               "NC",
> +               "NC",
> +               "ADC_IN2",
> +               "OPTION1",
> +               "WCSS_PWR_REQ",
> +               "PM845_GPIO24",
> +               "OPTION2",
> +               "PM845_SLB";
> +
> +       cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state {
> +               pins = "gpio12";
> +               function = "normal";
> +
> +               bias-pull-up;
> +               drive-push-pull;
> +               qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
> +       };
> +
> +       cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state {
> +               pins = "gpio10";
> +               function = "normal";
> +
> +               bias-pull-up;
> +               drive-push-pull;
> +               qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
> +       };
> +
> +       vol_up_pin_a: vol-up-active-state {
> +               pins = "gpio6";
> +               function = "normal";
> +               input-enable;
> +               bias-pull-up;
> +               qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> +       };
> +};
> +
> +&pm8998_resin {
> +       linux,code = <KEY_VOLUMEDOWN>;
> +       status = "okay";
> +};
> +
> +&pmi8998_lpg {
> +       status = "okay";
> +
> +       qcom,power-source = <1>;
> +
> +       led@3 {
> +               reg = <3>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_HEARTBEAT;
> +               function-enumerator = <3>;
> +
> +               linux,default-trigger = "heartbeat";
> +               default-state = "on";
> +       };
> +
> +       led@4 {
> +               reg = <4>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_INDICATOR;
> +               function-enumerator = <2>;
> +       };
> +
> +       led@5 {
> +               reg = <5>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_INDICATOR;
> +               function-enumerator = <1>;
> +       };
> +};
> +
> +/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
> +&q6afedai {
> +       dai@22 {
> +               reg = <QUATERNARY_MI2S_RX>;
> +               qcom,sd-lines = <0 1 2 3>;
> +       };
> +};
> +
> +&q6asmdai {
> +       dai@0 {
> +               reg = <0>;
> +       };
> +
> +       dai@1 {
> +               reg = <1>;
> +       };
> +
> +       dai@2 {
> +               reg = <2>;
> +       };
> +
> +       dai@3 {
> +               reg = <3>;
> +               direction = <2>;
> +               is-compress-dai;
> +       };
> +};
> +
> +&qupv3_id_0 {
> +       status = "okay";
> +};
> +
> +&qupv3_id_1 {
> +       status = "okay";
> +};
> +
> +&sdhc_2 {
> +       status = "okay";
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
> +
> +       vmmc-supply = <&vreg_l21a_2p95>;
> +       vqmmc-supply = <&vreg_l13a_2p95>;
> +
> +       bus-width = <4>;
> +       cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
> +};
> +
> +&sound {
> +       compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard";
> +       pinctrl-0 = <&quat_mi2s_active
> +                        &quat_mi2s_sd0_active
> +                        &quat_mi2s_sd1_active
> +                        &quat_mi2s_sd2_active
> +                        &quat_mi2s_sd3_active>;
> +       pinctrl-names = "default";
> +       model = "DB845c";
> +       audio-routing =
> +               "RX_BIAS", "MCLK",
> +               "AMIC1", "MIC BIAS1",
> +               "AMIC2", "MIC BIAS2",
> +               "DMIC0", "MIC BIAS1",
> +               "DMIC1", "MIC BIAS1",
> +               "DMIC2", "MIC BIAS3",
> +               "DMIC3", "MIC BIAS3",
> +               "SpkrLeft IN", "SPK1 OUT",
> +               "SpkrRight IN", "SPK2 OUT",
> +               "MM_DL1",  "MultiMedia1 Playback",
> +               "MM_DL2",  "MultiMedia2 Playback",
> +               "MM_DL4",  "MultiMedia4 Playback",
> +               "MultiMedia3 Capture", "MM_UL3";
> +
> +       mm1-dai-link {
> +               link-name = "MultiMedia1";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
> +               };
> +       };
> +
> +       mm2-dai-link {
> +               link-name = "MultiMedia2";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
> +               };
> +       };
> +
> +       mm3-dai-link {
> +               link-name = "MultiMedia3";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
> +               };
> +       };
> +
> +       mm4-dai-link {
> +               link-name = "MultiMedia4";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA4>;
> +               };
> +       };
> +
> +       hdmi-dai-link {
> +               link-name = "HDMI Playback";
> +               cpu {
> +                       sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&lt9611_codec 0>;
> +               };
> +       };
> +
> +       slim-dai-link {
> +               link-name = "SLIM Playback";
> +               cpu {
> +                       sound-dai = <&q6afedai SLIMBUS_0_RX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
> +               };
> +       };
> +
> +       slimcap-dai-link {
> +               link-name = "SLIM Capture";
> +               cpu {
> +                       sound-dai = <&q6afedai SLIMBUS_0_TX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&wcd9340 1>;
> +               };
> +       };
> +};
> +
> +&spi0 {
> +       status = "okay";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&qup_spi0_default>;
> +       cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
> +
> +       can@0 {
> +               compatible = "microchip,mcp2517fd";
> +               reg = <0>;
> +               clocks = <&clk40M>;
> +               interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> +               spi-max-frequency = <10000000>;
> +               vdd-supply = <&vdc_5v>;
> +               xceiver-supply = <&vdc_5v>;
> +       };
> +};
> +
> +&spi2 {
> +       /* On Low speed expansion */
> +       status = "okay";
> +};
> +
> +&tlmm {
> +       cam0_default: cam0-default-state {
> +               rst-pins {
> +                       pins = "gpio9";
> +                       function = "gpio";
> +
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +
> +               mclk0-pins {
> +                       pins = "gpio13";
> +                       function = "cam_mclk";
> +
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +       };
> +
> +       cam3_default: cam3-default-state {
> +               rst-pins {
> +                       function = "gpio";
> +                       pins = "gpio21";
> +
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +
> +               mclk3-pins {
> +                       function = "cam_mclk";
> +                       pins = "gpio16";
> +
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +       };
> +
> +       dsi_sw_sel: dsi-sw-sel-state {
> +               pins = "gpio120";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-disable;
> +               output-high;
> +       };
> +
> +       lt9611_irq_pin: lt9611-irq-state {
> +               pins = "gpio84";
> +               function = "gpio";
> +               bias-disable;
> +       };
> +
> +       pcie0_default_state: pcie0-default-state {
> +               clkreq-pins {
> +                       pins = "gpio36";
> +                       function = "pci_e0";
> +                       bias-pull-up;
> +               };
> +
> +               reset-n-pins {
> +                       pins = "gpio35";
> +                       function = "gpio";
> +
> +                       drive-strength = <2>;
> +                       output-low;
> +                       bias-pull-down;
> +               };
> +
> +               wake-n-pins {
> +                       pins = "gpio37";
> +                       function = "gpio";
> +
> +                       drive-strength = <2>;
> +                       bias-pull-up;
> +               };
> +       };
> +
> +       pcie0_pwren_state: pcie0-pwren-state {
> +               pins = "gpio90";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       pcie1_default_state: pcie1-default-state {
> +               perst-n-pins {
> +                       pins = "gpio102";
> +                       function = "gpio";
> +
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +
> +               clkreq-pins {
> +                       pins = "gpio103";
> +                       function = "pci_e1";
> +                       bias-pull-up;
> +               };
> +
> +               wake-n-pins {
> +                       pins = "gpio11";
> +                       function = "gpio";
> +
> +                       drive-strength = <2>;
> +                       bias-pull-up;
> +               };
> +
> +               reset-n-pins {
> +                       pins = "gpio75";
> +                       function = "gpio";
> +
> +                       drive-strength = <16>;
> +                       bias-pull-up;
> +                       output-high;
> +               };
> +       };
> +
> +       sdc2_default_state: sdc2-default-state {
> +               clk-pins {
> +                       pins = "sdc2_clk";
> +                       bias-disable;
> +
> +                       /*
> +                        * It seems that mmc_test reports errors if drive
> +                        * strength is not 16 on clk, cmd, and data pins.
> +                        */
> +                       drive-strength = <16>;
> +               };
> +
> +               cmd-pins {
> +                       pins = "sdc2_cmd";
> +                       bias-pull-up;
> +                       drive-strength = <10>;
> +               };
> +
> +               data-pins {
> +                       pins = "sdc2_data";
> +                       bias-pull-up;
> +                       drive-strength = <10>;
> +               };
> +       };
> +
> +       sdc2_card_det_n: sd-card-det-n-state {
> +               pins = "gpio126";
> +               function = "gpio";
> +               bias-pull-up;
> +       };
> +};
> +
> +&uart3 {
> +       label = "LS-UART0";
> +       pinctrl-0 = <&qup_uart3_4pin>;
> +
> +       status = "disabled";
> +};
> +
> +&uart6 {
> +       status = "okay";
> +
> +       pinctrl-0 = <&qup_uart6_4pin>;
> +
> +       bluetooth {
> +               compatible = "qcom,wcn3990-bt";
> +
> +               vddio-supply = <&vreg_s4a_1p8>;
> +               vddxo-supply = <&vreg_l7a_1p8>;
> +               vddrf-supply = <&vreg_l17a_1p3>;
> +               vddch0-supply = <&vreg_l25a_3p3>;
> +               max-speed = <3200000>;
> +       };
> +};
> +
> +&uart9 {
> +       label = "LS-UART1";
> +       status = "okay";
> +};
> +
> +&usb_1 {
> +       status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> +       dr_mode = "peripheral";
> +};
> +
> +&usb_1_hsphy {
> +       status = "okay";
> +
> +       vdd-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +       vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +
> +       qcom,imp-res-offset-value = <8>;
> +       qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
> +       qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
> +       qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
> +};
> +
> +&usb_1_qmpphy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l26a_1p2>;
> +       vdda-pll-supply = <&vreg_l1a_0p875>;
> +};
> +
> +&usb_2 {
> +       status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> +       dr_mode = "host";
> +};
> +
> +&usb_2_hsphy {
> +       status = "okay";
> +
> +       vdd-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +       vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +
> +       qcom,imp-res-offset-value = <8>;
> +       qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
> +};
> +
> +&usb_2_qmpphy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l26a_1p2>;
> +       vdda-pll-supply = <&vreg_l1a_0p875>;
> +};
> +
> +&ufs_mem_hc {
> +       status = "okay";
> +
> +       reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
> +
> +       vcc-supply = <&vreg_l20a_2p95>;
> +       vcc-max-microamp = <800000>;
> +};
> +
> +&ufs_mem_phy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l1a_0p875>;
> +       vdda-pll-supply = <&vreg_l26a_1p2>;
> +};
> +
> +&venus {
> +       status = "okay";
> +};
> +
> +&wcd9340 {
> +       reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
> +       vdd-buck-supply = <&vreg_s4a_1p8>;
> +       vdd-buck-sido-supply = <&vreg_s4a_1p8>;
> +       vdd-tx-supply = <&vreg_s4a_1p8>;
> +       vdd-rx-supply = <&vreg_s4a_1p8>;
> +       vdd-io-supply = <&vreg_s4a_1p8>;
> +
> +       swm: swm@c85 {
> +               left_spkr: speaker@0,1 {
> +                       compatible = "sdw10217201000";
> +                       reg = <0 1>;
> +                       powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
> +                       #thermal-sensor-cells = <0>;
> +                       sound-name-prefix = "SpkrLeft";
> +                       #sound-dai-cells = <0>;
> +               };
> +
> +               right_spkr: speaker@0,2 {
> +                       compatible = "sdw10217201000";
> +                       powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
> +                       reg = <0 2>;
> +                       #thermal-sensor-cells = <0>;
> +                       sound-name-prefix = "SpkrRight";
> +                       #sound-dai-cells = <0>;
> +               };
> +       };
> +};
> +
> +&wifi {
> +       status = "okay";
> +
> +       vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
> +       vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
> +       vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
> +       vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
> +
> +       qcom,snoc-host-cap-8bit-quirk;
> +       qcom,ath10k-calibration-variant = "Thundercomm_DB845C";
> +};
> +
> +/* PINCTRL - additions to nodes defined in sdm845.dtsi */
> +&qup_spi2_default {
> +       drive-strength = <16>;
> +};
> +
> +&qup_i2c10_default {
> +       drive-strength = <2>;
> +       bias-disable;
> +};
> +
> +&qup_uart9_rx {
> +       drive-strength = <2>;
> +       bias-pull-up;
> +};
> +
> +&qup_uart9_tx {
> +       drive-strength = <2>;
> +       bias-disable;
> +};
> +
> +/* PINCTRL - additions to nodes defined in sdm845.dtsi */
> +&qup_spi0_default {
> +       drive-strength = <6>;
> +       bias-disable;
> +};
> diff --git a/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi
> new file mode 100644
> index 000000000000..c78bd6e92406
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> +       chosen {
> +               stdout-path = "serial0:921600n8";
> +       };
> +};
> +
> +&tlmm {
> +       muic-i2c-n {
> +               pins = "gpio33", "gpio34";
> +               drive-strength = <0x2>;
> +               function = "gpio";
> +               bias-disable;
> +       };
> +};
> diff --git a/arch/arm/dts/sdm845-samsung-starqltechn.dts b/arch/arm/dts/sdm845-samsung-starqltechn.dts
> new file mode 100644
> index 000000000000..d37a433130b9
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-samsung-starqltechn.dts
> @@ -0,0 +1,460 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
> + *
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sdm845.dtsi"
> +
> +/ {
> +       chassis-type = "handset";
> +       model = "Samsung Galaxy S9 SM-G9600";
> +       compatible = "samsung,starqltechn", "qcom,sdm845";
> +
> +       chosen {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +               framebuffer: framebuffer@9d400000 {
> +                       compatible = "simple-framebuffer";
> +                       reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000
> +                       width = <1440>;
> +                       height = <2960>;
> +                       stride = <(1440 * 4)>;
> +                       format = "a8r8g8b8";
> +               };
> +       };
> +
> +       vph_pwr: vph-pwr-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vph_pwr";
> +               regulator-min-microvolt = <3700000>;
> +               regulator-max-microvolt = <3700000>;
> +       };
> +
> +       /*
> +        * Apparently RPMh does not provide support for PM8998 S4 because it
> +        * is always-on; model it as a fixed regulator.
> +        */
> +       vreg_s4a_1p8: pm8998-smps4 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vreg_s4a_1p8";
> +
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +
> +               regulator-always-on;
> +               regulator-boot-on;
> +
> +               vin-supply = <&vph_pwr>;
> +       };
> +
> +       reserved-memory {
> +               memory@9d400000 {
> +                       reg = <0x0 0x9d400000 0x0 0x02400000>;
> +                       no-map;
> +               };
> +
> +               memory@a1300000 {
> +                       compatible = "ramoops";
> +                       reg = <0x0 0xa1300000 0x0 0x100000>;
> +                       record-size = <0x40000>;
> +                       console-size = <0x40000>;
> +                       ftrace-size = <0x40000>;
> +                       pmsg-size = <0x40000>;
> +               };
> +       };
> +};
> +
> +
> +&apps_rsc {
> +       regulators-0 {
> +               compatible = "qcom,pm8998-rpmh-regulators";
> +               qcom,pmic-id = "a";
> +
> +               vdd-s1-supply = <&vph_pwr>;
> +               vdd-s2-supply = <&vph_pwr>;
> +               vdd-s3-supply = <&vph_pwr>;
> +               vdd-s4-supply = <&vph_pwr>;
> +               vdd-s5-supply = <&vph_pwr>;
> +               vdd-s6-supply = <&vph_pwr>;
> +               vdd-s7-supply = <&vph_pwr>;
> +               vdd-s8-supply = <&vph_pwr>;
> +               vdd-s9-supply = <&vph_pwr>;
> +               vdd-s10-supply = <&vph_pwr>;
> +               vdd-s11-supply = <&vph_pwr>;
> +               vdd-s12-supply = <&vph_pwr>;
> +               vdd-s13-supply = <&vph_pwr>;
> +               vdd-l1-l27-supply = <&vreg_s7a_1p025>;
> +               vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
> +               vdd-l3-l11-supply = <&vreg_s7a_1p025>;
> +               vdd-l4-l5-supply = <&vreg_s7a_1p025>;
> +               vdd-l6-supply = <&vph_pwr>;
> +               vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
> +               vdd-l26-supply = <&vreg_s3a_1p35>;
> +               vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
> +
> +               vreg_s2a_1p125: smps2 {
> +                       regulator-min-microvolt = <1100000>;
> +                       regulator-max-microvolt = <1100000>;
> +               };
> +
> +               vreg_s3a_1p35: smps3 {
> +                       regulator-min-microvolt = <1352000>;
> +                       regulator-max-microvolt = <1352000>;
> +               };
> +
> +               vreg_s5a_2p04: smps5 {
> +                       regulator-min-microvolt = <1904000>;
> +                       regulator-max-microvolt = <2040000>;
> +               };
> +
> +               vreg_s7a_1p025: smps7 {
> +                       regulator-min-microvolt = <900000>;
> +                       regulator-max-microvolt = <1028000>;
> +               };
> +
> +               vdd_qusb_hs0:
> +               vdda_hp_pcie_core:
> +               vdda_mipi_csi0_0p9:
> +               vdda_mipi_csi1_0p9:
> +               vdda_mipi_csi2_0p9:
> +               vdda_mipi_dsi0_pll:
> +               vdda_mipi_dsi1_pll:
> +               vdda_qlink_lv:
> +               vdda_qlink_lv_ck:
> +               vdda_qrefs_0p875:
> +               vdda_pcie_core:
> +               vdda_pll_cc_ebi01:
> +               vdda_pll_cc_ebi23:
> +               vdda_sp_sensor:
> +               vdda_ufs1_core:
> +               vdda_ufs2_core:
> +               vdda_usb1_ss_core:
> +               vdda_usb2_ss_core:
> +               vreg_l1a_0p875: ldo1 {
> +                       regulator-min-microvolt = <880000>;
> +                       regulator-max-microvolt = <880000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vddpx_10:
> +               vreg_l2a_1p2: ldo2 {
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +                       regulator-always-on;
> +               };
> +
> +               vreg_l3a_1p0: ldo3 {
> +                       regulator-min-microvolt = <1000000>;
> +                       regulator-max-microvolt = <1000000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vdd_wcss_cx:
> +               vdd_wcss_mx:
> +               vdda_wcss_pll:
> +               vreg_l5a_0p8: ldo5 {
> +                       regulator-min-microvolt = <800000>;
> +                       regulator-max-microvolt = <800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vddpx_13:
> +               vreg_l6a_1p8: ldo6 {
> +                       regulator-min-microvolt = <1856000>;
> +                       regulator-max-microvolt = <1856000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l7a_1p8: ldo7 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l8a_1p2: ldo8 {
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1248000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l9a_1p8: ldo9 {
> +                       regulator-min-microvolt = <1704000>;
> +                       regulator-max-microvolt = <2928000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l10a_1p8: ldo10 {
> +                       regulator-min-microvolt = <1704000>;
> +                       regulator-max-microvolt = <2928000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l11a_1p0: ldo11 {
> +                       regulator-min-microvolt = <1000000>;
> +                       regulator-max-microvolt = <1048000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vdd_qfprom:
> +               vdd_qfprom_sp:
> +               vdda_apc1_cs_1p8:
> +               vdda_gfx_cs_1p8:
> +               vdda_qrefs_1p8:
> +               vdda_qusb_hs0_1p8:
> +               vddpx_11:
> +               vreg_l12a_1p8: ldo12 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vddpx_2:
> +               vreg_l13a_2p95: ldo13 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <2960000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l14a_1p88: ldo14 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l15a_1p8: ldo15 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l16a_2p7: ldo16 {
> +                       regulator-min-microvolt = <2704000>;
> +                       regulator-max-microvolt = <2704000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l17a_1p3: ldo17 {
> +                       regulator-min-microvolt = <1304000>;
> +                       regulator-max-microvolt = <1304000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l18a_2p7: ldo18 {
> +                       regulator-min-microvolt = <2704000>;
> +                       regulator-max-microvolt = <2960000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l19a_3p0: ldo19 {
> +                       regulator-min-microvolt = <2856000>;
> +                       regulator-max-microvolt = <3104000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l20a_2p95: ldo20 {
> +                       regulator-min-microvolt = <2704000>;
> +                       regulator-max-microvolt = <2960000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l21a_2p95: ldo21 {
> +                       regulator-min-microvolt = <2704000>;
> +                       regulator-max-microvolt = <2960000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l22a_2p85: ldo22 {
> +                       regulator-min-microvolt = <2864000>;
> +                       regulator-max-microvolt = <3312000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l23a_3p3: ldo23 {
> +                       regulator-min-microvolt = <3000000>;
> +                       regulator-max-microvolt = <3312000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vdda_qusb_hs0_3p1:
> +               vreg_l24a_3p075: ldo24 {
> +                       regulator-min-microvolt = <3088000>;
> +                       regulator-max-microvolt = <3088000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l25a_3p3: ldo25 {
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3312000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vdda_hp_pcie_1p2:
> +               vdda_hv_ebi0:
> +               vdda_hv_ebi1:
> +               vdda_hv_ebi2:
> +               vdda_hv_ebi3:
> +               vdda_mipi_csi_1p25:
> +               vdda_mipi_dsi0_1p2:
> +               vdda_mipi_dsi1_1p2:
> +               vdda_pcie_1p2:
> +               vdda_ufs1_1p2:
> +               vdda_ufs2_1p2:
> +               vdda_usb1_ss_1p2:
> +               vdda_usb2_ss_1p2:
> +               vreg_l26a_1p2: ldo26 {
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_l28a_3p0: ldo28 {
> +                       regulator-min-microvolt = <2856000>;
> +                       regulator-max-microvolt = <3008000>;
> +                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +               };
> +
> +               vreg_lvs1a_1p8: lvs1 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +
> +               vreg_lvs2a_1p8: lvs2 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +       };
> +
> +       regulators-1 {
> +               compatible = "qcom,pm8005-rpmh-regulators";
> +               qcom,pmic-id = "c";
> +
> +               vdd-s1-supply = <&vph_pwr>;
> +               vdd-s2-supply = <&vph_pwr>;
> +               vdd-s3-supply = <&vph_pwr>;
> +               vdd-s4-supply = <&vph_pwr>;
> +
> +               vreg_s3c_0p6: smps3 {
> +                       regulator-min-microvolt = <600000>;
> +                       regulator-max-microvolt = <600000>;
> +               };
> +       };
> +};
> +
> +&gcc {
> +       protected-clocks = <GCC_QSPI_CORE_CLK>,
> +                               <GCC_QSPI_CORE_CLK_SRC>,
> +                               <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> +                               <GCC_LPASS_Q6_AXI_CLK>,
> +                               <GCC_LPASS_SWAY_CLK>;
> +};
> +
> +&i2c10 {
> +       clock-frequency = <400000>;
> +       status = "okay";
> +};
> +
> +&qupv3_id_1 {
> +       status = "okay";
> +};
> +
> +&uart9 {
> +       status = "okay";
> +};
> +
> +&ufs_mem_hc {
> +       reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
> +       vcc-supply = <&vreg_l20a_2p95>;
> +       vcc-max-microamp = <600000>;
> +       status = "okay";
> +};
> +
> +&ufs_mem_phy {
> +       vdda-phy-supply = <&vdda_ufs1_core>;
> +       vdda-pll-supply = <&vdda_ufs1_1p2>;
> +       status = "okay";
> +};
> +
> +&sdhc_2 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>;
> +       cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
> +       vmmc-supply = <&vreg_l21a_2p95>;
> +       vqmmc-supply = <&vddpx_2>;
> +       status = "okay";
> +};
> +
> +&usb_1 {
> +       status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> +       /* Until we have Type C hooked up we'll force this as peripheral. */
> +       dr_mode = "peripheral";
> +};
> +
> +&usb_1_hsphy {
> +       vdd-supply = <&vdda_usb1_ss_core>;
> +       vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
> +       vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
> +
> +       qcom,imp-res-offset-value = <8>;
> +       qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
> +       qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
> +       qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
> +       status = "okay";
> +};
> +
> +&usb_1_qmpphy {
> +       vdda-phy-supply = <&vdda_usb1_ss_1p2>;
> +       vdda-pll-supply = <&vdda_usb1_ss_core>;
> +       status = "okay";
> +};
> +
> +&wifi {
> +       vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
> +       vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
> +       vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
> +       vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
> +       status = "okay";
> +};
> +
> +&tlmm {
> +       gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
> +
> +       sdc2_clk_state: sdc2-clk-state {
> +               pins = "sdc2_clk";
> +               bias-disable;
> +
> +               /*
> +                * It seems that mmc_test reports errors if drive
> +                * strength is not 16 on clk, cmd, and data pins.
> +                */
> +               drive-strength = <16>;
> +       };
> +
> +       sdc2_cmd_state: sdc2-cmd-state {
> +               pins = "sdc2_cmd";
> +               bias-pull-up;
> +               drive-strength = <16>;
> +       };
> +
> +       sdc2_data_state: sdc2-data-state {
> +               pins = "sdc2_data";
> +               bias-pull-up;
> +               drive-strength = <16>;
> +       };
> +
> +       sd_card_det_n_state: sd-card-det-n-state {
> +               pins = "gpio126";
> +               function = "gpio";
> +               bias-pull-up;
> +       };
> +};
> diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> index 96c9749a52c0..bf5e6eb9d313 100644
> --- a/arch/arm/dts/sdm845.dtsi
> +++ b/arch/arm/dts/sdm845.dtsi
> @@ -1,119 +1,5752 @@
> -// SPDX-License-Identifier: GPL-2.0+
> +// SPDX-License-Identifier: GPL-2.0
>  /*
> - * Qualcomm SDM845 chip device tree source
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> + * SDM845 SoC device tree source
>   *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>   */
>
> -/dts-v1/;
> -
> +#include <dt-bindings/clock/qcom,camcc-sdm845.h>
> +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
>  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> -#include "skeleton64.dtsi"
> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
> +#include <dt-bindings/clock/qcom,lpass-sdm845.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,videocc-sdm845.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/firmware/qcom,scm.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> +#include <dt-bindings/interconnect/qcom,sdm845.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> +#include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
> +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
> +#include <dt-bindings/soc/qcom,apr.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +#include <dt-bindings/thermal/thermal.h>
>
>  / {
> -       soc: soc {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               ranges = <0 0 0 0xffffffff>;
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       aliases {
> +               i2c0 = &i2c0;
> +               i2c1 = &i2c1;
> +               i2c2 = &i2c2;
> +               i2c3 = &i2c3;
> +               i2c4 = &i2c4;
> +               i2c5 = &i2c5;
> +               i2c6 = &i2c6;
> +               i2c7 = &i2c7;
> +               i2c8 = &i2c8;
> +               i2c9 = &i2c9;
> +               i2c10 = &i2c10;
> +               i2c11 = &i2c11;
> +               i2c12 = &i2c12;
> +               i2c13 = &i2c13;
> +               i2c14 = &i2c14;
> +               i2c15 = &i2c15;
> +               spi0 = &spi0;
> +               spi1 = &spi1;
> +               spi2 = &spi2;
> +               spi3 = &spi3;
> +               spi4 = &spi4;
> +               spi5 = &spi5;
> +               spi6 = &spi6;
> +               spi7 = &spi7;
> +               spi8 = &spi8;
> +               spi9 = &spi9;
> +               spi10 = &spi10;
> +               spi11 = &spi11;
> +               spi12 = &spi12;
> +               spi13 = &spi13;
> +               spi14 = &spi14;
> +               spi15 = &spi15;
> +       };
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <38400000>;
> +                       clock-output-names = "xo_board";
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <32764>;
> +               };
> +       };
> +
> +       cpus: cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x0>;
> +                       clocks = <&cpufreq_hw 0>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <611>;
> +                       dynamic-power-coefficient = <154>;
> +                       qcom,freq-domain = <&cpufreq_hw 0>;
> +                       operating-points-v2 = <&cpu0_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD0>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_0>;
> +                       L2_0: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                               L3_0: l3-cache {
> +                                       compatible = "cache";
> +                                       cache-level = <3>;
> +                                       cache-unified;
> +                               };
> +                       };
> +               };
> +
> +               CPU1: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x100>;
> +                       clocks = <&cpufreq_hw 0>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <611>;
> +                       dynamic-power-coefficient = <154>;
> +                       qcom,freq-domain = <&cpufreq_hw 0>;
> +                       operating-points-v2 = <&cpu0_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD1>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_100>;
> +                       L2_100: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU2: cpu@200 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x200>;
> +                       clocks = <&cpufreq_hw 0>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <611>;
> +                       dynamic-power-coefficient = <154>;
> +                       qcom,freq-domain = <&cpufreq_hw 0>;
> +                       operating-points-v2 = <&cpu0_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD2>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_200>;
> +                       L2_200: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU3: cpu@300 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x300>;
> +                       clocks = <&cpufreq_hw 0>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <611>;
> +                       dynamic-power-coefficient = <154>;
> +                       qcom,freq-domain = <&cpufreq_hw 0>;
> +                       operating-points-v2 = <&cpu0_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       #cooling-cells = <2>;
> +                       power-domains = <&CPU_PD3>;
> +                       power-domain-names = "psci";
> +                       next-level-cache = <&L2_300>;
> +                       L2_300: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU4: cpu@400 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x400>;
> +                       clocks = <&cpufreq_hw 1>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <442>;
> +                       qcom,freq-domain = <&cpufreq_hw 1>;
> +                       operating-points-v2 = <&cpu4_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD4>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_400>;
> +                       L2_400: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU5: cpu@500 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x500>;
> +                       clocks = <&cpufreq_hw 1>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <442>;
> +                       qcom,freq-domain = <&cpufreq_hw 1>;
> +                       operating-points-v2 = <&cpu4_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD5>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_500>;
> +                       L2_500: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU6: cpu@600 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x600>;
> +                       clocks = <&cpufreq_hw 1>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <442>;
> +                       qcom,freq-domain = <&cpufreq_hw 1>;
> +                       operating-points-v2 = <&cpu4_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD6>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_600>;
> +                       L2_600: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU7: cpu@700 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo385";
> +                       reg = <0x0 0x700>;
> +                       clocks = <&cpufreq_hw 1>;
> +                       enable-method = "psci";
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <442>;
> +                       qcom,freq-domain = <&cpufreq_hw 1>;
> +                       operating-points-v2 = <&cpu4_opp_table>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
> +                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> +                       power-domains = <&CPU_PD7>;
> +                       power-domain-names = "psci";
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_700>;
> +                       L2_700: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&CPU0>;
> +                               };
> +
> +                               core1 {
> +                                       cpu = <&CPU1>;
> +                               };
> +
> +                               core2 {
> +                                       cpu = <&CPU2>;
> +                               };
> +
> +                               core3 {
> +                                       cpu = <&CPU3>;
> +                               };
> +
> +                               core4 {
> +                                       cpu = <&CPU4>;
> +                               };
> +
> +                               core5 {
> +                                       cpu = <&CPU5>;
> +                               };
> +
> +                               core6 {
> +                                       cpu = <&CPU6>;
> +                               };
> +
> +                               core7 {
> +                                       cpu = <&CPU7>;
> +                               };
> +                       };
> +               };
> +
> +               cpu_idle_states: idle-states {
> +                       entry-method = "psci";
> +
> +                       LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "little-rail-power-collapse";
> +                               arm,psci-suspend-param = <0x40000004>;
> +                               entry-latency-us = <350>;
> +                               exit-latency-us = <461>;
> +                               min-residency-us = <1890>;
> +                               local-timer-stop;
> +                       };
> +
> +                       BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "big-rail-power-collapse";
> +                               arm,psci-suspend-param = <0x40000004>;
> +                               entry-latency-us = <264>;
> +                               exit-latency-us = <621>;
> +                               min-residency-us = <952>;
> +                               local-timer-stop;
> +                       };
> +               };
> +
> +               domain-idle-states {
> +                       CLUSTER_SLEEP_0: cluster-sleep-0 {
> +                               compatible = "domain-idle-state";
> +                               arm,psci-suspend-param = <0x4100c244>;
> +                               entry-latency-us = <3263>;
> +                               exit-latency-us = <6562>;
> +                               min-residency-us = <9987>;
> +                       };
> +               };
> +       };
> +
> +       firmware {
> +               scm {
> +                       compatible = "qcom,scm-sdm845", "qcom,scm";
> +               };
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the size */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       cpu0_opp_table: opp-table-cpu0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               cpu0_opp1: opp-300000000 {
> +                       opp-hz = /bits/ 64 <300000000>;
> +                       opp-peak-kBps = <800000 4800000>;
> +               };
> +
> +               cpu0_opp2: opp-403200000 {
> +                       opp-hz = /bits/ 64 <403200000>;
> +                       opp-peak-kBps = <800000 4800000>;
> +               };
> +
> +               cpu0_opp3: opp-480000000 {
> +                       opp-hz = /bits/ 64 <480000000>;
> +                       opp-peak-kBps = <800000 6451200>;
> +               };
> +
> +               cpu0_opp4: opp-576000000 {
> +                       opp-hz = /bits/ 64 <576000000>;
> +                       opp-peak-kBps = <800000 6451200>;
> +               };
> +
> +               cpu0_opp5: opp-652800000 {
> +                       opp-hz = /bits/ 64 <652800000>;
> +                       opp-peak-kBps = <800000 7680000>;
> +               };
> +
> +               cpu0_opp6: opp-748800000 {
> +                       opp-hz = /bits/ 64 <748800000>;
> +                       opp-peak-kBps = <1804000 9216000>;
> +               };
> +
> +               cpu0_opp7: opp-825600000 {
> +                       opp-hz = /bits/ 64 <825600000>;
> +                       opp-peak-kBps = <1804000 9216000>;
> +               };
> +
> +               cpu0_opp8: opp-902400000 {
> +                       opp-hz = /bits/ 64 <902400000>;
> +                       opp-peak-kBps = <1804000 10444800>;
> +               };
> +
> +               cpu0_opp9: opp-979200000 {
> +                       opp-hz = /bits/ 64 <979200000>;
> +                       opp-peak-kBps = <1804000 11980800>;
> +               };
> +
> +               cpu0_opp10: opp-1056000000 {
> +                       opp-hz = /bits/ 64 <1056000000>;
> +                       opp-peak-kBps = <1804000 11980800>;
> +               };
> +
> +               cpu0_opp11: opp-1132800000 {
> +                       opp-hz = /bits/ 64 <1132800000>;
> +                       opp-peak-kBps = <2188000 13516800>;
> +               };
> +
> +               cpu0_opp12: opp-1228800000 {
> +                       opp-hz = /bits/ 64 <1228800000>;
> +                       opp-peak-kBps = <2188000 15052800>;
> +               };
> +
> +               cpu0_opp13: opp-1324800000 {
> +                       opp-hz = /bits/ 64 <1324800000>;
> +                       opp-peak-kBps = <2188000 16588800>;
> +               };
> +
> +               cpu0_opp14: opp-1420800000 {
> +                       opp-hz = /bits/ 64 <1420800000>;
> +                       opp-peak-kBps = <3072000 18124800>;
> +               };
> +
> +               cpu0_opp15: opp-1516800000 {
> +                       opp-hz = /bits/ 64 <1516800000>;
> +                       opp-peak-kBps = <3072000 19353600>;
> +               };
> +
> +               cpu0_opp16: opp-1612800000 {
> +                       opp-hz = /bits/ 64 <1612800000>;
> +                       opp-peak-kBps = <4068000 19353600>;
> +               };
> +
> +               cpu0_opp17: opp-1689600000 {
> +                       opp-hz = /bits/ 64 <1689600000>;
> +                       opp-peak-kBps = <4068000 20889600>;
> +               };
> +
> +               cpu0_opp18: opp-1766400000 {
> +                       opp-hz = /bits/ 64 <1766400000>;
> +                       opp-peak-kBps = <4068000 22425600>;
> +               };
> +       };
> +
> +       cpu4_opp_table: opp-table-cpu4 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               cpu4_opp1: opp-300000000 {
> +                       opp-hz = /bits/ 64 <300000000>;
> +                       opp-peak-kBps = <800000 4800000>;
> +               };
> +
> +               cpu4_opp2: opp-403200000 {
> +                       opp-hz = /bits/ 64 <403200000>;
> +                       opp-peak-kBps = <800000 4800000>;
> +               };
> +
> +               cpu4_opp3: opp-480000000 {
> +                       opp-hz = /bits/ 64 <480000000>;
> +                       opp-peak-kBps = <1804000 4800000>;
> +               };
> +
> +               cpu4_opp4: opp-576000000 {
> +                       opp-hz = /bits/ 64 <576000000>;
> +                       opp-peak-kBps = <1804000 4800000>;
> +               };
> +
> +               cpu4_opp5: opp-652800000 {
> +                       opp-hz = /bits/ 64 <652800000>;
> +                       opp-peak-kBps = <1804000 4800000>;
> +               };
> +
> +               cpu4_opp6: opp-748800000 {
> +                       opp-hz = /bits/ 64 <748800000>;
> +                       opp-peak-kBps = <1804000 4800000>;
> +               };
> +
> +               cpu4_opp7: opp-825600000 {
> +                       opp-hz = /bits/ 64 <825600000>;
> +                       opp-peak-kBps = <2188000 9216000>;
> +               };
> +
> +               cpu4_opp8: opp-902400000 {
> +                       opp-hz = /bits/ 64 <902400000>;
> +                       opp-peak-kBps = <2188000 9216000>;
> +               };
> +
> +               cpu4_opp9: opp-979200000 {
> +                       opp-hz = /bits/ 64 <979200000>;
> +                       opp-peak-kBps = <2188000 9216000>;
> +               };
> +
> +               cpu4_opp10: opp-1056000000 {
> +                       opp-hz = /bits/ 64 <1056000000>;
> +                       opp-peak-kBps = <3072000 9216000>;
> +               };
> +
> +               cpu4_opp11: opp-1132800000 {
> +                       opp-hz = /bits/ 64 <1132800000>;
> +                       opp-peak-kBps = <3072000 11980800>;
> +               };
> +
> +               cpu4_opp12: opp-1209600000 {
> +                       opp-hz = /bits/ 64 <1209600000>;
> +                       opp-peak-kBps = <4068000 11980800>;
> +               };
> +
> +               cpu4_opp13: opp-1286400000 {
> +                       opp-hz = /bits/ 64 <1286400000>;
> +                       opp-peak-kBps = <4068000 11980800>;
> +               };
> +
> +               cpu4_opp14: opp-1363200000 {
> +                       opp-hz = /bits/ 64 <1363200000>;
> +                       opp-peak-kBps = <4068000 15052800>;
> +               };
> +
> +               cpu4_opp15: opp-1459200000 {
> +                       opp-hz = /bits/ 64 <1459200000>;
> +                       opp-peak-kBps = <4068000 15052800>;
> +               };
> +
> +               cpu4_opp16: opp-1536000000 {
> +                       opp-hz = /bits/ 64 <1536000000>;
> +                       opp-peak-kBps = <5412000 15052800>;
> +               };
> +
> +               cpu4_opp17: opp-1612800000 {
> +                       opp-hz = /bits/ 64 <1612800000>;
> +                       opp-peak-kBps = <5412000 15052800>;
> +               };
> +
> +               cpu4_opp18: opp-1689600000 {
> +                       opp-hz = /bits/ 64 <1689600000>;
> +                       opp-peak-kBps = <5412000 19353600>;
> +               };
> +
> +               cpu4_opp19: opp-1766400000 {
> +                       opp-hz = /bits/ 64 <1766400000>;
> +                       opp-peak-kBps = <6220000 19353600>;
> +               };
> +
> +               cpu4_opp20: opp-1843200000 {
> +                       opp-hz = /bits/ 64 <1843200000>;
> +                       opp-peak-kBps = <6220000 19353600>;
> +               };
> +
> +               cpu4_opp21: opp-1920000000 {
> +                       opp-hz = /bits/ 64 <1920000000>;
> +                       opp-peak-kBps = <7216000 19353600>;
> +               };
> +
> +               cpu4_opp22: opp-1996800000 {
> +                       opp-hz = /bits/ 64 <1996800000>;
> +                       opp-peak-kBps = <7216000 20889600>;
> +               };
> +
> +               cpu4_opp23: opp-2092800000 {
> +                       opp-hz = /bits/ 64 <2092800000>;
> +                       opp-peak-kBps = <7216000 20889600>;
> +               };
> +
> +               cpu4_opp24: opp-2169600000 {
> +                       opp-hz = /bits/ 64 <2169600000>;
> +                       opp-peak-kBps = <7216000 20889600>;
> +               };
> +
> +               cpu4_opp25: opp-2246400000 {
> +                       opp-hz = /bits/ 64 <2246400000>;
> +                       opp-peak-kBps = <7216000 20889600>;
> +               };
> +
> +               cpu4_opp26: opp-2323200000 {
> +                       opp-hz = /bits/ 64 <2323200000>;
> +                       opp-peak-kBps = <7216000 20889600>;
> +               };
> +
> +               cpu4_opp27: opp-2400000000 {
> +                       opp-hz = /bits/ 64 <2400000000>;
> +                       opp-peak-kBps = <7216000 22425600>;
> +               };
> +
> +               cpu4_opp28: opp-2476800000 {
> +                       opp-hz = /bits/ 64 <2476800000>;
> +                       opp-peak-kBps = <7216000 22425600>;
> +               };
> +
> +               cpu4_opp29: opp-2553600000 {
> +                       opp-hz = /bits/ 64 <2553600000>;
> +                       opp-peak-kBps = <7216000 22425600>;
> +               };
> +
> +               cpu4_opp30: opp-2649600000 {
> +                       opp-hz = /bits/ 64 <2649600000>;
> +                       opp-peak-kBps = <7216000 22425600>;
> +               };
> +
> +               cpu4_opp31: opp-2745600000 {
> +                       opp-hz = /bits/ 64 <2745600000>;
> +                       opp-peak-kBps = <7216000 25497600>;
> +               };
> +
> +               cpu4_opp32: opp-2803200000 {
> +                       opp-hz = /bits/ 64 <2803200000>;
> +                       opp-peak-kBps = <7216000 25497600>;
> +               };
> +       };
> +
> +       dsi_opp_table: opp-table-dsi {
> +               compatible = "operating-points-v2";
> +
> +               opp-19200000 {
> +                       opp-hz = /bits/ 64 <19200000>;
> +                       required-opps = <&rpmhpd_opp_min_svs>;
> +               };
> +
> +               opp-180000000 {
> +                       opp-hz = /bits/ 64 <180000000>;
> +                       required-opps = <&rpmhpd_opp_low_svs>;
> +               };
> +
> +               opp-275000000 {
> +                       opp-hz = /bits/ 64 <275000000>;
> +                       required-opps = <&rpmhpd_opp_svs>;
> +               };
> +
> +               opp-328580000 {
> +                       opp-hz = /bits/ 64 <328580000>;
> +                       required-opps = <&rpmhpd_opp_svs_l1>;
> +               };
> +
> +               opp-358000000 {
> +                       opp-hz = /bits/ 64 <358000000>;
> +                       required-opps = <&rpmhpd_opp_nom>;
> +               };
> +       };
> +
> +       qspi_opp_table: opp-table-qspi {
> +               compatible = "operating-points-v2";
> +
> +               opp-19200000 {
> +                       opp-hz = /bits/ 64 <19200000>;
> +                       required-opps = <&rpmhpd_opp_min_svs>;
> +               };
> +
> +               opp-100000000 {
> +                       opp-hz = /bits/ 64 <100000000>;
> +                       required-opps = <&rpmhpd_opp_low_svs>;
> +               };
> +
> +               opp-150000000 {
> +                       opp-hz = /bits/ 64 <150000000>;
> +                       required-opps = <&rpmhpd_opp_svs>;
> +               };
> +
> +               opp-300000000 {
> +                       opp-hz = /bits/ 64 <300000000>;
> +                       required-opps = <&rpmhpd_opp_nom>;
> +               };
> +       };
> +
> +       qup_opp_table: opp-table-qup {
> +               compatible = "operating-points-v2";
> +
> +               opp-50000000 {
> +                       opp-hz = /bits/ 64 <50000000>;
> +                       required-opps = <&rpmhpd_opp_min_svs>;
> +               };
> +
> +               opp-75000000 {
> +                       opp-hz = /bits/ 64 <75000000>;
> +                       required-opps = <&rpmhpd_opp_low_svs>;
> +               };
> +
> +               opp-100000000 {
> +                       opp-hz = /bits/ 64 <100000000>;
> +                       required-opps = <&rpmhpd_opp_svs>;
> +               };
> +
> +               opp-128000000 {
> +                       opp-hz = /bits/ 64 <128000000>;
> +                       required-opps = <&rpmhpd_opp_nom>;
> +               };
> +       };
> +
> +       pmu {
> +               compatible = "arm,armv8-pmuv3";
> +               interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       psci: psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +
> +               CPU_PD0: power-domain-cpu0 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD1: power-domain-cpu1 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD2: power-domain-cpu2 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD3: power-domain-cpu3 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD4: power-domain-cpu4 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD5: power-domain-cpu5 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD6: power-domain-cpu6 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD7: power-domain-cpu7 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
> +               };
> +
> +               CLUSTER_PD: power-domain-cluster {
> +                       #power-domain-cells = <0>;
> +                       domain-idle-states = <&CLUSTER_SLEEP_0>;
> +               };
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               hyp_mem: hyp-mem@85700000 {
> +                       reg = <0 0x85700000 0 0x600000>;
> +                       no-map;
> +               };
> +
> +               xbl_mem: xbl-mem@85e00000 {
> +                       reg = <0 0x85e00000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               aop_mem: aop-mem@85fc0000 {
> +                       reg = <0 0x85fc0000 0 0x20000>;
> +                       no-map;
> +               };
> +
> +               aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
> +                       compatible = "qcom,cmd-db";
> +                       reg = <0x0 0x85fe0000 0 0x20000>;
> +                       no-map;
> +               };
> +
> +               smem@86000000 {
> +                       compatible = "qcom,smem";
> +                       reg = <0x0 0x86000000 0 0x200000>;
> +                       no-map;
> +                       hwlocks = <&tcsr_mutex 3>;
> +               };
> +
> +               tz_mem: tz@86200000 {
> +                       reg = <0 0x86200000 0 0x2d00000>;
> +                       no-map;
> +               };
> +
> +               rmtfs_mem: rmtfs@88f00000 {
> +                       compatible = "qcom,rmtfs-mem";
> +                       reg = <0 0x88f00000 0 0x200000>;
> +                       no-map;
> +
> +                       qcom,client-id = <1>;
> +                       qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
> +               };
> +
> +               qseecom_mem: qseecom@8ab00000 {
> +                       reg = <0 0x8ab00000 0 0x1400000>;
> +                       no-map;
> +               };
> +
> +               camera_mem: camera-mem@8bf00000 {
> +                       reg = <0 0x8bf00000 0 0x500000>;
> +                       no-map;
> +               };
> +
> +               ipa_fw_mem: ipa-fw@8c400000 {
> +                       reg = <0 0x8c400000 0 0x10000>;
> +                       no-map;
> +               };
> +
> +               ipa_gsi_mem: ipa-gsi@8c410000 {
> +                       reg = <0 0x8c410000 0 0x5000>;
> +                       no-map;
> +               };
> +
> +               gpu_mem: gpu@8c415000 {
> +                       reg = <0 0x8c415000 0 0x2000>;
> +                       no-map;
> +               };
> +
> +               adsp_mem: adsp@8c500000 {
> +                       reg = <0 0x8c500000 0 0x1a00000>;
> +                       no-map;
> +               };
> +
> +               wlan_msa_mem: wlan-msa@8df00000 {
> +                       reg = <0 0x8df00000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               mpss_region: mpss@8e000000 {
> +                       reg = <0 0x8e000000 0 0x7800000>;
> +                       no-map;
> +               };
> +
> +               venus_mem: venus@95800000 {
> +                       reg = <0 0x95800000 0 0x500000>;
> +                       no-map;
> +               };
> +
> +               cdsp_mem: cdsp@95d00000 {
> +                       reg = <0 0x95d00000 0 0x800000>;
> +                       no-map;
> +               };
> +
> +               mba_region: mba@96500000 {
> +                       reg = <0 0x96500000 0 0x200000>;
> +                       no-map;
> +               };
> +
> +               slpi_mem: slpi@96700000 {
> +                       reg = <0 0x96700000 0 0x1400000>;
> +                       no-map;
> +               };
> +
> +               spss_mem: spss@97b00000 {
> +                       reg = <0 0x97b00000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               mdata_mem: mpss-metadata {
> +                       alloc-ranges = <0 0xa0000000 0 0x20000000>;
> +                       size = <0 0x4000>;
> +                       no-map;
> +               };
> +
> +               fastrpc_mem: fastrpc {
> +                       compatible = "shared-dma-pool";
> +                       alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
> +                       alignment = <0x0 0x400000>;
> +                       size = <0x0 0x1000000>;
> +                       reusable;
> +               };
> +       };
> +
> +       adsp_pas: remoteproc-adsp {
> +               compatible = "qcom,sdm845-adsp-pas";
> +
> +               interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +               interrupt-names = "wdog", "fatal", "ready",
> +                                 "handover", "stop-ack";
> +
> +               clocks = <&rpmhcc RPMH_CXO_CLK>;
> +               clock-names = "xo";
> +
> +               memory-region = <&adsp_mem>;
> +
> +               qcom,qmp = <&aoss_qmp>;
> +
> +               qcom,smem-states = <&adsp_smp2p_out 0>;
> +               qcom,smem-state-names = "stop";
> +
> +               status = "disabled";
> +
> +               glink-edge {
> +                       interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
> +                       label = "lpass";
> +                       qcom,remote-pid = <2>;
> +                       mboxes = <&apss_shared 8>;
> +
> +                       apr {
> +                               compatible = "qcom,apr-v2";
> +                               qcom,glink-channels = "apr_audio_svc";
> +                               qcom,domain = <APR_DOMAIN_ADSP>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               qcom,intents = <512 20>;
> +
> +                               service@3 {
> +                                       reg = <APR_SVC_ADSP_CORE>;
> +                                       compatible = "qcom,q6core";
> +                                       qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
> +                               };
> +
> +                               q6afe: service@4 {
> +                                       compatible = "qcom,q6afe";
> +                                       reg = <APR_SVC_AFE>;
> +                                       qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
> +                                       q6afedai: dais {
> +                                               compatible = "qcom,q6afe-dais";
> +                                               #address-cells = <1>;
> +                                               #size-cells = <0>;
> +                                               #sound-dai-cells = <1>;
> +                                       };
> +                               };
> +
> +                               q6asm: service@7 {
> +                                       compatible = "qcom,q6asm";
> +                                       reg = <APR_SVC_ASM>;
> +                                       qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
> +                                       q6asmdai: dais {
> +                                               compatible = "qcom,q6asm-dais";
> +                                               #address-cells = <1>;
> +                                               #size-cells = <0>;
> +                                               #sound-dai-cells = <1>;
> +                                               iommus = <&apps_smmu 0x1821 0x0>;
> +                                       };
> +                               };
> +
> +                               q6adm: service@8 {
> +                                       compatible = "qcom,q6adm";
> +                                       reg = <APR_SVC_ADM>;
> +                                       qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
> +                                       q6routing: routing {
> +                                               compatible = "qcom,q6adm-routing";
> +                                               #sound-dai-cells = <0>;
> +                                       };
> +                               };
> +                       };
> +
> +                       fastrpc {
> +                               compatible = "qcom,fastrpc";
> +                               qcom,glink-channels = "fastrpcglink-apps-dsp";
> +                               label = "adsp";
> +                               qcom,non-secure-domain;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               compute-cb@3 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <3>;
> +                                       iommus = <&apps_smmu 0x1823 0x0>;
> +                               };
> +
> +                               compute-cb@4 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <4>;
> +                                       iommus = <&apps_smmu 0x1824 0x0>;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       cdsp_pas: remoteproc-cdsp {
> +               compatible = "qcom,sdm845-cdsp-pas";
> +
> +               interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
> +                                     <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                     <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                     <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                     <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +               interrupt-names = "wdog", "fatal", "ready",
> +                                 "handover", "stop-ack";
> +
> +               clocks = <&rpmhcc RPMH_CXO_CLK>;
> +               clock-names = "xo";
> +
> +               memory-region = <&cdsp_mem>;
> +
> +               qcom,qmp = <&aoss_qmp>;
> +
> +               qcom,smem-states = <&cdsp_smp2p_out 0>;
> +               qcom,smem-state-names = "stop";
> +
> +               status = "disabled";
> +
> +               glink-edge {
> +                       interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
> +                       label = "turing";
> +                       qcom,remote-pid = <5>;
> +                       mboxes = <&apss_shared 4>;
> +                       fastrpc {
> +                               compatible = "qcom,fastrpc";
> +                               qcom,glink-channels = "fastrpcglink-apps-dsp";
> +                               label = "cdsp";
> +                               qcom,non-secure-domain;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               compute-cb@1 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <1>;
> +                                       iommus = <&apps_smmu 0x1401 0x30>;
> +                               };
> +
> +                               compute-cb@2 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <2>;
> +                                       iommus = <&apps_smmu 0x1402 0x30>;
> +                               };
> +
> +                               compute-cb@3 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <3>;
> +                                       iommus = <&apps_smmu 0x1403 0x30>;
> +                               };
> +
> +                               compute-cb@4 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <4>;
> +                                       iommus = <&apps_smmu 0x1404 0x30>;
> +                               };
> +
> +                               compute-cb@5 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <5>;
> +                                       iommus = <&apps_smmu 0x1405 0x30>;
> +                               };
> +
> +                               compute-cb@6 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <6>;
> +                                       iommus = <&apps_smmu 0x1406 0x30>;
> +                               };
> +
> +                               compute-cb@7 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <7>;
> +                                       iommus = <&apps_smmu 0x1407 0x30>;
> +                               };
> +
> +                               compute-cb@8 {
> +                                       compatible = "qcom,fastrpc-compute-cb";
> +                                       reg = <8>;
> +                                       iommus = <&apps_smmu 0x1408 0x30>;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       smp2p-cdsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <94>, <432>;
> +
> +               interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
> +
> +               mboxes = <&apss_shared 6>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <5>;
> +
> +               cdsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               cdsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-lpass {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <443>, <429>;
> +
> +               interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
> +
> +               mboxes = <&apss_shared 10>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <2>;
> +
> +               adsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               adsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-mpss {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <435>, <428>;
> +               interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&apss_shared 14>;
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <1>;
> +
> +               modem_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               modem_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               ipa_smp2p_out: ipa-ap-to-modem {
> +                       qcom,entry-name = "ipa";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               ipa_smp2p_in: ipa-modem-to-ap {
> +                       qcom,entry-name = "ipa";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-slpi {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <481>, <430>;
> +               interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&apss_shared 26>;
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <3>;
> +
> +               slpi_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               slpi_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       soc: soc@0 {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges = <0 0 0 0 0x10 0>;
> +               dma-ranges = <0 0 0 0 0x10 0>;
>                 compatible = "simple-bus";
>
>                 gcc: clock-controller@100000 {
>                         compatible = "qcom,gcc-sdm845";
> -                       reg = <0x100000 0x1f0000>;
> +                       reg = <0 0x00100000 0 0x1f0000>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK_A>,
> +                                <&sleep_clk>,
> +                                <&pcie0_phy>,
> +                                <&pcie1_phy>;
> +                       clock-names = "bi_tcxo",
> +                                     "bi_tcxo_ao",
> +                                     "sleep_clk",
> +                                     "pcie_0_pipe_clk",
> +                                     "pcie_1_pipe_clk";
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       power-domains = <&rpmhpd SDM845_CX>;
> +               };
> +
> +               qfprom@784000 {
> +                       compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
> +                       reg = <0 0x00784000 0 0x8ff>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       qusb2p_hstx_trim: hstx-trim-primary@1eb {
> +                               reg = <0x1eb 0x1>;
> +                               bits = <1 4>;
> +                       };
> +
> +                       qusb2s_hstx_trim: hstx-trim-secondary@1eb {
> +                               reg = <0x1eb 0x2>;
> +                               bits = <6 4>;
> +                       };
> +               };
> +
> +               rng: rng@793000 {
> +                       compatible = "qcom,prng-ee";
> +                       reg = <0 0x00793000 0 0x1000>;
> +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
> +                       clock-names = "core";
> +               };
> +
> +               gpi_dma0: dma-controller@800000 {
> +                       #dma-cells = <3>;
> +                       compatible = "qcom,sdm845-gpi-dma";
> +                       reg = <0 0x00800000 0 0x60000>;
> +                       interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> +                       dma-channels = <13>;
> +                       dma-channel-mask = <0xfa>;
> +                       iommus = <&apps_smmu 0x0016 0x0>;
> +                       status = "disabled";
> +               };
> +
> +               qupv3_id_0: geniqup@8c0000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0 0x008c0000 0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +                       iommus = <&apps_smmu 0x3 0x0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
> +                       interconnect-names = "qup-core";
> +                       status = "disabled";
> +
> +                       i2c0: i2c@880000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00880000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c0_default>;
> +                               interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi0: spi@880000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00880000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi0_default>;
> +                               interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart0: serial@880000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00880000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart0_default>;
> +                               interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c1: i2c@884000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00884000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c1_default>;
> +                               interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi1: spi@884000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00884000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi1_default>;
> +                               interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 1 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart1: serial@884000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00884000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart1_default>;
> +                               interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c2: i2c@888000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00888000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c2_default>;
> +                               interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi2: spi@888000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00888000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi2_default>;
> +                               interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 2 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart2: serial@888000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00888000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart2_default>;
> +                               interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c3: i2c@88c000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x0088c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c3_default>;
> +                               interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi3: spi@88c000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x0088c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi3_default>;
> +                               interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 3 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart3: serial@88c000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x0088c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart3_default>;
> +                               interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c4: i2c@890000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00890000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c4_default>;
> +                               interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi4: spi@890000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00890000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi4_default>;
> +                               interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 4 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart4: serial@890000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00890000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart4_default>;
> +                               interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c5: i2c@894000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00894000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c5_default>;
> +                               interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 5 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi5: spi@894000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00894000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi5_default>;
> +                               interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 5 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart5: serial@894000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00894000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart5_default>;
> +                               interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c6: i2c@898000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00898000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c6_default>;
> +                               interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
> +                                      <&gpi_dma0 1 6 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi6: spi@898000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00898000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi6_default>;
> +                               interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 6 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart6: serial@898000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00898000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart6_default>;
> +                               interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c7: i2c@89c000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x0089c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c7_default>;
> +                               interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               status = "disabled";
> +                       };
> +
> +                       spi7: spi@89c000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x0089c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi7_default>;
> +                               interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
> +                                      <&gpi_dma0 1 7 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart7: serial@89c000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x0089c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart7_default>;
> +                               interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               gpi_dma1: dma-controller@a00000 {
> +                       #dma-cells = <3>;
> +                       compatible = "qcom,sdm845-gpi-dma";
> +                       reg = <0 0x00a00000 0 0x60000>;
> +                       interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> +                       dma-channels = <13>;
> +                       dma-channel-mask = <0xfa>;
> +                       iommus = <&apps_smmu 0x06d6 0x0>;
> +                       status = "disabled";
> +               };
> +
> +               qupv3_id_1: geniqup@ac0000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0 0x00ac0000 0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +                       iommus = <&apps_smmu 0x6c3 0x0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
> +                       interconnect-names = "qup-core";
> +                       status = "disabled";
> +
> +                       i2c8: i2c@a80000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a80000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c8_default>;
> +                               interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi8: spi@a80000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a80000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi8_default>;
> +                               interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 0 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart8: serial@a80000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a80000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart8_default>;
> +                               interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c9: i2c@a84000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a84000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c9_default>;
> +                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi9: spi@a84000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a84000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi9_default>;
> +                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 1 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart9: serial@a84000 {
> +                               compatible = "qcom,geni-debug-uart";
> +                               reg = <0 0x00a84000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart9_default>;
> +                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c10: i2c@a88000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c10_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi10: spi@a88000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi10_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 2 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart10: serial@a88000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart10_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c11: i2c@a8c000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a8c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c11_default>;
> +                               interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi11: spi@a8c000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a8c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi11_default>;
> +                               interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 3 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart11: serial@a8c000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a8c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart11_default>;
> +                               interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c12: i2c@a90000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a90000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c12_default>;
> +                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi12: spi@a90000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a90000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi12_default>;
> +                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 4 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart12: serial@a90000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a90000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart12_default>;
> +                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c13: i2c@a94000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a94000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c13_default>;
> +                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 5 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi13: spi@a94000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a94000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi13_default>;
> +                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 5 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart13: serial@a94000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a94000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart13_default>;
> +                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c14: i2c@a98000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a98000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c14_default>;
> +                               interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 6 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       spi14: spi@a98000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a98000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi14_default>;
> +                               interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 6 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart14: serial@a98000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a98000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart14_default>;
> +                               interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +
> +                       i2c15: i2c@a9c000 {
> +                               compatible = "qcom,geni-i2c";
> +                               reg = <0 0x00a9c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_i2c15_default>;
> +                               interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               status = "disabled";
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
> +                               interconnect-names = "qup-core", "qup-config", "qup-memory";
> +                               dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
> +                                      <&gpi_dma1 1 7 QCOM_GPI_I2C>;
> +                               dma-names = "tx", "rx";
> +                       };
> +
> +                       spi15: spi@a9c000 {
> +                               compatible = "qcom,geni-spi";
> +                               reg = <0 0x00a9c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_spi15_default>;
> +                               interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
> +                                      <&gpi_dma1 1 7 QCOM_GPI_SPI>;
> +                               dma-names = "tx", "rx";
> +                               status = "disabled";
> +                       };
> +
> +                       uart15: serial@a9c000 {
> +                               compatible = "qcom,geni-uart";
> +                               reg = <0 0x00a9c000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart15_default>;
> +                               interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +                               operating-points-v2 = <&qup_opp_table>;
> +                               interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
> +                                               <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
> +                               interconnect-names = "qup-core", "qup-config";
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               llcc: system-cache-controller@1100000 {
> +                       compatible = "qcom,sdm845-llcc";
> +                       reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
> +                             <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
> +                             <0 0x01300000 0 0x50000>;
> +                       reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
> +                                   "llcc3_base", "llcc_broadcast_base";
> +                       interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               dma@10a2000 {
> +                       compatible = "qcom,sdm845-dcc", "qcom,dcc";
> +                       reg = <0x0 0x010a2000 0x0 0x1000>,
> +                             <0x0 0x010ae000 0x0 0x2000>;
> +               };
> +
> +               pmu@114a000 {
> +                       compatible = "qcom,sdm845-llcc-bwmon";
> +                       reg = <0 0x0114a000 0 0x1000>;
> +                       interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
> +                       interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
> +
> +                       operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +                       llcc_bwmon_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               /*
> +                                * The interconnect path bandwidth taken from
> +                                * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
> +                                * interconnect.  This also matches the
> +                                * bandwidth table of qcom,llccbw (qcom,bw-tbl,
> +                                * bus width: 4 bytes) from msm-4.9 downstream
> +                                * kernel.
> +                                */
> +                               opp-0 {
> +                                       opp-peak-kBps = <800000>;
> +                               };
> +                               opp-1 {
> +                                       opp-peak-kBps = <1804000>;
> +                               };
> +                               opp-2 {
> +                                       opp-peak-kBps = <3072000>;
> +                               };
> +                               opp-3 {
> +                                       opp-peak-kBps = <5412000>;
> +                               };
> +                               opp-4 {
> +                                       opp-peak-kBps = <7216000>;
> +                               };
> +                       };
> +               };
> +
> +               pmu@1436400 {
> +                       compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
> +                       reg = <0 0x01436400 0 0x600>;
> +                       interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +                       interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
> +
> +                       operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> +                       cpu_bwmon_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               /*
> +                                * The interconnect path bandwidth taken from
> +                                * cpu4_opp_table bandwidth for OSM L3
> +                                * interconnect.  This also matches the OSM L3
> +                                * from bandwidth table of qcom,cpu4-l3lat-mon
> +                                * (qcom,core-dev-table, bus width: 16 bytes)
> +                                * from msm-4.9 downstream kernel.
> +                                */
> +                               opp-0 {
> +                                       opp-peak-kBps = <4800000>;
> +                               };
> +                               opp-1 {
> +                                       opp-peak-kBps = <9216000>;
> +                               };
> +                               opp-2 {
> +                                       opp-peak-kBps = <15052800>;
> +                               };
> +                               opp-3 {
> +                                       opp-peak-kBps = <20889600>;
> +                               };
> +                               opp-4 {
> +                                       opp-peak-kBps = <25497600>;
> +                               };
> +                       };
> +               };
> +
> +               pcie0: pci@1c00000 {
> +                       compatible = "qcom,pcie-sdm845";
> +                       reg = <0 0x01c00000 0 0x2000>,
> +                             <0 0x60000000 0 0xf1d>,
> +                             <0 0x60000f20 0 0xa8>,
> +                             <0 0x60100000 0 0x100000>,
> +                             <0 0x01c07000 0 0x1000>;
> +                       reg-names = "parf", "dbi", "elbi", "config", "mhi";
> +                       device_type = "pci";
> +                       linux,pci-domain = <0>;
> +                       bus-range = <0x00 0xff>;
> +                       num-lanes = <1>;
> +
> +                       #address-cells = <3>;
> +                       #size-cells = <2>;
> +
> +                       ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> +                                <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
> +
> +                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "msi";
> +                       #interrupt-cells = <1>;
> +                       interrupt-map-mask = <0 0 0 0x7>;
> +                       interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                       <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                       <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                       <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> +                                <&gcc GCC_PCIE_0_AUX_CLK>,
> +                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> +                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> +                       clock-names = "pipe",
> +                                     "aux",
> +                                     "cfg",
> +                                     "bus_master",
> +                                     "bus_slave",
> +                                     "slave_q2a",
> +                                     "tbu";
> +
> +                       iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
> +                                   <0x100 &apps_smmu 0x1c11 0x1>,
> +                                   <0x200 &apps_smmu 0x1c12 0x1>,
> +                                   <0x300 &apps_smmu 0x1c13 0x1>,
> +                                   <0x400 &apps_smmu 0x1c14 0x1>,
> +                                   <0x500 &apps_smmu 0x1c15 0x1>,
> +                                   <0x600 &apps_smmu 0x1c16 0x1>,
> +                                   <0x700 &apps_smmu 0x1c17 0x1>,
> +                                   <0x800 &apps_smmu 0x1c18 0x1>,
> +                                   <0x900 &apps_smmu 0x1c19 0x1>,
> +                                   <0xa00 &apps_smmu 0x1c1a 0x1>,
> +                                   <0xb00 &apps_smmu 0x1c1b 0x1>,
> +                                   <0xc00 &apps_smmu 0x1c1c 0x1>,
> +                                   <0xd00 &apps_smmu 0x1c1d 0x1>,
> +                                   <0xe00 &apps_smmu 0x1c1e 0x1>,
> +                                   <0xf00 &apps_smmu 0x1c1f 0x1>;
> +
> +                       resets = <&gcc GCC_PCIE_0_BCR>;
> +                       reset-names = "pci";
> +
> +                       power-domains = <&gcc PCIE_0_GDSC>;
> +
> +                       phys = <&pcie0_phy>;
> +                       phy-names = "pciephy";
> +
> +                       status = "disabled";
> +               };
> +
> +               pcie0_phy: phy@1c06000 {
> +                       compatible = "qcom,sdm845-qmp-pcie-phy";
> +                       reg = <0 0x01c06000 0 0x1000>;
> +                       clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                                <&gcc GCC_PCIE_0_CLKREF_CLK>,
> +                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
> +                                <&gcc GCC_PCIE_0_PIPE_CLK>;
> +                       clock-names = "aux",
> +                                     "cfg_ahb",
> +                                     "ref",
> +                                     "refgen",
> +                                     "pipe";
> +
> +                       clock-output-names = "pcie_0_pipe_clk";
> +                       #clock-cells = <0>;
> +
> +                       #phy-cells = <0>;
> +
> +                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> +                       reset-names = "phy";
> +
> +                       assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
> +                       assigned-clock-rates = <100000000>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pcie1: pci@1c08000 {
> +                       compatible = "qcom,pcie-sdm845";
> +                       reg = <0 0x01c08000 0 0x2000>,
> +                             <0 0x40000000 0 0xf1d>,
> +                             <0 0x40000f20 0 0xa8>,
> +                             <0 0x40100000 0 0x100000>,
> +                             <0 0x01c0c000 0 0x1000>;
> +                       reg-names = "parf", "dbi", "elbi", "config", "mhi";
> +                       device_type = "pci";
> +                       linux,pci-domain = <1>;
> +                       bus-range = <0x00 0xff>;
> +                       num-lanes = <1>;
> +
> +                       #address-cells = <3>;
> +                       #size-cells = <2>;
> +
> +                       ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> +                                <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> +                       interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "msi";
> +                       #interrupt-cells = <1>;
> +                       interrupt-map-mask = <0 0 0 0x7>;
> +                       interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                       <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                       <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                       <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +                       clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> +                                <&gcc GCC_PCIE_1_AUX_CLK>,
> +                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +                                <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> +                                <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> +                                <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> +                                <&gcc GCC_PCIE_1_CLKREF_CLK>,
> +                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> +                       clock-names = "pipe",
> +                                     "aux",
> +                                     "cfg",
> +                                     "bus_master",
> +                                     "bus_slave",
> +                                     "slave_q2a",
> +                                     "ref",
> +                                     "tbu";
> +
> +                       assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> +                       assigned-clock-rates = <19200000>;
> +
> +                       iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
> +                                   <0x100 &apps_smmu 0x1c01 0x1>,
> +                                   <0x200 &apps_smmu 0x1c02 0x1>,
> +                                   <0x300 &apps_smmu 0x1c03 0x1>,
> +                                   <0x400 &apps_smmu 0x1c04 0x1>,
> +                                   <0x500 &apps_smmu 0x1c05 0x1>,
> +                                   <0x600 &apps_smmu 0x1c06 0x1>,
> +                                   <0x700 &apps_smmu 0x1c07 0x1>,
> +                                   <0x800 &apps_smmu 0x1c08 0x1>,
> +                                   <0x900 &apps_smmu 0x1c09 0x1>,
> +                                   <0xa00 &apps_smmu 0x1c0a 0x1>,
> +                                   <0xb00 &apps_smmu 0x1c0b 0x1>,
> +                                   <0xc00 &apps_smmu 0x1c0c 0x1>,
> +                                   <0xd00 &apps_smmu 0x1c0d 0x1>,
> +                                   <0xe00 &apps_smmu 0x1c0e 0x1>,
> +                                   <0xf00 &apps_smmu 0x1c0f 0x1>;
> +
> +                       resets = <&gcc GCC_PCIE_1_BCR>;
> +                       reset-names = "pci";
> +
> +                       power-domains = <&gcc PCIE_1_GDSC>;
> +
> +                       phys = <&pcie1_phy>;
> +                       phy-names = "pciephy";
> +
> +                       status = "disabled";
> +               };
> +
> +               pcie1_phy: phy@1c0a000 {
> +                       compatible = "qcom,sdm845-qhp-pcie-phy";
> +                       reg = <0 0x01c0a000 0 0x2000>;
> +                       clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +                                <&gcc GCC_PCIE_1_CLKREF_CLK>,
> +                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
> +                                <&gcc GCC_PCIE_1_PIPE_CLK>;
> +                       clock-names = "aux",
> +                                     "cfg_ahb",
> +                                     "ref",
> +                                     "refgen",
> +                                     "pipe";
> +
> +                       clock-output-names = "pcie_1_pipe_clk";
> +                       #clock-cells = <0>;
> +
> +                       #phy-cells = <0>;
> +
> +                       resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> +                       reset-names = "phy";
> +
> +                       assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
> +                       assigned-clock-rates = <100000000>;
> +
> +                       status = "disabled";
> +               };
> +
> +               mem_noc: interconnect@1380000 {
> +                       compatible = "qcom,sdm845-mem-noc";
> +                       reg = <0 0x01380000 0 0x27200>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               dc_noc: interconnect@14e0000 {
> +                       compatible = "qcom,sdm845-dc-noc";
> +                       reg = <0 0x014e0000 0 0x400>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               config_noc: interconnect@1500000 {
> +                       compatible = "qcom,sdm845-config-noc";
> +                       reg = <0 0x01500000 0 0x5080>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               system_noc: interconnect@1620000 {
> +                       compatible = "qcom,sdm845-system-noc";
> +                       reg = <0 0x01620000 0 0x18080>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               aggre1_noc: interconnect@16e0000 {
> +                       compatible = "qcom,sdm845-aggre1-noc";
> +                       reg = <0 0x016e0000 0 0x15080>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               aggre2_noc: interconnect@1700000 {
> +                       compatible = "qcom,sdm845-aggre2-noc";
> +                       reg = <0 0x01700000 0 0x1f300>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               mmss_noc: interconnect@1740000 {
> +                       compatible = "qcom,sdm845-mmss-noc";
> +                       reg = <0 0x01740000 0 0x1c100>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               ufs_mem_hc: ufshc@1d84000 {
> +                       compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
> +                                    "jedec,ufs-2.0";
> +                       reg = <0 0x01d84000 0 0x2500>,
> +                             <0 0x01d90000 0 0x8000>;
> +                       reg-names = "std", "ice";
> +                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +                       phys = <&ufs_mem_phy_lanes>;
> +                       phy-names = "ufsphy";
> +                       lanes-per-direction = <2>;
> +                       power-domains = <&gcc UFS_PHY_GDSC>;
> +                       #reset-cells = <1>;
> +                       resets = <&gcc GCC_UFS_PHY_BCR>;
> +                       reset-names = "rst";
> +
> +                       iommus = <&apps_smmu 0x100 0xf>;
> +
> +                       clock-names =
> +                               "core_clk",
> +                               "bus_aggr_clk",
> +                               "iface_clk",
> +                               "core_clk_unipro",
> +                               "ref_clk",
> +                               "tx_lane0_sync_clk",
> +                               "rx_lane0_sync_clk",
> +                               "rx_lane1_sync_clk",
> +                               "ice_core_clk";
> +                       clocks =
> +                               <&gcc GCC_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_UFS_PHY_AHB_CLK>,
> +                               <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +                               <&rpmhcc RPMH_CXO_CLK>,
> +                               <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
> +                               <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> +                       freq-table-hz =
> +                               <50000000 200000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <37500000 150000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <75000000 300000000>;
> +
> +                       interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> +                       interconnect-names = "ufs-ddr", "cpu-ufs";
> +
> +                       status = "disabled";
> +               };
> +
> +               ufs_mem_phy: phy@1d87000 {
> +                       compatible = "qcom,sdm845-qmp-ufs-phy";
> +                       reg = <0 0x01d87000 0 0x18c>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       clock-names = "ref",
> +                                     "ref_aux";
> +                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
> +                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> +                       resets = <&ufs_mem_hc 0>;
> +                       reset-names = "ufsphy";
> +                       status = "disabled";
> +
> +                       ufs_mem_phy_lanes: phy@1d87400 {
> +                               reg = <0 0x01d87400 0 0x108>,
> +                                     <0 0x01d87600 0 0x1e0>,
> +                                     <0 0x01d87c00 0 0x1dc>,
> +                                     <0 0x01d87800 0 0x108>,
> +                                     <0 0x01d87a00 0 0x1e0>;
> +                               #phy-cells = <0>;
> +                       };
> +               };
> +
> +               cryptobam: dma-controller@1dc4000 {
> +                       compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +                       reg = <0 0x01dc4000 0 0x24000>;
> +                       interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&rpmhcc RPMH_CE_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +                       qcom,controlled-remotely;
> +                       iommus = <&apps_smmu 0x704 0x1>,
> +                                <&apps_smmu 0x706 0x1>,
> +                                <&apps_smmu 0x714 0x1>,
> +                                <&apps_smmu 0x716 0x1>;
> +               };
> +
> +               crypto: crypto@1dfa000 {
> +                       compatible = "qcom,crypto-v5.4";
> +                       reg = <0 0x01dfa000 0 0x6000>;
> +                       clocks = <&gcc GCC_CE1_AHB_CLK>,
> +                                <&gcc GCC_CE1_AXI_CLK>,
> +                                <&rpmhcc RPMH_CE_CLK>;
> +                       clock-names = "iface", "bus", "core";
> +                       dmas = <&cryptobam 6>, <&cryptobam 7>;
> +                       dma-names = "rx", "tx";
> +                       iommus = <&apps_smmu 0x704 0x1>,
> +                                <&apps_smmu 0x706 0x1>,
> +                                <&apps_smmu 0x714 0x1>,
> +                                <&apps_smmu 0x716 0x1>;
> +               };
> +
> +               ipa: ipa@1e40000 {
> +                       compatible = "qcom,sdm845-ipa";
> +
> +                       iommus = <&apps_smmu 0x720 0x0>,
> +                                <&apps_smmu 0x722 0x0>;
> +                       reg = <0 0x01e40000 0 0x7000>,
> +                             <0 0x01e47000 0 0x2000>,
> +                             <0 0x01e04000 0 0x2c000>;
> +                       reg-names = "ipa-reg",
> +                                   "ipa-shared",
> +                                   "gsi";
> +
> +                       interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
> +                                             <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
> +                                             <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "ipa",
> +                                         "gsi",
> +                                         "ipa-clock-query",
> +                                         "ipa-setup-ready";
> +
> +                       clocks = <&rpmhcc RPMH_IPA_CLK>;
> +                       clock-names = "core";
> +
> +                       interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
> +                                       <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
> +                       interconnect-names = "memory",
> +                                            "imem",
> +                                            "config";
> +
> +                       qcom,smem-states = <&ipa_smp2p_out 0>,
> +                                          <&ipa_smp2p_out 1>;
> +                       qcom,smem-state-names = "ipa-clock-enabled-valid",
> +                                               "ipa-clock-enabled";
> +
> +                       status = "disabled";
> +               };
> +
> +               tcsr_mutex: hwlock@1f40000 {
> +                       compatible = "qcom,tcsr-mutex";
> +                       reg = <0 0x01f40000 0 0x20000>;
> +                       #hwlock-cells = <1>;
> +               };
> +
> +               tcsr_regs_1: syscon@1f60000 {
> +                       compatible = "qcom,sdm845-tcsr", "syscon";
> +                       reg = <0 0x01f60000 0 0x20000>;
> +               };
> +
> +               tlmm: pinctrl@3400000 {
> +                       compatible = "qcom,sdm845-pinctrl";
> +                       reg = <0 0x03400000 0 0xc00000>;
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +                       gpio-ranges = <&tlmm 0 0 151>;
> +                       wakeup-parent = <&pdc_intc>;
> +
> +                       cci0_default: cci0-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio17", "gpio18";
> +                               function = "cci_i2c";
> +
> +                               bias-pull-up;
> +                               drive-strength = <2>; /* 2 mA */
> +                       };
> +
> +                       cci0_sleep: cci0-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio17", "gpio18";
> +                               function = "cci_i2c";
> +
> +                               drive-strength = <2>; /* 2 mA */
> +                               bias-pull-down;
> +                       };
> +
> +                       cci1_default: cci1-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio19", "gpio20";
> +                               function = "cci_i2c";
> +
> +                               bias-pull-up;
> +                               drive-strength = <2>; /* 2 mA */
> +                       };
> +
> +                       cci1_sleep: cci1-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio19", "gpio20";
> +                               function = "cci_i2c";
> +
> +                               drive-strength = <2>; /* 2 mA */
> +                               bias-pull-down;
> +                       };
> +
> +                       qspi_clk: qspi-clk-state {
> +                               pins = "gpio95";
> +                               function = "qspi_clk";
> +                       };
> +
> +                       qspi_cs0: qspi-cs0-state {
> +                               pins = "gpio90";
> +                               function = "qspi_cs";
> +                       };
> +
> +                       qspi_cs1: qspi-cs1-state {
> +                               pins = "gpio89";
> +                               function = "qspi_cs";
> +                       };
> +
> +                       qspi_data0: qspi-data0-state {
> +                               pins = "gpio91";
> +                               function = "qspi_data";
> +                       };
> +
> +                       qspi_data1: qspi-data1-state {
> +                               pins = "gpio92";
> +                               function = "qspi_data";
> +                       };
> +
> +                       qspi_data23: qspi-data23-state {
> +                               pins = "gpio93", "gpio94";
> +                               function = "qspi_data";
> +                       };
> +
> +                       qup_i2c0_default: qup-i2c0-default-state {
> +                               pins = "gpio0", "gpio1";
> +                               function = "qup0";
> +                       };
> +
> +                       qup_i2c1_default: qup-i2c1-default-state {
> +                               pins = "gpio17", "gpio18";
> +                               function = "qup1";
> +                       };
> +
> +                       qup_i2c2_default: qup-i2c2-default-state {
> +                               pins = "gpio27", "gpio28";
> +                               function = "qup2";
> +                       };
> +
> +                       qup_i2c3_default: qup-i2c3-default-state {
> +                               pins = "gpio41", "gpio42";
> +                               function = "qup3";
> +                       };
> +
> +                       qup_i2c4_default: qup-i2c4-default-state {
> +                               pins = "gpio89", "gpio90";
> +                               function = "qup4";
> +                       };
> +
> +                       qup_i2c5_default: qup-i2c5-default-state {
> +                               pins = "gpio85", "gpio86";
> +                               function = "qup5";
> +                       };
> +
> +                       qup_i2c6_default: qup-i2c6-default-state {
> +                               pins = "gpio45", "gpio46";
> +                               function = "qup6";
> +                       };
> +
> +                       qup_i2c7_default: qup-i2c7-default-state {
> +                               pins = "gpio93", "gpio94";
> +                               function = "qup7";
> +                       };
> +
> +                       qup_i2c8_default: qup-i2c8-default-state {
> +                               pins = "gpio65", "gpio66";
> +                               function = "qup8";
> +                       };
> +
> +                       qup_i2c9_default: qup-i2c9-default-state {
> +                               pins = "gpio6", "gpio7";
> +                               function = "qup9";
> +                       };
> +
> +                       qup_i2c10_default: qup-i2c10-default-state {
> +                               pins = "gpio55", "gpio56";
> +                               function = "qup10";
> +                       };
> +
> +                       qup_i2c11_default: qup-i2c11-default-state {
> +                               pins = "gpio31", "gpio32";
> +                               function = "qup11";
> +                       };
> +
> +                       qup_i2c12_default: qup-i2c12-default-state {
> +                               pins = "gpio49", "gpio50";
> +                               function = "qup12";
> +                       };
> +
> +                       qup_i2c13_default: qup-i2c13-default-state {
> +                               pins = "gpio105", "gpio106";
> +                               function = "qup13";
> +                       };
> +
> +                       qup_i2c14_default: qup-i2c14-default-state {
> +                               pins = "gpio33", "gpio34";
> +                               function = "qup14";
> +                       };
> +
> +                       qup_i2c15_default: qup-i2c15-default-state {
> +                               pins = "gpio81", "gpio82";
> +                               function = "qup15";
> +                       };
> +
> +                       qup_spi0_default: qup-spi0-default-state {
> +                               pins = "gpio0", "gpio1", "gpio2", "gpio3";
> +                               function = "qup0";
> +                       };
> +
> +                       qup_spi1_default: qup-spi1-default-state {
> +                               pins = "gpio17", "gpio18", "gpio19", "gpio20";
> +                               function = "qup1";
> +                       };
> +
> +                       qup_spi2_default: qup-spi2-default-state {
> +                               pins = "gpio27", "gpio28", "gpio29", "gpio30";
> +                               function = "qup2";
> +                       };
> +
> +                       qup_spi3_default: qup-spi3-default-state {
> +                               pins = "gpio41", "gpio42", "gpio43", "gpio44";
> +                               function = "qup3";
> +                       };
> +
> +                       qup_spi4_default: qup-spi4-default-state {
> +                               pins = "gpio89", "gpio90", "gpio91", "gpio92";
> +                               function = "qup4";
> +                       };
> +
> +                       qup_spi5_default: qup-spi5-default-state {
> +                               pins = "gpio85", "gpio86", "gpio87", "gpio88";
> +                               function = "qup5";
> +                       };
> +
> +                       qup_spi6_default: qup-spi6-default-state {
> +                               pins = "gpio45", "gpio46", "gpio47", "gpio48";
> +                               function = "qup6";
> +                       };
> +
> +                       qup_spi7_default: qup-spi7-default-state {
> +                               pins = "gpio93", "gpio94", "gpio95", "gpio96";
> +                               function = "qup7";
> +                       };
> +
> +                       qup_spi8_default: qup-spi8-default-state {
> +                               pins = "gpio65", "gpio66", "gpio67", "gpio68";
> +                               function = "qup8";
> +                       };
> +
> +                       qup_spi9_default: qup-spi9-default-state {
> +                               pins = "gpio6", "gpio7", "gpio4", "gpio5";
> +                               function = "qup9";
> +                       };
> +
> +                       qup_spi10_default: qup-spi10-default-state {
> +                               pins = "gpio55", "gpio56", "gpio53", "gpio54";
> +                               function = "qup10";
> +                       };
> +
> +                       qup_spi11_default: qup-spi11-default-state {
> +                               pins = "gpio31", "gpio32", "gpio33", "gpio34";
> +                               function = "qup11";
> +                       };
> +
> +                       qup_spi12_default: qup-spi12-default-state {
> +                               pins = "gpio49", "gpio50", "gpio51", "gpio52";
> +                               function = "qup12";
> +                       };
> +
> +                       qup_spi13_default: qup-spi13-default-state {
> +                               pins = "gpio105", "gpio106", "gpio107", "gpio108";
> +                               function = "qup13";
> +                       };
> +
> +                       qup_spi14_default: qup-spi14-default-state {
> +                               pins = "gpio33", "gpio34", "gpio31", "gpio32";
> +                               function = "qup14";
> +                       };
> +
> +                       qup_spi15_default: qup-spi15-default-state {
> +                               pins = "gpio81", "gpio82", "gpio83", "gpio84";
> +                               function = "qup15";
> +                       };
> +
> +                       qup_uart0_default: qup-uart0-default-state {
> +                               qup_uart0_tx: tx-pins {
> +                                       pins = "gpio2";
> +                                       function = "qup0";
> +                               };
> +
> +                               qup_uart0_rx: rx-pins {
> +                                       pins = "gpio3";
> +                                       function = "qup0";
> +                               };
> +                       };
> +
> +                       qup_uart1_default: qup-uart1-default-state {
> +                               qup_uart1_tx: tx-pins {
> +                                       pins = "gpio19";
> +                                       function = "qup1";
> +                               };
> +
> +                               qup_uart1_rx: rx-pins {
> +                                       pins = "gpio20";
> +                                       function = "qup1";
> +                               };
> +                       };
> +
> +                       qup_uart2_default: qup-uart2-default-state {
> +                               qup_uart2_tx: tx-pins {
> +                                       pins = "gpio29";
> +                                       function = "qup2";
> +                               };
> +
> +                               qup_uart2_rx: rx-pins {
> +                                       pins = "gpio30";
> +                                       function = "qup2";
> +                               };
> +                       };
> +
> +                       qup_uart3_default: qup-uart3-default-state {
> +                               qup_uart3_tx: tx-pins {
> +                                       pins = "gpio43";
> +                                       function = "qup3";
> +                               };
> +
> +                               qup_uart3_rx: rx-pins {
> +                                       pins = "gpio44";
> +                                       function = "qup3";
> +                               };
> +                       };
> +
> +                       qup_uart3_4pin: qup-uart3-4pin-state {
> +                               qup_uart3_4pin_cts: cts-pins {
> +                                       pins = "gpio41";
> +                                       function = "qup3";
> +                               };
> +
> +                               qup_uart3_4pin_rts_tx: rts-tx-pins {
> +                                       pins = "gpio42", "gpio43";
> +                                       function = "qup3";
> +                               };
> +
> +                               qup_uart3_4pin_rx: rx-pins {
> +                                       pins = "gpio44";
> +                                       function = "qup3";
> +                               };
> +                       };
> +
> +                       qup_uart4_default: qup-uart4-default-state {
> +                               qup_uart4_tx: tx-pins {
> +                                       pins = "gpio91";
> +                                       function = "qup4";
> +                               };
> +
> +                               qup_uart4_rx: rx-pins {
> +                                       pins = "gpio92";
> +                                       function = "qup4";
> +                               };
> +                       };
> +
> +                       qup_uart5_default: qup-uart5-default-state {
> +                               qup_uart5_tx: tx-pins {
> +                                       pins = "gpio87";
> +                                       function = "qup5";
> +                               };
> +
> +                               qup_uart5_rx: rx-pins {
> +                                       pins = "gpio88";
> +                                       function = "qup5";
> +                               };
> +                       };
> +
> +                       qup_uart6_default: qup-uart6-default-state {
> +                               qup_uart6_tx: tx-pins {
> +                                       pins = "gpio47";
> +                                       function = "qup6";
> +                               };
> +
> +                               qup_uart6_rx: rx-pins {
> +                                       pins = "gpio48";
> +                                       function = "qup6";
> +                               };
> +                       };
> +
> +                       qup_uart6_4pin: qup-uart6-4pin-state {
> +                               qup_uart6_4pin_cts: cts-pins {
> +                                       pins = "gpio45";
> +                                       function = "qup6";
> +                                       bias-pull-down;
> +                               };
> +
> +                               qup_uart6_4pin_rts_tx: rts-tx-pins {
> +                                       pins = "gpio46", "gpio47";
> +                                       function = "qup6";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +
> +                               qup_uart6_4pin_rx: rx-pins {
> +                                       pins = "gpio48";
> +                                       function = "qup6";
> +                                       bias-pull-up;
> +                               };
> +                       };
> +
> +                       qup_uart7_default: qup-uart7-default-state {
> +                               qup_uart7_tx: tx-pins {
> +                                       pins = "gpio95";
> +                                       function = "qup7";
> +                               };
> +
> +                               qup_uart7_rx: rx-pins {
> +                                       pins = "gpio96";
> +                                       function = "qup7";
> +                               };
> +                       };
> +
> +                       qup_uart8_default: qup-uart8-default-state {
> +                               qup_uart8_tx: tx-pins {
> +                                       pins = "gpio67";
> +                                       function = "qup8";
> +                               };
> +
> +                               qup_uart8_rx: rx-pins {
> +                                       pins = "gpio68";
> +                                       function = "qup8";
> +                               };
> +                       };
> +
> +                       qup_uart9_default: qup-uart9-default-state {
> +                               qup_uart9_tx: tx-pins {
> +                                       pins = "gpio4";
> +                                       function = "qup9";
> +                               };
> +
> +                               qup_uart9_rx: rx-pins {
> +                                       pins = "gpio5";
> +                                       function = "qup9";
> +                               };
> +                       };
> +
> +                       qup_uart10_default: qup-uart10-default-state {
> +                               qup_uart10_tx: tx-pins {
> +                                       pins = "gpio53";
> +                                       function = "qup10";
> +                               };
> +
> +                               qup_uart10_rx: rx-pins {
> +                                       pins = "gpio54";
> +                                       function = "qup10";
> +                               };
> +                       };
> +
> +                       qup_uart11_default: qup-uart11-default-state {
> +                               qup_uart11_tx: tx-pins {
> +                                       pins = "gpio33";
> +                                       function = "qup11";
> +                               };
> +
> +                               qup_uart11_rx: rx-pins {
> +                                       pins = "gpio34";
> +                                       function = "qup11";
> +                               };
> +                       };
> +
> +                       qup_uart12_default: qup-uart12-default-state {
> +                               qup_uart12_tx: tx-pins {
> +                                       pins = "gpio51";
> +                                       function = "qup0";
> +                               };
> +
> +                               qup_uart12_rx: rx-pins {
> +                                       pins = "gpio52";
> +                                       function = "qup0";
> +                               };
> +                       };
> +
> +                       qup_uart13_default: qup-uart13-default-state {
> +                               qup_uart13_tx: tx-pins {
> +                                       pins = "gpio107";
> +                                       function = "qup13";
> +                               };
> +
> +                               qup_uart13_rx: rx-pins {
> +                                       pins = "gpio108";
> +                                       function = "qup13";
> +                               };
> +                       };
> +
> +                       qup_uart14_default: qup-uart14-default-state {
> +                               qup_uart14_tx: tx-pins {
> +                                       pins = "gpio31";
> +                                       function = "qup14";
> +                               };
> +
> +                               qup_uart14_rx: rx-pins {
> +                                       pins = "gpio32";
> +                                       function = "qup14";
> +                               };
> +                       };
> +
> +                       qup_uart15_default: qup-uart15-default-state {
> +                               qup_uart15_tx: tx-pins {
> +                                       pins = "gpio83";
> +                                       function = "qup15";
> +                               };
> +
> +                               qup_uart15_rx: rx-pins {
> +                                       pins = "gpio84";
> +                                       function = "qup15";
> +                               };
> +                       };
> +
> +                       quat_mi2s_sleep: quat-mi2s-sleep-state {
> +                               pins = "gpio58", "gpio59";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       quat_mi2s_active: quat-mi2s-active-state {
> +                               pins = "gpio58", "gpio59";
> +                               function = "qua_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                               output-high;
> +                       };
> +
> +                       quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
> +                               pins = "gpio60";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
> +                               pins = "gpio60";
> +                               function = "qua_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
> +                               pins = "gpio61";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
> +                               pins = "gpio61";
> +                               function = "qua_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
> +                               pins = "gpio62";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
> +                               pins = "gpio62";
> +                               function = "qua_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
> +                               pins = "gpio63";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
> +                               pins = "gpio63";
> +                               function = "qua_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +               };
> +
> +               mss_pil: remoteproc@4080000 {
> +                       compatible = "qcom,sdm845-mss-pil";
> +                       reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
> +                       reg-names = "qdsp6", "rmb";
> +
> +                       interrupts-extended =
> +                               <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack",
> +                                         "shutdown-ack";
> +
> +                       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
> +                                <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
> +                                <&gcc GCC_BOOT_ROM_AHB_CLK>,
> +                                <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
> +                                <&gcc GCC_MSS_SNOC_AXI_CLK>,
> +                                <&gcc GCC_MSS_MFAB_AXIS_CLK>,
> +                                <&gcc GCC_PRNG_AHB_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "iface", "bus", "mem", "gpll0_mss",
> +                                     "snoc_axi", "mnoc_axi", "prng", "xo";
> +
> +                       qcom,qmp = <&aoss_qmp>;
> +
> +                       qcom,smem-states = <&modem_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
> +                                <&pdc_reset PDC_MODEM_SYNC_RESET>;
> +                       reset-names = "mss_restart", "pdc_reset";
> +
> +                       qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
> +
> +                       power-domains = <&rpmhpd SDM845_CX>,
> +                                       <&rpmhpd SDM845_MX>,
> +                                       <&rpmhpd SDM845_MSS>;
> +                       power-domain-names = "cx", "mx", "mss";
> +
> +                       status = "disabled";
> +
> +                       mba {
> +                               memory-region = <&mba_region>;
> +                       };
> +
> +                       mpss {
> +                               memory-region = <&mpss_region>;
> +                       };
> +
> +                       metadata {
> +                               memory-region = <&mdata_mem>;
> +                       };
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
> +                               label = "modem";
> +                               qcom,remote-pid = <1>;
> +                               mboxes = <&apss_shared 12>;
> +                       };
> +               };
> +
> +               gpucc: clock-controller@5090000 {
> +                       compatible = "qcom,sdm845-gpucc";
> +                       reg = <0 0x05090000 0 0x9000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> +                                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +                       clock-names = "bi_tcxo",
> +                                     "gcc_gpu_gpll0_clk_src",
> +                                     "gcc_gpu_gpll0_div_clk_src";
> +               };
> +
> +               slpi_pas: remoteproc@5c00000 {
> +                       compatible = "qcom,sdm845-slpi-pas";
> +                       reg = <0 0x5c00000 0 0x4000>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
> +                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                               "handover", "stop-ack";
> +
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "xo";
> +
> +                       qcom,qmp = <&aoss_qmp>;
> +
> +                       power-domains = <&rpmhpd SDM845_CX>,
> +                                       <&rpmhpd SDM845_MX>;
> +                       power-domain-names = "lcx", "lmx";
> +
> +                       memory-region = <&slpi_mem>;
> +
> +                       qcom,smem-states = <&slpi_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       status = "disabled";
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
> +                               label = "dsps";
> +                               qcom,remote-pid = <3>;
> +                               mboxes = <&apss_shared 24>;
> +
> +                               fastrpc {
> +                                       compatible = "qcom,fastrpc";
> +                                       qcom,glink-channels = "fastrpcglink-apps-dsp";
> +                                       label = "sdsp";
> +                                       qcom,non-secure-domain;
> +                                       qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
> +                                                     QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
> +                                       memory-region = <&fastrpc_mem>;
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       compute-cb@0 {
> +                                               compatible = "qcom,fastrpc-compute-cb";
> +                                               reg = <0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               stm@6002000 {
> +                       compatible = "arm,coresight-stm", "arm,primecell";
> +                       reg = <0 0x06002000 0 0x1000>,
> +                             <0 0x16280000 0 0x180000>;
> +                       reg-names = "stm-base", "stm-stimulus-base";
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       stm_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel0_in7>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@6041000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0 0x06041000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       funnel0_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_in0>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@7 {
> +                                       reg = <7>;
> +                                       funnel0_in7: endpoint {
> +                                               remote-endpoint = <&stm_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@6043000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0 0x06043000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       funnel2_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_in2>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@5 {
> +                                       reg = <5>;
> +                                       funnel2_in5: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_merge_funnel_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@6045000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0 0x06045000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       merge_funnel_out: endpoint {
> +                                               remote-endpoint = <&etf_in>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       merge_funnel_in0: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel0_out>;
> +                                       };
> +                               };
> +
> +                               port@2 {
> +                                       reg = <2>;
> +                                       merge_funnel_in2: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel2_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               replicator@6046000 {
> +                       compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> +                       reg = <0 0x06046000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       replicator_out: endpoint {
> +                                               remote-endpoint = <&etr_in>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               port {
> +                                       replicator_in: endpoint {
> +                                               remote-endpoint = <&etf_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etf@6047000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0 0x06047000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       etf_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&replicator_in>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       etf_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etr@6048000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0 0x06048000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,scatter-gather;
> +
> +                       in-ports {
> +                               port {
> +                                       etr_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&replicator_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7040000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07040000 0 0x1000>;
> +
> +                       cpu = <&CPU0>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm0_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7140000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07140000 0 0x1000>;
> +
> +                       cpu = <&CPU1>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm1_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7240000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07240000 0 0x1000>;
> +
> +                       cpu = <&CPU2>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm2_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in2>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7340000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07340000 0 0x1000>;
> +
> +                       cpu = <&CPU3>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm3_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in3>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7440000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07440000 0 0x1000>;
> +
> +                       cpu = <&CPU4>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm4_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in4>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7540000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07540000 0 0x1000>;
> +
> +                       cpu = <&CPU5>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm5_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in5>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7640000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07640000 0 0x1000>;
> +
> +                       cpu = <&CPU6>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm6_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in6>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm@7740000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0 0x07740000 0 0x1000>;
> +
> +                       cpu = <&CPU7>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       out-ports {
> +                               port {
> +                                       etm7_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_in7>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@7800000 { /* APSS Funnel */
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0 0x07800000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       apss_funnel_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_merge_funnel_in>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       apss_funnel_in0: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm0_out>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       apss_funnel_in1: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm1_out>;
> +                                       };
> +                               };
> +
> +                               port@2 {
> +                                       reg = <2>;
> +                                       apss_funnel_in2: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm2_out>;
> +                                       };
> +                               };
> +
> +                               port@3 {
> +                                       reg = <3>;
> +                                       apss_funnel_in3: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm3_out>;
> +                                       };
> +                               };
> +
> +                               port@4 {
> +                                       reg = <4>;
> +                                       apss_funnel_in4: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm4_out>;
> +                                       };
> +                               };
> +
> +                               port@5 {
> +                                       reg = <5>;
> +                                       apss_funnel_in5: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm5_out>;
> +                                       };
> +                               };
> +
> +                               port@6 {
> +                                       reg = <6>;
> +                                       apss_funnel_in6: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm6_out>;
> +                                       };
> +                               };
> +
> +                               port@7 {
> +                                       reg = <7>;
> +                                       apss_funnel_in7: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etm7_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@7810000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0 0x07810000 0 0x1000>;
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       apss_merge_funnel_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel2_in5>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               port {
> +                                       apss_merge_funnel_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               sdhc_2: mmc@8804000 {
> +                       compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
> +                       reg = <0 0x08804000 0 0x1000>;
> +
> +                       interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +
> +                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> +                                <&gcc GCC_SDCC2_APPS_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "iface", "core", "xo";
> +                       iommus = <&apps_smmu 0xa0 0xf>;
> +                       power-domains = <&rpmhpd SDM845_CX>;
> +                       operating-points-v2 = <&sdhc2_opp_table>;
> +
> +                       status = "disabled";
> +
> +                       sdhc2_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-9600000 {
> +                                       opp-hz = /bits/ 64 <9600000>;
> +                                       required-opps = <&rpmhpd_opp_min_svs>;
> +                               };
> +
> +                               opp-19200000 {
> +                                       opp-hz = /bits/ 64 <19200000>;
> +                                       required-opps = <&rpmhpd_opp_low_svs>;
> +                               };
> +
> +                               opp-100000000 {
> +                                       opp-hz = /bits/ 64 <100000000>;
> +                                       required-opps = <&rpmhpd_opp_svs>;
> +                               };
> +
> +                               opp-201500000 {
> +                                       opp-hz = /bits/ 64 <201500000>;
> +                                       required-opps = <&rpmhpd_opp_svs_l1>;
> +                               };
> +                       };
> +               };
> +
> +               qspi: spi@88df000 {
> +                       compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
> +                       reg = <0 0x088df000 0 0x600>;
> +                       iommus = <&apps_smmu 0x160 0x0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> +                                <&gcc GCC_QSPI_CORE_CLK>;
> +                       clock-names = "iface", "core";
> +                       power-domains = <&rpmhpd SDM845_CX>;
> +                       operating-points-v2 = <&qspi_opp_table>;
> +                       status = "disabled";
> +               };
> +
> +               slim: slim-ngd@171c0000 {
> +                       compatible = "qcom,slim-ngd-v2.1.0";
> +                       reg = <0 0x171c0000 0 0x2c000>;
> +                       interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       dmas = <&slimbam 3>, <&slimbam 4>;
> +                       dma-names = "rx", "tx";
> +
> +                       iommus = <&apps_smmu 0x1806 0x0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               lmh_cluster1: lmh@17d70800 {
> +                       compatible = "qcom,sdm845-lmh";
> +                       reg = <0 0x17d70800 0 0x400>;
> +                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +                       cpus = <&CPU4>;
> +                       qcom,lmh-temp-arm-millicelsius = <65000>;
> +                       qcom,lmh-temp-low-millicelsius = <94500>;
> +                       qcom,lmh-temp-high-millicelsius = <95000>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +               };
> +
> +               lmh_cluster0: lmh@17d78800 {
> +                       compatible = "qcom,sdm845-lmh";
> +                       reg = <0 0x17d78800 0 0x400>;
> +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +                       cpus = <&CPU0>;
> +                       qcom,lmh-temp-arm-millicelsius = <65000>;
> +                       qcom,lmh-temp-low-millicelsius = <94500>;
> +                       qcom,lmh-temp-high-millicelsius = <95000>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +               };
> +
> +               usb_1_hsphy: phy@88e2000 {
> +                       compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
> +                       reg = <0 0x088e2000 0 0x400>;
> +                       status = "disabled";
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> +                       nvmem-cells = <&qusb2p_hstx_trim>;
> +               };
> +
> +               usb_2_hsphy: phy@88e3000 {
> +                       compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
> +                       reg = <0 0x088e3000 0 0x400>;
> +                       status = "disabled";
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> +
> +                       nvmem-cells = <&qusb2s_hstx_trim>;
> +               };
> +
> +               usb_1_qmpphy: phy@88e8000 {
> +                       compatible = "qcom,sdm845-qmp-usb3-dp-phy";
> +                       reg = <0 0x088e8000 0 0x3000>;
> +                       status = "disabled";
> +
> +                       clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> +                                <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> +                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> +                                <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
> +                                <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
> +                       clock-names = "aux",
> +                                     "ref",
> +                                     "com_aux",
> +                                     "usb3_pipe",
> +                                     "cfg_ahb";
> +
> +                       resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> +                                <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> +                       reset-names = "phy", "common";
> +
> +                       #clock-cells = <1>;
> +                       #phy-cells = <1>;
> +               };
> +
> +               usb_2_qmpphy: phy@88eb000 {
> +                       compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> +                       reg = <0 0x088eb000 0 0x18c>;
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +
> +                       clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
> +                                <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                                <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> +                                <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
> +                       clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> +
> +                       resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> +                                <&gcc GCC_USB3_PHY_SEC_BCR>;
> +                       reset-names = "phy", "common";
> +
> +                       usb_2_ssphy: phy@88eb200 {
> +                               reg = <0 0x088eb200 0 0x128>,
> +                                     <0 0x088eb400 0 0x1fc>,
> +                                     <0 0x088eb800 0 0x218>,
> +                                     <0 0x088eb600 0 0x70>;
> +                               #clock-cells = <0>;
> +                               #phy-cells = <0>;
> +                               clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> +                               clock-names = "pipe0";
> +                               clock-output-names = "usb3_uni_phy_pipe_clk_src";
> +                       };
> +               };
> +
> +               usb_1: usb@a6f8800 {
> +                       compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
> +                       reg = <0 0x0a6f8800 0 0x400>;
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       dma-ranges;
> +
> +                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> +                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> +                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> +                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> +                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> +                       clock-names = "cfg_noc",
> +                                     "core",
> +                                     "iface",
> +                                     "sleep",
> +                                     "mock_utmi";
> +
> +                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <150000000>;
> +
> +                       interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hs_phy_irq", "ss_phy_irq",
> +                                         "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> +                       power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> +                       resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> +                       interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
> +                       interconnect-names = "usb-ddr", "apps-usb";
> +
> +                       usb_1_dwc3: usb@a600000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0 0x0a600000 0 0xcd00>;
> +                               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +                               iommus = <&apps_smmu 0x740 0>;
> +                               snps,dis_u2_susphy_quirk;
> +                               snps,dis_enblslpm_quirk;
> +                               phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                       };
> +               };
> +
> +               usb_2: usb@a8f8800 {
> +                       compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
> +                       reg = <0 0x0a8f8800 0 0x400>;
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       dma-ranges;
> +
> +                       clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> +                                <&gcc GCC_USB30_SEC_MASTER_CLK>,
> +                                <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> +                                <&gcc GCC_USB30_SEC_SLEEP_CLK>,
> +                                <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
> +                       clock-names = "cfg_noc",
> +                                     "core",
> +                                     "iface",
> +                                     "sleep",
> +                                     "mock_utmi";
> +
> +                       assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_SEC_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <150000000>;
> +
> +                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hs_phy_irq", "ss_phy_irq",
> +                                         "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> +                       power-domains = <&gcc USB30_SEC_GDSC>;
> +
> +                       resets = <&gcc GCC_USB30_SEC_BCR>;
> +
> +                       interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
> +                       interconnect-names = "usb-ddr", "apps-usb";
> +
> +                       usb_2_dwc3: usb@a800000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0 0x0a800000 0 0xcd00>;
> +                               interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +                               iommus = <&apps_smmu 0x760 0>;
> +                               snps,dis_u2_susphy_quirk;
> +                               snps,dis_enblslpm_quirk;
> +                               phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                       };
> +               };
> +
> +               venus: video-codec@aa00000 {
> +                       compatible = "qcom,sdm845-venus-v2";
> +                       reg = <0 0x0aa00000 0 0xff000>;
> +                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&videocc VENUS_GDSC>,
> +                                       <&videocc VCODEC0_GDSC>,
> +                                       <&videocc VCODEC1_GDSC>,
> +                                       <&rpmhpd SDM845_CX>;
> +                       power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
> +                       operating-points-v2 = <&venus_opp_table>;
> +                       clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
> +                                <&videocc VIDEO_CC_VENUS_AHB_CLK>,
> +                                <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
> +                                <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
> +                                <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
> +                                <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
> +                                <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
> +                       clock-names = "core", "iface", "bus",
> +                                     "vcodec0_core", "vcodec0_bus",
> +                                     "vcodec1_core", "vcodec1_bus";
> +                       iommus = <&apps_smmu 0x10a0 0x8>,
> +                                <&apps_smmu 0x10b0 0x0>;
> +                       memory-region = <&venus_mem>;
> +                       interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
> +                       interconnect-names = "video-mem", "cpu-cfg";
> +
> +                       status = "disabled";
> +
> +                       video-core0 {
> +                               compatible = "venus-decoder";
> +                       };
> +
> +                       video-core1 {
> +                               compatible = "venus-encoder";
> +                       };
> +
> +                       venus_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-100000000 {
> +                                       opp-hz = /bits/ 64 <100000000>;
> +                                       required-opps = <&rpmhpd_opp_min_svs>;
> +                               };
> +
> +                               opp-200000000 {
> +                                       opp-hz = /bits/ 64 <200000000>;
> +                                       required-opps = <&rpmhpd_opp_low_svs>;
> +                               };
> +
> +                               opp-320000000 {
> +                                       opp-hz = /bits/ 64 <320000000>;
> +                                       required-opps = <&rpmhpd_opp_svs>;
> +                               };
> +
> +                               opp-380000000 {
> +                                       opp-hz = /bits/ 64 <380000000>;
> +                                       required-opps = <&rpmhpd_opp_svs_l1>;
> +                               };
> +
> +                               opp-444000000 {
> +                                       opp-hz = /bits/ 64 <444000000>;
> +                                       required-opps = <&rpmhpd_opp_nom>;
> +                               };
> +
> +                               opp-533000097 {
> +                                       opp-hz = /bits/ 64 <533000097>;
> +                                       required-opps = <&rpmhpd_opp_turbo>;
> +                               };
> +                       };
> +               };
> +
> +               videocc: clock-controller@ab00000 {
> +                       compatible = "qcom,sdm845-videocc";
> +                       reg = <0 0x0ab00000 0 0x10000>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "bi_tcxo";
> +                       #clock-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               camss: camss@acb3000 {
> +                       compatible = "qcom,sdm845-camss";
> +
> +                       reg = <0 0x0acb3000 0 0x1000>,
> +                               <0 0x0acba000 0 0x1000>,
> +                               <0 0x0acc8000 0 0x1000>,
> +                               <0 0x0ac65000 0 0x1000>,
> +                               <0 0x0ac66000 0 0x1000>,
> +                               <0 0x0ac67000 0 0x1000>,
> +                               <0 0x0ac68000 0 0x1000>,
> +                               <0 0x0acaf000 0 0x4000>,
> +                               <0 0x0acb6000 0 0x4000>,
> +                               <0 0x0acc4000 0 0x4000>;
> +                       reg-names = "csid0",
> +                               "csid1",
> +                               "csid2",
> +                               "csiphy0",
> +                               "csiphy1",
> +                               "csiphy2",
> +                               "csiphy3",
> +                               "vfe0",
> +                               "vfe1",
> +                               "vfe_lite";
> +
> +                       interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "csid0",
> +                               "csid1",
> +                               "csid2",
> +                               "csiphy0",
> +                               "csiphy1",
> +                               "csiphy2",
> +                               "csiphy3",
> +                               "vfe0",
> +                               "vfe1",
> +                               "vfe_lite";
> +
> +                       power-domains = <&clock_camcc IFE_0_GDSC>,
> +                               <&clock_camcc IFE_1_GDSC>,
> +                               <&clock_camcc TITAN_TOP_GDSC>;
> +
> +                       clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> +                               <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_CSIPHY0_CLK>,
> +                               <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> +                               <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_CSIPHY1_CLK>,
> +                               <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> +                               <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_CSIPHY2_CLK>,
> +                               <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> +                               <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_CSIPHY3_CLK>,
> +                               <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> +                               <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
> +                               <&gcc GCC_CAMERA_AHB_CLK>,
> +                               <&gcc GCC_CAMERA_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_SOC_AHB_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_0_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_1_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_IFE_LITE_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> +                               <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
> +                       clock-names = "camnoc_axi",
> +                               "cpas_ahb",
> +                               "cphy_rx_src",
> +                               "csi0",
> +                               "csi0_src",
> +                               "csi1",
> +                               "csi1_src",
> +                               "csi2",
> +                               "csi2_src",
> +                               "csiphy0",
> +                               "csiphy0_timer",
> +                               "csiphy0_timer_src",
> +                               "csiphy1",
> +                               "csiphy1_timer",
> +                               "csiphy1_timer_src",
> +                               "csiphy2",
> +                               "csiphy2_timer",
> +                               "csiphy2_timer_src",
> +                               "csiphy3",
> +                               "csiphy3_timer",
> +                               "csiphy3_timer_src",
> +                               "gcc_camera_ahb",
> +                               "gcc_camera_axi",
> +                               "slow_ahb_src",
> +                               "soc_ahb",
> +                               "vfe0_axi",
> +                               "vfe0",
> +                               "vfe0_cphy_rx",
> +                               "vfe0_src",
> +                               "vfe1_axi",
> +                               "vfe1",
> +                               "vfe1_cphy_rx",
> +                               "vfe1_src",
> +                               "vfe_lite",
> +                               "vfe_lite_cphy_rx",
> +                               "vfe_lite_src";
> +
> +                       iommus = <&apps_smmu 0x0808 0x0>,
> +                                <&apps_smmu 0x0810 0x8>,
> +                                <&apps_smmu 0x0c08 0x0>,
> +                                <&apps_smmu 0x0c10 0x8>;
> +
> +                       status = "disabled";
> +
> +                       ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                               };
> +
> +                               port@2 {
> +                                       reg = <2>;
> +                               };
> +
> +                               port@3 {
> +                                       reg = <3>;
> +                               };
> +                       };
> +               };
> +
> +               cci: cci@ac4a000 {
> +                       compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       reg = <0 0x0ac4a000 0 0x4000>;
> +                       interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +                       power-domains = <&clock_camcc TITAN_TOP_GDSC>;
> +
> +                       clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_SOC_AHB_CLK>,
> +                               <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> +                               <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> +                               <&clock_camcc CAM_CC_CCI_CLK>,
> +                               <&clock_camcc CAM_CC_CCI_CLK_SRC>;
> +                       clock-names = "camnoc_axi",
> +                               "soc_ahb",
> +                               "slow_ahb_src",
> +                               "cpas_ahb",
> +                               "cci",
> +                               "cci_src";
> +
> +                       assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> +                               <&clock_camcc CAM_CC_CCI_CLK>;
> +                       assigned-clock-rates = <80000000>, <37500000>;
> +
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&cci0_default &cci1_default>;
> +                       pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> +
> +                       status = "disabled";
> +
> +                       cci_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +
> +                       cci_i2c1: i2c-bus@1 {
> +                               reg = <1>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
> +               clock_camcc: clock-controller@ad00000 {
> +                       compatible = "qcom,sdm845-camcc";
> +                       reg = <0 0x0ad00000 0 0x10000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "bi_tcxo";
> +               };
> +
> +               mdss: display-subsystem@ae00000 {
> +                       compatible = "qcom,sdm845-mdss";
> +                       reg = <0 0x0ae00000 0 0x1000>;
> +                       reg-names = "mdss";
> +
> +                       power-domains = <&dispcc MDSS_GDSC>;
> +
> +                       clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +                       clock-names = "iface", "core";
> +
> +                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
> +                                       <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
> +                       interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> +                       iommus = <&apps_smmu 0x880 0x8>,
> +                                <&apps_smmu 0xc80 0x8>;
> +
> +                       status = "disabled";
> +
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +
> +                       mdss_mdp: display-controller@ae01000 {
> +                               compatible = "qcom,sdm845-dpu";
> +                               reg = <0 0x0ae01000 0 0x8f000>,
> +                                     <0 0x0aeb0000 0 0x2008>;
> +                               reg-names = "mdp", "vbif";
> +
> +                               clocks = <&gcc GCC_DISP_AXI_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +                               clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
> +
> +                               assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +                               assigned-clock-rates = <19200000>;
> +                               operating-points-v2 = <&mdp_opp_table>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               dpu_intf0_out: endpoint {
> +                                                       remote-endpoint = <&dp_in>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               dpu_intf1_out: endpoint {
> +                                                       remote-endpoint = <&mdss_dsi0_in>;
> +                                               };
> +                                       };
> +
> +                                       port@2 {
> +                                               reg = <2>;
> +                                               dpu_intf2_out: endpoint {
> +                                                       remote-endpoint = <&mdss_dsi1_in>;
> +                                               };
> +                                       };
> +                               };
> +
> +                               mdp_opp_table: opp-table {
> +                                       compatible = "operating-points-v2";
> +
> +                                       opp-19200000 {
> +                                               opp-hz = /bits/ 64 <19200000>;
> +                                               required-opps = <&rpmhpd_opp_min_svs>;
> +                                       };
> +
> +                                       opp-171428571 {
> +                                               opp-hz = /bits/ 64 <171428571>;
> +                                               required-opps = <&rpmhpd_opp_low_svs>;
> +                                       };
> +
> +                                       opp-344000000 {
> +                                               opp-hz = /bits/ 64 <344000000>;
> +                                               required-opps = <&rpmhpd_opp_svs_l1>;
> +                                       };
> +
> +                                       opp-430000000 {
> +                                               opp-hz = /bits/ 64 <430000000>;
> +                                               required-opps = <&rpmhpd_opp_nom>;
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dp: displayport-controller@ae90000 {
> +                               status = "disabled";
> +                               compatible = "qcom,sdm845-dp";
> +
> +                               reg = <0 0x0ae90000 0 0x200>,
> +                                     <0 0x0ae90200 0 0x200>,
> +                                     <0 0x0ae90400 0 0x600>,
> +                                     <0 0x0ae90a00 0 0x600>,
> +                                     <0 0x0ae91000 0 0x600>;
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <12>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> +                               clock-names = "core_iface", "core_aux", "ctrl_link",
> +                                             "ctrl_link_iface", "stream_pixel";
> +                               assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> +                                                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> +                               assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> +                                                        <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +                               phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> +                               phy-names = "dp";
> +
> +                               operating-points-v2 = <&dp_opp_table>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               dp_in: endpoint {
> +                                                       remote-endpoint = <&dpu_intf0_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               dp_out: endpoint { };
> +                                       };
> +                               };
> +
> +                               dp_opp_table: opp-table {
> +                                       compatible = "operating-points-v2";
> +
> +                                       opp-162000000 {
> +                                               opp-hz = /bits/ 64 <162000000>;
> +                                               required-opps = <&rpmhpd_opp_low_svs>;
> +                                       };
> +
> +                                       opp-270000000 {
> +                                               opp-hz = /bits/ 64 <270000000>;
> +                                               required-opps = <&rpmhpd_opp_svs>;
> +                                       };
> +
> +                                       opp-540000000 {
> +                                               opp-hz = /bits/ 64 <540000000>;
> +                                               required-opps = <&rpmhpd_opp_svs_l1>;
> +                                       };
> +
> +                                       opp-810000000 {
> +                                               opp-hz = /bits/ 64 <810000000>;
> +                                               required-opps = <&rpmhpd_opp_nom>;
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0: dsi@ae94000 {
> +                               compatible = "qcom,sdm845-dsi-ctrl",
> +                                            "qcom,mdss-dsi-ctrl";
> +                               reg = <0 0x0ae94000 0 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <4>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> +                               clock-names = "byte",
> +                                             "byte_intf",
> +                                             "pixel",
> +                                             "core",
> +                                             "iface",
> +                                             "bus";
> +                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> +                               assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> +                               operating-points-v2 = <&dsi_opp_table>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +
> +                               phys = <&mdss_dsi0_phy>;
> +
> +                               status = "disabled";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_dsi0_in: endpoint {
> +                                                       remote-endpoint = <&dpu_intf1_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdss_dsi0_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0_phy: phy@ae94400 {
> +                               compatible = "qcom,dsi-phy-10nm";
> +                               reg = <0 0x0ae94400 0 0x200>,
> +                                     <0 0x0ae94600 0 0x280>,
> +                                     <0 0x0ae94a00 0 0x1e0>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_phy_lane",
> +                                           "dsi_pll";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&rpmhcc RPMH_CXO_CLK>;
> +                               clock-names = "iface", "ref";
> +
> +                               status = "disabled";
> +                       };
> +
> +                       mdss_dsi1: dsi@ae96000 {
> +                               compatible = "qcom,sdm845-dsi-ctrl",
> +                                            "qcom,mdss-dsi-ctrl";
> +                               reg = <0 0x0ae96000 0 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <5>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&dispcc DISP_CC_MDSS_AXI_CLK>;
> +                               clock-names = "byte",
> +                                             "byte_intf",
> +                                             "pixel",
> +                                             "core",
> +                                             "iface",
> +                                             "bus";
> +                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
> +                               assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
> +
> +                               operating-points-v2 = <&dsi_opp_table>;
> +                               power-domains = <&rpmhpd SDM845_CX>;
> +
> +                               phys = <&mdss_dsi1_phy>;
> +
> +                               status = "disabled";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_dsi1_in: endpoint {
> +                                                       remote-endpoint = <&dpu_intf2_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdss_dsi1_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi1_phy: phy@ae96400 {
> +                               compatible = "qcom,dsi-phy-10nm";
> +                               reg = <0 0x0ae96400 0 0x200>,
> +                                     <0 0x0ae96600 0 0x280>,
> +                                     <0 0x0ae96a00 0 0x10e>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_phy_lane",
> +                                           "dsi_pll";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                                        <&rpmhcc RPMH_CXO_CLK>;
> +                               clock-names = "iface", "ref";
> +
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               gpu: gpu@5000000 {
> +                       compatible = "qcom,adreno-630.2", "qcom,adreno";
> +
> +                       reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
> +                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
> +
> +                       /*
> +                        * Look ma, no clocks! The GPU clocks and power are
> +                        * controlled entirely by the GMU
> +                        */
> +
> +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       iommus = <&adreno_smmu 0>;
> +
> +                       operating-points-v2 = <&gpu_opp_table>;
> +
> +                       qcom,gmu = <&gmu>;
> +
> +                       interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
> +                       interconnect-names = "gfx-mem";
> +
> +                       status = "disabled";
> +
> +                       gpu_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-710000000 {
> +                                       opp-hz = /bits/ 64 <710000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +                                       opp-peak-kBps = <7216000>;
> +                               };
> +
> +                               opp-675000000 {
> +                                       opp-hz = /bits/ 64 <675000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +                                       opp-peak-kBps = <7216000>;
> +                               };
> +
> +                               opp-596000000 {
> +                                       opp-hz = /bits/ 64 <596000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +                                       opp-peak-kBps = <6220000>;
> +                               };
> +
> +                               opp-520000000 {
> +                                       opp-hz = /bits/ 64 <520000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +                                       opp-peak-kBps = <6220000>;
> +                               };
> +
> +                               opp-414000000 {
> +                                       opp-hz = /bits/ 64 <414000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +                                       opp-peak-kBps = <4068000>;
> +                               };
> +
> +                               opp-342000000 {
> +                                       opp-hz = /bits/ 64 <342000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +                                       opp-peak-kBps = <2724000>;
> +                               };
> +
> +                               opp-257000000 {
> +                                       opp-hz = /bits/ 64 <257000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +                                       opp-peak-kBps = <1648000>;
> +                               };
> +                       };
> +               };
> +
> +               adreno_smmu: iommu@5040000 {
> +                       compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +                       reg = <0 0x05040000 0 0x10000>;
> +                       #iommu-cells = <1>;
> +                       #global-interrupts = <2>;
> +                       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> +                       clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +                                <&gcc GCC_GPU_CFG_AHB_CLK>;
> +                       clock-names = "bus", "iface";
> +
> +                       power-domains = <&gpucc GPU_CX_GDSC>;
> +               };
> +
> +               gmu: gmu@506a000 {
> +                       compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
> +
> +                       reg = <0 0x0506a000 0 0x30000>,
> +                             <0 0x0b280000 0 0x10000>,
> +                             <0 0x0b480000 0 0x10000>;
> +                       reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> +
> +                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hfi", "gmu";
> +
> +                       clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> +                                <&gpucc GPU_CC_CXO_CLK>,
> +                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +                       clock-names = "gmu", "cxo", "axi", "memnoc";
> +
> +                       power-domains = <&gpucc GPU_CX_GDSC>,
> +                                       <&gpucc GPU_GX_GDSC>;
> +                       power-domain-names = "cx", "gx";
> +
> +                       iommus = <&adreno_smmu 5>;
> +
> +                       operating-points-v2 = <&gmu_opp_table>;
> +
> +                       status = "disabled";
> +
> +                       gmu_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-400000000 {
> +                                       opp-hz = /bits/ 64 <400000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +                               };
> +
> +                               opp-200000000 {
> +                                       opp-hz = /bits/ 64 <200000000>;
> +                                       opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +                               };
> +                       };
> +               };
> +
> +               dispcc: clock-controller@af00000 {
> +                       compatible = "qcom,sdm845-dispcc";
> +                       reg = <0 0x0af00000 0 0x10000>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> +                                <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> +                                <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
> +                                <&mdss_dsi0_phy 0>,
> +                                <&mdss_dsi0_phy 1>,
> +                                <&mdss_dsi1_phy 0>,
> +                                <&mdss_dsi1_phy 1>,
> +                                <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> +                                <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +                       clock-names = "bi_tcxo",
> +                                     "gcc_disp_gpll0_clk_src",
> +                                     "gcc_disp_gpll0_div_clk_src",
> +                                     "dsi0_phy_pll_out_byteclk",
> +                                     "dsi0_phy_pll_out_dsiclk",
> +                                     "dsi1_phy_pll_out_byteclk",
> +                                     "dsi1_phy_pll_out_dsiclk",
> +                                     "dp_link_clk_divsel_ten",
> +                                     "dp_vco_divided_clk_src_mux";
>                         #clock-cells = <1>;
>                         #reset-cells = <1>;
>                         #power-domain-cells = <1>;
>                 };
>
> -               tlmm: pinctrl@3400000 {
> -                       compatible = "qcom,sdm845-pinctrl";
> -                       reg = <0x3400000 0xc00000>;
> -                       gpio-count = <150>;
> -                       gpio-controller;
> -                       #gpio-cells = <2>;
> -                       gpio-ranges = <&tlmm 0 0 150>;
> +               pdc_intc: interrupt-controller@b220000 {
> +                       compatible = "qcom,sdm845-pdc", "qcom,pdc";
> +                       reg = <0 0x0b220000 0 0x30000>;
> +                       qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
> +                       #interrupt-cells = <2>;
> +                       interrupt-parent = <&intc>;
> +                       interrupt-controller;
> +               };
>
> -                       /* DEBUG UART */
> -                       qup_uart9: qup-uart9-default {
> -                               pins = "GPIO_4", "GPIO_5";
> -                               function = "qup9";
> +               pdc_reset: reset-controller@b2e0000 {
> +                       compatible = "qcom,sdm845-pdc-global";
> +                       reg = <0 0x0b2e0000 0 0x20000>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               tsens0: thermal-sensor@c263000 {
> +                       compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
> +                       reg = <0 0x0c263000 0 0x1ff>, /* TM */
> +                             <0 0x0c222000 0 0x1ff>; /* SROT */
> +                       #qcom,sensors = <13>;
> +                       interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow", "critical";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               tsens1: thermal-sensor@c265000 {
> +                       compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
> +                       reg = <0 0x0c265000 0 0x1ff>, /* TM */
> +                             <0 0x0c223000 0 0x1ff>; /* SROT */
> +                       #qcom,sensors = <8>;
> +                       interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow", "critical";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               aoss_reset: reset-controller@c2a0000 {
> +                       compatible = "qcom,sdm845-aoss-cc";
> +                       reg = <0 0x0c2a0000 0 0x31000>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               aoss_qmp: power-management@c300000 {
> +                       compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
> +                       reg = <0 0x0c300000 0 0x400>;
> +                       interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
> +                       mboxes = <&apss_shared 0>;
> +
> +                       #clock-cells = <0>;
> +
> +                       cx_cdev: cx {
> +                               #cooling-cells = <2>;
> +                       };
> +
> +                       ebi_cdev: ebi {
> +                               #cooling-cells = <2>;
>                         };
>                 };
>
> -               qupv3_id_1: geniqup@ac0000 {
> -                       compatible = "qcom,geni-se-qup";
> -                       reg = <0x00ac0000 0x6000>;
> +               sram@c3f0000 {
> +                       compatible = "qcom,sdm845-rpmh-stats";
> +                       reg = <0 0x0c3f0000 0 0x400>;
> +               };
> +
> +               spmi_bus: spmi@c440000 {
> +                       compatible = "qcom,spmi-pmic-arb";
> +                       reg = <0 0x0c440000 0 0x1100>,
> +                             <0 0x0c600000 0 0x2000000>,
> +                             <0 0x0e600000 0 0x100000>,
> +                             <0 0x0e700000 0 0xa0000>,
> +                             <0 0x0c40a000 0 0x26000>;
> +                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +                       interrupt-names = "periph_irq";
> +                       interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,ee = <0>;
> +                       qcom,channel = <0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <0>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <4>;
> +               };
> +
> +               sram@146bf000 {
> +                       compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
> +                       reg = <0 0x146bf000 0 0x1000>;
> +
>                         #address-cells = <1>;
>                         #size-cells = <1>;
> -                       ranges;
>
> -                       uart9: serial@a84000 {
> -                               compatible = "qcom,geni-debug-uart";
> -                               reg = <0xa84000 0x4000>;
> -                               clock-names = "se";
> -                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> -                               pinctrl-names = "default";
> -                               pinctrl-0 = <&qup_uart9>;
> +                       ranges = <0 0 0x146bf000 0x1000>;
> +
> +                       pil-reloc@94c {
> +                               compatible = "qcom,pil-reloc-info";
> +                               reg = <0x94c 0xc8>;
>                         };
>                 };
>
> -               spmi@c440000 {
> -                       compatible = "qcom,spmi-pmic-arb";
> -                       reg = <0xc440000 0x1100>,
> -                             <0xc600000 0x2000000>,
> -                             <0xe600000 0x100000>;
> -                       reg-names = "core", "chnls", "obsrvr";
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x1>;
> +               apps_smmu: iommu@15000000 {
> +                       compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> +                       reg = <0 0x15000000 0 0x80000>;
> +                       #iommu-cells = <2>;
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
> +               };
>
> -                       qcom,revid@100 {
> -                               compatible = "qcom,qpnp-revid";
> -                               reg = <0x100 0x100>;
> +               lpasscc: clock-controller@17014000 {
> +                       compatible = "qcom,sdm845-lpasscc";
> +                       reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
> +                       reg-names = "cc", "qdsp6ss";
> +                       #clock-cells = <1>;
> +                       status = "disabled";
> +               };
> +
> +               gladiator_noc: interconnect@17900000 {
> +                       compatible = "qcom,sdm845-gladiator-noc";
> +                       reg = <0 0x17900000 0 0xd080>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               watchdog@17980000 {
> +                       compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
> +                       reg = <0 0x17980000 0 0x1000>;
> +                       clocks = <&sleep_clk>;
> +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               apss_shared: mailbox@17990000 {
> +                       compatible = "qcom,sdm845-apss-shared";
> +                       reg = <0 0x17990000 0 0x1000>;
> +                       #mbox-cells = <1>;
> +               };
> +
> +               apps_rsc: rsc@179c0000 {
> +                       label = "apps_rsc";
> +                       compatible = "qcom,rpmh-rsc";
> +                       reg = <0 0x179c0000 0 0x10000>,
> +                             <0 0x179d0000 0 0x10000>,
> +                             <0 0x179e0000 0 0x10000>;
> +                       reg-names = "drv-0", "drv-1", "drv-2";
> +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,tcs-offset = <0xd00>;
> +                       qcom,drv-id = <2>;
> +                       qcom,tcs-config = <ACTIVE_TCS  2>,
> +                                         <SLEEP_TCS   3>,
> +                                         <WAKE_TCS    3>,
> +                                         <CONTROL_TCS 1>;
> +                       power-domains = <&CLUSTER_PD>;
> +
> +                       apps_bcm_voter: bcm-voter {
> +                               compatible = "qcom,bcm-voter";
>                         };
>
> -                       pmic0: pm8998@0 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x0 0x1>;
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x1>;
> -
> -                               pm8998_pon: pon@800 {
> -                                       compatible = "qcom,pm8998-pon";
> -
> -                                       reg = <0x800 0x100>;
> -                                       mode-bootloader = <0x2>;
> -                                       mode-recovery = <0x1>;
> -
> -                                       pm8998_pwrkey: pwrkey {
> -                                               compatible = "qcom,pm8941-pwrkey";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                       };
> -
> -                                       pm8998_resin: resin {
> -                                               compatible = "qcom,pm8941-resin";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                               status = "disabled";
> -                                       };
> -                               };
> -
> -                               pm8998_gpios: pm8998_gpios@c000 {
> -                                       compatible = "qcom,pm8998-gpio";
> -                                       reg = <0xc000 0x1a00>;
> -                                       gpio-controller;
> -                                       gpio-ranges = <&pm8998_gpios 0 0 26>;
> -                                       #gpio-cells = <2>;
> -                               };
> +                       rpmhcc: clock-controller {
> +                               compatible = "qcom,sdm845-rpmh-clk";
> +                               #clock-cells = <1>;
> +                               clock-names = "xo";
> +                               clocks = <&xo_board>;
>                         };
>
> -                       pmic1: pm8998@1 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x1 0x0>;
> -                               #address-cells = <0x2>;
> -                               #size-cells = <0x0>;
> +                       rpmhpd: power-controller {
> +                               compatible = "qcom,sdm845-rpmhpd";
> +                               #power-domain-cells = <1>;
> +                               operating-points-v2 = <&rpmhpd_opp_table>;
> +
> +                               rpmhpd_opp_table: opp-table {
> +                                       compatible = "operating-points-v2";
> +
> +                                       rpmhpd_opp_ret: opp1 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> +                                       };
> +
> +                                       rpmhpd_opp_min_svs: opp2 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +                                       };
> +
> +                                       rpmhpd_opp_low_svs: opp3 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +                                       };
> +
> +                                       rpmhpd_opp_svs: opp4 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +                                       };
> +
> +                                       rpmhpd_opp_svs_l1: opp5 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +                                       };
> +
> +                                       rpmhpd_opp_nom: opp6 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +                                       };
> +
> +                                       rpmhpd_opp_nom_l1: opp7 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +                                       };
> +
> +                                       rpmhpd_opp_nom_l2: opp8 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> +                                       };
> +
> +                                       rpmhpd_opp_turbo: opp9 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +                                       };
> +
> +                                       rpmhpd_opp_turbo_l1: opp10 {
> +                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               intc: interrupt-controller@17a00000 {
> +                       compatible = "arm,gic-v3";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       #interrupt-cells = <3>;
> +                       interrupt-controller;
> +                       reg = <0 0x17a00000 0 0x10000>,     /* GICD */
> +                             <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
> +                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       msi-controller@17a40000 {
> +                               compatible = "arm,gic-v3-its";
> +                               msi-controller;
> +                               #msi-cells = <1>;
> +                               reg = <0 0x17a40000 0 0x20000>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               slimbam: dma-controller@17184000 {
> +                       compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +                       qcom,controlled-remotely;
> +                       reg = <0 0x17184000 0 0x2a000>;
> +                       num-channels = <31>;
> +                       interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> +                       #dma-cells = <1>;
> +                       qcom,ee = <1>;
> +                       qcom,num-ees = <2>;
> +                       iommus = <&apps_smmu 0x1806 0x0>;
> +               };
> +
> +               timer@17c90000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0 0 0 0x20000000>;
> +                       compatible = "arm,armv7-timer-mem";
> +                       reg = <0 0x17c90000 0 0x1000>;
> +
> +                       frame@17ca0000 {
> +                               frame-number = <0>;
> +                               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17ca0000 0x1000>,
> +                                     <0x17cb0000 0x1000>;
> +                       };
> +
> +                       frame@17cc0000 {
> +                               frame-number = <1>;
> +                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17cc0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@17cd0000 {
> +                               frame-number = <2>;
> +                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17cd0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@17ce0000 {
> +                               frame-number = <3>;
> +                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17ce0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@17cf0000 {
> +                               frame-number = <4>;
> +                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17cf0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@17d00000 {
> +                               frame-number = <5>;
> +                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17d00000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@17d10000 {
> +                               frame-number = <6>;
> +                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x17d10000 0x1000>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               osm_l3: interconnect@17d41000 {
> +                       compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
> +                       reg = <0 0x17d41000 0 0x1400>;
> +
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> +                       clock-names = "xo", "alternate";
> +
> +                       #interconnect-cells = <1>;
> +               };
> +
> +               cpufreq_hw: cpufreq@17d43000 {
> +                       compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
> +                       reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
> +                       reg-names = "freq-domain0", "freq-domain1";
> +
> +                       interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
> +
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> +                       clock-names = "xo", "alternate";
> +
> +                       #freq-domain-cells = <1>;
> +                       #clock-cells = <1>;
> +               };
> +
> +               wifi: wifi@18800000 {
> +                       compatible = "qcom,wcn3990-wifi";
> +                       status = "disabled";
> +                       reg = <0 0x18800000 0 0x800000>;
> +                       reg-names = "membase";
> +                       memory-region = <&wlan_msa_mem>;
> +                       clock-names = "cxo_ref_clk_pin";
> +                       clocks = <&rpmhcc RPMH_RF_CLK2>;
> +                       interrupts =
> +                               <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
> +                       iommus = <&apps_smmu 0x0040 0x1>;
> +               };
> +       };
> +
> +       sound: sound {
> +       };
> +
> +       thermal-zones {
> +               cpu0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 1>;
> +
> +                       trips {
> +                               cpu0_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu0_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu0_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 2>;
> +
> +                       trips {
> +                               cpu1_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu1_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu1_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 3>;
> +
> +                       trips {
> +                               cpu2_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu2_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu2_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu3-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 4>;
> +
> +                       trips {
> +                               cpu3_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu3_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu3_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu4-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 7>;
> +
> +                       trips {
> +                               cpu4_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu4_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu4_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu5-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 8>;
> +
> +                       trips {
> +                               cpu5_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu5_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu5_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu6-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 9>;
> +
> +                       trips {
> +                               cpu6_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu6_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu6_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu7-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 10>;
> +
> +                       trips {
> +                               cpu7_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu7_alert1: trip-point1 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu7_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <1000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               aoss0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 0>;
> +
> +                       trips {
> +                               aoss0_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               cluster0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 5>;
> +
> +                       trips {
> +                               cluster0_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cluster0_crit: cluster0_crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cluster1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 6>;
> +
> +                       trips {
> +                               cluster1_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cluster1_crit: cluster1_crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               gpu-top-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 11>;
> +
> +                       trips {
> +                               gpu1_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               gpu-bottom-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 12>;
> +
> +                       trips {
> +                               gpu2_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               aoss1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 0>;
> +
> +                       trips {
> +                               aoss1_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               q6-modem-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 1>;
> +
> +                       trips {
> +                               q6_modem_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               mem-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 2>;
> +
> +                       trips {
> +                               mem_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               wlan-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 3>;
> +
> +                       trips {
> +                               wlan_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               q6-hvx-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 4>;
> +
> +                       trips {
> +                               q6_hvx_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               camera-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 5>;
> +
> +                       trips {
> +                               camera_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               video-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 6>;
> +
> +                       trips {
> +                               video_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               modem-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 7>;
> +
> +                       trips {
> +                               modem_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
>                         };
>                 };
>         };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> +       };
>  };
> diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi
> deleted file mode 100644
> index 55c6d18412ba..000000000000
> --- a/arch/arm/dts/starqltechn-uboot.dtsi
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> - *
> - */
> -
> -/
> -{
> -       framebuffer@9D400000 {
> -               bootph-all;
> -       };
> -       soc {
> -               bootph-all;
> -               serial@a84000 {
> -                       bootph-all;
> -               };
> -               clock-controller@100000 {
> -                       bootph-all;
> -               };
> -               pinctrl@3400000 {
> -                       bootph-all;
> -               };
> -       };
> -};
> -
> diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
> deleted file mode 100644
> index 0842e19adb60..000000000000
> --- a/arch/arm/dts/starqltechn.dts
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Samsung S9 SM-G9600 (starqltechn) board device tree source
> - *
> - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
> - *
> - */
> -
> -/dts-v1/;
> -
> -#include "sdm845.dtsi"
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/input/input.h>
> -
> -/ {
> -       model = "Samsung S9 (SM-G9600)";
> -       compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
> -       #address-cells = <2>;
> -       #size-cells = <2>;
> -
> -       chosen {
> -               stdout-path = "serial0:921600n8";
> -       };
> -
> -       aliases {
> -               serial0 = &uart9;
> -       };
> -
> -       memory {
> -               device_type = "memory";
> -               reg = <0 0x80000000 0 0xfe1bffff>;
> -       };
> -
> -       psci {
> -               compatible = "arm,psci-1.0";
> -               method = "smc";
> -       };
> -
> -       framebuffer: framebuffer@9D400000 {
> -               compatible = "simple-framebuffer";
> -               reg = <0 0x9D400000 0 (2960 * 1440 * 4)>;//2400000
> -               width = <1440>;
> -               height = <2960>;
> -               stride = <(1440 * 4)>;
> -               format = "a8r8g8b8";
> -       };
> -
> -       soc: soc {
> -               serial@a84000 {
> -                       status = "okay";
> -               };
> -       };
> -};
> -
> -&pm8998_resin {
> -       status = "okay";
> -};
> -
> -&tlmm {
> -       muic_i2c: muic-i2c-n {
> -               pins = "GPIO_33", "GPIO_34";
> -               drive-strength = <0x2>;
> -               function = "gpio";
> -               bias-disable;
> -       };
> -};
> -
> -#include "starqltechn-uboot.dtsi"
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index a84f5aee444e..222db6448aba 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -2,7 +2,7 @@ CONFIG_ARM=y
>  CONFIG_SKIP_LOWLEVEL_INIT=y
>  CONFIG_POSITION_INDEPENDENT=y
>  CONFIG_ARCH_SNAPDRAGON=y
> -CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
> +CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c"
>  CONFIG_SYS_LOAD_ADDR=0x0
>  CONFIG_BUTTON_CMD=y
>  CONFIG_FIT=y
>
> --
> 2.43.1
>

Re: [PATCH v4 32/39] dts: msm8916: replace with upstream DTS

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Drop the U-Boot specific dragonboard410c.dts in favour of the upstream
> msm8916-sbc.dts. No additional changes are needed to this DTS for U-Boot
> support.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/Makefile                   |    2 +-
>  arch/arm/dts/apq8016-sbc-u-boot.dtsi    |   20 +
>  arch/arm/dts/apq8016-sbc.dts            |  729 +++++++++
>  arch/arm/dts/dragonboard410c-uboot.dtsi |   44 -
>  arch/arm/dts/dragonboard410c.dts        |  221 ---
>  arch/arm/dts/msm8916.dtsi               | 2702 +++++++++++++++++++++++++++++++
>  configs/dragonboard410c_defconfig       |    2 +-
>  7 files changed, 3453 insertions(+), 267 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 3f4e49b3e445..9ba1a94da5d0 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -631,7 +631,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
>
>  dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
>
> -dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
> +dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
>         dragonboard820c.dtb \
>         sdm845-db845c.dtb \
>         sdm845-samsung-starqltechn.dtb \
> diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
> new file mode 100644
> index 000000000000..585d54d29623
> --- /dev/null
> +++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024, Linaro Ltd.
> + */
> +
> +/ {
> +       /* When running as a first-stage bootloader this isn't filled in automatically */
> +       memory@80000000 {
> +               reg = <0 0x80000000 0 0x3da00000>;
> +       };
> +};
> +
> +/*
> + * When running as a first-stage bootloader, we need to re-configure the UART pins
> + * because SBL de-initialises them. Indicate that the UART pins should be configured
> + * during all boot stages.
> + */
> +&blsp_uart2_default {
> +       bootph-all;
> +};
> diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-sbc.dts
> new file mode 100644
> index 000000000000..9ffad7d1f2b6
> --- /dev/null
> +++ b/arch/arm/dts/apq8016-sbc.dts
> @@ -0,0 +1,729 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "msm8916-pm8916.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
> +#include <dt-bindings/sound/apq8016-lpass.h>
> +
> +/ {
> +       model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
> +       compatible = "qcom,apq8016-sbc", "qcom,apq8016";
> +
> +       aliases {
> +               mmc0 = &sdhc_1; /* eMMC */
> +               mmc1 = &sdhc_2; /* SD card */
> +               serial0 = &blsp_uart2;
> +               serial1 = &blsp_uart1;
> +               usid0 = &pm8916_0;
> +               i2c0 = &blsp_i2c2;
> +               i2c1 = &blsp_i2c6;
> +               i2c3 = &blsp_i2c4;
> +               spi0 = &blsp_spi5;
> +               spi1 = &blsp_spi3;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0";
> +       };
> +
> +       reserved-memory {
> +               ramoops@bff00000 {
> +                       compatible = "ramoops";
> +                       reg = <0x0 0xbff00000 0x0 0x100000>;
> +
> +                       record-size = <0x20000>;
> +                       console-size = <0x20000>;
> +                       ftrace-size = <0x20000>;
> +               };
> +       };
> +
> +       usb2513 {
> +               compatible = "smsc,usb3503";
> +               reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
> +               initial-mode = <1>;
> +       };
> +
> +       usb_id: usb-id {
> +               compatible = "linux,extcon-usb-gpio";
> +               id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&usb_id_default>;
> +       };
> +
> +       hdmi-out {
> +               compatible = "hdmi-connector";
> +               type = "a";
> +
> +               port {
> +                       hdmi_con: endpoint {
> +                               remote-endpoint = <&adv7533_out>;
> +                       };
> +               };
> +       };
> +
> +       gpio-keys {
> +               compatible = "gpio-keys";
> +               autorepeat;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&msm_key_volp_n_default>;
> +
> +               button {
> +                       label = "Volume Up";
> +                       linux,code = <KEY_VOLUMEUP>;
> +                       gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
> +               };
> +       };
> +
> +       leds {
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&tlmm_leds>,
> +                           <&pm8916_gpios_leds>,
> +                           <&pm8916_mpps_leds>;
> +
> +               compatible = "gpio-leds";
> +
> +               led@1 {
> +                       label = "apq8016-sbc:green:user1";
> +                       function = LED_FUNCTION_HEARTBEAT;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "heartbeat";
> +                       default-state = "off";
> +               };
> +
> +               led@2 {
> +                       label = "apq8016-sbc:green:user2";
> +                       function = LED_FUNCTION_DISK_ACTIVITY;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "mmc0";
> +                       default-state = "off";
> +               };
> +
> +               led@3 {
> +                       label = "apq8016-sbc:green:user3";
> +                       function = LED_FUNCTION_DISK_ACTIVITY;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "mmc1";
> +                       default-state = "off";
> +               };
> +
> +               led@4 {
> +                       label = "apq8016-sbc:green:user4";
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "none";
> +                       panic-indicator;
> +                       default-state = "off";
> +               };
> +
> +               led@5 {
> +                       label = "apq8016-sbc:yellow:wlan";
> +                       function = LED_FUNCTION_WLAN;
> +                       color = <LED_COLOR_ID_YELLOW>;
> +                       gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "phy0tx";
> +                       default-state = "off";
> +               };
> +
> +               led@6 {
> +                       label = "apq8016-sbc:blue:bt";
> +                       function = LED_FUNCTION_BLUETOOTH;
> +                       color = <LED_COLOR_ID_BLUE>;
> +                       gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "bluetooth-power";
> +                       default-state = "off";
> +               };
> +       };
> +};
> +
> +&blsp_i2c2 {
> +       /* On Low speed expansion: LS-I2C0 */
> +       status = "okay";
> +};
> +
> +&blsp_i2c4 {
> +       /* On High speed expansion: HS-I2C2 */
> +       status = "okay";
> +
> +       adv_bridge: bridge@39 {
> +               status = "okay";
> +
> +               compatible = "adi,adv7533";
> +               reg = <0x39>;
> +
> +               interrupt-parent = <&tlmm>;
> +               interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
> +
> +               adi,dsi-lanes = <4>;
> +               clocks = <&rpmcc RPM_SMD_BB_CLK2>;
> +               clock-names = "cec";
> +
> +               pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
> +
> +               avdd-supply = <&pm8916_l6>;
> +               a2vdd-supply = <&pm8916_l6>;
> +               dvdd-supply = <&pm8916_l6>;
> +               pvdd-supply = <&pm8916_l6>;
> +               v1p2-supply = <&pm8916_l6>;
> +               v3p3-supply = <&pm8916_l17>;
> +
> +               pinctrl-names = "default","sleep";
> +               pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
> +               pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
> +               #sound-dai-cells = <1>;
> +
> +               ports {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       port@0 {
> +                               reg = <0>;
> +                               adv7533_in: endpoint {
> +                                       remote-endpoint = <&mdss_dsi0_out>;
> +                               };
> +                       };
> +
> +                       port@1 {
> +                               reg = <1>;
> +                               adv7533_out: endpoint {
> +                                       remote-endpoint = <&hdmi_con>;
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&blsp_i2c6 {
> +       /* On Low speed expansion: LS-I2C1 */
> +       status = "okay";
> +};
> +
> +&blsp_spi3 {
> +       /* On High speed expansion: HS-SPI1 */
> +       status = "okay";
> +};
> +
> +&blsp_spi5 {
> +       /* On Low speed expansion: LS-SPI0 */
> +       status = "okay";
> +};
> +
> +&blsp_uart1 {
> +       status = "okay";
> +       label = "LS-UART0";
> +};
> +
> +&blsp_uart2 {
> +       status = "okay";
> +       label = "LS-UART1";
> +};
> +
> +&camss {
> +       status = "okay";
> +};
> +
> +&gpu {
> +       status = "okay";
> +};
> +
> +&lpass {
> +       status = "okay";
> +};
> +
> +&lpass_codec {
> +       status = "okay";
> +};
> +
> +&mba_mem {
> +       status = "okay";
> +};
> +
> +&mdss {
> +       status = "okay";
> +};
> +
> +&mdss_dsi0_out {
> +       data-lanes = <0 1 2 3>;
> +       remote-endpoint = <&adv7533_in>;
> +};
> +
> +&mpss {
> +       status = "okay";
> +
> +       firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn";
> +};
> +
> +&mpss_mem {
> +       status = "okay";
> +       reg = <0x0 0x86800000 0x0 0x2b00000>;
> +};
> +
> +&pm8916_codec {
> +       status = "okay";
> +       qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
> +       qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
> +};
> +
> +&pm8916_resin {
> +       status = "okay";
> +       linux,code = <KEY_VOLUMEDOWN>;
> +};
> +
> +&pm8916_rpm_regulators {
> +       /*
> +        * The 96Boards specification expects a 1.8V power rail on the low-speed
> +        * expansion connector that is able to provide at least 0.18W / 100 mA.
> +        * L15/L16 are connected in parallel to provide 55 mA each. A minimum load
> +        * must be specified to ensure the regulators are not put in LPM where they
> +        * would only provide 5 mA.
> +        */
> +       pm8916_l15: l15 {
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +               regulator-system-load = <50000>;
> +               regulator-allow-set-load;
> +               regulator-always-on;
> +       };
> +       pm8916_l16: l16 {
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +               regulator-system-load = <50000>;
> +               regulator-allow-set-load;
> +               regulator-always-on;
> +       };
> +
> +       pm8916_l17: l17 {
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +       };
> +};
> +
> +&sdhc_1 {
> +       status = "okay";
> +};
> +
> +&sdhc_2 {
> +       status = "okay";
> +
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
> +       pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
> +
> +       cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
> +};
> +
> +&sound {
> +       status = "okay";
> +
> +       pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
> +       pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
> +       pinctrl-names = "default", "sleep";
> +       model = "DB410c";
> +       audio-routing =
> +               "AMIC2", "MIC BIAS Internal2",
> +               "AMIC3", "MIC BIAS External1";
> +
> +       quaternary-dai-link {
> +               link-name = "ADV7533";
> +               cpu {
> +                       sound-dai = <&lpass MI2S_QUATERNARY>;
> +               };
> +               codec {
> +                       sound-dai = <&adv_bridge 0>;
> +               };
> +       };
> +
> +       primary-dai-link {
> +               link-name = "WCD";
> +               cpu {
> +                       sound-dai = <&lpass MI2S_PRIMARY>;
> +               };
> +               codec {
> +                       sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
> +               };
> +       };
> +
> +       tertiary-dai-link {
> +               link-name = "WCD-Capture";
> +               cpu {
> +                       sound-dai = <&lpass MI2S_TERTIARY>;
> +               };
> +               codec {
> +                       sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
> +               };
> +       };
> +};
> +
> +&usb {
> +       status = "okay";
> +       extcon = <&usb_id>, <&usb_id>;
> +
> +       pinctrl-names = "default", "device";
> +       pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
> +       pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
> +};
> +
> +&usb_hs_phy {
> +       extcon = <&usb_id>;
> +};
> +
> +&venus {
> +       status = "okay";
> +};
> +
> +&venus_mem {
> +       status = "okay";
> +};
> +
> +&wcnss {
> +       status = "okay";
> +       firmware-name = "qcom/apq8016/wcnss.mbn";
> +};
> +
> +&wcnss_ctrl {
> +       firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
> +};
> +
> +&wcnss_iris {
> +       compatible = "qcom,wcn3620";
> +};
> +
> +&wcnss_mem {
> +       status = "okay";
> +};
> +
> +/* Enable CoreSight */
> +&cti0 { status = "okay"; };
> +&cti1 { status = "okay"; };
> +&cti12 { status = "okay"; };
> +&cti13 { status = "okay"; };
> +&cti14 { status = "okay"; };
> +&cti15 { status = "okay"; };
> +&debug0 { status = "okay"; };
> +&debug1 { status = "okay"; };
> +&debug2 { status = "okay"; };
> +&debug3 { status = "okay"; };
> +&etf { status = "okay"; };
> +&etm0 { status = "okay"; };
> +&etm1 { status = "okay"; };
> +&etm2 { status = "okay"; };
> +&etm3 { status = "okay"; };
> +&etr { status = "okay"; };
> +&funnel0 { status = "okay"; };
> +&funnel1 { status = "okay"; };
> +&replicator { status = "okay"; };
> +&stm { status = "okay"; };
> +&tpiu { status = "okay"; };
> +
> +/*
> + * 2mA drive strength is not enough when connecting multiple
> + * I2C devices with different pull up resistors.
> + */
> +&blsp_i2c2_default {
> +       drive-strength = <16>;
> +};
> +
> +&blsp_i2c4_default {
> +       drive-strength = <16>;
> +};
> +
> +&blsp_i2c6_default {
> +       drive-strength = <16>;
> +};
> +
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + *         NC = not connected (pin out but not routed from the chip to
> + *              anything the board)
> + *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + *         LSEC = Low Speed External Connector
> + *         HSEC = High Speed External Connector
> + *
> + * Line names are taken from the schematic "DragonBoard410c"
> + * dated monday, august 31, 2015. Page 5 in particular.
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
> +&tlmm {
> +       gpio-line-names =
> +               "[UART0_TX]", /* GPIO_0, LSEC pin 5 */
> +               "[UART0_RX]", /* GPIO_1, LSEC pin 7 */
> +               "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
> +               "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
> +               "[UART1_TX]", /* GPIO_4, LSEC pin 11 */
> +               "[UART1_RX]", /* GPIO_5, LSEC pin 13 */
> +               "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
> +               "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
> +               "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
> +               "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
> +               "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
> +               "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
> +               "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
> +               "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
> +               "[I2C3_SDA]", /* HSEC pin 38 */
> +               "[I2C3_SCL]", /* HSEC pin 36 */
> +               "[SPI0_MOSI]", /* LSEC pin 14 */
> +               "[SPI0_MISO]", /* LSEC pin 10 */
> +               "[SPI0_CS_N]", /* LSEC pin 12 */
> +               "[SPI0_CLK]", /* LSEC pin 8 */
> +               "HDMI_HPD_N", /* GPIO 20 */
> +               "USR_LED_1_CTRL",
> +               "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
> +               "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
> +               "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
> +               "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
> +               "[CSI0_MCLK]", /* HSEC pin 15 */
> +               "[CSI1_MCLK]", /* HSEC pin 17 */
> +               "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
> +               "[I2C2_SDA]", /* HSEC pin 34 */
> +               "[I2C2_SCL]", /* HSEC pin 32 */
> +               "DSI2HDMI_INT_N",
> +               "DSI_SW_SEL_APQ",
> +               "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
> +               "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
> +               "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
> +               "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
> +               "FORCED_USB_BOOT",
> +               "SD_CARD_DET_N",
> +               "[WCSS_BT_SSBI]",
> +               "[WCSS_WLAN_DATA_2]", /* GPIO 40 */
> +               "[WCSS_WLAN_DATA_1]",
> +               "[WCSS_WLAN_DATA_0]",
> +               "[WCSS_WLAN_SET]",
> +               "[WCSS_WLAN_CLK]",
> +               "[WCSS_FM_SSBI]",
> +               "[WCSS_FM_SDI]",
> +               "[WCSS_BT_DAT_CTL]",
> +               "[WCSS_BT_DAT_STB]",
> +               "NC",
> +               "NC", /* GPIO 50 */
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC", /* GPIO 60 */
> +               "NC",
> +               "NC",
> +               "[CDC_PDM0_CLK]",
> +               "[CDC_PDM0_SYNC]",
> +               "[CDC_PDM0_TX0]",
> +               "[CDC_PDM0_RX0]",
> +               "[CDC_PDM0_RX1]",
> +               "[CDC_PDM0_RX2]",
> +               "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
> +               "NC", /* GPIO 70 */
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC", /* GPIO 74 */
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "BOOT_CONFIG_0", /* GPIO 80 */
> +               "BOOT_CONFIG_1",
> +               "BOOT_CONFIG_2",
> +               "BOOT_CONFIG_3",
> +               "NC",
> +               "NC",
> +               "BOOT_CONFIG_5",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC", /* GPIO 90 */
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC", /* GPIO 100 */
> +               "NC",
> +               "NC",
> +               "NC",
> +               "SSBI_GPS",
> +               "NC",
> +               "NC",
> +               "KEY_VOLP_N",
> +               "NC",
> +               "NC",
> +               "[LS_EXP_MI2S_WS]", /* GPIO 110 */
> +               "NC",
> +               "NC",
> +               "[LS_EXP_MI2S_SCK]",
> +               "[LS_EXP_MI2S_DATA0]",
> +               "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
> +               "NC",
> +               "[DSI2HDMI_MI2S_WS]",
> +               "[DSI2HDMI_MI2S_SCK]",
> +               "[DSI2HDMI_MI2S_DATA0]",
> +               "USR_LED_2_CTRL", /* GPIO 120 */
> +               "SB_HS_ID";
> +
> +       sdc2_cd_default: sdc2-cd-default-state {
> +               pins = "gpio38";
> +               function = "gpio";
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       tlmm_leds: tlmm-leds-state {
> +               pins = "gpio21", "gpio120";
> +               function = "gpio";
> +
> +               output-low;
> +       };
> +
> +       usb_id_default: usb-id-default-state {
> +               pins = "gpio121";
> +               function = "gpio";
> +
> +               drive-strength = <8>;
> +               bias-pull-up;
> +       };
> +
> +       adv7533_int_active: adv533-int-active-state {
> +               pins = "gpio31";
> +               function = "gpio";
> +
> +               drive-strength = <16>;
> +               bias-disable;
> +       };
> +
> +       adv7533_int_suspend: adv7533-int-suspend-state {
> +               pins = "gpio31";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       adv7533_switch_active: adv7533-switch-active-state {
> +               pins = "gpio32";
> +               function = "gpio";
> +
> +               drive-strength = <16>;
> +               bias-disable;
> +       };
> +
> +       adv7533_switch_suspend: adv7533-switch-suspend-state {
> +               pins = "gpio32";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       msm_key_volp_n_default: msm-key-volp-n-default-state {
> +               pins = "gpio107";
> +               function = "gpio";
> +
> +               drive-strength = <8>;
> +               bias-pull-up;
> +       };
> +};
> +
> +&pm8916_gpios {
> +       gpio-line-names =
> +               "USR_LED_3_CTRL",
> +               "USR_LED_4_CTRL",
> +               "USB_HUB_RESET_N_PM",
> +               "USB_SW_SEL_PM";
> +
> +       usb_hub_reset_pm: usb-hub-reset-pm-state {
> +               pins = "gpio3";
> +               function = PMIC_GPIO_FUNC_NORMAL;
> +
> +               input-disable;
> +               output-high;
> +       };
> +
> +       usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {
> +               pins = "gpio3";
> +               function = PMIC_GPIO_FUNC_NORMAL;
> +
> +               output-low;
> +       };
> +
> +       usb_sw_sel_pm: usb-sw-sel-pm-state {
> +               pins = "gpio4";
> +               function = PMIC_GPIO_FUNC_NORMAL;
> +
> +               power-source = <PM8916_GPIO_VPH>;
> +               input-disable;
> +               output-high;
> +       };
> +
> +       usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {
> +               pins = "gpio4";
> +               function = PMIC_GPIO_FUNC_NORMAL;
> +
> +               power-source = <PM8916_GPIO_VPH>;
> +               input-disable;
> +               output-low;
> +       };
> +
> +       pm8916_gpios_leds: pm8916-gpios-leds-state {
> +               pins = "gpio1", "gpio2";
> +               function = PMIC_GPIO_FUNC_NORMAL;
> +
> +               output-low;
> +       };
> +};
> +
> +&pm8916_mpps {
> +       gpio-line-names =
> +               "VDD_PX_BIAS",
> +               "WLAN_LED_CTRL",
> +               "BT_LED_CTRL",
> +               "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&ls_exp_gpio_f>;
> +
> +       ls_exp_gpio_f: pm8916-mpp4-state {
> +               pins = "mpp4";
> +               function = "digital";
> +
> +               output-low;
> +               power-source = <PM8916_MPP_L5>; /* 1.8V */
> +       };
> +
> +       pm8916_mpps_leds: pm8916-mpps-state {
> +               pins = "mpp2", "mpp3";
> +               function = "digital";
> +
> +               output-low;
> +       };
> +};
> diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi
> deleted file mode 100644
> index cec64bf80f99..000000000000
> --- a/arch/arm/dts/dragonboard410c-uboot.dtsi
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * U-Boot addition to handle Dragonboard 410c pins
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - */
> -
> -/ {
> -
> -       smem {
> -               bootph-all;
> -       };
> -
> -       soc {
> -               bootph-all;
> -
> -               pinctrl@1000000 {
> -                       bootph-all;
> -
> -                       uart {
> -                               bootph-all;
> -                       };
> -               };
> -
> -               qcom,gcc@1800000 {
> -                       bootph-all;
> -               };
> -
> -               serial@78b0000 {
> -                       bootph-all;
> -               };
> -       };
> -};
> -
> -
> -&pm8916_gpios {
> -       usb_hub_reset_pm {
> -               gpios = <&pm8916_gpios 2 0>;
> -       };
> -
> -       usb_sw_sel_pm {
> -               gpios = <&pm8916_gpios 3 0>;
> -       };
> -};
> diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
> deleted file mode 100644
> index 453642b25705..000000000000
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ /dev/null
> @@ -1,221 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm APQ8016 based Dragonboard 410C board device tree source
> - *
> - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> - */
> -
> -/dts-v1/;
> -
> -#include "skeleton64.dtsi"
> -#include <dt-bindings/gpio/gpio.h>
> -
> -/ {
> -       model = "Qualcomm Technologies, Inc. Dragonboard 410c";
> -       compatible = "qcom,apq8016-sbc", "qcom,apq8016";
> -       qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
> -       qcom,board-id = <0x10018 0x0>;
> -       #address-cells = <0x2>;
> -       #size-cells = <0x2>;
> -
> -       aliases {
> -               usb0 = "/soc/ehci@78d9000";
> -       };
> -
> -       memory {
> -               device_type = "memory";
> -               reg = <0 0x80000000 0 0x3da00000>;
> -       };
> -
> -       reserved-memory {
> -               #address-cells = <2>;
> -               #size-cells = <2>;
> -               ranges;
> -
> -               smem_mem: smem_region@86300000 {
> -                       reg = <0x0 0x86300000 0x0 0x100000>;
> -                       no-map;
> -               };
> -       };
> -
> -       chosen {
> -               stdout-path = "/soc/serial@78b0000";
> -       };
> -
> -       smem {
> -               compatible = "qcom,smem";
> -               memory-region = <&smem_mem>;
> -               qcom,rpm-msg-ram = <&rpm_msg_ram>;
> -       };
> -
> -       soc {
> -               #address-cells = <0x1>;
> -               #size-cells = <0x1>;
> -               ranges = <0x0 0x0 0x0 0xffffffff>;
> -               compatible = "simple-bus";
> -
> -               rpm_msg_ram: memory@60000 {
> -                       compatible = "qcom,rpm-msg-ram";
> -                       reg = <0x60000 0x8000>;
> -               };
> -
> -               soc_gpios: pinctrl@1000000 {
> -                       compatible = "qcom,msm8916-pinctrl";
> -                       reg = <0x1000000 0x400000>;
> -                       gpio-controller;
> -                       gpio-count = <122>;
> -                       gpio-bank-name="soc";
> -                       #gpio-cells = <2>;
> -
> -                       blsp1_uart: uart {
> -                               function = "blsp1_uart";
> -                               pins = "GPIO_4", "GPIO_5";
> -                               drive-strength = <8>;
> -                               bias-disable;
> -                       };
> -               };
> -               clkc: qcom,gcc@1800000 {
> -                       compatible = "qcom,gcc-msm8916";
> -                       reg = <0x1800000 0x80000>;
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x0>;
> -                       #clock-cells = <0x1>;
> -               };
> -
> -               serial@78b0000 {
> -                       compatible = "qcom,msm-uartdm-v1.4";
> -                       reg = <0x78b0000 0x200>;
> -                       clocks = <&clkc 4>;
> -                       clock-names = "core";
> -                       pinctrl-names = "uart";
> -                       pinctrl-0 = <&blsp1_uart>;
> -               };
> -
> -               ehci@78d9000 {
> -                       compatible = "qcom,ci-hdrc";
> -                       reg = <0x78d9000 0x400>;
> -                       phys = <&ehci_phy>;
> -
> -                       ulpi {
> -                               usb_hs_phy: phy {
> -                                       compatible = "qcom,usb-hs-phy-msm8916",
> -                                                    "qcom,usb-hs-phy";
> -                                       #phy-cells = <0>;
> -                                       clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> -                                       clock-names = "ref", "sleep";
> -                                       resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
> -                                       reset-names = "phy", "por";
> -                                       qcom,init-seq = /bits/ 8 <0x0 0x44>,
> -                                                                <0x1 0x6b>,
> -                                                                <0x2 0x24>,
> -                                                                <0x3 0x13>;
> -                               };
> -                       };
> -               };
> -
> -               sdhci@07824000 {
> -                       compatible = "qcom,sdhci-msm-v4";
> -                       reg = <0x7824900 0x11c 0x7824000 0x800>;
> -                       bus-width = <0x8>;
> -                       index = <0x0>;
> -                       non-removable;
> -                       clock = <&clkc 0>;
> -                       clock-frequency = <100000000>;
> -               };
> -
> -               sdhci@07864000 {
> -                       compatible = "qcom,sdhci-msm-v4";
> -                       reg = <0x7864900 0x11c 0x7864000 0x800>;
> -                       index = <0x1>;
> -                       bus-width = <0x4>;
> -                       clock = <&clkc 1>;
> -                       clock-frequency = <200000000>;
> -                       cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
> -               };
> -
> -               wcnss {
> -                       bt {
> -                               compatible="qcom,wcnss-bt";
> -                       };
> -
> -                       wifi {
> -                               compatible="qcom,wcnss-wlan";
> -                       };
> -               };
> -
> -               spmi_bus: spmi@200f000 {
> -                       compatible = "qcom,spmi-pmic-arb";
> -                       reg = <0x0200f000 0x001000>,
> -                             <0x02400000 0x400000>,
> -                             <0x02c00000 0x400000>,
> -                             <0x03800000 0x200000>,
> -                             <0x0200a000 0x002100>;
> -                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x1>;
> -                       pmic0: pm8916@0 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x0 0x1>;
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x1>;
> -
> -                               pon@800 {
> -                                       compatible = "qcom,pm8916-pon";
> -                                       reg = <0x800 0x100>;
> -                                       mode-bootloader = <0x2>;
> -                                       mode-recovery = <0x1>;
> -
> -                                       pwrkey {
> -                                               compatible = "qcom,pm8941-pwrkey";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                       };
> -
> -                                       pm8916_resin: resin {
> -                                               compatible = "qcom,pm8941-resin";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                       };
> -                               };
> -
> -                               pm8916_gpios: pm8916_gpios@c000 {
> -                                       compatible = "qcom,pm8916-gpio";
> -                                       reg = <0xc000 0x400>;
> -                                       gpio-controller;
> -                                       gpio-ranges = <&pm8916_gpios 0 0 4>;
> -                                       #gpio-cells = <2>;
> -                               };
> -                       };
> -
> -                       pmic1: pm8916@1 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x1 0x1>;
> -                       };
> -               };
> -       };
> -
> -       leds {
> -               compatible = "gpio-leds";
> -               user1 {
> -                       label = "green:user1";
> -                       gpios = <&soc_gpios 21 0>;
> -               };
> -
> -               user2 {
> -                       label = "green:user2";
> -                       gpios = <&soc_gpios 120 0>;
> -               };
> -
> -               user3 {
> -                       label = "green:user3";
> -                       gpios = <&pm8916_gpios 0 0>;
> -               };
> -
> -               user4 {
> -                       label = "green:user4";
> -                       gpios = <&pm8916_gpios 1 0>;
> -               };
> -       };
> -};
> -
> -#include "dragonboard410c-uboot.dtsi"
> diff --git a/arch/arm/dts/msm8916.dtsi b/arch/arm/dts/msm8916.dtsi
> new file mode 100644
> index 000000000000..4f799b536a92
> --- /dev/null
> +++ b/arch/arm/dts/msm8916.dtsi
> @@ -0,0 +1,2702 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/arm/coresight-cti-dt.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8916.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/interconnect/qcom,msm8916.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/reset/qcom,gcc-msm8916.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the reg */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               tz-apps@86000000 {
> +                       reg = <0x0 0x86000000 0x0 0x300000>;
> +                       no-map;
> +               };
> +
> +               smem@86300000 {
> +                       compatible = "qcom,smem";
> +                       reg = <0x0 0x86300000 0x0 0x100000>;
> +                       no-map;
> +
> +                       hwlocks = <&tcsr_mutex 3>;
> +                       qcom,rpm-msg-ram = <&rpm_msg_ram>;
> +               };
> +
> +               hypervisor@86400000 {
> +                       reg = <0x0 0x86400000 0x0 0x100000>;
> +                       no-map;
> +               };
> +
> +               tz@86500000 {
> +                       reg = <0x0 0x86500000 0x0 0x180000>;
> +                       no-map;
> +               };
> +
> +               reserved@86680000 {
> +                       reg = <0x0 0x86680000 0x0 0x80000>;
> +                       no-map;
> +               };
> +
> +               rmtfs@86700000 {
> +                       compatible = "qcom,rmtfs-mem";
> +                       reg = <0x0 0x86700000 0x0 0xe0000>;
> +                       no-map;
> +
> +                       qcom,client-id = <1>;
> +               };
> +
> +               rfsa@867e0000 {
> +                       reg = <0x0 0x867e0000 0x0 0x20000>;
> +                       no-map;
> +               };
> +
> +               mpss_mem: mpss@86800000 {
> +                       /*
> +                        * The memory region for the mpss firmware is generally
> +                        * relocatable and could be allocated dynamically.
> +                        * However, many firmware versions tend to fail when
> +                        * loaded to some special addresses, so it is hard to
> +                        * define reliable alloc-ranges.
> +                        *
> +                        * alignment = <0x0 0x400000>;
> +                        * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> +                        */
> +                       reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
> +                       no-map;
> +                       status = "disabled";
> +               };
> +
> +               wcnss_mem: wcnss {
> +                       size = <0x0 0x600000>;
> +                       alignment = <0x0 0x100000>;
> +                       alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> +                       no-map;
> +                       status = "disabled";
> +               };
> +
> +               venus_mem: venus {
> +                       size = <0x0 0x500000>;
> +                       alignment = <0x0 0x100000>;
> +                       alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> +                       no-map;
> +                       status = "disabled";
> +               };
> +
> +               mba_mem: mba {
> +                       size = <0x0 0x100000>;
> +                       alignment = <0x0 0x100000>;
> +                       alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> +                       no-map;
> +                       status = "disabled";
> +               };
> +       };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <19200000>;
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <32768>;
> +               };
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x0>;
> +                       next-level-cache = <&L2_0>;
> +                       enable-method = "psci";
> +                       clocks = <&apcs>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       #cooling-cells = <2>;
> +                       power-domains = <&CPU_PD0>;
> +                       power-domain-names = "psci";
> +                       qcom,acc = <&cpu0_acc>;
> +                       qcom,saw = <&cpu0_saw>;
> +               };
> +
> +               CPU1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x1>;
> +                       next-level-cache = <&L2_0>;
> +                       enable-method = "psci";
> +                       clocks = <&apcs>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       #cooling-cells = <2>;
> +                       power-domains = <&CPU_PD1>;
> +                       power-domain-names = "psci";
> +                       qcom,acc = <&cpu1_acc>;
> +                       qcom,saw = <&cpu1_saw>;
> +               };
> +
> +               CPU2: cpu@2 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x2>;
> +                       next-level-cache = <&L2_0>;
> +                       enable-method = "psci";
> +                       clocks = <&apcs>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       #cooling-cells = <2>;
> +                       power-domains = <&CPU_PD2>;
> +                       power-domain-names = "psci";
> +                       qcom,acc = <&cpu2_acc>;
> +                       qcom,saw = <&cpu2_saw>;
> +               };
> +
> +               CPU3: cpu@3 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x3>;
> +                       next-level-cache = <&L2_0>;
> +                       enable-method = "psci";
> +                       clocks = <&apcs>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       #cooling-cells = <2>;
> +                       power-domains = <&CPU_PD3>;
> +                       power-domain-names = "psci";
> +                       qcom,acc = <&cpu3_acc>;
> +                       qcom,saw = <&cpu3_saw>;
> +               };
> +
> +               L2_0: l2-cache {
> +                       compatible = "cache";
> +                       cache-level = <2>;
> +                       cache-unified;
> +               };
> +
> +               idle-states {
> +                       entry-method = "psci";
> +
> +                       CPU_SLEEP_0: cpu-sleep-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "standalone-power-collapse";
> +                               arm,psci-suspend-param = <0x40000002>;
> +                               entry-latency-us = <130>;
> +                               exit-latency-us = <150>;
> +                               min-residency-us = <2000>;
> +                               local-timer-stop;
> +                       };
> +               };
> +
> +               domain-idle-states {
> +
> +                       CLUSTER_RET: cluster-retention {
> +                               compatible = "domain-idle-state";
> +                               arm,psci-suspend-param = <0x41000012>;
> +                               entry-latency-us = <500>;
> +                               exit-latency-us = <500>;
> +                               min-residency-us = <2000>;
> +                       };
> +
> +                       CLUSTER_PWRDN: cluster-gdhs {
> +                               compatible = "domain-idle-state";
> +                               arm,psci-suspend-param = <0x41000032>;
> +                               entry-latency-us = <2000>;
> +                               exit-latency-us = <2000>;
> +                               min-residency-us = <6000>;
> +                       };
> +               };
> +       };
> +
> +       cpu_opp_table: opp-table-cpu {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-200000000 {
> +                       opp-hz = /bits/ 64 <200000000>;
> +               };
> +               opp-400000000 {
> +                       opp-hz = /bits/ 64 <400000000>;
> +               };
> +               opp-800000000 {
> +                       opp-hz = /bits/ 64 <800000000>;
> +               };
> +               opp-998400000 {
> +                       opp-hz = /bits/ 64 <998400000>;
> +               };
> +       };
> +
> +       firmware {
> +               scm: scm {
> +                       compatible = "qcom,scm-msm8916", "qcom,scm";
> +                       clocks = <&gcc GCC_CRYPTO_CLK>,
> +                                <&gcc GCC_CRYPTO_AXI_CLK>,
> +                                <&gcc GCC_CRYPTO_AHB_CLK>;
> +                       clock-names = "core", "bus", "iface";
> +                       #reset-cells = <1>;
> +
> +                       qcom,dload-mode = <&tcsr 0x6100>;
> +               };
> +       };
> +
> +       pmu {
> +               compatible = "arm,cortex-a53-pmu";
> +               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +
> +               CPU_PD0: power-domain-cpu0 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD1: power-domain-cpu1 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD2: power-domain-cpu2 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&CPU_SLEEP_0>;
> +               };
> +
> +               CPU_PD3: power-domain-cpu3 {
> +                       #power-domain-cells = <0>;
> +                       power-domains = <&CLUSTER_PD>;
> +                       domain-idle-states = <&CPU_SLEEP_0>;
> +               };
> +
> +               CLUSTER_PD: power-domain-cluster {
> +                       #power-domain-cells = <0>;
> +                       domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
> +               };
> +       };
> +
> +       rpm: remoteproc {
> +               compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
> +
> +               smd-edge {
> +                       interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> +                       qcom,ipc = <&apcs 8 0>;
> +                       qcom,smd-edge = <15>;
> +
> +                       rpm_requests: rpm-requests {
> +                               compatible = "qcom,rpm-msm8916";
> +                               qcom,smd-channels = "rpm_requests";
> +
> +                               rpmcc: clock-controller {
> +                                       compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
> +                                       #clock-cells = <1>;
> +                                       clocks = <&xo_board>;
> +                                       clock-names = "xo";
> +                               };
> +
> +                               rpmpd: power-controller {
> +                                       compatible = "qcom,msm8916-rpmpd";
> +                                       #power-domain-cells = <1>;
> +                                       operating-points-v2 = <&rpmpd_opp_table>;
> +
> +                                       rpmpd_opp_table: opp-table {
> +                                               compatible = "operating-points-v2";
> +
> +                                               rpmpd_opp_ret: opp1 {
> +                                                       opp-level = <1>;
> +                                               };
> +                                               rpmpd_opp_svs_krait: opp2 {
> +                                                       opp-level = <2>;
> +                                               };
> +                                               rpmpd_opp_svs_soc: opp3 {
> +                                                       opp-level = <3>;
> +                                               };
> +                                               rpmpd_opp_nom: opp4 {
> +                                                       opp-level = <4>;
> +                                               };
> +                                               rpmpd_opp_turbo: opp5 {
> +                                                       opp-level = <5>;
> +                                               };
> +                                               rpmpd_opp_super_turbo: opp6 {
> +                                                       opp-level = <6>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +               };
> +       };
> +
> +       smp2p-hexagon {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <435>, <428>;
> +
> +               interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
> +
> +               qcom,ipc = <&apcs 8 14>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <1>;
> +
> +               hexagon_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               hexagon_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-wcnss {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <451>, <431>;
> +
> +               interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
> +
> +               qcom,ipc = <&apcs 8 18>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <4>;
> +
> +               wcnss_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               wcnss_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smsm {
> +               compatible = "qcom,smsm";
> +
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               qcom,ipc-1 = <&apcs 8 13>;
> +               qcom,ipc-3 = <&apcs 8 19>;
> +
> +               apps_smsm: apps@0 {
> +                       reg = <0>;
> +
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               hexagon_smsm: hexagon@1 {
> +                       reg = <1>;
> +                       interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               wcnss_smsm: wcnss@6 {
> +                       reg = <6>;
> +                       interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       soc: soc@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0 0 0 0xffffffff>;
> +               compatible = "simple-bus";
> +
> +               rng@22000 {
> +                       compatible = "qcom,prng";
> +                       reg = <0x00022000 0x200>;
> +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
> +                       clock-names = "core";
> +               };
> +
> +               restart@4ab000 {
> +                       compatible = "qcom,pshold";
> +                       reg = <0x004ab000 0x4>;
> +               };
> +
> +               qfprom: qfprom@5c000 {
> +                       compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
> +                       reg = <0x0005c000 0x1000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       tsens_base1: base1@d0 {
> +                               reg = <0xd0 0x1>;
> +                               bits = <0 7>;
> +                       };
> +
> +                       tsens_s0_p1: s0-p1@d0 {
> +                               reg = <0xd0 0x2>;
> +                               bits = <7 5>;
> +                       };
> +
> +                       tsens_s0_p2: s0-p2@d1 {
> +                               reg = <0xd1 0x2>;
> +                               bits = <4 5>;
> +                       };
> +
> +                       tsens_s1_p1: s1-p1@d2 {
> +                               reg = <0xd2 0x1>;
> +                               bits = <1 5>;
> +                       };
> +                       tsens_s1_p2: s1-p2@d2 {
> +                               reg = <0xd2 0x2>;
> +                               bits = <6 5>;
> +                       };
> +                       tsens_s2_p1: s2-p1@d3 {
> +                               reg = <0xd3 0x1>;
> +                               bits = <3 5>;
> +                       };
> +
> +                       tsens_s2_p2: s2-p2@d4 {
> +                               reg = <0xd4 0x1>;
> +                               bits = <0 5>;
> +                       };
> +
> +                       // no tsens with hw_id 3
> +
> +                       tsens_s4_p1: s4-p1@d4 {
> +                               reg = <0xd4 0x2>;
> +                               bits = <5 5>;
> +                       };
> +
> +                       tsens_s4_p2: s4-p2@d5 {
> +                               reg = <0xd5 0x1>;
> +                               bits = <2 5>;
> +                       };
> +
> +                       tsens_s5_p1: s5-p1@d5 {
> +                               reg = <0xd5 0x2>;
> +                               bits = <7 5>;
> +                       };
> +
> +                       tsens_s5_p2: s5-p2@d6 {
> +                               reg = <0xd6 0x2>;
> +                               bits = <4 5>;
> +                       };
> +
> +                       tsens_base2: base2@d7 {
> +                               reg = <0xd7 0x1>;
> +                               bits = <1 7>;
> +                       };
> +
> +                       tsens_mode: mode@ef {
> +                               reg = <0xef 0x1>;
> +                               bits = <5 3>;
> +                       };
> +               };
> +
> +               rpm_msg_ram: sram@60000 {
> +                       compatible = "qcom,rpm-msg-ram";
> +                       reg = <0x00060000 0x8000>;
> +               };
> +
> +               sram@290000 {
> +                       compatible = "qcom,msm8916-rpm-stats";
> +                       reg = <0x00290000 0x10000>;
> +               };
> +
> +               bimc: interconnect@400000 {
> +                       compatible = "qcom,msm8916-bimc";
> +                       reg = <0x00400000 0x62000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
> +                                <&rpmcc RPM_SMD_BIMC_A_CLK>;
> +               };
> +
> +               tsens: thermal-sensor@4a9000 {
> +                       compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
> +                       reg = <0x004a9000 0x1000>, /* TM */
> +                             <0x004a8000 0x1000>; /* SROT */
> +
> +                       // no hw_id 3
> +                       nvmem-cells = <&tsens_mode>,
> +                                     <&tsens_base1>, <&tsens_base2>,
> +                                     <&tsens_s0_p1>, <&tsens_s0_p2>,
> +                                     <&tsens_s1_p1>, <&tsens_s1_p2>,
> +                                     <&tsens_s2_p1>, <&tsens_s2_p2>,
> +                                     <&tsens_s4_p1>, <&tsens_s4_p2>,
> +                                     <&tsens_s5_p1>, <&tsens_s5_p2>;
> +                       nvmem-cell-names = "mode",
> +                                          "base1", "base2",
> +                                          "s0_p1", "s0_p2",
> +                                          "s1_p1", "s1_p2",
> +                                          "s2_p1", "s2_p2",
> +                                          "s4_p1", "s4_p2",
> +                                          "s5_p1", "s5_p2";
> +                       #qcom,sensors = <5>;
> +                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               pcnoc: interconnect@500000 {
> +                       compatible = "qcom,msm8916-pcnoc";
> +                       reg = <0x00500000 0x11000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
> +                                <&rpmcc RPM_SMD_PCNOC_A_CLK>;
> +               };
> +
> +               snoc: interconnect@580000 {
> +                       compatible = "qcom,msm8916-snoc";
> +                       reg = <0x00580000 0x14000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
> +                                <&rpmcc RPM_SMD_SNOC_A_CLK>;
> +               };
> +
> +               stm: stm@802000 {
> +                       compatible = "arm,coresight-stm", "arm,primecell";
> +                       reg = <0x00802000 0x1000>,
> +                             <0x09280000 0x180000>;
> +                       reg-names = "stm-base", "stm-stimulus-base";
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               port {
> +                                       stm_out: endpoint {
> +                                               remote-endpoint = <&funnel0_in7>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               /* System CTIs */
> +               /* CTI 0 - TMC connections */
> +               cti0: cti@810000 {
> +                       compatible = "arm,coresight-cti", "arm,primecell";
> +                       reg = <0x00810000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       status = "disabled";
> +               };
> +
> +               /* CTI 1 - TPIU connections */
> +               cti1: cti@811000 {
> +                       compatible = "arm,coresight-cti", "arm,primecell";
> +                       reg = <0x00811000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       status = "disabled";
> +               };
> +
> +               /* CTIs 2-11 - no information - not instantiated */
> +
> +               tpiu: tpiu@820000 {
> +                       compatible = "arm,coresight-tpiu", "arm,primecell";
> +                       reg = <0x00820000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       in-ports {
> +                               port {
> +                                       tpiu_in: endpoint {
> +                                               remote-endpoint = <&replicator_out1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel0: funnel@821000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x00821000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               /*
> +                                * Not described input ports:
> +                                * 0 - connected to Resource and Power Manger CPU ETM
> +                                * 1 - not-connected
> +                                * 2 - connected to Modem CPU ETM
> +                                * 3 - not-connected
> +                                * 5 - not-connected
> +                                * 6 - connected trought funnel to Wireless CPU ETM
> +                                * 7 - connected to STM component
> +                                */
> +
> +                               port@4 {
> +                                       reg = <4>;
> +                                       funnel0_in4: endpoint {
> +                                               remote-endpoint = <&funnel1_out>;
> +                                       };
> +                               };
> +
> +                               port@7 {
> +                                       reg = <7>;
> +                                       funnel0_in7: endpoint {
> +                                               remote-endpoint = <&stm_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       funnel0_out: endpoint {
> +                                               remote-endpoint = <&etf_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               replicator: replicator@824000 {
> +                       compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> +                       reg = <0x00824000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       replicator_out0: endpoint {
> +                                               remote-endpoint = <&etr_in>;
> +                                       };
> +                               };
> +                               port@1 {
> +                                       reg = <1>;
> +                                       replicator_out1: endpoint {
> +                                               remote-endpoint = <&tpiu_in>;
> +                                       };
> +                               };
> +                       };
> +
> +                       in-ports {
> +                               port {
> +                                       replicator_in: endpoint {
> +                                               remote-endpoint = <&etf_out>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etf: etf@825000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0x00825000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       in-ports {
> +                               port {
> +                                       etf_in: endpoint {
> +                                               remote-endpoint = <&funnel0_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       etf_out: endpoint {
> +                                               remote-endpoint = <&replicator_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etr: etr@826000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0x00826000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       in-ports {
> +                               port {
> +                                       etr_in: endpoint {
> +                                               remote-endpoint = <&replicator_out0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x00841000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       status = "disabled";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       funnel1_in0: endpoint {
> +                                               remote-endpoint = <&etm0_out>;
> +                                       };
> +                               };
> +                               port@1 {
> +                                       reg = <1>;
> +                                       funnel1_in1: endpoint {
> +                                               remote-endpoint = <&etm1_out>;
> +                                       };
> +                               };
> +                               port@2 {
> +                                       reg = <2>;
> +                                       funnel1_in2: endpoint {
> +                                               remote-endpoint = <&etm2_out>;
> +                                       };
> +                               };
> +                               port@3 {
> +                                       reg = <3>;
> +                                       funnel1_in3: endpoint {
> +                                               remote-endpoint = <&etm3_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       funnel1_out: endpoint {
> +                                               remote-endpoint = <&funnel0_in4>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               debug0: debug@850000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x00850000 0x1000>;
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +                       cpu = <&CPU0>;
> +                       status = "disabled";
> +               };
> +
> +               debug1: debug@852000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x00852000 0x1000>;
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +                       cpu = <&CPU1>;
> +                       status = "disabled";
> +               };
> +
> +               debug2: debug@854000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x00854000 0x1000>;
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +                       cpu = <&CPU2>;
> +                       status = "disabled";
> +               };
> +
> +               debug3: debug@856000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x00856000 0x1000>;
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +                       cpu = <&CPU3>;
> +                       status = "disabled";
> +               };
> +
> +               /* Core CTIs; CTIs 12-15 */
> +               /* CTI - CPU-0 */
> +               cti12: cti@858000 {
> +                       compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> +                                    "arm,primecell";
> +                       reg = <0x00858000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU0>;
> +                       arm,cs-dev-assoc = <&etm0>;
> +
> +                       status = "disabled";
> +               };
> +
> +               /* CTI - CPU-1 */
> +               cti13: cti@859000 {
> +                       compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> +                                    "arm,primecell";
> +                       reg = <0x00859000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU1>;
> +                       arm,cs-dev-assoc = <&etm1>;
> +
> +                       status = "disabled";
> +               };
> +
> +               /* CTI - CPU-2 */
> +               cti14: cti@85a000 {
> +                       compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> +                                    "arm,primecell";
> +                       reg = <0x0085a000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU2>;
> +                       arm,cs-dev-assoc = <&etm2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               /* CTI - CPU-3 */
> +               cti15: cti@85b000 {
> +                       compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> +                                    "arm,primecell";
> +                       reg = <0x0085b000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU3>;
> +                       arm,cs-dev-assoc = <&etm3>;
> +
> +                       status = "disabled";
> +               };
> +
> +               etm0: etm@85c000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x0085c000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       cpu = <&CPU0>;
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               port {
> +                                       etm0_out: endpoint {
> +                                               remote-endpoint = <&funnel1_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm1: etm@85d000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x0085d000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       cpu = <&CPU1>;
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               port {
> +                                       etm1_out: endpoint {
> +                                               remote-endpoint = <&funnel1_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm2: etm@85e000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x0085e000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       cpu = <&CPU2>;
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               port {
> +                                       etm2_out: endpoint {
> +                                               remote-endpoint = <&funnel1_in2>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm3: etm@85f000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x0085f000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +                       arm,coresight-loses-context-with-cpu;
> +
> +                       cpu = <&CPU3>;
> +
> +                       status = "disabled";
> +
> +                       out-ports {
> +                               port {
> +                                       etm3_out: endpoint {
> +                                               remote-endpoint = <&funnel1_in3>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               tlmm: pinctrl@1000000 {
> +                       compatible = "qcom,msm8916-pinctrl";
> +                       reg = <0x01000000 0x300000>;
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       gpio-ranges = <&tlmm 0 0 122>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +
> +                       blsp_i2c1_default: blsp-i2c1-default-state {
> +                               pins = "gpio2", "gpio3";
> +                               function = "blsp_i2c1";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c1_sleep: blsp-i2c1-sleep-state {
> +                               pins = "gpio2", "gpio3";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c2_default: blsp-i2c2-default-state {
> +                               pins = "gpio6", "gpio7";
> +                               function = "blsp_i2c2";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c2_sleep: blsp-i2c2-sleep-state {
> +                               pins = "gpio6", "gpio7";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c3_default: blsp-i2c3-default-state {
> +                               pins = "gpio10", "gpio11";
> +                               function = "blsp_i2c3";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c3_sleep: blsp-i2c3-sleep-state {
> +                               pins = "gpio10", "gpio11";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c4_default: blsp-i2c4-default-state {
> +                               pins = "gpio14", "gpio15";
> +                               function = "blsp_i2c4";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c4_sleep: blsp-i2c4-sleep-state {
> +                               pins = "gpio14", "gpio15";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c5_default: blsp-i2c5-default-state {
> +                               pins = "gpio18", "gpio19";
> +                               function = "blsp_i2c5";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c5_sleep: blsp-i2c5-sleep-state {
> +                               pins = "gpio18", "gpio19";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c6_default: blsp-i2c6-default-state {
> +                               pins = "gpio22", "gpio23";
> +                               function = "blsp_i2c6";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_i2c6_sleep: blsp-i2c6-sleep-state {
> +                               pins = "gpio22", "gpio23";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_spi1_default: blsp-spi1-default-state {
> +                               spi-pins {
> +                                       pins = "gpio0", "gpio1", "gpio3";
> +                                       function = "blsp_spi1";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio2";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi1_sleep: blsp-spi1-sleep-state {
> +                               pins = "gpio0", "gpio1", "gpio2", "gpio3";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_spi2_default: blsp-spi2-default-state {
> +                               spi-pins {
> +                                       pins = "gpio4", "gpio5", "gpio7";
> +                                       function = "blsp_spi2";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio6";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi2_sleep: blsp-spi2-sleep-state {
> +                               pins = "gpio4", "gpio5", "gpio6", "gpio7";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_spi3_default: blsp-spi3-default-state {
> +                               spi-pins {
> +                                       pins = "gpio8", "gpio9", "gpio11";
> +                                       function = "blsp_spi3";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio10";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi3_sleep: blsp-spi3-sleep-state {
> +                               pins = "gpio8", "gpio9", "gpio10", "gpio11";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_spi4_default: blsp-spi4-default-state {
> +                               spi-pins {
> +                                       pins = "gpio12", "gpio13", "gpio15";
> +                                       function = "blsp_spi4";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio14";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi4_sleep: blsp-spi4-sleep-state {
> +                               pins = "gpio12", "gpio13", "gpio14", "gpio15";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_spi5_default: blsp-spi5-default-state {
> +                               spi-pins {
> +                                       pins = "gpio16", "gpio17", "gpio19";
> +                                       function = "blsp_spi5";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio18";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi5_sleep: blsp-spi5-sleep-state {
> +                               pins = "gpio16", "gpio17", "gpio18", "gpio19";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_spi6_default: blsp-spi6-default-state {
> +                               spi-pins {
> +                                       pins = "gpio20", "gpio21", "gpio23";
> +                                       function = "blsp_spi6";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +                               cs-pins {
> +                                       pins = "gpio22";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp_spi6_sleep: blsp-spi6-sleep-state {
> +                               pins = "gpio20", "gpio21", "gpio22", "gpio23";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_uart1_default: blsp-uart1-default-state {
> +                               /* TX, RX, CTS_N, RTS_N */
> +                               pins = "gpio0", "gpio1", "gpio2", "gpio3";
> +                               function = "blsp_uart1";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_uart1_sleep: blsp-uart1-sleep-state {
> +                               pins = "gpio0", "gpio1", "gpio2", "gpio3";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp_uart2_default: blsp-uart2-default-state {
> +                               pins = "gpio4", "gpio5";
> +                               function = "blsp_uart2";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp_uart2_sleep: blsp-uart2-sleep-state {
> +                               pins = "gpio4", "gpio5";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       camera_front_default: camera-front-default-state {
> +                               pwdn-pins {
> +                                       pins = "gpio33";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                               rst-pins {
> +                                       pins = "gpio28";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                               mclk1-pins {
> +                                       pins = "gpio27";
> +                                       function = "cam_mclk1";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       camera_rear_default: camera-rear-default-state {
> +                               pwdn-pins {
> +                                       pins = "gpio34";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                               rst-pins {
> +                                       pins = "gpio35";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                               mclk0-pins {
> +                                       pins = "gpio26";
> +                                       function = "cam_mclk0";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       cci0_default: cci0-default-state {
> +                               pins = "gpio29", "gpio30";
> +                               function = "cci_i2c";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       cdc_dmic_default: cdc-dmic-default-state {
> +                               clk-pins {
> +                                       pins = "gpio0";
> +                                       function = "dmic0_clk";
> +                                       drive-strength = <8>;
> +                               };
> +                               data-pins {
> +                                       pins = "gpio1";
> +                                       function = "dmic0_data";
> +                                       drive-strength = <8>;
> +                               };
> +                       };
> +
> +                       cdc_dmic_sleep: cdc-dmic-sleep-state {
> +                               clk-pins {
> +                                       pins = "gpio0";
> +                                       function = "dmic0_clk";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                               data-pins {
> +                                       pins = "gpio1";
> +                                       function = "dmic0_data";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       cdc_pdm_default: cdc-pdm-default-state {
> +                               pins = "gpio63", "gpio64", "gpio65", "gpio66",
> +                                      "gpio67", "gpio68";
> +                               function = "cdc_pdm0";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       cdc_pdm_sleep: cdc-pdm-sleep-state {
> +                               pins = "gpio63", "gpio64", "gpio65", "gpio66",
> +                                      "gpio67", "gpio68";
> +                               function = "cdc_pdm0";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       pri_mi2s_default: mi2s-pri-default-state {
> +                               pins = "gpio113", "gpio114", "gpio115", "gpio116";
> +                               function = "pri_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       pri_mi2s_sleep: mi2s-pri-sleep-state {
> +                               pins = "gpio113", "gpio114", "gpio115", "gpio116";
> +                               function = "pri_mi2s";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
> +                               pins = "gpio116";
> +                               function = "pri_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
> +                               pins = "gpio116";
> +                               function = "pri_mi2s";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       pri_mi2s_ws_default: mi2s-pri-ws-default-state {
> +                               pins = "gpio110";
> +                               function = "pri_mi2s_ws";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
> +                               pins = "gpio110";
> +                               function = "pri_mi2s_ws";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       sec_mi2s_default: mi2s-sec-default-state {
> +                               pins = "gpio112", "gpio117", "gpio118", "gpio119";
> +                               function = "sec_mi2s";
> +                               drive-strength = <8>;
> +                               bias-disable;
> +                       };
> +
> +                       sec_mi2s_sleep: mi2s-sec-sleep-state {
> +                               pins = "gpio112", "gpio117", "gpio118", "gpio119";
> +                               function = "sec_mi2s";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       sdc1_default: sdc1-default-state {
> +                               clk-pins {
> +                                       pins = "sdc1_clk";
> +                                       bias-disable;
> +                                       drive-strength = <16>;
> +                               };
> +                               cmd-pins {
> +                                       pins = "sdc1_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +                               data-pins {
> +                                       pins = "sdc1_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +                       };
> +
> +                       sdc1_sleep: sdc1-sleep-state {
> +                               clk-pins {
> +                                       pins = "sdc1_clk";
> +                                       bias-disable;
> +                                       drive-strength = <2>;
> +                               };
> +                               cmd-pins {
> +                                       pins = "sdc1_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +                               data-pins {
> +                                       pins = "sdc1_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +                       };
> +
> +                       sdc2_default: sdc2-default-state {
> +                               clk-pins {
> +                                       pins = "sdc2_clk";
> +                                       bias-disable;
> +                                       drive-strength = <16>;
> +                               };
> +                               cmd-pins {
> +                                       pins = "sdc2_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +                               data-pins {
> +                                       pins = "sdc2_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +                       };
> +
> +                       sdc2_sleep: sdc2-sleep-state {
> +                               clk-pins {
> +                                       pins = "sdc2_clk";
> +                                       bias-disable;
> +                                       drive-strength = <2>;
> +                               };
> +                               cmd-pins {
> +                                       pins = "sdc2_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +                               data-pins {
> +                                       pins = "sdc2_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +                       };
> +
> +                       wcss_wlan_default: wcss-wlan-default-state {
> +                               pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
> +                               function = "wcss_wlan";
> +                               drive-strength = <6>;
> +                               bias-pull-up;
> +                       };
> +               };
> +
> +               gcc: clock-controller@1800000 {
> +                       compatible = "qcom,gcc-msm8916";
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       reg = <0x01800000 0x80000>;
> +                       clocks = <&xo_board>,
> +                                <&sleep_clk>,
> +                                <&mdss_dsi0_phy 1>,
> +                                <&mdss_dsi0_phy 0>,
> +                                <0>,
> +                                <0>,
> +                                <0>;
> +                       clock-names = "xo",
> +                                     "sleep_clk",
> +                                     "dsi0pll",
> +                                     "dsi0pllbyte",
> +                                     "ext_mclk",
> +                                     "ext_pri_i2s",
> +                                     "ext_sec_i2s";
> +               };
> +
> +               tcsr_mutex: hwlock@1905000 {
> +                       compatible = "qcom,tcsr-mutex";
> +                       reg = <0x01905000 0x20000>;
> +                       #hwlock-cells = <1>;
> +               };
> +
> +               tcsr: syscon@1937000 {
> +                       compatible = "qcom,tcsr-msm8916", "syscon";
> +                       reg = <0x01937000 0x30000>;
> +               };
> +
> +               mdss: display-subsystem@1a00000 {
> +                       status = "disabled";
> +                       compatible = "qcom,mdss";
> +                       reg = <0x01a00000 0x1000>,
> +                             <0x01ac8000 0x3000>;
> +                       reg-names = "mdss_phys", "vbif_phys";
> +
> +                       power-domains = <&gcc MDSS_GDSC>;
> +
> +                       clocks = <&gcc GCC_MDSS_AHB_CLK>,
> +                                <&gcc GCC_MDSS_AXI_CLK>,
> +                                <&gcc GCC_MDSS_VSYNC_CLK>;
> +                       clock-names = "iface",
> +                                     "bus",
> +                                     "vsync";
> +
> +                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       mdss_mdp: display-controller@1a01000 {
> +                               compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
> +                               reg = <0x01a01000 0x89000>;
> +                               reg-names = "mdp_phys";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <0>;
> +
> +                               clocks = <&gcc GCC_MDSS_AHB_CLK>,
> +                                        <&gcc GCC_MDSS_AXI_CLK>,
> +                                        <&gcc GCC_MDSS_MDP_CLK>,
> +                                        <&gcc GCC_MDSS_VSYNC_CLK>;
> +                               clock-names = "iface",
> +                                             "bus",
> +                                             "core",
> +                                             "vsync";
> +
> +                               iommus = <&apps_iommu 4>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_mdp_intf1_out: endpoint {
> +                                                       remote-endpoint = <&mdss_dsi0_in>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0: dsi@1a98000 {
> +                               compatible = "qcom,msm8916-dsi-ctrl",
> +                                            "qcom,mdss-dsi-ctrl";
> +                               reg = <0x01a98000 0x25c>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <4>;
> +
> +                               assigned-clocks = <&gcc BYTE0_CLK_SRC>,
> +                                                 <&gcc PCLK0_CLK_SRC>;
> +                               assigned-clock-parents = <&mdss_dsi0_phy 0>,
> +                                                        <&mdss_dsi0_phy 1>;
> +
> +                               clocks = <&gcc GCC_MDSS_MDP_CLK>,
> +                                        <&gcc GCC_MDSS_AHB_CLK>,
> +                                        <&gcc GCC_MDSS_AXI_CLK>,
> +                                        <&gcc GCC_MDSS_BYTE0_CLK>,
> +                                        <&gcc GCC_MDSS_PCLK0_CLK>,
> +                                        <&gcc GCC_MDSS_ESC0_CLK>;
> +                               clock-names = "mdp_core",
> +                                             "iface",
> +                                             "bus",
> +                                             "byte",
> +                                             "pixel",
> +                                             "core";
> +                               phys = <&mdss_dsi0_phy>;
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_dsi0_in: endpoint {
> +                                                       remote-endpoint = <&mdss_mdp_intf1_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdss_dsi0_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0_phy: phy@1a98300 {
> +                               compatible = "qcom,dsi-phy-28nm-lp";
> +                               reg = <0x01a98300 0xd4>,
> +                                     <0x01a98500 0x280>,
> +                                     <0x01a98780 0x30>;
> +                               reg-names = "dsi_pll",
> +                                           "dsi_phy",
> +                                           "dsi_phy_regulator";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&gcc GCC_MDSS_AHB_CLK>,
> +                                        <&xo_board>;
> +                               clock-names = "iface", "ref";
> +                       };
> +               };
> +
> +               camss: camss@1b0ac00 {
> +                       compatible = "qcom,msm8916-camss";
> +                       reg = <0x01b0ac00 0x200>,
> +                               <0x01b00030 0x4>,
> +                               <0x01b0b000 0x200>,
> +                               <0x01b00038 0x4>,
> +                               <0x01b08000 0x100>,
> +                               <0x01b08400 0x100>,
> +                               <0x01b0a000 0x500>,
> +                               <0x01b00020 0x10>,
> +                               <0x01b10000 0x1000>;
> +                       reg-names = "csiphy0",
> +                               "csiphy0_clk_mux",
> +                               "csiphy1",
> +                               "csiphy1_clk_mux",
> +                               "csid0",
> +                               "csid1",
> +                               "ispif",
> +                               "csi_clk_mux",
> +                               "vfe0";
> +                       interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "csiphy0",
> +                               "csiphy1",
> +                               "csid0",
> +                               "csid1",
> +                               "ispif",
> +                               "vfe0";
> +                       power-domains = <&gcc VFE_GDSC>;
> +                       clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0PHY_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0PIX_CLK>,
> +                               <&gcc GCC_CAMSS_CSI0RDI_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1PHY_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1PIX_CLK>,
> +                               <&gcc GCC_CAMSS_CSI1RDI_CLK>,
> +                               <&gcc GCC_CAMSS_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_VFE0_CLK>,
> +                               <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
> +                               <&gcc GCC_CAMSS_VFE_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_VFE_AXI_CLK>;
> +                       clock-names = "top_ahb",
> +                               "ispif_ahb",
> +                               "csiphy0_timer",
> +                               "csiphy1_timer",
> +                               "csi0_ahb",
> +                               "csi0",
> +                               "csi0_phy",
> +                               "csi0_pix",
> +                               "csi0_rdi",
> +                               "csi1_ahb",
> +                               "csi1",
> +                               "csi1_phy",
> +                               "csi1_pix",
> +                               "csi1_rdi",
> +                               "ahb",
> +                               "vfe0",
> +                               "csi_vfe0",
> +                               "vfe_ahb",
> +                               "vfe_axi";
> +                       iommus = <&apps_iommu 3>;
> +                       status = "disabled";
> +                       ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                               };
> +                       };
> +               };
> +
> +               cci: cci@1b0c000 {
> +                       compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x01b0c000 0x1000>;
> +                       interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> +                       clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CCI_CLK>,
> +                               <&gcc GCC_CAMSS_AHB_CLK>;
> +                       clock-names = "camss_top_ahb", "cci_ahb",
> +                                         "cci", "camss_ahb";
> +                       assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> +                                         <&gcc GCC_CAMSS_CCI_CLK>;
> +                       assigned-clock-rates = <80000000>, <19200000>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&cci0_default>;
> +                       status = "disabled";
> +
> +                       cci_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
> +               gpu: gpu@1c00000 {
> +                       compatible = "qcom,adreno-306.0", "qcom,adreno";
> +                       reg = <0x01c00000 0x20000>;
> +                       reg-names = "kgsl_3d0_reg_memory";
> +                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "kgsl_3d0_irq";
> +                       clock-names =
> +                           "core",
> +                           "iface",
> +                           "mem",
> +                           "mem_iface",
> +                           "alt_mem_iface",
> +                           "gfx3d";
> +                       clocks =
> +                           <&gcc GCC_OXILI_GFX3D_CLK>,
> +                           <&gcc GCC_OXILI_AHB_CLK>,
> +                           <&gcc GCC_OXILI_GMEM_CLK>,
> +                           <&gcc GCC_BIMC_GFX_CLK>,
> +                           <&gcc GCC_BIMC_GPU_CLK>,
> +                           <&gcc GFX3D_CLK_SRC>;
> +                       power-domains = <&gcc OXILI_GDSC>;
> +                       operating-points-v2 = <&gpu_opp_table>;
> +                       iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
> +                       status = "disabled";
> +
> +                       gpu_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-400000000 {
> +                                       opp-hz = /bits/ 64 <400000000>;
> +                               };
> +                               opp-19200000 {
> +                                       opp-hz = /bits/ 64 <19200000>;
> +                               };
> +                       };
> +               };
> +
> +               venus: video-codec@1d00000 {
> +                       compatible = "qcom,msm8916-venus";
> +                       reg = <0x01d00000 0xff000>;
> +                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&gcc VENUS_GDSC>;
> +                       clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
> +                                <&gcc GCC_VENUS0_AHB_CLK>,
> +                                <&gcc GCC_VENUS0_AXI_CLK>;
> +                       clock-names = "core", "iface", "bus";
> +                       iommus = <&apps_iommu 5>;
> +                       memory-region = <&venus_mem>;
> +                       status = "disabled";
> +
> +                       video-decoder {
> +                               compatible = "venus-decoder";
> +                       };
> +
> +                       video-encoder {
> +                               compatible = "venus-encoder";
> +                       };
> +               };
> +
> +               apps_iommu: iommu@1ef0000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       #iommu-cells = <1>;
> +                       compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
> +                       ranges = <0 0x01e20000 0x20000>;
> +                       reg = <0x01ef0000 0x3000>;
> +                       clocks = <&gcc GCC_SMMU_CFG_CLK>,
> +                                <&gcc GCC_APSS_TCU_CLK>;
> +                       clock-names = "iface", "bus";
> +                       qcom,iommu-secure-id = <17>;
> +
> +                       /* VFE */
> +                       iommu-ctx@3000 {
> +                               compatible = "qcom,msm-iommu-v1-sec";
> +                               reg = <0x3000 0x1000>;
> +                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +
> +                       /* MDP_0 */
> +                       iommu-ctx@4000 {
> +                               compatible = "qcom,msm-iommu-v1-ns";
> +                               reg = <0x4000 0x1000>;
> +                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +
> +                       /* VENUS_NS */
> +                       iommu-ctx@5000 {
> +                               compatible = "qcom,msm-iommu-v1-sec";
> +                               reg = <0x5000 0x1000>;
> +                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +               };
> +
> +               gpu_iommu: iommu@1f08000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       #iommu-cells = <1>;
> +                       compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
> +                       ranges = <0 0x01f08000 0x10000>;
> +                       clocks = <&gcc GCC_SMMU_CFG_CLK>,
> +                                <&gcc GCC_GFX_TCU_CLK>;
> +                       clock-names = "iface", "bus";
> +                       qcom,iommu-secure-id = <18>;
> +
> +                       /* GFX3D_USER */
> +                       iommu-ctx@1000 {
> +                               compatible = "qcom,msm-iommu-v1-ns";
> +                               reg = <0x1000 0x1000>;
> +                               interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +
> +                       /* GFX3D_PRIV */
> +                       iommu-ctx@2000 {
> +                               compatible = "qcom,msm-iommu-v1-ns";
> +                               reg = <0x2000 0x1000>;
> +                               interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +               };
> +
> +               spmi_bus: spmi@200f000 {
> +                       compatible = "qcom,spmi-pmic-arb";
> +                       reg = <0x0200f000 0x001000>,
> +                             <0x02400000 0x400000>,
> +                             <0x02c00000 0x400000>,
> +                             <0x03800000 0x200000>,
> +                             <0x0200a000 0x002100>;
> +                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +                       interrupt-names = "periph_irq";
> +                       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,ee = <0>;
> +                       qcom,channel = <0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <0>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <4>;
> +               };
> +
> +               bam_dmux_dma: dma-controller@4044000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x04044000 0x19000>;
> +                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +
> +                       num-channels = <6>;
> +                       qcom,num-ees = <1>;
> +                       qcom,powered-remotely;
> +
> +                       status = "disabled";
> +               };
> +
> +               mpss: remoteproc@4080000 {
> +                       compatible = "qcom,msm8916-mss-pil";
> +                       reg = <0x04080000 0x100>,
> +                             <0x04020000 0x040>;
> +
> +                       reg-names = "qdsp6", "rmb";
> +
> +                       interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
> +                                             <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack";
> +
> +                       power-domains = <&rpmpd MSM8916_VDDCX>,
> +                                       <&rpmpd MSM8916_VDDMX>;
> +                       power-domain-names = "cx", "mx";
> +
> +                       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
> +                                <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
> +                                <&gcc GCC_BOOT_ROM_AHB_CLK>,
> +                                <&xo_board>;
> +                       clock-names = "iface", "bus", "mem", "xo";
> +
> +                       qcom,smem-states = <&hexagon_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       resets = <&scm 0>;
> +                       reset-names = "mss_restart";
> +
> +                       qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
> +
> +                       status = "disabled";
> +
> +                       mba {
> +                               memory-region = <&mba_mem>;
> +                       };
> +
> +                       mpss {
> +                               memory-region = <&mpss_mem>;
> +                       };
> +
> +                       bam_dmux: bam-dmux {
> +                               compatible = "qcom,bam-dmux";
> +
> +                               interrupt-parent = <&hexagon_smsm>;
> +                               interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
> +                               interrupt-names = "pc", "pc-ack";
> +
> +                               qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
> +                               qcom,smem-state-names = "pc", "pc-ack";
> +
> +                               dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
> +                               dma-names = "tx", "rx";
> +
> +                               status = "disabled";
> +                       };
> +
> +                       smd-edge {
> +                               interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
> +
> +                               qcom,smd-edge = <0>;
> +                               qcom,ipc = <&apcs 8 12>;
> +                               qcom,remote-pid = <1>;
> +
> +                               label = "hexagon";
> +
> +                               fastrpc {
> +                                       compatible = "qcom,fastrpc";
> +                                       qcom,smd-channels = "fastrpcsmd-apps-dsp";
> +                                       label = "adsp";
> +                                       qcom,non-secure-domain;
> +
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       cb@1 {
> +                                               compatible = "qcom,fastrpc-compute-cb";
> +                                               reg = <1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               sound: sound@7702000 {
> +                       status = "disabled";
> +                       compatible = "qcom,apq8016-sbc-sndcard";
> +                       reg = <0x07702000 0x4>, <0x07702004 0x4>;
> +                       reg-names = "mic-iomux", "spkr-iomux";
> +               };
> +
> +               lpass: audio-controller@7708000 {
> +                       status = "disabled";
> +                       compatible = "qcom,apq8016-lpass-cpu";
> +
> +                       /*
> +                        * Note: Unlike the name would suggest, the SEC_I2S_CLK
> +                        * is actually only used by Tertiary MI2S while
> +                        * Primary/Secondary MI2S both use the PRI_I2S_CLK.
> +                        */
> +                       clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
> +                                <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
> +                                <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
> +                                <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
> +                                <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
> +                                <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
> +                                <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
> +
> +                       clock-names = "ahbix-clk",
> +                                       "mi2s-bit-clk0",
> +                                       "mi2s-bit-clk1",
> +                                       "mi2s-bit-clk2",
> +                                       "mi2s-bit-clk3",
> +                                       "pcnoc-mport-clk",
> +                                       "pcnoc-sway-clk";
> +                       #sound-dai-cells = <1>;
> +
> +                       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "lpass-irq-lpaif";
> +                       reg = <0x07708000 0x10000>;
> +                       reg-names = "lpass-lpaif";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               lpass_codec: audio-codec@771c000 {
> +                       compatible = "qcom,msm8916-wcd-digital-codec";
> +                       reg = <0x0771c000 0x400>;
> +                       clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
> +                                <&gcc GCC_CODEC_DIGCODEC_CLK>;
> +                       clock-names = "ahbix-clk", "mclk";
> +                       #sound-dai-cells = <1>;
> +                       status = "disabled";
> +               };
> +
> +               sdhc_1: mmc@7824900 {
> +                       compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
> +                       reg = <0x07824900 0x11c>, <0x07824000 0x800>;
> +                       reg-names = "hc", "core";
> +
> +                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +                                <&gcc GCC_SDCC1_APPS_CLK>,
> +                                <&xo_board>;
> +                       clock-names = "iface", "core", "xo";
> +                       pinctrl-0 = <&sdc1_default>;
> +                       pinctrl-1 = <&sdc1_sleep>;
> +                       pinctrl-names = "default", "sleep";
> +                       mmc-ddr-1_8v;
> +                       bus-width = <8>;
> +                       non-removable;
> +                       status = "disabled";
> +               };
> +
> +               sdhc_2: mmc@7864900 {
> +                       compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
> +                       reg = <0x07864900 0x11c>, <0x07864000 0x800>;
> +                       reg-names = "hc", "core";
> +
> +                       interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> +                                <&gcc GCC_SDCC2_APPS_CLK>,
> +                                <&xo_board>;
> +                       clock-names = "iface", "core", "xo";
> +                       pinctrl-0 = <&sdc2_default>;
> +                       pinctrl-1 = <&sdc2_sleep>;
> +                       pinctrl-names = "default", "sleep";
> +                       bus-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_dma: dma-controller@7884000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x07884000 0x23000>;
> +                       interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +               };
> +
> +               blsp_uart1: serial@78af000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078af000 0x200>;
> +                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 0>, <&blsp_dma 1>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_uart1_default>;
> +                       pinctrl-1 = <&blsp_uart1_sleep>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_uart2: serial@78b0000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078b0000 0x200>;
> +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 2>, <&blsp_dma 3>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_uart2_default>;
> +                       pinctrl-1 = <&blsp_uart2_sleep>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c1: i2c@78b5000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b5000 0x500>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 4>, <&blsp_dma 5>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c1_default>;
> +                       pinctrl-1 = <&blsp_i2c1_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi1: spi@78b5000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b5000 0x500>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 4>, <&blsp_dma 5>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi1_default>;
> +                       pinctrl-1 = <&blsp_spi1_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c2: i2c@78b6000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b6000 0x500>;
> +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 6>, <&blsp_dma 7>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c2_default>;
> +                       pinctrl-1 = <&blsp_i2c2_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi2: spi@78b6000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b6000 0x500>;
> +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 6>, <&blsp_dma 7>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi2_default>;
> +                       pinctrl-1 = <&blsp_spi2_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c3: i2c@78b7000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b7000 0x500>;
> +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 8>, <&blsp_dma 9>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c3_default>;
> +                       pinctrl-1 = <&blsp_i2c3_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi3: spi@78b7000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b7000 0x500>;
> +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 8>, <&blsp_dma 9>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi3_default>;
> +                       pinctrl-1 = <&blsp_spi3_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c4: i2c@78b8000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b8000 0x500>;
> +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 10>, <&blsp_dma 11>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c4_default>;
> +                       pinctrl-1 = <&blsp_i2c4_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi4: spi@78b8000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b8000 0x500>;
> +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 10>, <&blsp_dma 11>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi4_default>;
> +                       pinctrl-1 = <&blsp_spi4_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c5: i2c@78b9000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b9000 0x500>;
> +                       interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 12>, <&blsp_dma 13>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c5_default>;
> +                       pinctrl-1 = <&blsp_i2c5_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi5: spi@78b9000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b9000 0x500>;
> +                       interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 12>, <&blsp_dma 13>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi5_default>;
> +                       pinctrl-1 = <&blsp_spi5_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_i2c6: i2c@78ba000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078ba000 0x500>;
> +                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 14>, <&blsp_dma 15>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_i2c6_default>;
> +                       pinctrl-1 = <&blsp_i2c6_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp_spi6: spi@78ba000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078ba000 0x500>;
> +                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp_dma 14>, <&blsp_dma 15>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp_spi6_default>;
> +                       pinctrl-1 = <&blsp_spi6_sleep>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               usb: usb@78d9000 {
> +                       compatible = "qcom,ci-hdrc";
> +                       reg = <0x078d9000 0x200>,
> +                             <0x078d9200 0x200>;
> +                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_USB_HS_AHB_CLK>,
> +                                <&gcc GCC_USB_HS_SYSTEM_CLK>;
> +                       clock-names = "iface", "core";
> +                       assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
> +                       assigned-clock-rates = <80000000>;
> +                       resets = <&gcc GCC_USB_HS_BCR>;
> +                       reset-names = "core";
> +                       phy_type = "ulpi";
> +                       dr_mode = "otg";
> +                       hnp-disable;
> +                       srp-disable;
> +                       adp-disable;
> +                       ahb-burst-config = <0>;
> +                       phy-names = "usb-phy";
> +                       phys = <&usb_hs_phy>;
> +                       status = "disabled";
> +                       #reset-cells = <1>;
> +
> +                       ulpi {
> +                               usb_hs_phy: phy {
> +                                       compatible = "qcom,usb-hs-phy-msm8916",
> +                                                    "qcom,usb-hs-phy";
> +                                       #phy-cells = <0>;
> +                                       clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> +                                       clock-names = "ref", "sleep";
> +                                       resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
> +                                       reset-names = "phy", "por";
> +                                       qcom,init-seq = /bits/ 8 <0x0 0x44>,
> +                                                                <0x1 0x6b>,
> +                                                                <0x2 0x24>,
> +                                                                <0x3 0x13>;
> +                               };
> +                       };
> +               };
> +
> +               wcnss: remoteproc@a204000 {
> +                       compatible = "qcom,pronto-v2-pil", "qcom,pronto";
> +                       reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
> +                       reg-names = "ccu", "dxe", "pmu";
> +
> +                       memory-region = <&wcnss_mem>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
> +
> +                       power-domains = <&rpmpd MSM8916_VDDCX>,
> +                                       <&rpmpd MSM8916_VDDMX>;
> +                       power-domain-names = "cx", "mx";
> +
> +                       qcom,smem-states = <&wcnss_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&wcss_wlan_default>;
> +
> +                       status = "disabled";
> +
> +                       wcnss_iris: iris {
> +                               /* Separate chip, compatible is board-specific */
> +                               clocks = <&rpmcc RPM_SMD_RF_CLK2>;
> +                               clock-names = "xo";
> +                       };
> +
> +                       smd-edge {
> +                               interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
> +
> +                               qcom,ipc = <&apcs 8 17>;
> +                               qcom,smd-edge = <6>;
> +                               qcom,remote-pid = <4>;
> +
> +                               label = "pronto";
> +
> +                               wcnss_ctrl: wcnss {
> +                                       compatible = "qcom,wcnss";
> +                                       qcom,smd-channels = "WCNSS_CTRL";
> +
> +                                       qcom,mmio = <&wcnss>;
> +
> +                                       wcnss_bt: bluetooth {
> +                                               compatible = "qcom,wcnss-bt";
> +                                       };
> +
> +                                       wcnss_wifi: wifi {
> +                                               compatible = "qcom,wcnss-wlan";
> +
> +                                               interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +                                                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +                                               interrupt-names = "tx", "rx";
> +
> +                                               qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
> +                                               qcom,smem-state-names = "tx-enable", "tx-rings-empty";
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               intc: interrupt-controller@b000000 {
> +                       compatible = "qcom,msm-qgic2";
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +                       reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
> +                             <0x0b001000 0x1000>, <0x0b004000 0x2000>;
> +                       interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +               };
> +
> +               apcs: mailbox@b011000 {
> +                       compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
> +                       reg = <0x0b011000 0x1000>;
> +                       #mbox-cells = <1>;
> +                       clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
> +                       clock-names = "pll", "aux";
> +                       #clock-cells = <0>;
> +               };
> +
> +               a53pll: clock@b016000 {
> +                       compatible = "qcom,msm8916-a53pll";
> +                       reg = <0x0b016000 0x40>;
> +                       #clock-cells = <0>;
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +               };
> +
> +               timer@b020000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       compatible = "arm,armv7-timer-mem";
> +                       reg = <0x0b020000 0x1000>;
> +                       clock-frequency = <19200000>;
> +
> +                       frame@b021000 {
> +                               frame-number = <0>;
> +                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b021000 0x1000>,
> +                                     <0x0b022000 0x1000>;
> +                       };
> +
> +                       frame@b023000 {
> +                               frame-number = <1>;
> +                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b023000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b024000 {
> +                               frame-number = <2>;
> +                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b024000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b025000 {
> +                               frame-number = <3>;
> +                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b025000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b026000 {
> +                               frame-number = <4>;
> +                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b026000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b027000 {
> +                               frame-number = <5>;
> +                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b027000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b028000 {
> +                               frame-number = <6>;
> +                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b028000 0x1000>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               cpu0_acc: power-manager@b088000 {
> +                       compatible = "qcom,msm8916-acc";
> +                       reg = <0x0b088000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu0_saw: power-manager@b089000 {
> +                       compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
> +                       reg = <0x0b089000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu1_acc: power-manager@b098000 {
> +                       compatible = "qcom,msm8916-acc";
> +                       reg = <0x0b098000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu1_saw: power-manager@b099000 {
> +                       compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
> +                       reg = <0x0b099000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu2_acc: power-manager@b0a8000 {
> +                       compatible = "qcom,msm8916-acc";
> +                       reg = <0x0b0a8000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu2_saw: power-manager@b0a9000 {
> +                       compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
> +                       reg = <0x0b0a9000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu3_acc: power-manager@b0b8000 {
> +                       compatible = "qcom,msm8916-acc";
> +                       reg = <0x0b0b8000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +
> +               cpu3_saw: power-manager@b0b9000 {
> +                       compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
> +                       reg = <0x0b0b9000 0x1000>;
> +                       status = "reserved"; /* Controlled by PSCI firmware */
> +               };
> +       };
> +
> +       thermal-zones {
> +               cpu0-1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 5>;
> +
> +                       trips {
> +                               cpu0_1_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu0_1_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu0_1_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu2-3-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 4>;
> +
> +                       trips {
> +                               cpu2_3_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu2_3_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu2_3_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               gpu-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 2>;
> +
> +                       trips {
> +                               gpu_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               gpu_crit: gpu-crit {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               camera-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 1>;
> +
> +                       trips {
> +                               cam_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               modem-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 0>;
> +
> +                       trips {
> +                               modem_alert0: trip-point0 {
> +                                       temperature = <85000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +       };
> +};
> diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
> index efdee8a40fa3..0481ceeb6c65 100644
> --- a/configs/dragonboard410c_defconfig
> +++ b/configs/dragonboard410c_defconfig
> @@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
>  CONFIG_ENV_SIZE=0x2000
>  CONFIG_ENV_OFFSET=0x0
> -CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
> +CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc"
>  CONFIG_OF_LIBFDT_OVERLAY=y
>  CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
>  CONFIG_SYS_LOAD_ADDR=0x80080000
>
> --
> 2.43.1
>

Re: [PATCH v4 36/39] dts: msm8996: replace with upstream DTS

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Drop the U-Boot specific dragonboard820c.dts file in favour of the
> upstream apq8096-db820c.dts and an additional -u-boot.dtsi with the
> U-Boot specific additions.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/Makefile                   |    2 +-
>  arch/arm/dts/apq8096-db820c-u-boot.dtsi |   14 +
>  arch/arm/dts/apq8096-db820c.dts         | 1137 +++++++++
>  arch/arm/dts/dragonboard820c-uboot.dtsi |   32 -
>  arch/arm/dts/dragonboard820c.dts        |  153 --
>  arch/arm/dts/msm8996.dtsi               | 3884 +++++++++++++++++++++++++++++++
>  configs/dragonboard820c_defconfig       |    2 +-
>  7 files changed, 5037 insertions(+), 187 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9ba1a94da5d0..54aaf022c2eb 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -632,7 +632,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
>  dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
>
>  dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
> -       dragonboard820c.dtb \
> +       apq8096-db820c.dtb \
>         sdm845-db845c.dtb \
>         sdm845-samsung-starqltechn.dtb \
>         qcs404-evb.dtb
> diff --git a/arch/arm/dts/apq8096-db820c-u-boot.dtsi b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
> new file mode 100644
> index 000000000000..be61ea262b90
> --- /dev/null
> +++ b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024, Linaro Ltd.
> + */
> +
> +/ {
> +       /* Ensure that the fdtfile variable is generated properly */
> +       compatible = "qcom,apq8096-db820c", "qcom,apq8096";
> +};
> +
> +&sdhc2 {
> +       status = "okay";
> +       clock-frequency = <100000000>;
> +};
> diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts
> new file mode 100644
> index 000000000000..e8148b3d6c50
> --- /dev/null
> +++ b/arch/arm/dts/apq8096-db820c.dts
> @@ -0,0 +1,1137 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "msm8996.dtsi"
> +#include "pm8994.dtsi"
> +#include "pmi8994.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/sound/qcom,q6afe.h>
> +#include <dt-bindings/sound/qcom,q6asm.h>
> +#include <dt-bindings/sound/qcom,wcd9335.h>
> +
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + *         NC      = not connected (pin out but not routed from the chip to
> + *                   anything the board)
> + *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + *         LSEC    = Low Speed External Connector
> + *         P HSEC  = Primary High Speed External Connector
> + *         S HSEC  = Secondary High Speed External Connector
> + *         J14     = Camera Connector
> + *         TP      = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
> +/ {
> +       model = "Qualcomm Technologies, Inc. DB820c";
> +       compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
> +
> +       aliases {
> +               serial0 = &blsp2_uart2;
> +               serial1 = &blsp2_uart3;
> +               serial2 = &blsp1_uart2;
> +               i2c0 = &blsp1_i2c3;
> +               i2c1 = &blsp2_i2c1;
> +               i2c2 = &blsp2_i2c1;
> +               spi0 = &blsp1_spi1;
> +               spi1 = &blsp2_spi6;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       div1_mclk: divclk1 {
> +               compatible = "gpio-gate-clock";
> +               pinctrl-0 = <&audio_mclk>;
> +               pinctrl-names = "default";
> +               clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
> +               #clock-cells = <0>;
> +               enable-gpios = <&pm8994_gpios 15 0>;
> +       };
> +
> +       divclk4: divclk4 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <32768>;
> +               clock-output-names = "divclk4";
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&divclk4_pin_a>;
> +       };
> +
> +       gpio-keys {
> +               compatible = "gpio-keys";
> +               autorepeat;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&volume_up_gpio>;
> +
> +               button {
> +                       label = "Volume Up";
> +                       linux,code = <KEY_VOLUMEUP>;
> +                       gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
> +               };
> +       };
> +
> +       usb2_id: usb2-id {
> +               compatible = "linux,extcon-usb-gpio";
> +               id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&usb2_vbus_det_gpio>;
> +       };
> +
> +       usb3_id: usb3-id {
> +               compatible = "linux,extcon-usb-gpio";
> +               id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&usb3_vbus_det_gpio>;
> +       };
> +
> +       vph_pwr: vph-pwr-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vph_pwr";
> +               regulator-always-on;
> +               regulator-boot-on;
> +
> +               regulator-min-microvolt = <3700000>;
> +               regulator-max-microvolt = <3700000>;
> +       };
> +
> +       wlan_en: wlan-en-1-8v {
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&wlan_en_gpios>;
> +               compatible = "regulator-fixed";
> +               regulator-name = "wlan-en-regulator";
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +
> +               gpio = <&pm8994_gpios 8 0>;
> +
> +               /* WLAN card specific delay */
> +               startup-delay-us = <70000>;
> +               enable-active-high;
> +       };
> +};
> +
> +&blsp1_i2c3 {
> +       /* On Low speed expansion: LS-I2C0 */
> +       status = "okay";
> +};
> +
> +&blsp1_spi1 {
> +       /* On Low speed expansion */
> +       status = "okay";
> +};
> +
> +&blsp1_uart2 {
> +       label = "BT-UART";
> +       status = "okay";
> +
> +       bluetooth {
> +               compatible = "qcom,qca6174-bt";
> +
> +               /* bt_disable_n gpio */
> +               enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
> +
> +               clocks = <&divclk4>;
> +       };
> +};
> +
> +&adsp_pil {
> +       status = "okay";
> +       firmware-name = "qcom/apq8096/adsp.mbn";
> +};
> +
> +&blsp2_i2c1 {
> +       /* On High speed expansion: HS-I2C2 */
> +       status = "okay";
> +};
> +
> +&blsp2_i2c1 {
> +       /* On Low speed expansion: LS-I2C1 */
> +       status = "okay";
> +};
> +
> +&blsp2_spi6 {
> +       /* On High speed expansion */
> +       status = "okay";
> +};
> +
> +&blsp2_uart2 {
> +       label = "LS-UART1";
> +       status = "okay";
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&blsp2_uart2_2pins_default>;
> +       pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
> +};
> +
> +&blsp2_uart3 {
> +       label = "LS-UART0";
> +       status = "disabled";
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&blsp2_uart3_4pins_default>;
> +       pinctrl-1 = <&blsp2_uart3_4pins_sleep>;
> +};
> +
> +&camss {
> +       vdda-supply = <&vreg_l2a_1p25>;
> +};
> +
> +&gpu {
> +       status = "okay";
> +};
> +
> +&hsusb_phy1 {
> +       status = "okay";
> +
> +       vdd-supply = <&vreg_l28a_0p925>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +       vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +};
> +
> +&hsusb_phy2 {
> +       status = "okay";
> +
> +       vdd-supply = <&vreg_l28a_0p925>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +       vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +};
> +
> +&mdp {
> +       status = "okay";
> +};
> +
> +&mdss {
> +       status = "okay";
> +};
> +
> +&mdss_hdmi {
> +       status = "okay";
> +
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
> +       pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
> +
> +       core-vdda-supply = <&vreg_l12a_1p8>;
> +       core-vcc-supply = <&vreg_s4a_1p8>;
> +};
> +
> +&mdss_hdmi_phy {
> +       status = "okay";
> +
> +       vddio-supply = <&vreg_l12a_1p8>;
> +       vcca-supply = <&vreg_l28a_0p925>;
> +       #phy-cells = <0>;
> +};
> +
> +&mmcc {
> +       vdd-gfx-supply = <&vdd_gfx>;
> +};
> +
> +&mss_pil {
> +       status = "okay";
> +       pll-supply = <&vreg_l12a_1p8>;
> +       firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn";
> +};
> +
> +&pm8994_resin {
> +       status = "okay";
> +       linux,code = <KEY_VOLUMEDOWN>;
> +};
> +
> +&tlmm {
> +       gpio-line-names =
> +               "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
> +               "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
> +               "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
> +               "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
> +               "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
> +               "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
> +               "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
> +               "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
> +               "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
> +               "TP93", /* GPIO_9 */
> +               "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
> +               "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> +               "NC", /* GPIO_12 */
> +               "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
> +               "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> +               "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
> +               "TP99", /* GPIO_16 */
> +               "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
> +               "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
> +               "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> +               "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> +               "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> +               "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
> +               "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
> +               "GPIO-D", /* GPIO_24, LSEC pin 26 */
> +               "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
> +               "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
> +               "BLSP6_I2C_SDA", /* GPIO_27 */
> +               "BLSP6_I2C_SCL", /* GPIO_28 */
> +               "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
> +               "GPIO30", /* GPIO_30, S HSEC pin 4 */
> +               "HDMI_CEC", /* GPIO_31 */
> +               "HDMI_DDC_CLOCK", /* GPIO_32 */
> +               "HDMI_DDC_DATA", /* GPIO_33 */
> +               "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
> +               "PCIE0_RST_N", /* GPIO_35 */
> +               "PCIE0_CLKREQ_N", /* GPIO_36 */
> +               "PCIE0_WAKE", /* GPIO_37 */
> +               "SD_CARD_DET_N", /* GPIO_38 */
> +               "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
> +               "W_DISABLE_N", /* GPIO_40 */
> +               "[BLSP9_UART_TX]", /* GPIO_41 */
> +               "[BLSP9_UART_RX]", /* GPIO_42 */
> +               "[BLSP2_UART_CTS_N]", /* GPIO_43 */
> +               "[BLSP2_UART_RFR_N]", /* GPIO_44 */
> +               "[BLSP3_UART_TX]", /* GPIO_45 */
> +               "[BLSP3_UART_RX]", /* GPIO_46 */
> +               "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
> +               "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
> +               "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
> +               "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
> +               "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
> +               "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
> +               "[CODEC_INT1_N]", /* GPIO_53 */
> +               "[CODEC_INT2_N]", /* GPIO_54 */
> +               "[BLSP7_I2C_SDA]", /* GPIO_55 */
> +               "[BLSP7_I2C_SCL]", /* GPIO_56 */
> +               "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
> +               "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
> +               "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
> +               "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
> +               "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
> +               "GPIO-E", /* GPIO_62, LSEC pin 27 */
> +               "TP87", /* GPIO_63 */
> +               "[CODEC_RST_N]", /* GPIO_64 */
> +               "[PCM1_CLK]", /* GPIO_65 */
> +               "[PCM1_SYNC]", /* GPIO_66 */
> +               "[PCM1_DIN]", /* GPIO_67 */
> +               "[PCM1_DOUT]", /* GPIO_68 */
> +               "AUDIO_REF_CLK", /* GPIO_69 */
> +               "SLIMBUS_CLK", /* GPIO_70 */
> +               "SLIMBUS_DATA0", /* GPIO_71 */
> +               "SLIMBUS_DATA1", /* GPIO_72 */
> +               "NC", /* GPIO_73 */
> +               "NC", /* GPIO_74 */
> +               "NC", /* GPIO_75 */
> +               "NC", /* GPIO_76 */
> +               "TP94", /* GPIO_77 */
> +               "NC", /* GPIO_78 */
> +               "TP95", /* GPIO_79 */
> +               "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
> +               "TP88", /* GPIO_81 */
> +               "TP89", /* GPIO_82 */
> +               "TP90", /* GPIO_83 */
> +               "TP91", /* GPIO_84 */
> +               "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
> +               "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
> +               "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
> +               "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
> +               "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
> +               "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
> +               "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
> +               "NC", /* GPIO_92 */
> +               "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
> +               "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
> +               "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
> +               "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
> +               "NC", /* GPIO_97 */
> +               "CAM1_STANDBY_N", /* GPIO_98 */
> +               "NC", /* GPIO_99 */
> +               "NC", /* GPIO_100 */
> +               "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
> +               "BOOT_CONFIG1", /* GPIO_102 */
> +               "USB_HUB_RESET", /* GPIO_103 */
> +               "CAM1_RST_N", /* GPIO_104 */
> +               "NC", /* GPIO_105 */
> +               "NC", /* GPIO_106 */
> +               "NC", /* GPIO_107 */
> +               "NC", /* GPIO_108 */
> +               "NC", /* GPIO_109 */
> +               "NC", /* GPIO_110 */
> +               "NC", /* GPIO_111 */
> +               "NC", /* GPIO_112 */
> +               "PMI8994_BUA", /* GPIO_113 */
> +               "PCIE2_RST_N", /* GPIO_114 */
> +               "PCIE2_CLKREQ_N", /* GPIO_115 */
> +               "PCIE2_WAKE", /* GPIO_116 */
> +               "SSC_IRQ_0", /* GPIO_117 */
> +               "SSC_IRQ_1", /* GPIO_118 */
> +               "SSC_IRQ_2", /* GPIO_119 */
> +               "NC", /* GPIO_120 */
> +               "GPIO121", /* GPIO_121, S HSEC pin 2 */
> +               "NC", /* GPIO_122 */
> +               "SSC_IRQ_6", /* GPIO_123 */
> +               "SSC_IRQ_7", /* GPIO_124 */
> +               "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
> +               "BOOT_CONFIG5", /* GPIO_126 */
> +               "NC", /* GPIO_127 */
> +               "NC", /* GPIO_128 */
> +               "BOOT_CONFIG7", /* GPIO_129 */
> +               "PCIE1_RST_N", /* GPIO_130 */
> +               "PCIE1_CLKREQ_N", /* GPIO_131 */
> +               "PCIE1_WAKE", /* GPIO_132 */
> +               "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
> +               "NC", /* GPIO_134 */
> +               "NC", /* GPIO_135 */
> +               "BOOT_CONFIG8", /* GPIO_136 */
> +               "NC", /* GPIO_137 */
> +               "NC", /* GPIO_138 */
> +               "GPS_SSBI2", /* GPIO_139 */
> +               "GPS_SSBI1", /* GPIO_140 */
> +               "NC", /* GPIO_141 */
> +               "NC", /* GPIO_142 */
> +               "NC", /* GPIO_143 */
> +               "BOOT_CONFIG6", /* GPIO_144 */
> +               "NC", /* GPIO_145 */
> +               "NC", /* GPIO_146 */
> +               "NC", /* GPIO_147 */
> +               "NC", /* GPIO_148 */
> +               "NC"; /* GPIO_149 */
> +
> +       sdc2_cd_on: sdc2-cd-on-state {
> +               pins = "gpio38";
> +               function = "gpio";
> +               bias-pull-up;
> +               drive-strength = <16>;
> +       };
> +
> +       sdc2_cd_off: sdc2-cd-off-state {
> +               pins = "gpio38";
> +               function = "gpio";
> +               bias-pull-up;
> +               drive-strength = <2>;
> +       };
> +
> +       hdmi_hpd_active: hdmi-hpd-active-state {
> +               pins = "gpio34";
> +               function = "hdmi_hot";
> +               bias-pull-down;
> +               drive-strength = <16>;
> +       };
> +
> +       hdmi_hpd_suspend: hdmi-hpd-suspend-state {
> +               pins = "gpio34";
> +               function = "hdmi_hot";
> +               bias-pull-down;
> +               drive-strength = <2>;
> +       };
> +
> +       hdmi_ddc_active: hdmi-ddc-active-state {
> +               pins = "gpio32", "gpio33";
> +               function = "hdmi_ddc";
> +               drive-strength = <2>;
> +               bias-pull-up;
> +       };
> +
> +       hdmi_ddc_suspend: hdmi-ddc-suspend-state {
> +               pins = "gpio32", "gpio33";
> +               function = "hdmi_ddc";
> +               drive-strength = <2>;
> +               bias-pull-down;
> +       };
> +};
> +
> +&pcie0 {
> +       status = "okay";
> +       perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
> +       vddpe-3v3-supply = <&wlan_en>;
> +       vdda-supply = <&vreg_l28a_0p925>;
> +};
> +
> +&pcie1 {
> +       status = "okay";
> +       perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
> +       vdda-supply = <&vreg_l28a_0p925>;
> +};
> +
> +&pcie2 {
> +       status = "okay";
> +       perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
> +       vdda-supply = <&vreg_l28a_0p925>;
> +};
> +
> +&pcie_phy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l28a_0p925>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +};
> +
> +&pm8994_gpios {
> +       gpio-line-names =
> +               "NC",
> +               "KEY_VOLP_N",
> +               "NC",
> +               "BL1_PWM",
> +               "GPIO-F", /* BL0_PWM, LSEC pin 28 */
> +               "BL1_EN",
> +               "NC",
> +               "WLAN_EN",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "DIVCLK1",
> +               "DIVCLK2",
> +               "DIVCLK3",
> +               "DIVCLK4",
> +               "BT_EN",
> +               "PMIC_SLB",
> +               "PMIC_BUA",
> +               "USB_VBUS_DET";
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
> +
> +       ls_exp_gpio_f: pm8994-gpio5-state {
> +               pinconf {
> +                       pins = "gpio5";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       output-low;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +               };
> +       };
> +
> +       bt_en_gpios: bt-en-pios-state {
> +               pinconf {
> +                       pins = "gpio19";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       output-low;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +                       qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
> +                       bias-pull-down;
> +               };
> +       };
> +
> +       wlan_en_gpios: wlan-en-gpios-state {
> +               pinconf {
> +                       pins = "gpio8";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       output-low;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +                       qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
> +                       bias-pull-down;
> +               };
> +       };
> +
> +       audio_mclk: clk-div1-state {
> +               pinconf {
> +                       pins = "gpio15";
> +                       function = "func1";
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +               };
> +       };
> +
> +       volume_up_gpio: pm8996-gpio2-state {
> +               pinconf {
> +                       pins = "gpio2";
> +                       function = "normal";
> +                       input-enable;
> +                       drive-push-pull;
> +                       bias-pull-up;
> +                       qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +               };
> +       };
> +
> +       divclk4_pin_a: divclk4-state {
> +               pinconf {
> +                       pins = "gpio18";
> +                       function = PMIC_GPIO_FUNC_FUNC2;
> +
> +                       bias-disable;
> +                       power-source = <PM8994_GPIO_S4>;
> +               };
> +       };
> +
> +       usb3_vbus_det_gpio: pm8996-gpio22-state {
> +               pinconf {
> +                       pins = "gpio22";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       input-enable;
> +                       bias-pull-down;
> +                       qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +               };
> +       };
> +};
> +
> +&pm8994_mpps {
> +       gpio-line-names =
> +               "VDDPX_BIAS",
> +               "WIFI_LED",
> +               "NC",
> +               "BT_LED",
> +               "PM_MPP05",
> +               "PM_MPP06",
> +               "PM_MPP07",
> +               "NC";
> +};
> +
> +&pm8994_spmi_regulators {
> +       qcom,saw-reg = <&saw3>;
> +       vdd_s11-supply = <&vph_pwr>;
> +
> +       s9 {
> +               qcom,saw-slave;
> +       };
> +       s10 {
> +               qcom,saw-slave;
> +       };
> +       s11 {
> +               qcom,saw-leader;
> +               regulator-name = "VDD_APCC";
> +               regulator-always-on;
> +               regulator-min-microvolt = <980000>;
> +               regulator-max-microvolt = <980000>;
> +       };
> +};
> +
> +&pmi8994_gpios {
> +       gpio-line-names =
> +               "NC",
> +               "SPKR_AMP_EN1",
> +               "SPKR_AMP_EN2",
> +               "TP61",
> +               "NC",
> +               "USB2_VBUS_DET",
> +               "NC",
> +               "NC",
> +               "NC",
> +               "NC";
> +
> +       usb2_vbus_det_gpio: pmi8996-gpio6-state {
> +               pinconf {
> +                       pins = "gpio6";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       input-enable;
> +                       bias-pull-down;
> +                       qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> +                       power-source = <PM8994_GPIO_S4>; /* 1.8V */
> +               };
> +       };
> +};
> +
> +&pmi8994_lpg {
> +       qcom,power-source = <1>;
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pmi8994_mpp2_userled4>;
> +
> +       qcom,dtest = <0 0>,
> +                    <0 0>,
> +                    <0 0>,
> +                    <4 1>;
> +
> +       status = "okay";
> +
> +       led@1 {
> +               reg = <1>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_HEARTBEAT;
> +               function-enumerator = <1>;
> +
> +               linux,default-trigger = "heartbeat";
> +               default-state = "on";
> +       };
> +
> +       led@2 {
> +               reg = <2>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_HEARTBEAT;
> +               function-enumerator = <0>;
> +       };
> +
> +       led@3 {
> +               reg = <3>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_HEARTBEAT;
> +               function-enumerator = <2>;
> +       };
> +
> +       led@4 {
> +               reg = <4>;
> +               color = <LED_COLOR_ID_GREEN>;
> +               function = LED_FUNCTION_HEARTBEAT;
> +               function-enumerator = <3>;
> +       };
> +};
> +
> +&pmi8994_mpps {
> +       pmi8994_mpp2_userled4: mpp2-userled4-state {
> +               pins = "mpp2";
> +               function = "sink";
> +
> +               output-low;
> +               qcom,dtest = <4>;
> +       };
> +};
> +
> +&pmi8994_spmi_regulators {
> +       vdd_s2-supply = <&vph_pwr>;
> +
> +       vdd_gfx: s2 {
> +               regulator-name = "VDD_GFX";
> +               regulator-min-microvolt = <980000>;
> +               regulator-max-microvolt = <980000>;
> +       };
> +};
> +
> +&rpm_requests {
> +       regulators-0 {
> +               compatible = "qcom,rpm-pm8994-regulators";
> +
> +               vdd_s1-supply = <&vph_pwr>;
> +               vdd_s2-supply = <&vph_pwr>;
> +               vdd_s3-supply = <&vph_pwr>;
> +               vdd_s4-supply = <&vph_pwr>;
> +               vdd_s5-supply = <&vph_pwr>;
> +               vdd_s6-supply = <&vph_pwr>;
> +               vdd_s7-supply = <&vph_pwr>;
> +               vdd_s8-supply = <&vph_pwr>;
> +               vdd_s9-supply = <&vph_pwr>;
> +               vdd_s10-supply = <&vph_pwr>;
> +               vdd_s11-supply = <&vph_pwr>;
> +               vdd_s12-supply = <&vph_pwr>;
> +               vdd_l1-supply = <&vreg_s1b_1p025>;
> +               vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
> +               vdd_l3_l11-supply = <&vreg_s3a_1p3>;
> +               vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
> +               vdd_l5_l7-supply = <&vreg_s5a_2p15>;
> +               vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
> +               vdd_l8_l16_l30-supply = <&vph_pwr>;
> +               vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
> +               vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
> +               vdd_l14_l15-supply = <&vreg_s5a_2p15>;
> +               vdd_l17_l29-supply = <&vph_pwr_bbyp>;
> +               vdd_l20_l21-supply = <&vph_pwr_bbyp>;
> +               vdd_l25-supply = <&vreg_s3a_1p3>;
> +               vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
> +
> +               vreg_s3a_1p3: s3 {
> +                       regulator-name = "vreg_s3a_1p3";
> +                       regulator-min-microvolt = <1300000>;
> +                       regulator-max-microvolt = <1300000>;
> +               };
> +
> +               /**
> +                * 1.8v required on LS expansion
> +                * for mezzanine boards
> +                */
> +               vreg_s4a_1p8: s4 {
> +                       regulator-name = "vreg_s4a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on;
> +               };
> +               vreg_s5a_2p15: s5 {
> +                       regulator-name = "vreg_s5a_2p15";
> +                       regulator-min-microvolt = <2150000>;
> +                       regulator-max-microvolt = <2150000>;
> +               };
> +               vreg_s7a_1p0: s7 {
> +                       regulator-name = "vreg_s7a_1p0";
> +                       regulator-min-microvolt = <800000>;
> +                       regulator-max-microvolt = <800000>;
> +               };
> +
> +               vreg_l1a_1p0: l1 {
> +                       regulator-name = "vreg_l1a_1p0";
> +                       regulator-min-microvolt = <1000000>;
> +                       regulator-max-microvolt = <1000000>;
> +               };
> +               vreg_l2a_1p25: l2 {
> +                       regulator-name = "vreg_l2a_1p25";
> +                       regulator-min-microvolt = <1250000>;
> +                       regulator-max-microvolt = <1250000>;
> +               };
> +               vreg_l3a_0p875: l3 {
> +                       regulator-name = "vreg_l3a_0p875";
> +                       regulator-min-microvolt = <850000>;
> +                       regulator-max-microvolt = <850000>;
> +               };
> +               vreg_l4a_1p225: l4 {
> +                       regulator-name = "vreg_l4a_1p225";
> +                       regulator-min-microvolt = <1225000>;
> +                       regulator-max-microvolt = <1225000>;
> +               };
> +               vreg_l6a_1p2: l6 {
> +                       regulator-name = "vreg_l6a_1p2";
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +               };
> +               vreg_l8a_1p8: l8 {
> +                       regulator-name = "vreg_l8a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l9a_1p8: l9 {
> +                       regulator-name = "vreg_l9a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l10a_1p8: l10 {
> +                       regulator-name = "vreg_l10a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l11a_1p15: l11 {
> +                       regulator-name = "vreg_l11a_1p15";
> +                       regulator-min-microvolt = <1150000>;
> +                       regulator-max-microvolt = <1150000>;
> +               };
> +               vreg_l12a_1p8: l12 {
> +                       regulator-name = "vreg_l12a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l13a_2p95: l13 {
> +                       regulator-name = "vreg_l13a_2p95";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <2950000>;
> +               };
> +               vreg_l14a_1p8: l14 {
> +                       regulator-name = "vreg_l14a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l15a_1p8: l15 {
> +                       regulator-name = "vreg_l15a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l16a_2p7: l16 {
> +                       regulator-name = "vreg_l16a_2p7";
> +                       regulator-min-microvolt = <2700000>;
> +                       regulator-max-microvolt = <2700000>;
> +               };
> +               vreg_l17a_2p8: l17 {
> +                       regulator-name = "vreg_l17a_2p8";
> +                       regulator-min-microvolt = <2500000>;
> +                       regulator-max-microvolt = <2500000>;
> +               };
> +               vreg_l18a_2p85: l18 {
> +                       regulator-name = "vreg_l18a_2p85";
> +                       regulator-min-microvolt = <2700000>;
> +                       regulator-max-microvolt = <2900000>;
> +               };
> +               vreg_l19a_2p8: l19 {
> +                       regulator-name = "vreg_l19a_2p8";
> +                       regulator-min-microvolt = <3000000>;
> +                       regulator-max-microvolt = <3000000>;
> +               };
> +               vreg_l20a_2p95: l20 {
> +                       regulator-name = "vreg_l20a_2p95";
> +                       regulator-min-microvolt = <2950000>;
> +                       regulator-max-microvolt = <2950000>;
> +                       regulator-allow-set-load;
> +               };
> +               vreg_l21a_2p95: l21 {
> +                       regulator-name = "vreg_l21a_2p95";
> +                       regulator-min-microvolt = <2950000>;
> +                       regulator-max-microvolt = <2950000>;
> +                       regulator-allow-set-load;
> +                       regulator-system-load = <200000>;
> +               };
> +               vreg_l22a_3p0: l22 {
> +                       regulator-name = "vreg_l22a_3p0";
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3300000>;
> +               };
> +               vreg_l23a_2p8: l23 {
> +                       regulator-name = "vreg_l23a_2p8";
> +                       regulator-min-microvolt = <2800000>;
> +                       regulator-max-microvolt = <2800000>;
> +               };
> +               vreg_l24a_3p075: l24 {
> +                       regulator-name = "vreg_l24a_3p075";
> +                       regulator-min-microvolt = <3075000>;
> +                       regulator-max-microvolt = <3075000>;
> +               };
> +               vreg_l25a_1p2: l25 {
> +                       regulator-name = "vreg_l25a_1p2";
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +                       regulator-allow-set-load;
> +               };
> +               vreg_l26a_0p8: l27 {
> +                       regulator-name = "vreg_l26a_0p8";
> +                       regulator-min-microvolt = <1000000>;
> +                       regulator-max-microvolt = <1000000>;
> +               };
> +               vreg_l28a_0p925: l28 {
> +                       regulator-name = "vreg_l28a_0p925";
> +                       regulator-min-microvolt = <925000>;
> +                       regulator-max-microvolt = <925000>;
> +                       regulator-allow-set-load;
> +               };
> +               vreg_l29a_2p8: l29 {
> +                       regulator-name = "vreg_l29a_2p8";
> +                       regulator-min-microvolt = <2800000>;
> +                       regulator-max-microvolt = <2800000>;
> +               };
> +               vreg_l30a_1p8: l30 {
> +                       regulator-name = "vreg_l30a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +               vreg_l32a_1p8: l32 {
> +                       regulator-name = "vreg_l32a_1p8";
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +
> +               vreg_lvs1a_1p8: lvs1 {
> +                       regulator-name = "vreg_lvs1a_1p8";
> +               };
> +
> +               vreg_lvs2a_1p8: lvs2 {
> +                       regulator-name = "vreg_lvs2a_1p8";
> +               };
> +       };
> +
> +       regulators-1 {
> +               compatible = "qcom,rpm-pmi8994-regulators";
> +
> +               vdd_s1-supply = <&vph_pwr>;
> +               vdd_s2-supply = <&vph_pwr>;
> +               vdd_s3-supply = <&vph_pwr>;
> +               vdd_bst_byp-supply = <&vph_pwr>;
> +
> +               vph_pwr_bbyp: boost-bypass {
> +                       regulator-name = "vph_pwr_bbyp";
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3300000>;
> +               };
> +
> +               vreg_s1b_1p025: s1 {
> +                       regulator-name = "vreg_s1b_1p025";
> +                       regulator-min-microvolt = <1025000>;
> +                       regulator-max-microvolt = <1025000>;
> +               };
> +       };
> +};
> +
> +&sdhc2 {
> +       /* External SD card */
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>;
> +       pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>;
> +       cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
> +       vmmc-supply = <&vreg_l21a_2p95>;
> +       vqmmc-supply = <&vreg_l13a_2p95>;
> +       status = "okay";
> +};
> +
> +&q6asmdai {
> +       dai@0 {
> +               reg = <0>;
> +       };
> +
> +       dai@1 {
> +               reg = <1>;
> +       };
> +
> +       dai@2 {
> +               reg = <2>;
> +       };
> +};
> +
> +&slim_msm {
> +       status = "okay";
> +
> +       slim@1 {
> +               reg = <1>;
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               tasha_ifd: tas-ifd@0,0 {
> +                       compatible = "slim217,1a0";
> +                       reg = <0 0>;
> +               };
> +
> +               wcd9335: codec@1,0 {
> +                       compatible = "slim217,1a0";
> +                       reg = <1 0>;
> +
> +                       clock-names = "mclk", "slimbus";
> +                       clocks = <&div1_mclk>,
> +                                <&rpmcc RPM_SMD_BB_CLK1>;
> +                       interrupt-parent = <&tlmm>;
> +                       interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <53 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "intr1", "intr2";
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
> +                       pinctrl-names = "default";
> +
> +                       reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
> +                       slim-ifc-dev = <&tasha_ifd>;
> +
> +                       #sound-dai-cells = <1>;
> +
> +                       vdd-buck-supply = <&vreg_s4a_1p8>;
> +                       vdd-buck-sido-supply = <&vreg_s4a_1p8>;
> +                       vdd-tx-supply = <&vreg_s4a_1p8>;
> +                       vdd-rx-supply = <&vreg_s4a_1p8>;
> +                       vdd-io-supply = <&vreg_s4a_1p8>;
> +               };
> +       };
> +};
> +
> +&sound {
> +       compatible = "qcom,apq8096-sndcard";
> +       model = "DB820c";
> +       audio-routing = "RX_BIAS", "MCLK",
> +               "MM_DL1",  "MultiMedia1 Playback",
> +               "MM_DL2",  "MultiMedia2 Playback",
> +               "MultiMedia3 Capture", "MM_UL3";
> +
> +       mm1-dai-link {
> +               link-name = "MultiMedia1";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
> +               };
> +       };
> +
> +       mm2-dai-link {
> +               link-name = "MultiMedia2";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
> +               };
> +       };
> +
> +       mm3-dai-link {
> +               link-name = "MultiMedia3";
> +               cpu {
> +                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
> +               };
> +       };
> +
> +       hdmi-dai-link {
> +               link-name = "HDMI";
> +               cpu {
> +                       sound-dai = <&q6afedai HDMI_RX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&mdss_hdmi 0>;
> +               };
> +       };
> +
> +       slim-dai-link {
> +               link-name = "SLIM Playback";
> +               cpu {
> +                       sound-dai = <&q6afedai SLIMBUS_6_RX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&wcd9335 AIF4_PB>;
> +               };
> +       };
> +
> +       slimcap-dai-link {
> +               link-name = "SLIM Capture";
> +               cpu {
> +                       sound-dai = <&q6afedai SLIMBUS_0_TX>;
> +               };
> +
> +               platform {
> +                       sound-dai = <&q6routing>;
> +               };
> +
> +               codec {
> +                       sound-dai = <&wcd9335 AIF1_CAP>;
> +               };
> +       };
> +};
> +
> +&ufsphy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l28a_0p925>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +};
> +
> +&ufshc {
> +       status = "okay";
> +
> +       vcc-supply = <&vreg_l20a_2p95>;
> +       vccq-supply = <&vreg_l25a_1p2>;
> +       vccq2-supply = <&vreg_s4a_1p8>;
> +       vdd-hba-supply = <&vreg_l25a_1p2>;
> +
> +       vcc-max-microamp = <600000>;
> +       vccq-max-microamp = <450000>;
> +       vccq2-max-microamp = <450000>;
> +};
> +
> +&usb2 {
> +       status = "okay";
> +       extcon = <&usb2_id>;
> +};
> +
> +&usb2_dwc3 {
> +       extcon = <&usb2_id>;
> +       dr_mode = "otg";
> +       maximum-speed = "high-speed";
> +};
> +
> +&usb3 {
> +       status = "okay";
> +       extcon = <&usb3_id>;
> +};
> +
> +&usb3_dwc3 {
> +       extcon = <&usb3_id>;
> +       dr_mode = "otg";
> +};
> +
> +&usb3phy {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vreg_l28a_0p925>;
> +       vdda-pll-supply = <&vreg_l12a_1p8>;
> +};
> +
> +&venus {
> +       status = "okay";
> +};
> diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
> deleted file mode 100644
> index d93c7c1fbdee..000000000000
> --- a/arch/arm/dts/dragonboard820c-uboot.dtsi
> +++ /dev/null
> @@ -1,32 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * U-Boot addition to handle Dragonboard 820c pins
> - *
> - * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> - */
> -
> -/ {
> -       smem {
> -               bootph-all;
> -       };
> -
> -       soc {
> -               bootph-all;
> -
> -               pinctrl@1010000 {
> -                       bootph-all;
> -
> -                       uart {
> -                               bootph-all;
> -                       };
> -               };
> -
> -               clock-controller@300000 {
> -                       bootph-all;
> -               };
> -
> -               serial@75b0000 {
> -                       bootph-all;
> -               };
> -       };
> -};
> diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
> deleted file mode 100644
> index 282c37e28f42..000000000000
> --- a/arch/arm/dts/dragonboard820c.dts
> +++ /dev/null
> @@ -1,153 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm APQ8096 based Dragonboard 820C board device tree source
> - *
> - * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> - */
> -
> -/dts-v1/;
> -
> -#include "skeleton64.dtsi"
> -#include <dt-bindings/clock/qcom,gcc-msm8996.h>
> -
> -/ {
> -       model = "Qualcomm Technologies, Inc. DB820c";
> -       compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
> -       #address-cells = <2>;
> -       #size-cells = <2>;
> -
> -       aliases {
> -               serial0 = &blsp2_uart2;
> -       };
> -
> -       chosen {
> -               stdout-path = "serial0:115200n8";
> -       };
> -
> -       memory {
> -               device_type = "memory";
> -               reg = <0 0x80000000 0 0xc0000000>;
> -       };
> -
> -       reserved-memory {
> -               #address-cells = <2>;
> -               #size-cells = <2>;
> -               ranges;
> -
> -               smem_mem: smem_region@86300000 {
> -                       reg = <0x0 0x86300000 0x0 0x200000>;
> -                       no-map;
> -               };
> -       };
> -
> -       psci {
> -               compatible = "arm,psci-1.0";
> -               method = "smc";
> -       };
> -
> -       smem {
> -               compatible = "qcom,smem";
> -               memory-region = <&smem_mem>;
> -       };
> -
> -       soc: soc {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               ranges = <0 0 0 0xffffffff>;
> -               compatible = "simple-bus";
> -
> -               gcc: clock-controller@300000 {
> -                       compatible = "qcom,gcc-msm8996";
> -                       #clock-cells = <1>;
> -                       #reset-cells = <1>;
> -                       #power-domain-cells = <1>;
> -                       reg = <0x300000 0x90000>;
> -               };
> -
> -               pinctrl: pinctrl@1010000 {
> -                       compatible = "qcom,msm8996-pinctrl";
> -                       reg = <0x1010000 0x400000>;
> -
> -                       blsp8_uart: uart {
> -                               function = "blsp_uart8";
> -                               pins = "GPIO_4", "GPIO_5";
> -                               drive-strength = <8>;
> -                               bias-disable;
> -                       };
> -               };
> -
> -               blsp2_uart2: serial@75b0000 {
> -                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> -                       reg = <0x75b0000 0x1000>;
> -                       clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
> -                       clock-names = "core";
> -                       pinctrl-names = "uart";
> -                       pinctrl-0 = <&blsp8_uart>;
> -               };
> -
> -               sdhc2: sdhci@74a4900 {
> -                       compatible = "qcom,sdhci-msm-v4";
> -                       reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
> -                       index = <0x0>;
> -                       bus-width = <4>;
> -                       clock = <&gcc GCC_SDCC1_APPS_CLK>;
> -                       clock-frequency = <200000000>;
> -                };
> -
> -               spmi_bus: spmi@400f000 {
> -                       compatible = "qcom,spmi-pmic-arb";
> -                       reg = <0x0400f000 0x1000>,
> -                             <0x04400000 0x800000>,
> -                             <0x04c00000 0x800000>,
> -                             <0x05800000 0x200000>,
> -                             <0x0400a000 0x002100>;
> -                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x1>;
> -
> -                       pmic0: pm8994@0 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x0 0x1>;
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x1>;
> -
> -                               pm8994_pon: pon@800 {
> -                                       compatible = "qcom,pm8916-pon";
> -                                       reg = <0x800 0x100>;
> -                                       mode-bootloader = <0x2>;
> -                                       mode-recovery = <0x1>;
> -
> -                                       pwrkey {
> -                                               compatible = "qcom,pm8941-pwrkey";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                       };
> -
> -                                       pm8994_resin: resin {
> -                                               compatible = "qcom,pm8941-resin";
> -                                               debounce = <15625>;
> -                                               bias-pull-up;
> -                                       };
> -                               };
> -
> -                               pm8994_gpios: pm8994_gpios@c000 {
> -                                       compatible = "qcom,pm8994-gpio";
> -                                       reg = <0xc000 0x400>;
> -                                       gpio-controller;
> -                                       gpio-ranges = <&pm8994_gpios 0 0 22>;
> -                                       #gpio-cells = <2>;
> -                               };
> -                       };
> -
> -                       pmic1: pm8994@1 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x1 0x1>;
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x1>;
> -                       };
> -               };
> -       };
> -
> -};
> -
> -#include "dragonboard820c-uboot.dtsi"
> diff --git a/arch/arm/dts/msm8996.dtsi b/arch/arm/dts/msm8996.dtsi
> new file mode 100644
> index 000000000000..6ba9da9e6a8b
> --- /dev/null
> +++ b/arch/arm/dts/msm8996.dtsi
> @@ -0,0 +1,3884 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8996.h>
> +#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/interconnect/qcom,msm8996.h>
> +#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
> +#include <dt-bindings/firmware/qcom,scm.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,apr.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <19200000>;
> +                       clock-output-names = "xo_board";
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <32764>;
> +                       clock-output-names = "sleep_clk";
> +               };
> +       };
> +
> +       cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo";
> +                       reg = <0x0 0x0>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       clocks = <&kryocc 0>;
> +                       interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
> +                       operating-points-v2 = <&cluster0_opp>;
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_0>;
> +                       L2_0: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                       };
> +               };
> +
> +               CPU1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo";
> +                       reg = <0x0 0x1>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       clocks = <&kryocc 0>;
> +                       interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
> +                       operating-points-v2 = <&cluster0_opp>;
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_0>;
> +               };
> +
> +               CPU2: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo";
> +                       reg = <0x0 0x100>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       clocks = <&kryocc 1>;
> +                       interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
> +                       operating-points-v2 = <&cluster1_opp>;
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_1>;
> +                       L2_1: l2-cache {
> +                               compatible = "cache";
> +                               cache-level = <2>;
> +                               cache-unified;
> +                       };
> +               };
> +
> +               CPU3: cpu@101 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo";
> +                       reg = <0x0 0x101>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       clocks = <&kryocc 1>;
> +                       interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
> +                       operating-points-v2 = <&cluster1_opp>;
> +                       #cooling-cells = <2>;
> +                       next-level-cache = <&L2_1>;
> +               };
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&CPU0>;
> +                               };
> +
> +                               core1 {
> +                                       cpu = <&CPU1>;
> +                               };
> +                       };
> +
> +                       cluster1 {
> +                               core0 {
> +                                       cpu = <&CPU2>;
> +                               };
> +
> +                               core1 {
> +                                       cpu = <&CPU3>;
> +                               };
> +                       };
> +               };
> +
> +               idle-states {
> +                       entry-method = "psci";
> +
> +                       CPU_SLEEP_0: cpu-sleep-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "standalone-power-collapse";
> +                               arm,psci-suspend-param = <0x00000004>;
> +                               entry-latency-us = <130>;
> +                               exit-latency-us = <80>;
> +                               min-residency-us = <300>;
> +                       };
> +               };
> +       };
> +
> +       cluster0_opp: opp-table-cluster0 {
> +               compatible = "operating-points-v2-kryo-cpu";
> +               nvmem-cells = <&speedbin_efuse>;
> +               opp-shared;
> +
> +               /* Nominal fmax for now */
> +               opp-307200000 {
> +                       opp-hz = /bits/ 64 <307200000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-422400000 {
> +                       opp-hz = /bits/ 64 <422400000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-480000000 {
> +                       opp-hz = /bits/ 64 <480000000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-556800000 {
> +                       opp-hz = /bits/ 64 <556800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-652800000 {
> +                       opp-hz = /bits/ 64 <652800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <384000>;
> +               };
> +               opp-729600000 {
> +                       opp-hz = /bits/ 64 <729600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <460800>;
> +               };
> +               opp-844800000 {
> +                       opp-hz = /bits/ 64 <844800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <537600>;
> +               };
> +               opp-960000000 {
> +                       opp-hz = /bits/ 64 <960000000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <672000>;
> +               };
> +               opp-1036800000 {
> +                       opp-hz = /bits/ 64 <1036800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <672000>;
> +               };
> +               opp-1113600000 {
> +                       opp-hz = /bits/ 64 <1113600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <825600>;
> +               };
> +               opp-1190400000 {
> +                       opp-hz = /bits/ 64 <1190400000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <825600>;
> +               };
> +               opp-1228800000 {
> +                       opp-hz = /bits/ 64 <1228800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <902400>;
> +               };
> +               opp-1324800000 {
> +                       opp-hz = /bits/ 64 <1324800000>;
> +                       opp-supported-hw = <0xd>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1056000>;
> +               };
> +               opp-1363200000 {
> +                       opp-hz = /bits/ 64 <1363200000>;
> +                       opp-supported-hw = <0x2>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1132800>;
> +               };
> +               opp-1401600000 {
> +                       opp-hz = /bits/ 64 <1401600000>;
> +                       opp-supported-hw = <0xd>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1132800>;
> +               };
> +               opp-1478400000 {
> +                       opp-hz = /bits/ 64 <1478400000>;
> +                       opp-supported-hw = <0x9>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1190400>;
> +               };
> +               opp-1497600000 {
> +                       opp-hz = /bits/ 64 <1497600000>;
> +                       opp-supported-hw = <0x04>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1305600>;
> +               };
> +               opp-1593600000 {
> +                       opp-hz = /bits/ 64 <1593600000>;
> +                       opp-supported-hw = <0x9>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1382400>;
> +               };
> +       };
> +
> +       cluster1_opp: opp-table-cluster1 {
> +               compatible = "operating-points-v2-kryo-cpu";
> +               nvmem-cells = <&speedbin_efuse>;
> +               opp-shared;
> +
> +               /* Nominal fmax for now */
> +               opp-307200000 {
> +                       opp-hz = /bits/ 64 <307200000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-403200000 {
> +                       opp-hz = /bits/ 64 <403200000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-480000000 {
> +                       opp-hz = /bits/ 64 <480000000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-556800000 {
> +                       opp-hz = /bits/ 64 <556800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-652800000 {
> +                       opp-hz = /bits/ 64 <652800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-729600000 {
> +                       opp-hz = /bits/ 64 <729600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <307200>;
> +               };
> +               opp-806400000 {
> +                       opp-hz = /bits/ 64 <806400000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <384000>;
> +               };
> +               opp-883200000 {
> +                       opp-hz = /bits/ 64 <883200000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <460800>;
> +               };
> +               opp-940800000 {
> +                       opp-hz = /bits/ 64 <940800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <537600>;
> +               };
> +               opp-1036800000 {
> +                       opp-hz = /bits/ 64 <1036800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <595200>;
> +               };
> +               opp-1113600000 {
> +                       opp-hz = /bits/ 64 <1113600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <672000>;
> +               };
> +               opp-1190400000 {
> +                       opp-hz = /bits/ 64 <1190400000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <672000>;
> +               };
> +               opp-1248000000 {
> +                       opp-hz = /bits/ 64 <1248000000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <748800>;
> +               };
> +               opp-1324800000 {
> +                       opp-hz = /bits/ 64 <1324800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <825600>;
> +               };
> +               opp-1401600000 {
> +                       opp-hz = /bits/ 64 <1401600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <902400>;
> +               };
> +               opp-1478400000 {
> +                       opp-hz = /bits/ 64 <1478400000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <979200>;
> +               };
> +               opp-1555200000 {
> +                       opp-hz = /bits/ 64 <1555200000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1056000>;
> +               };
> +               opp-1632000000 {
> +                       opp-hz = /bits/ 64 <1632000000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1190400>;
> +               };
> +               opp-1708800000 {
> +                       opp-hz = /bits/ 64 <1708800000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1228800>;
> +               };
> +               opp-1785600000 {
> +                       opp-hz = /bits/ 64 <1785600000>;
> +                       opp-supported-hw = <0xf>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1305600>;
> +               };
> +               opp-1804800000 {
> +                       opp-hz = /bits/ 64 <1804800000>;
> +                       opp-supported-hw = <0xe>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1305600>;
> +               };
> +               opp-1824000000 {
> +                       opp-hz = /bits/ 64 <1824000000>;
> +                       opp-supported-hw = <0x1>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1382400>;
> +               };
> +               opp-1900800000 {
> +                       opp-hz = /bits/ 64 <1900800000>;
> +                       opp-supported-hw = <0x4>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1305600>;
> +               };
> +               opp-1920000000 {
> +                       opp-hz = /bits/ 64 <1920000000>;
> +                       opp-supported-hw = <0x1>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1459200>;
> +               };
> +               opp-1996800000 {
> +                       opp-hz = /bits/ 64 <1996800000>;
> +                       opp-supported-hw = <0x1>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1593600>;
> +               };
> +               opp-2073600000 {
> +                       opp-hz = /bits/ 64 <2073600000>;
> +                       opp-supported-hw = <0x1>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1593600>;
> +               };
> +               opp-2150400000 {
> +                       opp-hz = /bits/ 64 <2150400000>;
> +                       opp-supported-hw = <0x1>;
> +                       clock-latency-ns = <200000>;
> +                       opp-peak-kBps = <1593600>;
> +               };
> +       };
> +
> +       firmware {
> +               scm {
> +                       compatible = "qcom,scm-msm8996", "qcom,scm";
> +                       qcom,dload-mode = <&tcsr_2 0x13000>;
> +               };
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the reg */
> +               reg = <0x0 0x80000000 0x0 0x0>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       rpm: remoteproc {
> +               compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
> +
> +               glink-edge {
> +                       compatible = "qcom,glink-rpm";
> +                       interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> +                       qcom,rpm-msg-ram = <&rpm_msg_ram>;
> +                       mboxes = <&apcs_glb 0>;
> +
> +                       rpm_requests: rpm-requests {
> +                               compatible = "qcom,rpm-msm8996";
> +                               qcom,glink-channels = "rpm_requests";
> +
> +                               rpmcc: clock-controller {
> +                                       compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
> +                                       #clock-cells = <1>;
> +                                       clocks = <&xo_board>;
> +                                       clock-names = "xo";
> +                               };
> +
> +                               rpmpd: power-controller {
> +                                       compatible = "qcom,msm8996-rpmpd";
> +                                       #power-domain-cells = <1>;
> +                                       operating-points-v2 = <&rpmpd_opp_table>;
> +
> +                                       rpmpd_opp_table: opp-table {
> +                                               compatible = "operating-points-v2";
> +
> +                                               rpmpd_opp1: opp1 {
> +                                                       opp-level = <1>;
> +                                               };
> +
> +                                               rpmpd_opp2: opp2 {
> +                                                       opp-level = <2>;
> +                                               };
> +
> +                                               rpmpd_opp3: opp3 {
> +                                                       opp-level = <3>;
> +                                               };
> +
> +                                               rpmpd_opp4: opp4 {
> +                                                       opp-level = <4>;
> +                                               };
> +
> +                                               rpmpd_opp5: opp5 {
> +                                                       opp-level = <5>;
> +                                               };
> +
> +                                               rpmpd_opp6: opp6 {
> +                                                       opp-level = <6>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +               };
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               hyp_mem: memory@85800000 {
> +                       reg = <0x0 0x85800000 0x0 0x600000>;
> +                       no-map;
> +               };
> +
> +               xbl_mem: memory@85e00000 {
> +                       reg = <0x0 0x85e00000 0x0 0x200000>;
> +                       no-map;
> +               };
> +
> +               smem_mem: smem-mem@86000000 {
> +                       reg = <0x0 0x86000000 0x0 0x200000>;
> +                       no-map;
> +               };
> +
> +               tz_mem: memory@86200000 {
> +                       reg = <0x0 0x86200000 0x0 0x2600000>;
> +                       no-map;
> +               };
> +
> +               rmtfs_mem: rmtfs {
> +                       compatible = "qcom,rmtfs-mem";
> +
> +                       size = <0x0 0x200000>;
> +                       alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
> +                       no-map;
> +
> +                       qcom,client-id = <1>;
> +                       qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
> +               };
> +
> +               mpss_mem: mpss@88800000 {
> +                       reg = <0x0 0x88800000 0x0 0x6200000>;
> +                       no-map;
> +               };
> +
> +               adsp_mem: adsp@8ea00000 {
> +                       reg = <0x0 0x8ea00000 0x0 0x1b00000>;
> +                       no-map;
> +               };
> +
> +               slpi_mem: slpi@90500000 {
> +                       reg = <0x0 0x90500000 0x0 0xa00000>;
> +                       no-map;
> +               };
> +
> +               gpu_mem: gpu@90f00000 {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0x0 0x90f00000 0x0 0x100000>;
> +                       no-map;
> +               };
> +
> +               venus_mem: venus@91000000 {
> +                       reg = <0x0 0x91000000 0x0 0x500000>;
> +                       no-map;
> +               };
> +
> +               mba_mem: mba@91500000 {
> +                       reg = <0x0 0x91500000 0x0 0x200000>;
> +                       no-map;
> +               };
> +
> +               mdata_mem: mpss-metadata {
> +                       alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
> +                       size = <0x0 0x4000>;
> +                       no-map;
> +               };
> +       };
> +
> +       smem {
> +               compatible = "qcom,smem";
> +               memory-region = <&smem_mem>;
> +               hwlocks = <&tcsr_mutex 3>;
> +       };
> +
> +       smp2p-adsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <443>, <429>;
> +
> +               interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
> +
> +               mboxes = <&apcs_glb 10>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <2>;
> +
> +               adsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               adsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-mpss {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <435>, <428>;
> +
> +               interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
> +
> +               mboxes = <&apcs_glb 14>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <1>;
> +
> +               mpss_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               mpss_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-slpi {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <481>, <430>;
> +
> +               interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
> +
> +               mboxes = <&apcs_glb 26>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <3>;
> +
> +               slpi_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               slpi_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       soc: soc@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0 0 0 0xffffffff>;
> +               compatible = "simple-bus";
> +
> +               pcie_phy: phy-wrapper@34000 {
> +                       compatible = "qcom,msm8996-qmp-pcie-phy";
> +                       reg = <0x00034000 0x488>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0x0 0x00034000 0x4000>;
> +
> +                       clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +                               <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
> +                               <&gcc GCC_PCIE_CLKREF_CLK>;
> +                       clock-names = "aux", "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_PCIE_PHY_BCR>,
> +                               <&gcc GCC_PCIE_PHY_COM_BCR>,
> +                               <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
> +                       reset-names = "phy", "common", "cfg";
> +
> +                       status = "disabled";
> +
> +                       pciephy_0: phy@1000 {
> +                               reg = <0x1000 0x130>,
> +                                     <0x1200 0x200>,
> +                                     <0x1400 0x1dc>;
> +
> +                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> +                               clock-names = "pipe0";
> +                               resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> +                               reset-names = "lane0";
> +
> +                               #clock-cells = <0>;
> +                               clock-output-names = "pcie_0_pipe_clk_src";
> +
> +                               #phy-cells = <0>;
> +                       };
> +
> +                       pciephy_1: phy@2000 {
> +                               reg = <0x2000 0x130>,
> +                                     <0x2200 0x200>,
> +                                     <0x2400 0x1dc>;
> +
> +                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> +                               clock-names = "pipe1";
> +                               resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> +                               reset-names = "lane1";
> +
> +                               #clock-cells = <0>;
> +                               clock-output-names = "pcie_1_pipe_clk_src";
> +
> +                               #phy-cells = <0>;
> +                       };
> +
> +                       pciephy_2: phy@3000 {
> +                               reg = <0x3000 0x130>,
> +                                     <0x3200 0x200>,
> +                                     <0x3400 0x1dc>;
> +
> +                               clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
> +                               clock-names = "pipe2";
> +                               resets = <&gcc GCC_PCIE_2_PHY_BCR>;
> +                               reset-names = "lane2";
> +
> +                               #clock-cells = <0>;
> +                               clock-output-names = "pcie_2_pipe_clk_src";
> +
> +                               #phy-cells = <0>;
> +                       };
> +               };
> +
> +               rpm_msg_ram: sram@68000 {
> +                       compatible = "qcom,rpm-msg-ram";
> +                       reg = <0x00068000 0x6000>;
> +               };
> +
> +               qfprom@74000 {
> +                       compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
> +                       reg = <0x00074000 0x8ff>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       qusb2p_hstx_trim: hstx_trim@24e {
> +                               reg = <0x24e 0x2>;
> +                               bits = <5 4>;
> +                       };
> +
> +                       qusb2s_hstx_trim: hstx_trim@24f {
> +                               reg = <0x24f 0x1>;
> +                               bits = <1 4>;
> +                       };
> +
> +                       speedbin_efuse: speedbin@133 {
> +                               reg = <0x133 0x1>;
> +                               bits = <5 3>;
> +                       };
> +               };
> +
> +               rng: rng@83000 {
> +                       compatible = "qcom,prng-ee";
> +                       reg = <0x00083000 0x1000>;
> +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
> +                       clock-names = "core";
> +               };
> +
> +               gcc: clock-controller@300000 {
> +                       compatible = "qcom,gcc-msm8996";
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       reg = <0x00300000 0x90000>;
> +
> +                       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> +                                <&rpmcc RPM_SMD_LN_BB_CLK>,
> +                                <&sleep_clk>,
> +                                <&pciephy_0>,
> +                                <&pciephy_1>,
> +                                <&pciephy_2>,
> +                                <&ssusb_phy_0>,
> +                                <&ufsphy_lane 0>,
> +                                <&ufsphy_lane 1>,
> +                                <&ufsphy_lane 2>;
> +                       clock-names = "cxo",
> +                                     "cxo2",
> +                                     "sleep_clk",
> +                                     "pcie_0_pipe_clk_src",
> +                                     "pcie_1_pipe_clk_src",
> +                                     "pcie_2_pipe_clk_src",
> +                                     "usb3_phy_pipe_clk_src",
> +                                     "ufs_rx_symbol_0_clk_src",
> +                                     "ufs_rx_symbol_1_clk_src",
> +                                     "ufs_tx_symbol_0_clk_src";
> +               };
> +
> +               bimc: interconnect@408000 {
> +                       compatible = "qcom,msm8996-bimc";
> +                       reg = <0x00408000 0x5a000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
> +                                <&rpmcc RPM_SMD_BIMC_A_CLK>;
> +               };
> +
> +               tsens0: thermal-sensor@4a9000 {
> +                       compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
> +                       reg = <0x004a9000 0x1000>, /* TM */
> +                             <0x004a8000 0x1000>; /* SROT */
> +                       #qcom,sensors = <13>;
> +                       interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow", "critical";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               tsens1: thermal-sensor@4ad000 {
> +                       compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
> +                       reg = <0x004ad000 0x1000>, /* TM */
> +                             <0x004ac000 0x1000>; /* SROT */
> +                       #qcom,sensors = <8>;
> +                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow", "critical";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               cryptobam: dma-controller@644000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x00644000 0x24000>;
> +                       interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_CE1_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +                       qcom,controlled-remotely;
> +               };
> +
> +               crypto: crypto@67a000 {
> +                       compatible = "qcom,crypto-v5.4";
> +                       reg = <0x0067a000 0x6000>;
> +                       clocks = <&gcc GCC_CE1_AHB_CLK>,
> +                                <&gcc GCC_CE1_AXI_CLK>,
> +                                <&gcc GCC_CE1_CLK>;
> +                       clock-names = "iface", "bus", "core";
> +                       dmas = <&cryptobam 6>, <&cryptobam 7>;
> +                       dma-names = "rx", "tx";
> +               };
> +
> +               cnoc: interconnect@500000 {
> +                       compatible = "qcom,msm8996-cnoc";
> +                       reg = <0x00500000 0x1000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
> +                                <&rpmcc RPM_SMD_CNOC_A_CLK>;
> +               };
> +
> +               snoc: interconnect@524000 {
> +                       compatible = "qcom,msm8996-snoc";
> +                       reg = <0x00524000 0x1c000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
> +                                <&rpmcc RPM_SMD_SNOC_A_CLK>;
> +               };
> +
> +               a0noc: interconnect@543000 {
> +                       compatible = "qcom,msm8996-a0noc";
> +                       reg = <0x00543000 0x6000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "aggre0_snoc_axi",
> +                                     "aggre0_cnoc_ahb",
> +                                     "aggre0_noc_mpu_cfg";
> +                       clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
> +                                <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
> +                                <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
> +                       power-domains = <&gcc AGGRE0_NOC_GDSC>;
> +               };
> +
> +               a1noc: interconnect@562000 {
> +                       compatible = "qcom,msm8996-a1noc";
> +                       reg = <0x00562000 0x5000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
> +                                <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
> +               };
> +
> +               a2noc: interconnect@583000 {
> +                       compatible = "qcom,msm8996-a2noc";
> +                       reg = <0x00583000 0x7000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
> +                       clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
> +                                <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
> +                                <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
> +                                <&gcc GCC_UFS_AXI_CLK>;
> +               };
> +
> +               mnoc: interconnect@5a4000 {
> +                       compatible = "qcom,msm8996-mnoc";
> +                       reg = <0x005a4000 0x1c000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a", "iface";
> +                       clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
> +                                <&rpmcc RPM_SMD_MMAXI_A_CLK>,
> +                                <&mmcc AHB_CLK_SRC>;
> +               };
> +
> +               pnoc: interconnect@5c0000 {
> +                       compatible = "qcom,msm8996-pnoc";
> +                       reg = <0x005c0000 0x3000>;
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
> +                                <&rpmcc RPM_SMD_PCNOC_A_CLK>;
> +               };
> +
> +               tcsr_mutex: hwlock@740000 {
> +                       compatible = "qcom,tcsr-mutex";
> +                       reg = <0x00740000 0x20000>;
> +                       #hwlock-cells = <1>;
> +               };
> +
> +               tcsr_1: syscon@760000 {
> +                       compatible = "qcom,tcsr-msm8996", "syscon";
> +                       reg = <0x00760000 0x20000>;
> +               };
> +
> +               tcsr_2: syscon@7a0000 {
> +                       compatible = "qcom,tcsr-msm8996", "syscon";
> +                       reg = <0x007a0000 0x18000>;
> +               };
> +
> +               mmcc: clock-controller@8c0000 {
> +                       compatible = "qcom,mmcc-msm8996";
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       reg = <0x008c0000 0x40000>;
> +                       clocks = <&xo_board>,
> +                                <&gcc GPLL0>,
> +                                <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
> +                                <&mdss_dsi0_phy 1>,
> +                                <&mdss_dsi0_phy 0>,
> +                                <&mdss_dsi1_phy 1>,
> +                                <&mdss_dsi1_phy 0>,
> +                                <&mdss_hdmi_phy>;
> +                       clock-names = "xo",
> +                                     "gpll0",
> +                                     "gcc_mmss_noc_cfg_ahb_clk",
> +                                     "dsi0pll",
> +                                     "dsi0pllbyte",
> +                                     "dsi1pll",
> +                                     "dsi1pllbyte",
> +                                     "hdmipll";
> +                       assigned-clocks = <&mmcc MMPLL9_PLL>,
> +                                         <&mmcc MMPLL1_PLL>,
> +                                         <&mmcc MMPLL3_PLL>,
> +                                         <&mmcc MMPLL4_PLL>,
> +                                         <&mmcc MMPLL5_PLL>;
> +                       assigned-clock-rates = <624000000>,
> +                                              <810000000>,
> +                                              <980000000>,
> +                                              <960000000>,
> +                                              <825000000>;
> +               };
> +
> +               mdss: display-subsystem@900000 {
> +                       compatible = "qcom,mdss";
> +
> +                       reg = <0x00900000 0x1000>,
> +                             <0x009b0000 0x1040>,
> +                             <0x009b8000 0x1040>;
> +                       reg-names = "mdss_phys",
> +                                   "vbif_phys",
> +                                   "vbif_nrt_phys";
> +
> +                       power-domains = <&mmcc MDSS_GDSC>;
> +                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +
> +                       clocks = <&mmcc MDSS_AHB_CLK>,
> +                                <&mmcc MDSS_MDP_CLK>;
> +                       clock-names = "iface", "core";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       status = "disabled";
> +
> +                       mdp: display-controller@901000 {
> +                               compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
> +                               reg = <0x00901000 0x90000>;
> +                               reg-names = "mdp_phys";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <0>;
> +
> +                               clocks = <&mmcc MDSS_AHB_CLK>,
> +                                        <&mmcc MDSS_AXI_CLK>,
> +                                        <&mmcc MDSS_MDP_CLK>,
> +                                        <&mmcc SMMU_MDP_AXI_CLK>,
> +                                        <&mmcc MDSS_VSYNC_CLK>;
> +                               clock-names = "iface",
> +                                             "bus",
> +                                             "core",
> +                                             "iommu",
> +                                             "vsync";
> +
> +                               iommus = <&mdp_smmu 0>;
> +
> +                               assigned-clocks = <&mmcc MDSS_MDP_CLK>,
> +                                        <&mmcc MDSS_VSYNC_CLK>;
> +                               assigned-clock-rates = <300000000>,
> +                                        <19200000>;
> +
> +                               interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
> +                                               <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
> +                                               <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
> +                               interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdp5_intf3_out: endpoint {
> +                                                       remote-endpoint = <&mdss_hdmi_in>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdp5_intf1_out: endpoint {
> +                                                       remote-endpoint = <&mdss_dsi0_in>;
> +                                               };
> +                                       };
> +
> +                                       port@2 {
> +                                               reg = <2>;
> +                                               mdp5_intf2_out: endpoint {
> +                                                       remote-endpoint = <&mdss_dsi1_in>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0: dsi@994000 {
> +                               compatible = "qcom,msm8996-dsi-ctrl",
> +                                            "qcom,mdss-dsi-ctrl";
> +                               reg = <0x00994000 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <4>;
> +
> +                               clocks = <&mmcc MDSS_MDP_CLK>,
> +                                        <&mmcc MDSS_BYTE0_CLK>,
> +                                        <&mmcc MDSS_AHB_CLK>,
> +                                        <&mmcc MDSS_AXI_CLK>,
> +                                        <&mmcc MMSS_MISC_AHB_CLK>,
> +                                        <&mmcc MDSS_PCLK0_CLK>,
> +                                        <&mmcc MDSS_ESC0_CLK>;
> +                               clock-names = "mdp_core",
> +                                             "byte",
> +                                             "iface",
> +                                             "bus",
> +                                             "core_mmss",
> +                                             "pixel",
> +                                             "core";
> +                               assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
> +                               assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> +                               phys = <&mdss_dsi0_phy>;
> +                               status = "disabled";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_dsi0_in: endpoint {
> +                                                       remote-endpoint = <&mdp5_intf1_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdss_dsi0_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi0_phy: phy@994400 {
> +                               compatible = "qcom,dsi-phy-14nm";
> +                               reg = <0x00994400 0x100>,
> +                                     <0x00994500 0x300>,
> +                                     <0x00994800 0x188>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_phy_lane",
> +                                           "dsi_pll";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> +                               clock-names = "iface", "ref";
> +                               status = "disabled";
> +                       };
> +
> +                       mdss_dsi1: dsi@996000 {
> +                               compatible = "qcom,msm8996-dsi-ctrl",
> +                                            "qcom,mdss-dsi-ctrl";
> +                               reg = <0x00996000 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <5>;
> +
> +                               clocks = <&mmcc MDSS_MDP_CLK>,
> +                                        <&mmcc MDSS_BYTE1_CLK>,
> +                                        <&mmcc MDSS_AHB_CLK>,
> +                                        <&mmcc MDSS_AXI_CLK>,
> +                                        <&mmcc MMSS_MISC_AHB_CLK>,
> +                                        <&mmcc MDSS_PCLK1_CLK>,
> +                                        <&mmcc MDSS_ESC1_CLK>;
> +                               clock-names = "mdp_core",
> +                                             "byte",
> +                                             "iface",
> +                                             "bus",
> +                                             "core_mmss",
> +                                             "pixel",
> +                                             "core";
> +                               assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
> +                               assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
> +
> +                               phys = <&mdss_dsi1_phy>;
> +                               status = "disabled";
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_dsi1_in: endpoint {
> +                                                       remote-endpoint = <&mdp5_intf2_out>;
> +                                               };
> +                                       };
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                               mdss_dsi1_out: endpoint {
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_dsi1_phy: phy@996400 {
> +                               compatible = "qcom,dsi-phy-14nm";
> +                               reg = <0x00996400 0x100>,
> +                                     <0x00996500 0x300>,
> +                                     <0x00996800 0x188>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_phy_lane",
> +                                           "dsi_pll";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> +                               clock-names = "iface", "ref";
> +                               status = "disabled";
> +                       };
> +
> +                       mdss_hdmi: hdmi-tx@9a0000 {
> +                               compatible = "qcom,hdmi-tx-8996";
> +                               reg = <0x009a0000 0x50c>,
> +                                     <0x00070000 0x6158>,
> +                                     <0x009e0000 0xfff>;
> +                               reg-names = "core_physical",
> +                                           "qfprom_physical",
> +                                           "hdcp_physical";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <8>;
> +
> +                               clocks = <&mmcc MDSS_MDP_CLK>,
> +                                        <&mmcc MDSS_AHB_CLK>,
> +                                        <&mmcc MDSS_HDMI_CLK>,
> +                                        <&mmcc MDSS_HDMI_AHB_CLK>,
> +                                        <&mmcc MDSS_EXTPCLK_CLK>;
> +                               clock-names =
> +                                       "mdp_core",
> +                                       "iface",
> +                                       "core",
> +                                       "alt_iface",
> +                                       "extp";
> +
> +                               phys = <&mdss_hdmi_phy>;
> +                               #sound-dai-cells = <1>;
> +
> +                               status = "disabled";
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@0 {
> +                                               reg = <0>;
> +                                               mdss_hdmi_in: endpoint {
> +                                                       remote-endpoint = <&mdp5_intf3_out>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +
> +                       mdss_hdmi_phy: phy@9a0600 {
> +                               #phy-cells = <0>;
> +                               compatible = "qcom,hdmi-phy-8996";
> +                               reg = <0x009a0600 0x1c4>,
> +                                     <0x009a0a00 0x124>,
> +                                     <0x009a0c00 0x124>,
> +                                     <0x009a0e00 0x124>,
> +                                     <0x009a1000 0x124>,
> +                                     <0x009a1200 0x0c8>;
> +                               reg-names = "hdmi_pll",
> +                                           "hdmi_tx_l0",
> +                                           "hdmi_tx_l1",
> +                                           "hdmi_tx_l2",
> +                                           "hdmi_tx_l3",
> +                                           "hdmi_phy";
> +
> +                               clocks = <&mmcc MDSS_AHB_CLK>,
> +                                        <&gcc GCC_HDMI_CLKREF_CLK>,
> +                                        <&xo_board>;
> +                               clock-names = "iface",
> +                                             "ref",
> +                                             "xo";
> +
> +                               #clock-cells = <0>;
> +
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               gpu: gpu@b00000 {
> +                       compatible = "qcom,adreno-530.2", "qcom,adreno";
> +
> +                       reg = <0x00b00000 0x3f000>;
> +                       reg-names = "kgsl_3d0_reg_memory";
> +
> +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> +                               <&mmcc GPU_AHB_CLK>,
> +                               <&mmcc GPU_GX_RBBMTIMER_CLK>,
> +                               <&gcc GCC_BIMC_GFX_CLK>,
> +                               <&gcc GCC_MMSS_BIMC_GFX_CLK>;
> +
> +                       clock-names = "core",
> +                               "iface",
> +                               "rbbmtimer",
> +                               "mem",
> +                               "mem_iface";
> +
> +                       interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
> +                       interconnect-names = "gfx-mem";
> +
> +                       power-domains = <&mmcc GPU_GX_GDSC>;
> +                       iommus = <&adreno_smmu 0>;
> +
> +                       nvmem-cells = <&speedbin_efuse>;
> +                       nvmem-cell-names = "speed_bin";
> +
> +                       operating-points-v2 = <&gpu_opp_table>;
> +
> +                       status = "disabled";
> +
> +                       #cooling-cells = <2>;
> +
> +                       gpu_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               /*
> +                                * 624Mhz is only available on speed bins 0 and 3.
> +                                * 560Mhz is only available on speed bins 0, 2 and 3.
> +                                * All the rest are available on all bins of the hardware.
> +                                */
> +                               opp-624000000 {
> +                                       opp-hz = /bits/ 64 <624000000>;
> +                                       opp-supported-hw = <0x09>;
> +                               };
> +                               opp-560000000 {
> +                                       opp-hz = /bits/ 64 <560000000>;
> +                                       opp-supported-hw = <0x0d>;
> +                               };
> +                               opp-510000000 {
> +                                       opp-hz = /bits/ 64 <510000000>;
> +                                       opp-supported-hw = <0xff>;
> +                               };
> +                               opp-401800000 {
> +                                       opp-hz = /bits/ 64 <401800000>;
> +                                       opp-supported-hw = <0xff>;
> +                               };
> +                               opp-315000000 {
> +                                       opp-hz = /bits/ 64 <315000000>;
> +                                       opp-supported-hw = <0xff>;
> +                               };
> +                               opp-214000000 {
> +                                       opp-hz = /bits/ 64 <214000000>;
> +                                       opp-supported-hw = <0xff>;
> +                               };
> +                               opp-133000000 {
> +                                       opp-hz = /bits/ 64 <133000000>;
> +                                       opp-supported-hw = <0xff>;
> +                               };
> +                       };
> +
> +                       zap-shader {
> +                               memory-region = <&gpu_mem>;
> +                       };
> +               };
> +
> +               tlmm: pinctrl@1010000 {
> +                       compatible = "qcom,msm8996-pinctrl";
> +                       reg = <0x01010000 0x300000>;
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       gpio-ranges = <&tlmm 0 0 150>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +
> +                       blsp1_spi1_default: blsp1-spi1-default-state {
> +                               spi-pins {
> +                                       pins = "gpio0", "gpio1", "gpio3";
> +                                       function = "blsp_spi1";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +
> +                               cs-pins {
> +                                       pins = "gpio2";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp1_spi1_sleep: blsp1-spi1-sleep-state {
> +                               pins = "gpio0", "gpio1", "gpio2", "gpio3";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
> +                               pins = "gpio4", "gpio5";
> +                               function = "blsp_uart8";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
> +                               pins = "gpio4", "gpio5";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c2_default: blsp2-i2c2-state {
> +                               pins = "gpio6", "gpio7";
> +                               function = "blsp_i2c8";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
> +                               pins = "gpio6", "gpio7";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp1_i2c6_default: blsp1-i2c6-state {
> +                               pins = "gpio27", "gpio28";
> +                               function = "blsp_i2c6";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
> +                               pins = "gpio27", "gpio28";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci0_default: cci0-default-state {
> +                               pins = "gpio17", "gpio18";
> +                               function = "cci_i2c";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       camera0_state_on:
> +                       camera_rear_default: camera-rear-default-state {
> +                               camera0_mclk: mclk0-pins {
> +                                       pins = "gpio13";
> +                                       function = "cam_mclk";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               camera0_rst: rst-pins {
> +                                       pins = "gpio25";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               camera0_pwdn: pwdn-pins {
> +                                       pins = "gpio26";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       cci1_default: cci1-default-state {
> +                               pins = "gpio19", "gpio20";
> +                               function = "cci_i2c";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       camera1_state_on:
> +                       camera_board_default: camera-board-default-state {
> +                               mclk1-pins {
> +                                       pins = "gpio14";
> +                                       function = "cam_mclk";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               pwdn-pins {
> +                                       pins = "gpio98";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               rst-pins {
> +                                       pins = "gpio104";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       camera2_state_on:
> +                       camera_front_default: camera-front-default-state {
> +                               camera2_mclk: mclk2-pins {
> +                                       pins = "gpio15";
> +                                       function = "cam_mclk";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               camera2_rst: rst-pins {
> +                                       pins = "gpio23";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +
> +                               pwdn-pins {
> +                                       pins = "gpio133";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       pcie0_state_on: pcie0-state-on-state {
> +                               perst-pins {
> +                                       pins = "gpio35";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +
> +                               clkreq-pins {
> +                                       pins = "gpio36";
> +                                       function = "pci_e0";
> +                                       drive-strength = <2>;
> +                                       bias-pull-up;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio37";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-up;
> +                               };
> +                       };
> +
> +                       pcie0_state_off: pcie0-state-off-state {
> +                               perst-pins {
> +                                       pins = "gpio35";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +
> +                               clkreq-pins {
> +                                       pins = "gpio36";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio37";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       blsp1_uart2_default: blsp1-uart2-default-state {
> +                               pins = "gpio41", "gpio42", "gpio43", "gpio44";
> +                               function = "blsp_uart2";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp1_uart2_sleep: blsp1-uart2-sleep-state {
> +                               pins = "gpio41", "gpio42", "gpio43", "gpio44";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp1_i2c3_default: blsp1-i2c3-default-state {
> +                               pins = "gpio47", "gpio48";
> +                               function = "blsp_i2c3";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
> +                               pins = "gpio47", "gpio48";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
> +                               pins = "gpio49", "gpio50", "gpio51", "gpio52";
> +                               function = "blsp_uart9";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
> +                               pins = "gpio49", "gpio50", "gpio51", "gpio52";
> +                               function = "blsp_uart9";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c3_default: blsp2-i2c3-state-state {
> +                               pins = "gpio51", "gpio52";
> +                               function = "blsp_i2c9";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
> +                               pins = "gpio51", "gpio52";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       wcd_intr_default: wcd-intr-default-state {
> +                               pins = "gpio54";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp2_i2c1_default: blsp2-i2c1-state {
> +                               pins = "gpio55", "gpio56";
> +                               function = "blsp_i2c7";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
> +                               pins = "gpio55", "gpio56";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c5_default: blsp2-i2c5-state {
> +                               pins = "gpio60", "gpio61";
> +                               function = "blsp_i2c11";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       /* Sleep state for BLSP2_I2C5 is missing.. */
> +
> +                       cdc_reset_active: cdc-reset-active-state {
> +                               pins = "gpio64";
> +                               function = "gpio";
> +                               drive-strength = <16>;
> +                               bias-pull-down;
> +                               output-high;
> +                       };
> +
> +                       cdc_reset_sleep: cdc-reset-sleep-state {
> +                               pins = "gpio64";
> +                               function = "gpio";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                               output-low;
> +                       };
> +
> +                       blsp2_spi6_default: blsp2-spi6-default-state {
> +                               spi-pins {
> +                                       pins = "gpio85", "gpio86", "gpio88";
> +                                       function = "blsp_spi12";
> +                                       drive-strength = <12>;
> +                                       bias-disable;
> +                               };
> +
> +                               cs-pins {
> +                                       pins = "gpio87";
> +                                       function = "gpio";
> +                                       drive-strength = <16>;
> +                                       bias-disable;
> +                                       output-high;
> +                               };
> +                       };
> +
> +                       blsp2_spi6_sleep: blsp2-spi6-sleep-state {
> +                               pins = "gpio85", "gpio86", "gpio87", "gpio88";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       blsp2_i2c6_default: blsp2-i2c6-state {
> +                               pins = "gpio87", "gpio88";
> +                               function = "blsp_i2c12";
> +                               drive-strength = <16>;
> +                               bias-disable;
> +                       };
> +
> +                       blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
> +                               pins = "gpio87", "gpio88";
> +                               function = "gpio";
> +                               drive-strength = <2>;
> +                               bias-disable;
> +                       };
> +
> +                       pcie1_state_on: pcie1-on-state {
> +                               perst-pins {
> +                                       pins = "gpio130";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +
> +                               clkreq-pins {
> +                                       pins = "gpio131";
> +                                       function = "pci_e1";
> +                                       drive-strength = <2>;
> +                                       bias-pull-up;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio132";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +                       };
> +
> +                       pcie1_state_off: pcie1-off-state {
> +                               /* Perst is missing? */
> +                               clkreq-pins {
> +                                       pins = "gpio131";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio132";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       pcie2_state_on: pcie2-on-state {
> +                               perst-pins {
> +                                       pins = "gpio114";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +
> +                               clkreq-pins {
> +                                       pins = "gpio115";
> +                                       function = "pci_e2";
> +                                       drive-strength = <2>;
> +                                       bias-pull-up;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio116";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-pull-down;
> +                               };
> +                       };
> +
> +                       pcie2_state_off: pcie2-off-state {
> +                               /* Perst is missing? */
> +                               clkreq-pins {
> +                                       pins = "gpio115";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +
> +                               wake-pins {
> +                                       pins = "gpio116";
> +                                       function = "gpio";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                       };
> +
> +                       sdc1_state_on: sdc1-on-state {
> +                               clk-pins {
> +                                       pins = "sdc1_clk";
> +                                       bias-disable;
> +                                       drive-strength = <16>;
> +                               };
> +
> +                               cmd-pins {
> +                                       pins = "sdc1_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +
> +                               data-pins {
> +                                       pins = "sdc1_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +
> +                               rclk-pins {
> +                                       pins = "sdc1_rclk";
> +                                       bias-pull-down;
> +                               };
> +                       };
> +
> +                       sdc1_state_off: sdc1-off-state {
> +                               clk-pins {
> +                                       pins = "sdc1_clk";
> +                                       bias-disable;
> +                                       drive-strength = <2>;
> +                               };
> +
> +                               cmd-pins {
> +                                       pins = "sdc1_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +
> +                               data-pins {
> +                                       pins = "sdc1_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +
> +                               rclk-pins {
> +                                       pins = "sdc1_rclk";
> +                                       bias-pull-down;
> +                               };
> +                       };
> +
> +                       sdc2_state_on: sdc2-on-state {
> +                               clk-pins {
> +                                       pins = "sdc2_clk";
> +                                       bias-disable;
> +                                       drive-strength = <16>;
> +                               };
> +
> +                               cmd-pins {
> +                                       pins = "sdc2_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +
> +                               data-pins {
> +                                       pins = "sdc2_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <10>;
> +                               };
> +                       };
> +
> +                       sdc2_state_off: sdc2-off-state {
> +                               clk-pins {
> +                                       pins = "sdc2_clk";
> +                                       bias-disable;
> +                                       drive-strength = <2>;
> +                               };
> +
> +                               cmd-pins {
> +                                       pins = "sdc2_cmd";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +
> +                               data-pins {
> +                                       pins = "sdc2_data";
> +                                       bias-pull-up;
> +                                       drive-strength = <2>;
> +                               };
> +                       };
> +               };
> +
> +               sram@290000 {
> +                       compatible = "qcom,rpm-stats";
> +                       reg = <0x00290000 0x10000>;
> +               };
> +
> +               spmi_bus: spmi@400f000 {
> +                       compatible = "qcom,spmi-pmic-arb";
> +                       reg = <0x0400f000 0x1000>,
> +                             <0x04400000 0x800000>,
> +                             <0x04c00000 0x800000>,
> +                             <0x05800000 0x200000>,
> +                             <0x0400a000 0x002100>;
> +                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +                       interrupt-names = "periph_irq";
> +                       interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,ee = <0>;
> +                       qcom,channel = <0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <0>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <4>;
> +               };
> +
> +               bus@0 {
> +                       power-domains = <&gcc AGGRE0_NOC_GDSC>;
> +                       compatible = "simple-pm-bus";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0x0 0x0 0xffffffff>;
> +
> +                       pcie0: pcie@600000 {
> +                               compatible = "qcom,pcie-msm8996";
> +                               status = "disabled";
> +                               power-domains = <&gcc PCIE0_GDSC>;
> +                               bus-range = <0x00 0xff>;
> +                               num-lanes = <1>;
> +
> +                               reg = <0x00600000 0x2000>,
> +                                     <0x0c000000 0xf1d>,
> +                                     <0x0c000f20 0xa8>,
> +                                     <0x0c100000 0x100000>;
> +                               reg-names = "parf", "dbi", "elbi","config";
> +
> +                               phys = <&pciephy_0>;
> +                               phy-names = "pciephy";
> +
> +                               #address-cells = <3>;
> +                               #size-cells = <2>;
> +                               ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
> +                                        <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
> +
> +                               device_type = "pci";
> +
> +                               interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupt-names = "msi";
> +                               #interrupt-cells = <1>;
> +                               interrupt-map-mask = <0 0 0 0x7>;
> +                               interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                               <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                               <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                               <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +                               pinctrl-names = "default", "sleep";
> +                               pinctrl-0 = <&pcie0_state_on>;
> +                               pinctrl-1 = <&pcie0_state_off>;
> +
> +                               linux,pci-domain = <0>;
> +
> +                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> +                                       <&gcc GCC_PCIE_0_AUX_CLK>,
> +                                       <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                                       <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +                                       <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
> +
> +                               clock-names = "pipe",
> +                                               "aux",
> +                                               "cfg",
> +                                               "bus_master",
> +                                               "bus_slave";
> +                       };
> +
> +                       pcie1: pcie@608000 {
> +                               compatible = "qcom,pcie-msm8996";
> +                               power-domains = <&gcc PCIE1_GDSC>;
> +                               bus-range = <0x00 0xff>;
> +                               num-lanes = <1>;
> +
> +                               status = "disabled";
> +
> +                               reg = <0x00608000 0x2000>,
> +                                     <0x0d000000 0xf1d>,
> +                                     <0x0d000f20 0xa8>,
> +                                     <0x0d100000 0x100000>;
> +
> +                               reg-names = "parf", "dbi", "elbi","config";
> +
> +                               phys = <&pciephy_1>;
> +                               phy-names = "pciephy";
> +
> +                               #address-cells = <3>;
> +                               #size-cells = <2>;
> +                               ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
> +                                        <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
> +
> +                               device_type = "pci";
> +
> +                               interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupt-names = "msi";
> +                               #interrupt-cells = <1>;
> +                               interrupt-map-mask = <0 0 0 0x7>;
> +                               interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                               <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                               <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                               <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +                               pinctrl-names = "default", "sleep";
> +                               pinctrl-0 = <&pcie1_state_on>;
> +                               pinctrl-1 = <&pcie1_state_off>;
> +
> +                               linux,pci-domain = <1>;
> +
> +                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> +                                       <&gcc GCC_PCIE_1_AUX_CLK>,
> +                                       <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +                                       <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> +                                       <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
> +
> +                               clock-names = "pipe",
> +                                               "aux",
> +                                               "cfg",
> +                                               "bus_master",
> +                                               "bus_slave";
> +                       };
> +
> +                       pcie2: pcie@610000 {
> +                               compatible = "qcom,pcie-msm8996";
> +                               power-domains = <&gcc PCIE2_GDSC>;
> +                               bus-range = <0x00 0xff>;
> +                               num-lanes = <1>;
> +                               status = "disabled";
> +                               reg = <0x00610000 0x2000>,
> +                                     <0x0e000000 0xf1d>,
> +                                     <0x0e000f20 0xa8>,
> +                                     <0x0e100000 0x100000>;
> +
> +                               reg-names = "parf", "dbi", "elbi","config";
> +
> +                               phys = <&pciephy_2>;
> +                               phy-names = "pciephy";
> +
> +                               #address-cells = <3>;
> +                               #size-cells = <2>;
> +                               ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
> +                                        <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
> +
> +                               device_type = "pci";
> +
> +                               interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupt-names = "msi";
> +                               #interrupt-cells = <1>;
> +                               interrupt-map-mask = <0 0 0 0x7>;
> +                               interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                               <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                               <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                               <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +                               pinctrl-names = "default", "sleep";
> +                               pinctrl-0 = <&pcie2_state_on>;
> +                               pinctrl-1 = <&pcie2_state_off>;
> +
> +                               linux,pci-domain = <2>;
> +                               clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
> +                                       <&gcc GCC_PCIE_2_AUX_CLK>,
> +                                       <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
> +                                       <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
> +                                       <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
> +
> +                               clock-names = "pipe",
> +                                               "aux",
> +                                               "cfg",
> +                                               "bus_master",
> +                                               "bus_slave";
> +                       };
> +               };
> +
> +               ufshc: ufshc@624000 {
> +                       compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
> +                                    "jedec,ufs-2.0";
> +                       reg = <0x00624000 0x2500>;
> +                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       phys = <&ufsphy_lane>;
> +                       phy-names = "ufsphy";
> +
> +                       power-domains = <&gcc UFS_GDSC>;
> +
> +                       clock-names =
> +                               "core_clk_src",
> +                               "core_clk",
> +                               "bus_clk",
> +                               "bus_aggr_clk",
> +                               "iface_clk",
> +                               "core_clk_unipro_src",
> +                               "core_clk_unipro",
> +                               "core_clk_ice",
> +                               "ref_clk",
> +                               "tx_lane0_sync_clk",
> +                               "rx_lane0_sync_clk";
> +                       clocks =
> +                               <&gcc UFS_AXI_CLK_SRC>,
> +                               <&gcc GCC_UFS_AXI_CLK>,
> +                               <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
> +                               <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
> +                               <&gcc GCC_UFS_AHB_CLK>,
> +                               <&gcc UFS_ICE_CORE_CLK_SRC>,
> +                               <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
> +                               <&gcc GCC_UFS_ICE_CORE_CLK>,
> +                               <&rpmcc RPM_SMD_LN_BB_CLK>,
> +                               <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
> +                       freq-table-hz =
> +                               <100000000 200000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <150000000 300000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>;
> +
> +                       interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
> +                                       <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
> +                       interconnect-names = "ufs-ddr", "cpu-ufs";
> +
> +                       lanes-per-direction = <1>;
> +                       #reset-cells = <1>;
> +                       status = "disabled";
> +               };
> +
> +               ufsphy: phy@627000 {
> +                       compatible = "qcom,msm8996-qmp-ufs-phy";
> +                       reg = <0x00627000 0x1c4>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       clocks = <&gcc GCC_UFS_CLKREF_CLK>;
> +                       clock-names = "ref";
> +
> +                       resets = <&ufshc 0>;
> +                       reset-names = "ufsphy";
> +                       status = "disabled";
> +
> +                       ufsphy_lane: phy@627400 {
> +                               reg = <0x627400 0x12c>,
> +                                     <0x627600 0x200>,
> +                                     <0x627c00 0x1b4>;
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +                       };
> +               };
> +
> +               camss: camss@a34000 {
> +                       compatible = "qcom,msm8996-camss";
> +                       reg = <0x00a34000 0x1000>,
> +                             <0x00a00030 0x4>,
> +                             <0x00a35000 0x1000>,
> +                             <0x00a00038 0x4>,
> +                             <0x00a36000 0x1000>,
> +                             <0x00a00040 0x4>,
> +                             <0x00a30000 0x100>,
> +                             <0x00a30400 0x100>,
> +                             <0x00a30800 0x100>,
> +                             <0x00a30c00 0x100>,
> +                             <0x00a31000 0x500>,
> +                             <0x00a00020 0x10>,
> +                             <0x00a10000 0x1000>,
> +                             <0x00a14000 0x1000>;
> +                       reg-names = "csiphy0",
> +                               "csiphy0_clk_mux",
> +                               "csiphy1",
> +                               "csiphy1_clk_mux",
> +                               "csiphy2",
> +                               "csiphy2_clk_mux",
> +                               "csid0",
> +                               "csid1",
> +                               "csid2",
> +                               "csid3",
> +                               "ispif",
> +                               "csi_clk_mux",
> +                               "vfe0",
> +                               "vfe1";
> +                       interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
> +                               <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "csiphy0",
> +                               "csiphy1",
> +                               "csiphy2",
> +                               "csid0",
> +                               "csid1",
> +                               "csid2",
> +                               "csid3",
> +                               "ispif",
> +                               "vfe0",
> +                               "vfe1";
> +                       power-domains = <&mmcc VFE0_GDSC>,
> +                                       <&mmcc VFE1_GDSC>;
> +                       clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
> +                               <&mmcc CAMSS_ISPIF_AHB_CLK>,
> +                               <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
> +                               <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
> +                               <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
> +                               <&mmcc CAMSS_CSI0_AHB_CLK>,
> +                               <&mmcc CAMSS_CSI0_CLK>,
> +                               <&mmcc CAMSS_CSI0PHY_CLK>,
> +                               <&mmcc CAMSS_CSI0PIX_CLK>,
> +                               <&mmcc CAMSS_CSI0RDI_CLK>,
> +                               <&mmcc CAMSS_CSI1_AHB_CLK>,
> +                               <&mmcc CAMSS_CSI1_CLK>,
> +                               <&mmcc CAMSS_CSI1PHY_CLK>,
> +                               <&mmcc CAMSS_CSI1PIX_CLK>,
> +                               <&mmcc CAMSS_CSI1RDI_CLK>,
> +                               <&mmcc CAMSS_CSI2_AHB_CLK>,
> +                               <&mmcc CAMSS_CSI2_CLK>,
> +                               <&mmcc CAMSS_CSI2PHY_CLK>,
> +                               <&mmcc CAMSS_CSI2PIX_CLK>,
> +                               <&mmcc CAMSS_CSI2RDI_CLK>,
> +                               <&mmcc CAMSS_CSI3_AHB_CLK>,
> +                               <&mmcc CAMSS_CSI3_CLK>,
> +                               <&mmcc CAMSS_CSI3PHY_CLK>,
> +                               <&mmcc CAMSS_CSI3PIX_CLK>,
> +                               <&mmcc CAMSS_CSI3RDI_CLK>,
> +                               <&mmcc CAMSS_AHB_CLK>,
> +                               <&mmcc CAMSS_VFE0_CLK>,
> +                               <&mmcc CAMSS_CSI_VFE0_CLK>,
> +                               <&mmcc CAMSS_VFE0_AHB_CLK>,
> +                               <&mmcc CAMSS_VFE0_STREAM_CLK>,
> +                               <&mmcc CAMSS_VFE1_CLK>,
> +                               <&mmcc CAMSS_CSI_VFE1_CLK>,
> +                               <&mmcc CAMSS_VFE1_AHB_CLK>,
> +                               <&mmcc CAMSS_VFE1_STREAM_CLK>,
> +                               <&mmcc CAMSS_VFE_AHB_CLK>,
> +                               <&mmcc CAMSS_VFE_AXI_CLK>;
> +                       clock-names = "top_ahb",
> +                               "ispif_ahb",
> +                               "csiphy0_timer",
> +                               "csiphy1_timer",
> +                               "csiphy2_timer",
> +                               "csi0_ahb",
> +                               "csi0",
> +                               "csi0_phy",
> +                               "csi0_pix",
> +                               "csi0_rdi",
> +                               "csi1_ahb",
> +                               "csi1",
> +                               "csi1_phy",
> +                               "csi1_pix",
> +                               "csi1_rdi",
> +                               "csi2_ahb",
> +                               "csi2",
> +                               "csi2_phy",
> +                               "csi2_pix",
> +                               "csi2_rdi",
> +                               "csi3_ahb",
> +                               "csi3",
> +                               "csi3_phy",
> +                               "csi3_pix",
> +                               "csi3_rdi",
> +                               "ahb",
> +                               "vfe0",
> +                               "csi_vfe0",
> +                               "vfe0_ahb",
> +                               "vfe0_stream",
> +                               "vfe1",
> +                               "csi_vfe1",
> +                               "vfe1_ahb",
> +                               "vfe1_stream",
> +                               "vfe_ahb",
> +                               "vfe_axi";
> +                       iommus = <&vfe_smmu 0>,
> +                                <&vfe_smmu 1>,
> +                                <&vfe_smmu 2>,
> +                                <&vfe_smmu 3>;
> +                       status = "disabled";
> +                       ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
> +               cci: cci@a0c000 {
> +                       compatible = "qcom,msm8996-cci";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xa0c000 0x1000>;
> +                       interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
> +                       power-domains = <&mmcc CAMSS_GDSC>;
> +                       clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
> +                                <&mmcc CAMSS_CCI_AHB_CLK>,
> +                                <&mmcc CAMSS_CCI_CLK>,
> +                                <&mmcc CAMSS_AHB_CLK>;
> +                       clock-names = "camss_top_ahb",
> +                                     "cci_ahb",
> +                                     "cci",
> +                                     "camss_ahb";
> +                       assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
> +                                         <&mmcc CAMSS_CCI_CLK>;
> +                       assigned-clock-rates = <80000000>, <37500000>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&cci0_default &cci1_default>;
> +                       status = "disabled";
> +
> +                       cci_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +
> +                       cci_i2c1: i2c-bus@1 {
> +                               reg = <1>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
> +               adreno_smmu: iommu@b40000 {
> +                       compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +                       reg = <0x00b40000 0x10000>;
> +
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> +                       #iommu-cells = <1>;
> +
> +                       clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
> +                                <&mmcc GPU_AHB_CLK>;
> +                       clock-names = "bus", "iface";
> +
> +                       power-domains = <&mmcc GPU_GDSC>;
> +               };
> +
> +               venus: video-codec@c00000 {
> +                       compatible = "qcom,msm8996-venus";
> +                       reg = <0x00c00000 0xff000>;
> +                       interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&mmcc VENUS_GDSC>;
> +                       clocks = <&mmcc VIDEO_CORE_CLK>,
> +                                <&mmcc VIDEO_AHB_CLK>,
> +                                <&mmcc VIDEO_AXI_CLK>,
> +                                <&mmcc VIDEO_MAXI_CLK>;
> +                       clock-names = "core", "iface", "bus", "mbus";
> +                       interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
> +                                       <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
> +                       interconnect-names = "video-mem", "cpu-cfg";
> +                       iommus = <&venus_smmu 0x00>,
> +                                <&venus_smmu 0x01>,
> +                                <&venus_smmu 0x0a>,
> +                                <&venus_smmu 0x07>,
> +                                <&venus_smmu 0x0e>,
> +                                <&venus_smmu 0x0f>,
> +                                <&venus_smmu 0x08>,
> +                                <&venus_smmu 0x09>,
> +                                <&venus_smmu 0x0b>,
> +                                <&venus_smmu 0x0c>,
> +                                <&venus_smmu 0x0d>,
> +                                <&venus_smmu 0x10>,
> +                                <&venus_smmu 0x11>,
> +                                <&venus_smmu 0x21>,
> +                                <&venus_smmu 0x28>,
> +                                <&venus_smmu 0x29>,
> +                                <&venus_smmu 0x2b>,
> +                                <&venus_smmu 0x2c>,
> +                                <&venus_smmu 0x2d>,
> +                                <&venus_smmu 0x31>;
> +                       memory-region = <&venus_mem>;
> +                       status = "disabled";
> +
> +                       video-decoder {
> +                               compatible = "venus-decoder";
> +                               clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
> +                               clock-names = "core";
> +                               power-domains = <&mmcc VENUS_CORE0_GDSC>;
> +                       };
> +
> +                       video-encoder {
> +                               compatible = "venus-encoder";
> +                               clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
> +                               clock-names = "core";
> +                               power-domains = <&mmcc VENUS_CORE1_GDSC>;
> +                       };
> +               };
> +
> +               mdp_smmu: iommu@d00000 {
> +                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> +                       reg = <0x00d00000 0x10000>;
> +
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> +                       #iommu-cells = <1>;
> +                       clocks = <&mmcc SMMU_MDP_AXI_CLK>,
> +                                <&mmcc SMMU_MDP_AHB_CLK>;
> +                       clock-names = "bus", "iface";
> +
> +                       power-domains = <&mmcc MDSS_GDSC>;
> +               };
> +
> +               venus_smmu: iommu@d40000 {
> +                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> +                       reg = <0x00d40000 0x20000>;
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
> +                       clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
> +                                <&mmcc SMMU_VIDEO_AHB_CLK>;
> +                       clock-names = "bus", "iface";
> +                       #iommu-cells = <1>;
> +                       status = "okay";
> +               };
> +
> +               vfe_smmu: iommu@da0000 {
> +                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> +                       reg = <0x00da0000 0x10000>;
> +
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
> +                       clocks = <&mmcc SMMU_VFE_AXI_CLK>,
> +                                <&mmcc SMMU_VFE_AHB_CLK>;
> +                       clock-names = "bus", "iface";
> +                       #iommu-cells = <1>;
> +               };
> +
> +               lpass_q6_smmu: iommu@1600000 {
> +                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> +                       reg = <0x01600000 0x20000>;
> +                       #iommu-cells = <1>;
> +                       power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
> +
> +                       #global-interrupts = <1>;
> +                       interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> +                               <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
> +                                <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
> +                       clock-names = "bus", "iface";
> +               };
> +
> +               slpi_pil: remoteproc@1c00000 {
> +                       compatible = "qcom,msm8996-slpi-pil";
> +                       reg = <0x01c00000 0x4000>;
> +
> +                       interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
> +                                             <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog",
> +                                         "fatal",
> +                                         "ready",
> +                                         "handover",
> +                                         "stop-ack";
> +
> +                       clocks = <&xo_board>,
> +                                <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
> +                       clock-names = "xo", "aggre2";
> +
> +                       memory-region = <&slpi_mem>;
> +
> +                       qcom,smem-states = <&slpi_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       power-domains = <&rpmpd MSM8996_VDDSSCX>;
> +                       power-domain-names = "ssc_cx";
> +
> +                       status = "disabled";
> +
> +                       smd-edge {
> +                               interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
> +
> +                               label = "dsps";
> +                               mboxes = <&apcs_glb 25>;
> +                               qcom,smd-edge = <3>;
> +                               qcom,remote-pid = <3>;
> +                       };
> +               };
> +
> +               mss_pil: remoteproc@2080000 {
> +                       compatible = "qcom,msm8996-mss-pil";
> +                       reg = <0x2080000 0x100>,
> +                             <0x2180000 0x020>;
> +                       reg-names = "qdsp6", "rmb";
> +
> +                       interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
> +                                             <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> +                                             <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack",
> +                                         "shutdown-ack";
> +
> +                       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
> +                                <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
> +                                <&gcc GCC_BOOT_ROM_AHB_CLK>,
> +                                <&xo_board>,
> +                                <&gcc GCC_MSS_GPLL0_DIV_CLK>,
> +                                <&gcc GCC_MSS_SNOC_AXI_CLK>,
> +                                <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
> +                                <&rpmcc RPM_SMD_PCNOC_CLK>,
> +                                <&rpmcc RPM_SMD_QDSS_CLK>;
> +                       clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
> +                                     "snoc_axi", "mnoc_axi", "pnoc", "qdss";
> +
> +                       resets = <&gcc GCC_MSS_RESTART>;
> +                       reset-names = "mss_restart";
> +
> +                       power-domains = <&rpmpd MSM8996_VDDCX>,
> +                                       <&rpmpd MSM8996_VDDMX>;
> +                       power-domain-names = "cx", "mx";
> +
> +                       qcom,smem-states = <&mpss_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
> +
> +                       status = "disabled";
> +
> +                       mba {
> +                               memory-region = <&mba_mem>;
> +                       };
> +
> +                       mpss {
> +                               memory-region = <&mpss_mem>;
> +                       };
> +
> +                       metadata {
> +                               memory-region = <&mdata_mem>;
> +                       };
> +
> +                       smd-edge {
> +                               interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
> +
> +                               label = "mpss";
> +                               mboxes = <&apcs_glb 12>;
> +                               qcom,smd-edge = <0>;
> +                               qcom,remote-pid = <1>;
> +                       };
> +               };
> +
> +               stm@3002000 {
> +                       compatible = "arm,coresight-stm", "arm,primecell";
> +                       reg = <0x3002000 0x1000>,
> +                             <0x8280000 0x180000>;
> +                       reg-names = "stm-base", "stm-stimulus-base";
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       out-ports {
> +                               port {
> +                                       stm_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel0_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               tpiu@3020000 {
> +                       compatible = "arm,coresight-tpiu", "arm,primecell";
> +                       reg = <0x3020000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               port {
> +                                       tpiu_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&replicator_out1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3021000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3021000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@7 {
> +                                       reg = <7>;
> +                                       funnel0_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&stm_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       funnel0_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3022000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3022000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@6 {
> +                                       reg = <6>;
> +                                       funnel1_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_merge_funnel_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       funnel1_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3023000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3023000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +
> +                       out-ports {
> +                               port {
> +                                       funnel2_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_in2>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3025000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3025000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       merge_funnel_in0: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel0_out>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       merge_funnel_in1: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel1_out>;
> +                                       };
> +                               };
> +
> +                               port@2 {
> +                                       reg = <2>;
> +                                       merge_funnel_in2: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel2_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       merge_funnel_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etf_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               replicator@3026000 {
> +                       compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> +                       reg = <0x3026000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               port {
> +                                       replicator_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etf_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       replicator_out0: endpoint {
> +                                               remote-endpoint =
> +                                                 <&etr_in>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       replicator_out1: endpoint {
> +                                               remote-endpoint =
> +                                                 <&tpiu_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etf@3027000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0x3027000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               port {
> +                                       etf_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&merge_funnel_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       etf_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&replicator_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etr@3028000 {
> +                       compatible = "arm,coresight-tmc", "arm,primecell";
> +                       reg = <0x3028000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +                       arm,scatter-gather;
> +
> +                       in-ports {
> +                               port {
> +                                       etr_in: endpoint {
> +                                               remote-endpoint =
> +                                                 <&replicator_out0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               debug@3810000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x3810000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU0>;
> +               };
> +
> +               etm@3840000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x3840000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       cpu = <&CPU0>;
> +
> +                       out-ports {
> +                               port {
> +                                       etm0_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel0_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               debug@3910000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x3910000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU1>;
> +               };
> +
> +               etm@3940000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x3940000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       cpu = <&CPU1>;
> +
> +                       out-ports {
> +                               port {
> +                                       etm1_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel0_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@39b0000 { /* APSS Funnel 0 */
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x39b0000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       apss_funnel0_in0: endpoint {
> +                                               remote-endpoint = <&etm0_out>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       apss_funnel0_in1: endpoint {
> +                                               remote-endpoint = <&etm1_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       apss_funnel0_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_merge_funnel_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               debug@3a10000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x3a10000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU2>;
> +               };
> +
> +               etm@3a40000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x3a40000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       cpu = <&CPU2>;
> +
> +                       out-ports {
> +                               port {
> +                                       etm2_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel1_in0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               debug@3b10000 {
> +                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +                       reg = <0x3b10000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>;
> +                       clock-names = "apb_pclk";
> +
> +                       cpu = <&CPU3>;
> +               };
> +
> +               etm@3b40000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x3b40000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       cpu = <&CPU3>;
> +
> +                       out-ports {
> +                               port {
> +                                       etm3_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel1_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3bb0000 { /* APSS Funnel 1 */
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3bb0000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       apss_funnel1_in0: endpoint {
> +                                               remote-endpoint = <&etm2_out>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       apss_funnel1_in1: endpoint {
> +                                               remote-endpoint = <&etm3_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       apss_funnel1_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_merge_funnel_in1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel@3bc0000 {
> +                       compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +                       reg = <0x3bc0000 0x1000>;
> +
> +                       clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +                       clock-names = "apb_pclk", "atclk";
> +
> +                       in-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port@0 {
> +                                       reg = <0>;
> +                                       apss_merge_funnel_in0: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel0_out>;
> +                                       };
> +                               };
> +
> +                               port@1 {
> +                                       reg = <1>;
> +                                       apss_merge_funnel_in1: endpoint {
> +                                               remote-endpoint =
> +                                                 <&apss_funnel1_out>;
> +                                       };
> +                               };
> +                       };
> +
> +                       out-ports {
> +                               port {
> +                                       apss_merge_funnel_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel1_in>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               kryocc: clock-controller@6400000 {
> +                       compatible = "qcom,msm8996-apcc";
> +                       reg = <0x06400000 0x90000>;
> +
> +                       clock-names = "xo", "sys_apcs_aux";
> +                       clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
> +
> +                       #clock-cells = <1>;
> +               };
> +
> +               usb3: usb@6af8800 {
> +                       compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
> +                       reg = <0x06af8800 0x400>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
> +
> +                       clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
> +                                <&gcc GCC_USB30_MASTER_CLK>,
> +                                <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
> +                                <&gcc GCC_USB30_SLEEP_CLK>,
> +                                <&gcc GCC_USB30_MOCK_UTMI_CLK>;
> +                       clock-names = "cfg_noc",
> +                                     "core",
> +                                     "iface",
> +                                     "sleep",
> +                                     "mock_utmi";
> +
> +                       assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <120000000>;
> +
> +                       interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
> +                                       <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
> +                       interconnect-names = "usb-ddr", "apps-usb";
> +
> +                       power-domains = <&gcc USB30_GDSC>;
> +                       status = "disabled";
> +
> +                       usb3_dwc3: usb@6a00000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x06a00000 0xcc00>;
> +                               interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&hsusb_phy1>, <&ssusb_phy_0>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                               snps,hird-threshold = /bits/ 8 <0>;
> +                               snps,dis_u2_susphy_quirk;
> +                               snps,dis_enblslpm_quirk;
> +                               snps,is-utmi-l1-suspend;
> +                               tx-fifo-resize;
> +                       };
> +               };
> +
> +               usb3phy: phy@7410000 {
> +                       compatible = "qcom,msm8996-qmp-usb3-phy";
> +                       reg = <0x07410000 0x1c4>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
> +                               <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                               <&gcc GCC_USB3_CLKREF_CLK>;
> +                       clock-names = "aux", "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_USB3_PHY_BCR>,
> +                               <&gcc GCC_USB3PHY_PHY_BCR>;
> +                       reset-names = "phy", "common";
> +                       status = "disabled";
> +
> +                       ssusb_phy_0: phy@7410200 {
> +                               reg = <0x07410200 0x200>,
> +                                     <0x07410400 0x130>,
> +                                     <0x07410600 0x1a8>;
> +                               #phy-cells = <0>;
> +
> +                               #clock-cells = <0>;
> +                               clock-output-names = "usb3_phy_pipe_clk_src";
> +                               clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
> +                               clock-names = "pipe0";
> +                       };
> +               };
> +
> +               hsusb_phy1: phy@7411000 {
> +                       compatible = "qcom,msm8996-qusb2-phy";
> +                       reg = <0x07411000 0x180>;
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                               <&gcc GCC_RX1_USB2_CLKREF_CLK>;
> +                       clock-names = "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +                       nvmem-cells = <&qusb2p_hstx_trim>;
> +                       status = "disabled";
> +               };
> +
> +               hsusb_phy2: phy@7412000 {
> +                       compatible = "qcom,msm8996-qusb2-phy";
> +                       reg = <0x07412000 0x180>;
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +                               <&gcc GCC_RX2_USB2_CLKREF_CLK>;
> +                       clock-names = "cfg_ahb", "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> +                       nvmem-cells = <&qusb2s_hstx_trim>;
> +                       status = "disabled";
> +               };
> +
> +               sdhc1: mmc@7464900 {
> +                       compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
> +                       reg = <0x07464900 0x11c>, <0x07464000 0x800>;
> +                       reg-names = "hc", "core";
> +
> +                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +
> +                       clock-names = "iface", "core", "xo";
> +                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +                               <&gcc GCC_SDCC1_APPS_CLK>,
> +                               <&rpmcc RPM_SMD_XO_CLK_SRC>;
> +                       resets = <&gcc GCC_SDCC1_BCR>;
> +
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&sdc1_state_on>;
> +                       pinctrl-1 = <&sdc1_state_off>;
> +
> +                       bus-width = <8>;
> +                       non-removable;
> +                       status = "disabled";
> +               };
> +
> +               sdhc2: mmc@74a4900 {
> +                       compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
> +                       reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
> +                       reg-names = "hc", "core";
> +
> +                       interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +
> +                       clock-names = "iface", "core", "xo";
> +                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> +                               <&gcc GCC_SDCC2_APPS_CLK>,
> +                               <&rpmcc RPM_SMD_XO_CLK_SRC>;
> +                       resets = <&gcc GCC_SDCC2_BCR>;
> +
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&sdc2_state_on>;
> +                       pinctrl-1 = <&sdc2_state_off>;
> +
> +                       bus-width = <4>;
> +                       status = "disabled";
> +                };
> +
> +               blsp1_dma: dma-controller@7544000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x07544000 0x2b000>;
> +                       interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       qcom,controlled-remotely;
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +               };
> +
> +               blsp1_uart2: serial@7570000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x07570000 0x1000>;
> +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp1_uart2_default>;
> +                       pinctrl-1 = <&blsp1_uart2_sleep>;
> +                       dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
> +                       dma-names = "tx", "rx";
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi1: spi@7575000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x07575000 0x600>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp1_spi1_default>;
> +                       pinctrl-1 = <&blsp1_spi1_sleep>;
> +                       dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c3: i2c@7577000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x07577000 0x1000>;
> +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp1_i2c3_default>;
> +                       pinctrl-1 = <&blsp1_i2c3_sleep>;
> +                       dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c6: i2c@757a000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x757a000 0x1000>;
> +                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp1_i2c6_default>;
> +                       pinctrl-1 = <&blsp1_i2c6_sleep>;
> +                       dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_dma: dma-controller@7584000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x07584000 0x2b000>;
> +                       interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       qcom,controlled-remotely;
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +               };
> +
> +               blsp2_uart2: serial@75b0000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x075b0000 0x1000>;
> +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       status = "disabled";
> +               };
> +
> +               blsp2_uart3: serial@75b1000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x075b1000 0x1000>;
> +                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c1: i2c@75b5000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x075b5000 0x1000>;
> +                       interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp2_i2c1_default>;
> +                       pinctrl-1 = <&blsp2_i2c1_sleep>;
> +                       dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c2: i2c@75b6000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x075b6000 0x1000>;
> +                       interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp2_i2c2_default>;
> +                       pinctrl-1 = <&blsp2_i2c2_sleep>;
> +                       dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c3: i2c@75b7000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x075b7000 0x1000>;
> +                       interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       clock-frequency = <400000>;
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp2_i2c3_default>;
> +                       pinctrl-1 = <&blsp2_i2c3_sleep>;
> +                       dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c5: i2c@75b9000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x75b9000 0x1000>;
> +                       interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp2_i2c5_default>;
> +                       dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c6: i2c@75ba000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x75ba000 0x1000>;
> +                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp2_i2c6_default>;
> +                       pinctrl-1 = <&blsp2_i2c6_sleep>;
> +                       dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_spi6: spi@75ba000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x075ba000 0x600>;
> +                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default", "sleep";
> +                       pinctrl-0 = <&blsp2_spi6_default>;
> +                       pinctrl-1 = <&blsp2_spi6_sleep>;
> +                       dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
> +                       dma-names = "tx", "rx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               usb2: usb@76f8800 {
> +                       compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
> +                       reg = <0x076f8800 0x400>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +
> +                       interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hs_phy_irq";
> +
> +                       clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
> +                               <&gcc GCC_USB20_MASTER_CLK>,
> +                               <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +                               <&gcc GCC_USB20_SLEEP_CLK>,
> +                               <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
> +                       clock-names = "cfg_noc",
> +                                     "core",
> +                                     "iface",
> +                                     "sleep",
> +                                     "mock_utmi";
> +
> +                       assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB20_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <60000000>;
> +
> +                       power-domains = <&gcc USB30_GDSC>;
> +                       qcom,select-utmi-as-pipe-clk;
> +                       status = "disabled";
> +
> +                       usb2_dwc3: usb@7600000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x07600000 0xcc00>;
> +                               interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&hsusb_phy2>;
> +                               phy-names = "usb2-phy";
> +                               maximum-speed = "high-speed";
> +                               snps,dis_u2_susphy_quirk;
> +                               snps,dis_enblslpm_quirk;
> +                       };
> +               };
> +
> +               slimbam: dma-controller@9184000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       qcom,controlled-remotely;
> +                       reg = <0x09184000 0x32000>;
> +                       num-channels = <31>;
> +                       interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> +                       #dma-cells = <1>;
> +                       qcom,ee = <1>;
> +                       qcom,num-ees = <2>;
> +               };
> +
> +               slim_msm: slim-ngd@91c0000 {
> +                       compatible = "qcom,slim-ngd-v1.5.0";
> +                       reg = <0x091c0000 0x2c000>;
> +                       interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
> +                       dmas = <&slimbam 3>, <&slimbam 4>;
> +                       dma-names = "rx", "tx";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       status = "disabled";
> +               };
> +
> +               adsp_pil: remoteproc@9300000 {
> +                       compatible = "qcom,msm8996-adsp-pil";
> +                       reg = <0x09300000 0x80000>;
> +
> +                       interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack";
> +
> +                       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
> +                       clock-names = "xo";
> +
> +                       memory-region = <&adsp_mem>;
> +
> +                       qcom,smem-states = <&adsp_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       power-domains = <&rpmpd MSM8996_VDDCX>;
> +                       power-domain-names = "cx";
> +
> +                       status = "disabled";
> +
> +                       smd-edge {
> +                               interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
> +
> +                               label = "lpass";
> +                               mboxes = <&apcs_glb 8>;
> +                               qcom,smd-edge = <1>;
> +                               qcom,remote-pid = <2>;
> +
> +                               apr {
> +                                       power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
> +                                       compatible = "qcom,apr-v2";
> +                                       qcom,smd-channels = "apr_audio_svc";
> +                                       qcom,domain = <APR_DOMAIN_ADSP>;
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       service@3 {
> +                                               reg = <APR_SVC_ADSP_CORE>;
> +                                               compatible = "qcom,q6core";
> +                                       };
> +
> +                                       q6afe: service@4 {
> +                                               compatible = "qcom,q6afe";
> +                                               reg = <APR_SVC_AFE>;
> +                                               q6afedai: dais {
> +                                                       compatible = "qcom,q6afe-dais";
> +                                                       #address-cells = <1>;
> +                                                       #size-cells = <0>;
> +                                                       #sound-dai-cells = <1>;
> +                                                       dai@1 {
> +                                                               reg = <1>;
> +                                                       };
> +                                               };
> +                                       };
> +
> +                                       q6asm: service@7 {
> +                                               compatible = "qcom,q6asm";
> +                                               reg = <APR_SVC_ASM>;
> +                                               q6asmdai: dais {
> +                                                       compatible = "qcom,q6asm-dais";
> +                                                       #address-cells = <1>;
> +                                                       #size-cells = <0>;
> +                                                       #sound-dai-cells = <1>;
> +                                                       iommus = <&lpass_q6_smmu 1>;
> +                                               };
> +                                       };
> +
> +                                       q6adm: service@8 {
> +                                               compatible = "qcom,q6adm";
> +                                               reg = <APR_SVC_ADM>;
> +                                               q6routing: routing {
> +                                                       compatible = "qcom,q6adm-routing";
> +                                                       #sound-dai-cells = <0>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               apcs_glb: mailbox@9820000 {
> +                       compatible = "qcom,msm8996-apcs-hmss-global";
> +                       reg = <0x09820000 0x1000>;
> +
> +                       #mbox-cells = <1>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               timer@9840000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       compatible = "arm,armv7-timer-mem";
> +                       reg = <0x09840000 0x1000>;
> +                       clock-frequency = <19200000>;
> +
> +                       frame@9850000 {
> +                               frame-number = <0>;
> +                               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x09850000 0x1000>,
> +                                     <0x09860000 0x1000>;
> +                       };
> +
> +                       frame@9870000 {
> +                               frame-number = <1>;
> +                               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x09870000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@9880000 {
> +                               frame-number = <2>;
> +                               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x09880000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@9890000 {
> +                               frame-number = <3>;
> +                               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x09890000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@98a0000 {
> +                               frame-number = <4>;
> +                               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x098a0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@98b0000 {
> +                               frame-number = <5>;
> +                               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x098b0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@98c0000 {
> +                               frame-number = <6>;
> +                               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x098c0000 0x1000>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               saw3: syscon@9a10000 {
> +                       compatible = "syscon";
> +                       reg = <0x09a10000 0x1000>;
> +               };
> +
> +               cbf: clock-controller@9a11000 {
> +                       compatible = "qcom,msm8996-cbf";
> +                       reg = <0x09a11000 0x10000>;
> +                       clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
> +                       #clock-cells = <0>;
> +                       #interconnect-cells = <1>;
> +               };
> +
> +               intc: interrupt-controller@9bc0000 {
> +                       compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
> +                       #interrupt-cells = <3>;
> +                       interrupt-controller;
> +                       #redistributor-regions = <1>;
> +                       redistributor-stride = <0x0 0x40000>;
> +                       reg = <0x09bc0000 0x10000>,
> +                             <0x09c00000 0x100000>;
> +                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +       };
> +
> +       sound: sound {
> +       };
> +
> +       thermal-zones {
> +               cpu0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 3>;
> +
> +                       trips {
> +                               cpu0_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu0_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 5>;
> +
> +                       trips {
> +                               cpu1_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu1_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 8>;
> +
> +                       trips {
> +                               cpu2_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu2_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               cpu3-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 10>;
> +
> +                       trips {
> +                               cpu3_alert0: trip-point0 {
> +                                       temperature = <75000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +
> +                               cpu3_crit: cpu-crit {
> +                                       temperature = <110000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               gpu-top-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 6>;
> +
> +                       trips {
> +                               gpu1_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&gpu1_alert0>;
> +                                       cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               gpu-bottom-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 7>;
> +
> +                       trips {
> +                               gpu2_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&gpu2_alert0>;
> +                                       cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               m4m-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 1>;
> +
> +                       trips {
> +                               m4m_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               l3-or-venus-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 2>;
> +
> +                       trips {
> +                               l3_or_venus_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               cluster0-l2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 7>;
> +
> +                       trips {
> +                               cluster0_l2_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               cluster1-l2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 12>;
> +
> +                       trips {
> +                               cluster1_l2_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               camera-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 1>;
> +
> +                       trips {
> +                               camera_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               q6-dsp-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 2>;
> +
> +                       trips {
> +                               q6_dsp_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               mem-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 3>;
> +
> +                       trips {
> +                               mem_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               modemtx-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens1 4>;
> +
> +                       trips {
> +                               modemtx_alert0: trip-point0 {
> +                                       temperature = <90000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +       };
> +};
> diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
> index 89847ce0b307..bf70258ec040 100644
> --- a/configs/dragonboard820c_defconfig
> +++ b/configs/dragonboard820c_defconfig
> @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x804000
>  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
>  CONFIG_ENV_SIZE=0x4000
> -CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
> +CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c"
>  CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
>  CONFIG_SYS_LOAD_ADDR=0x80080000
>  CONFIG_DISTRO_DEFAULTS=y
>
> --
> 2.43.1
>

Re: [PATCH v4 38/39] dts: qcs404-evb: replace with upstream DT

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Drop the U-Boot specific DTS in favour of upstream. We'll only include
> the -4000 variant as that is what U-Boot already supported.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/Makefile                    |    2 +-
>  arch/arm/dts/pms405.dtsi                 |  149 +++
>  arch/arm/dts/qcs404-evb-4000-u-boot.dtsi |   48 +
>  arch/arm/dts/qcs404-evb-4000.dts         |   96 ++
>  arch/arm/dts/qcs404-evb-uboot.dtsi       |   30 -
>  arch/arm/dts/qcs404-evb.dts              |  390 -------
>  arch/arm/dts/qcs404-evb.dtsi             |  389 +++++++
>  arch/arm/dts/qcs404.dtsi                 | 1829 ++++++++++++++++++++++++++++++
>  8 files changed, 2512 insertions(+), 421 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 54aaf022c2eb..c4f0873dbb1f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -635,7 +635,7 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
>         apq8096-db820c.dtb \
>         sdm845-db845c.dtb \
>         sdm845-samsung-starqltechn.dtb \
> -       qcs404-evb.dtb
> +       qcs404-evb-4000.dtb
>
>  dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
>
> diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi
> new file mode 100644
> index 000000000000..461ad97032f7
> --- /dev/null
> +++ b/arch/arm/dts/pms405.dtsi
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +#include <dt-bindings/spmi/spmi.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       thermal-zones {
> +               pms405-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&pms405_temp>;
> +
> +                       trips {
> +                               pms405_alert0: pms405-alert0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               pms405_crit: pms405-crit {
> +                                       temperature = <125000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&spmi_bus {
> +       pms405_0: pms405@0 {
> +               compatible = "qcom,pms405", "qcom,spmi-pmic";
> +               reg = <0x0 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pms405_gpios: gpio@c000 {
> +                       compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pms405_gpios 0 0 12>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               pon@800 {
> +                       compatible = "qcom,pms405-pon";
> +                       reg = <0x0800>;
> +                       mode-bootloader = <0x2>;
> +                       mode-recovery = <0x1>;
> +
> +                       pwrkey {
> +                               compatible = "qcom,pm8941-pwrkey";
> +                               interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               linux,code = <KEY_POWER>;
> +                       };
> +               };
> +
> +               pms405_temp: temp-alarm@2400 {
> +                       compatible = "qcom,spmi-temp-alarm";
> +                       reg = <0x2400>;
> +                       interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
> +                       io-channels = <&pms405_adc ADC5_DIE_TEMP>;
> +                       io-channel-names = "thermal";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
> +               pms405_adc: adc@3100 {
> +                       compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
> +                       reg = <0x3100>;
> +                       interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #io-channel-cells = <1>;
> +
> +                       channel@0 {
> +                               reg = <ADC5_REF_GND>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "ref_gnd";
> +                       };
> +
> +                       channel@1 {
> +                               reg = <ADC5_1P25VREF>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "vref_1p25";
> +                       };
> +
> +                       channel@131 {
> +                               reg = <ADC5_VPH_PWR>;
> +                               qcom,pre-scaling = <1 3>;
> +                               label = "vph_pwr";
> +                       };
> +
> +                       channel@6 {
> +                               reg = <ADC5_DIE_TEMP>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "die_temp";
> +                       };
> +
> +                       channel@77 {
> +                               reg = <ADC5_AMUX_THM1_100K_PU>;
> +                               qcom,ratiometric;
> +                               qcom,hw-settle-time = <200>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "pa_therm1";
> +                       };
> +
> +                       channel@79 {
> +                               reg = <ADC5_AMUX_THM3_100K_PU>;
> +                               qcom,ratiometric;
> +                               qcom,hw-settle-time = <200>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "pa_therm3";
> +                       };
> +
> +                       channel@76 {
> +                               reg = <ADC5_XO_THERM_100K_PU>;
> +                               qcom,ratiometric;
> +                               qcom,hw-settle-time = <200>;
> +                               qcom,pre-scaling = <1 1>;
> +                               label = "xo_therm";
> +                       };
> +               };
> +
> +               rtc@6000 {
> +                       compatible = "qcom,pm8941-rtc";
> +                       reg = <0x6000>, <0x6100>;
> +                       reg-names = "rtc", "alarm";
> +                       interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> +               };
> +       };
> +
> +       pms405_1: pms405@1 {
> +               compatible = "qcom,pms405", "qcom,spmi-pmic";
> +               reg = <0x1 SPMI_USID>;
> +
> +               pms405_spmi_regulators: regulators {
> +                       compatible = "qcom,pms405-regulators";
> +               };
> +       };
> +};
> diff --git a/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
> new file mode 100644
> index 000000000000..d3033ea42ec1
> --- /dev/null
> +++ b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/delete-node/ &usb3_vbus_reg;
> +/delete-node/ &usb_vbus_boost_pin;
> +
> +/ {
> +       /* U-Boot uses different bindings for GPIO regulators, this
> +        * one is required for USB
> +        */
> +       usb3_vbus_reg: usb3_vbus_reg {
> +               compatible = "regulator-gpio";
> +               regulator-name = "usb3_vbus_reg";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +               enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +               states = <0 0>, <5000000 1>;
> +       };
> +};
> +
> +&blsp1_uart2 {
> +       /* This defines the bit clock divider which defines the baud rate.
> +        * 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
> +        * clock driver in U-Boot hardcodes a 1843200Hz frequency for the
> +        * UART core clock, and 1843200 / 16 = 115200.
> +        */
> +       bit-rate = <0xFF>;
> +};
> +
> +&gcc {
> +       /* The clock framework in U-Boot "sort of" has the idea of linking an
> +        * individual clock to a device via uclass_priv. However the qcom clock
> +        * driver instead associates many clocks with a single device. This is
> +        * usually fine but it seems that assigned-clocks wreak havoc on this
> +        * and we wind up having a reference to the XO clock which is associated
> +        * with the qcom_clk device...
> +        * For now we'll just remove these properties, no other board has these.
> +        */
> +       /delete-property/ assigned-clock-rates;
> +       /delete-property/ assigned-clocks;
> +};
> +
> +&usb3_dwc3 {
> +       /* Make sure the VBUS supply is switched on */
> +       vbus-supply = <&usb3_vbus_reg>;
> +};
> diff --git a/arch/arm/dts/qcs404-evb-4000.dts b/arch/arm/dts/qcs404-evb-4000.dts
> new file mode 100644
> index 000000000000..358827c2fbd3
> --- /dev/null
> +++ b/arch/arm/dts/qcs404-evb-4000.dts
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "qcs404-evb.dtsi"
> +
> +/ {
> +       model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
> +       compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
> +                    "qcom,qcs404";
> +};
> +
> +&ethernet {
> +       status = "okay";
> +
> +       snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
> +       snps,reset-active-low;
> +       snps,reset-delays-us = <0 10000 10000>;
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&ethernet_defaults>;
> +
> +       phy-handle = <&phy1>;
> +       phy-mode = "rgmii";
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               compatible = "snps,dwmac-mdio";
> +               phy1: phy@4 {
> +                       compatible = "ethernet-phy-ieee802.3-c22";
> +                       device_type = "ethernet-phy";
> +                       reg = <0x4>;
> +               };
> +       };
> +};
> +
> +&tlmm {
> +       ethernet_defaults: ethernet-defaults-state {
> +               int-pins {
> +                       pins = "gpio61";
> +                       function = "rgmii_int";
> +                       bias-disable;
> +                       drive-strength = <2>;
> +               };
> +               mdc-pins {
> +                       pins = "gpio76";
> +                       function = "rgmii_mdc";
> +                       bias-pull-up;
> +               };
> +               mdio-pins {
> +                       pins = "gpio75";
> +                       function = "rgmii_mdio";
> +                       bias-pull-up;
> +               };
> +               tx-pins {
> +                       pins = "gpio67", "gpio66", "gpio65", "gpio64";
> +                       function = "rgmii_tx";
> +                       bias-pull-up;
> +                       drive-strength = <16>;
> +               };
> +               rx-pins {
> +                       pins = "gpio73", "gpio72", "gpio71", "gpio70";
> +                       function = "rgmii_rx";
> +                       bias-disable;
> +                       drive-strength = <2>;
> +               };
> +               tx-ctl-pins {
> +                       pins = "gpio68";
> +                       function = "rgmii_ctl";
> +                       bias-pull-up;
> +                       drive-strength = <16>;
> +               };
> +               rx-ctl-pins {
> +                       pins = "gpio74";
> +                       function = "rgmii_ctl";
> +                       bias-disable;
> +                       drive-strength = <2>;
> +               };
> +               tx-ck-pins {
> +                       pins = "gpio63";
> +                       function = "rgmii_ck";
> +                       bias-pull-up;
> +                       drive-strength = <16>;
> +               };
> +               rx-ck-pins {
> +                       pins = "gpio69";
> +                       function = "rgmii_ck";
> +                       bias-disable;
> +                       drive-strength = <2>;
> +               };
> +       };
> +};
> diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi
> deleted file mode 100644
> index b4c5f3fa4301..000000000000
> --- a/arch/arm/dts/qcs404-evb-uboot.dtsi
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * U-Boot addition to handle QCS404 EVB pre-relocation devices
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -/ {
> -       soc {
> -               bootph-all;
> -
> -               pinctrl_north@1300000 {
> -                       bootph-all;
> -               };
> -
> -               clock-controller@1800000 {
> -                       bootph-all;
> -               };
> -
> -               serial@78b1000 {
> -                       bootph-all;
> -               };
> -       };
> -};
> -
> -&pms405_gpios {
> -       usb_vbus_boost_pin {
> -               gpios = <&pms405_gpios 2 0>;
> -       };
> -};
> diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
> deleted file mode 100644
> index 07bf7dd0b32f..000000000000
> --- a/arch/arm/dts/qcs404-evb.dts
> +++ /dev/null
> @@ -1,390 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Qualcomm QCS404 based evaluation board device tree source
> - *
> - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> - */
> -
> -/dts-v1/;
> -
> -#include "skeleton64.dtsi"
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/qcom,gcc-qcs404.h>
> -
> -/ {
> -       model = "Qualcomm Technologies, Inc. QCS404 EVB";
> -       compatible = "qcom,qcs404-evb", "qcom,qcs404";
> -       #address-cells = <0x2>;
> -       #size-cells = <0x2>;
> -
> -       chosen {
> -               stdout-path = "serial0:115200n8";
> -       };
> -
> -       aliases {
> -               serial0 = &debug_uart;
> -               i2c0 = &blsp1_i2c0;
> -               i2c1 = &blsp1_i2c1;
> -               i2c2 = &blsp1_i2c2;
> -               i2c3 = &blsp1_i2c3;
> -               i2c4 = &blsp1_i2c4;
> -       };
> -
> -       memory {
> -               device_type = "memory";
> -               reg = <0 0x80000000 0 0x40000000>;
> -       };
> -
> -       soc {
> -               #address-cells = <0x1>;
> -               #size-cells = <0x1>;
> -               ranges = <0x0 0x0 0x0 0xffffffff>;
> -               compatible = "simple-bus";
> -
> -               soc_gpios: pinctrl_north@1300000 {
> -                       compatible = "qcom,qcs404-pinctrl";
> -                       reg = <0x1300000 0x200000>;
> -                       gpio-controller;
> -                       gpio-count = <120>;
> -                       gpio-bank-name="soc";
> -                       #gpio-cells = <2>;
> -
> -                       blsp1_uart2: uart {
> -                               pins = "GPIO_17", "GPIO_18";
> -                               function = "blsp_uart2";
> -                       };
> -
> -                       blsp1_i2c0_default: blsp1-i2c0-default {
> -                               pins = "GPIO_32", "GPIO_33";
> -                               function = "blsp_i2c0";
> -                       };
> -
> -                       blsp1_i2c1_default: blsp1-i2c1-default {
> -                               pins = "GPIO_24", "GPIO_25";
> -                               function = "blsp_i2c1";
> -                       };
> -
> -                       blsp1_i2c2_default: blsp1-i2c2-default {
> -                               sda {
> -                                       pins = "GPIO_19";
> -                                       function = "blsp_i2c_sda_a2";
> -                               };
> -
> -                               scl {
> -                                       pins = "GPIO_20";
> -                                       function = "blsp_i2c_scl_a2";
> -                               };
> -                       };
> -
> -                       blsp1_i2c3_default: blsp1-i2c3-default {
> -                               pins = "GPIO_84", "GPIO_85";
> -                               function = "blsp_i2c3";
> -                       };
> -
> -                       blsp1_i2c4_default: blsp1-i2c4-default {
> -                               pins = "GPIO_117", "GPIO_118";
> -                               function = "blsp_i2c4";
> -                       };
> -
> -                       ethernet_defaults: ethernet-defaults {
> -                               int {
> -                                       pins = "GPIO_61";
> -                                       function = "rgmii_int";
> -                                       bias-disable;
> -                                       drive-strength = <2>;
> -                               };
> -                               mdc {
> -                                       pins = "GPIO_76";
> -                                       function = "rgmii_mdc";
> -                                       bias-pull-up;
> -                               };
> -                               mdio {
> -                                       pins = "GPIO_75";
> -                                       function = "rgmii_mdio";
> -                                       bias-pull-up;
> -                               };
> -                               tx {
> -                                       pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
> -                                       function = "rgmii_tx";
> -                                       bias-pull-up;
> -                                       drive-strength = <16>;
> -                               };
> -                               rx {
> -                                       pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
> -                                       function = "rgmii_rx";
> -                                       bias-disable;
> -                                       drive-strength = <2>;
> -                               };
> -                               tx-ctl {
> -                                       pins = "GPIO_68";
> -                                       function = "rgmii_ctl";
> -                                       bias-pull-up;
> -                                       drive-strength = <16>;
> -                               };
> -                               rx-ctl {
> -                                       pins = "GPIO_74";
> -                                       function = "rgmii_ctl";
> -                                       bias-disable;
> -                                       drive-strength = <2>;
> -                               };
> -                               tx-ck {
> -                                       pins = "GPIO_63";
> -                                       function = "rgmii_ck";
> -                                       bias-pull-up;
> -                                       drive-strength = <16>;
> -                               };
> -                               rx-ck {
> -                                       pins = "GPIO_69";
> -                                       function = "rgmii_ck";
> -                                       bias-disable;
> -                                       drive-strength = <2>;
> -                               };
> -                       };
> -               };
> -
> -               blsp1_i2c0: i2c@78b5000 {
> -                       compatible = "qcom,i2c-qup-v2.2.1";
> -                       reg = <0x078b5000 0x600>;
> -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> -                                <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
> -                       clock-names = "iface", "core";
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&blsp1_i2c0_default>;
> -                       #address-cells = <1>;
> -                       #size-cells = <0>;
> -               };
> -
> -               blsp1_i2c1: i2c@78b6000 {
> -                       compatible = "qcom,i2c-qup-v2.2.1";
> -                       reg = <0x078b6000 0x600>;
> -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> -                                <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
> -                       clock-names = "iface", "core";
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&blsp1_i2c1_default>;
> -                       #address-cells = <1>;
> -                       #size-cells = <0>;
> -               };
> -
> -               blsp1_i2c2: i2c@78b7000 {
> -                       compatible = "qcom,i2c-qup-v2.2.1";
> -                       reg = <0x078b7000 0x600>;
> -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> -                                <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> -                       clock-names = "iface", "core";
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&blsp1_i2c2_default>;
> -                       #address-cells = <1>;
> -                       #size-cells = <0>;
> -               };
> -
> -               blsp1_i2c3: i2c@78b8000 {
> -                       compatible = "qcom,i2c-qup-v2.2.1";
> -                       reg = <0x078b8000 0x600>;
> -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> -                                <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
> -                       clock-names = "iface", "core";
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&blsp1_i2c3_default>;
> -                       #address-cells = <1>;
> -                       #size-cells = <0>;
> -               };
> -
> -               blsp1_i2c4: i2c@78b9000 {
> -                       compatible = "qcom,i2c-qup-v2.2.1";
> -                       reg = <0x078b9000 0x600>;
> -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> -                                <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
> -                       clock-names = "iface", "core";
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&blsp1_i2c4_default>;
> -                       #address-cells = <1>;
> -                       #size-cells = <0>;
> -               };
> -
> -               gcc: clock-controller@1800000 {
> -                       compatible = "qcom,gcc-qcs404";
> -                       reg = <0x1800000 0x80000>;
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x0>;
> -                       #clock-cells = <1>;
> -                       #reset-cells = <1>;
> -               };
> -
> -               debug_uart: serial@78b1000 {
> -                       compatible = "qcom,msm-uartdm-v1.4";
> -                       reg = <0x78b1000 0x200>;
> -                       clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> -                               <&gcc GCC_BLSP1_AHB_CLK>;
> -                       bit-rate = <0xFF>;
> -                       pinctrl-names = "uart";
> -                       pinctrl-0 = <&blsp1_uart2>;
> -               };
> -
> -               sdhci@7804000 {
> -                       compatible = "qcom,sdhci-msm-v5";
> -                       reg = <0x7804000 0x1000 0x7805000 0x1000>;
> -                       clock = <&gcc GCC_SDCC1_APPS_CLK>,
> -                               <&gcc GCC_SDCC1_AHB_CLK>;
> -                       bus-width = <0x8>;
> -                       index = <0x0>;
> -                       non-removable;
> -                       mmc-ddr-1_8v;
> -                       mmc-hs400-1_8v;
> -               };
> -
> -               usb3_phy: phy@78000 {
> -                       compatible = "qcom,usb-ss-28nm-phy";
> -                       #phy-cells = <0>;
> -                       reg = <0x78000 0x400>;
> -                       clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> -                                <&gcc GCC_USB3_PHY_PIPE_CLK>;
> -                       clock-names = "ahb", "pipe";
> -                       resets = <&gcc GCC_USB3_PHY_BCR>,
> -                                <&gcc GCC_USB3PHY_PHY_BCR>;
> -                       reset-names = "com", "phy";
> -               };
> -
> -               usb2_phy_prim: phy@7a000 {
> -                       compatible = "qcom,usb-hs-28nm-femtophy";
> -                       #phy-cells = <0>;
> -                       reg = <0x7a000 0x200>;
> -                       clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> -                                <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> -                       clock-names = "ahb", "sleep";
> -                       resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
> -                                <&gcc GCC_USB2A_PHY_BCR>;
> -                       reset-names = "phy", "por";
> -               };
> -
> -               usb2_phy_sec: phy@7c000 {
> -                       compatible = "qcom,usb-hs-28nm-femtophy";
> -                       #phy-cells = <0>;
> -                       reg = <0x7c000 0x200>;
> -                       clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> -                                <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> -                       clock-names = "ahb", "sleep";
> -                       resets = <&gcc GCC_QUSB2_PHY_BCR>,
> -                                <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
> -                       reset-names = "phy", "por";
> -               };
> -
> -               usb3: usb@7678800 {
> -                       compatible = "qcom,dwc3";
> -                       reg = <0x7678800 0x400>;
> -                       #address-cells = <1>;
> -                       #size-cells = <1>;
> -                       ranges;
> -                       clocks = <&gcc GCC_USB30_MASTER_CLK>,
> -                                <&gcc GCC_SYS_NOC_USB3_CLK>,
> -                                <&gcc GCC_USB30_SLEEP_CLK>,
> -                                <&gcc GCC_USB30_MOCK_UTMI_CLK>;
> -                       clock-names = "core", "iface", "sleep", "mock_utmi";
> -
> -                       dwc3@7580000 {
> -                               compatible = "snps,dwc3";
> -                               reg = <0x7580000 0xcd00>;
> -                               phys = <&usb2_phy_prim>, <&usb3_phy>;
> -                               phy-names = "usb2-phy", "usb3-phy";
> -                               dr_mode = "host";
> -                               snps,has-lpm-erratum;
> -                               snps,hird-threshold = /bits/ 8 <0x10>;
> -                               snps,usb3_lpm_capable;
> -                               maximum-speed = "super-speed";
> -                       };
> -               };
> -
> -               usb2: usb@79b8800 {
> -                       compatible = "qcom,dwc3";
> -                       reg = <0x79b8800 0x400>;
> -                       #address-cells = <1>;
> -                       #size-cells = <1>;
> -                       ranges;
> -                       clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
> -                                <&gcc GCC_PCNOC_USB2_CLK>,
> -                                <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
> -                                <&gcc GCC_USB20_MOCK_UTMI_CLK>;
> -                       clock-names = "core", "iface", "sleep", "mock_utmi";
> -
> -                       dwc3@78c0000 {
> -                               compatible = "snps,dwc3";
> -                               reg = <0x78c0000 0xcc00>;
> -                               phys = <&usb2_phy_sec>;
> -                               phy-names = "usb2-phy";
> -                               dr_mode = "peripheral";
> -                               snps,has-lpm-erratum;
> -                               snps,hird-threshold = /bits/ 8 <0x10>;
> -                               snps,usb3_lpm_capable;
> -                               maximum-speed = "high-speed";
> -                       };
> -               };
> -
> -               ethernet: ethernet@7a80000 {
> -                       compatible = "qcom,qcs404-ethqos";
> -                       reg = <0x07a80000 0x10000>,
> -                               <0x07a96000 0x100>;
> -                       reg-names = "stmmaceth", "rgmii";
> -                       clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
> -                       clocks = <&gcc GCC_ETH_AXI_CLK>,
> -                                <&gcc GCC_ETH_SLAVE_AHB_CLK>,
> -                                <&gcc GCC_ETH_PTP_CLK>,
> -                                <&gcc GCC_ETH_RGMII_CLK>;
> -
> -                       resets = <&gcc GCC_EMAC_BCR>;
> -                       reset-names = "emac";
> -
> -                       snps,tso;
> -                       rx-fifo-depth = <4096>;
> -                       tx-fifo-depth = <4096>;
> -
> -                       snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
> -                       snps,reset-active-low;
> -                       snps,reset-delays-us = <0 10000 10000>;
> -
> -                       pinctrl-names = "default";
> -                       pinctrl-0 = <&ethernet_defaults>;
> -
> -                       phy-handle = <&phy1>;
> -                       phy-mode = "rgmii";
> -                       max-speed = <1000>;
> -
> -                       mdio {
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x0>;
> -                               compatible = "snps,dwmac-mdio";
> -                               phy1: phy@3 {
> -                                       compatible = "ethernet-phy-ieee802.3-c22";
> -                                       device_type = "ethernet-phy";
> -                                       reg = <0x3>;
> -                               };
> -                       };
> -               };
> -
> -               spmi@200f000 {
> -                       compatible = "qcom,spmi-pmic-arb";
> -                       reg = <0x200f000 0x001000>,
> -                             <0x2400000 0x800000>,
> -                             <0x2c00000 0x800000>;
> -                       reg-names = "core", "chnls", "obsrvr";
> -                       #address-cells = <0x1>;
> -                       #size-cells = <0x1>;
> -
> -                       pms405_0: pms405@0 {
> -                               compatible = "qcom,spmi-pmic";
> -                               reg = <0x0 0x1>;
> -                               #address-cells = <0x1>;
> -                               #size-cells = <0x1>;
> -
> -                               pms405_gpios: pms405_gpios@c000 {
> -                                       compatible = "qcom,pms405-gpio";
> -                                       reg = <0xc000 0x400>;
> -                                       gpio-controller;
> -                                       gpio-ranges = <&pms405_gpios 0 0 12>;
> -                                       #gpio-cells = <2>;
> -                               };
> -                       };
> -               };
> -       };
> -};
> -
> -#include "qcs404-evb-uboot.dtsi"
> diff --git a/arch/arm/dts/qcs404-evb.dtsi b/arch/arm/dts/qcs404-evb.dtsi
> new file mode 100644
> index 000000000000..10655401528e
> --- /dev/null
> +++ b/arch/arm/dts/qcs404-evb.dtsi
> @@ -0,0 +1,389 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "qcs404.dtsi"
> +#include "pms405.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +
> +/ {
> +       aliases {
> +               serial0 = &blsp1_uart2;
> +               serial1 = &blsp1_uart3;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0";
> +       };
> +
> +       vph_pwr: vph-pwr-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vph_pwr";
> +               regulator-always-on;
> +               regulator-boot-on;
> +       };
> +
> +       vdd_ch0_3p3:
> +       vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "eSMPS3_3P3";
> +
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +               regulator-always-on;
> +       };
> +
> +       usb3_vbus_reg: regulator-usb3-vbus {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VBUS_BOOST_5V";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +               gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&usb_vbus_boost_pin>;
> +               vin-supply = <&vph_pwr>;
> +               enable-active-high;
> +
> +               /* TODO: Drop this when introducing role switching */
> +               regulator-always-on;
> +       };
> +};
> +
> +&blsp1_uart3 {
> +       status = "okay";
> +
> +       bluetooth {
> +               compatible = "qcom,wcn3990-bt";
> +               vddio-supply = <&vreg_l6_1p8>;
> +               vddxo-supply = <&vreg_l5_1p8>;
> +               vddrf-supply = <&vreg_l1_1p3>;
> +               vddch0-supply = <&vdd_ch0_3p3>;
> +
> +               local-bd-address = [ 02 00 00 00 5a ad ];
> +
> +               max-speed = <3200000>;
> +       };
> +};
> +
> +&blsp1_dma {
> +       qcom,controlled-remotely;
> +};
> +
> +&blsp2_dma {
> +       qcom,controlled-remotely;
> +};
> +
> +&gcc {
> +       protected-clocks = <GCC_BIMC_CDSP_CLK>,
> +                          <GCC_CDSP_CFG_AHB_CLK>,
> +                          <GCC_CDSP_BIMC_CLK_SRC>,
> +                          <GCC_CDSP_TBU_CLK>,
> +                          <141>, /* GCC_WCSS_Q6_AHB_CLK */
> +                          <142>; /* GCC_WCSS_Q6_AXIM_CLK */
> +};
> +
> +&pms405_spmi_regulators {
> +       vdd_s3-supply = <&vph_pwr>;
> +
> +       pms405_s3: s3 {
> +               regulator-always-on;
> +               regulator-boot-on;
> +               regulator-name = "vdd_apc";
> +               regulator-initial-mode = <1>;
> +               regulator-min-microvolt = <1048000>;
> +               regulator-max-microvolt = <1384000>;
> +       };
> +};
> +
> +&pcie {
> +       status = "okay";
> +
> +       perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&perst_state>;
> +};
> +
> +&pcie_phy {
> +       status = "okay";
> +
> +       vdda-vp-supply = <&vreg_l3_1p05>;
> +       vdda-vph-supply = <&vreg_l5_1p8>;
> +};
> +
> +&remoteproc_adsp {
> +       status = "okay";
> +};
> +
> +&remoteproc_cdsp {
> +       status = "okay";
> +};
> +
> +&remoteproc_wcss {
> +       status = "okay";
> +};
> +
> +&rpm_requests {
> +       regulators {
> +               compatible = "qcom,rpm-pms405-regulators";
> +
> +               vdd_s1-supply = <&vph_pwr>;
> +               vdd_s2-supply = <&vph_pwr>;
> +               vdd_s3-supply = <&vph_pwr>;
> +               vdd_s4-supply = <&vph_pwr>;
> +               vdd_s5-supply = <&vph_pwr>;
> +               vdd_l1_l2-supply = <&vreg_s5_1p35>;
> +               vdd_l3_l8-supply = <&vreg_s5_1p35>;
> +               vdd_l4-supply = <&vreg_s5_1p35>;
> +               vdd_l5_l6-supply = <&vreg_s4_1p8>;
> +               vdd_l7-supply = <&vph_pwr>;
> +               vdd_l9-supply = <&vreg_s5_1p35>;
> +               vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
> +
> +               vreg_s4_1p8: s4 {
> +                       regulator-min-microvolt = <1728000>;
> +                       regulator-max-microvolt = <1920000>;
> +               };
> +
> +               vreg_s5_1p35: s5 {
> +                       regulator-min-microvolt = <1352000>;
> +                       regulator-max-microvolt = <1352000>;
> +               };
> +
> +               vreg_l1_1p3: l1 {
> +                       regulator-min-microvolt = <1240000>;
> +                       regulator-max-microvolt = <1352000>;
> +               };
> +
> +               vreg_l2_1p275: l2 {
> +                       regulator-min-microvolt = <1048000>;
> +                       regulator-max-microvolt = <1280000>;
> +               };
> +
> +               vreg_l3_1p05: l3 {
> +                       regulator-min-microvolt = <1048000>;
> +                       regulator-max-microvolt = <1160000>;
> +               };
> +
> +               vreg_l4_1p2: l4 {
> +                       regulator-min-microvolt = <1144000>;
> +                       regulator-max-microvolt = <1256000>;
> +               };
> +
> +               vreg_l5_1p8: l5 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +
> +               vreg_l6_1p8: l6 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on;
> +               };
> +
> +               vreg_l7_1p8: l7 {
> +                       regulator-min-microvolt = <1616000>;
> +                       regulator-max-microvolt = <3000000>;
> +               };
> +
> +               vreg_l8_1p2: l8 {
> +                       regulator-min-microvolt = <1136000>;
> +                       regulator-max-microvolt = <1352000>;
> +               };
> +
> +               vreg_l10_3p3: l10 {
> +                       regulator-min-microvolt = <2936000>;
> +                       regulator-max-microvolt = <3088000>;
> +               };
> +
> +               vreg_l11_sdc2: l11 {
> +                       regulator-min-microvolt = <2696000>;
> +                       regulator-max-microvolt = <3304000>;
> +               };
> +
> +               vreg_l12_3p3: l12 {
> +                       regulator-min-microvolt = <3050000>;
> +                       regulator-max-microvolt = <3300000>;
> +               };
> +
> +               vreg_l13_3p3: l13 {
> +                       regulator-min-microvolt = <3000000>;
> +                       regulator-max-microvolt = <3300000>;
> +               };
> +       };
> +};
> +
> +&sdcc1 {
> +       status = "okay";
> +
> +       supports-cqe;
> +       mmc-ddr-1_8v;
> +       mmc-hs400-1_8v;
> +       bus-width = <8>;
> +       non-removable;
> +
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&sdc1_on>;
> +       pinctrl-1 = <&sdc1_off>;
> +};
> +
> +&tlmm {
> +       perst_state: perst-state {
> +               pins = "gpio43";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-disable;
> +               output-low;
> +       };
> +
> +       sdc1_on: sdc1-on-state {
> +               clk-pins {
> +                       pins = "sdc1_clk";
> +                       bias-disable;
> +                       drive-strength = <16>;
> +               };
> +
> +               cmd-pins {
> +                       pins = "sdc1_cmd";
> +                       bias-pull-up;
> +                       drive-strength = <10>;
> +               };
> +
> +               data-pins {
> +                       pins = "sdc1_data";
> +                       bias-pull-up;
> +                       drive-strength = <10>;
> +               };
> +
> +               rclk-pins {
> +                       pins = "sdc1_rclk";
> +                       bias-pull-down;
> +               };
> +       };
> +
> +       sdc1_off: sdc1-off-state {
> +               clk-pins {
> +                       pins = "sdc1_clk";
> +                       bias-disable;
> +                       drive-strength = <2>;
> +               };
> +
> +               cmd-pins {
> +                       pins = "sdc1_cmd";
> +                       bias-pull-up;
> +                       drive-strength = <2>;
> +               };
> +
> +               data-pins {
> +                       pins = "sdc1_data";
> +                       bias-pull-up;
> +                       drive-strength = <2>;
> +               };
> +
> +               rclk-pins {
> +                       pins = "sdc1_rclk";
> +                       bias-pull-down;
> +               };
> +       };
> +
> +       usb3_id_pin: usb3-id-state {
> +               pins = "gpio116";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-pull-up;
> +       };
> +};
> +
> +&pms405_gpios {
> +       usb_vbus_boost_pin: usb-vbus-boost-state {
> +               pinconf {
> +                       pins = "gpio3";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       output-low;
> +                       power-source = <1>;
> +               };
> +       };
> +       usb3_vbus_pin: usb3-vbus-state {
> +               pinconf {
> +                       pins = "gpio12";
> +                       function = PMIC_GPIO_FUNC_NORMAL;
> +                       input-enable;
> +                       bias-pull-down;
> +                       power-source = <1>;
> +               };
> +       };
> +};
> +
> +&usb2 {
> +       status = "okay";
> +};
> +
> +&usb2_phy_sec {
> +       vdd-supply = <&vreg_l4_1p2>;
> +       vdda1p8-supply = <&vreg_l5_1p8>;
> +       vdda3p3-supply = <&vreg_l12_3p3>;
> +       status = "okay";
> +};
> +
> +&usb3 {
> +       status = "okay";
> +
> +};
> +
> +&usb3_dwc3 {
> +       dr_mode = "host";
> +};
> +
> +&usb2_phy_prim {
> +       vdd-supply = <&vreg_l4_1p2>;
> +       vdda1p8-supply = <&vreg_l5_1p8>;
> +       vdda3p3-supply = <&vreg_l12_3p3>;
> +       status = "okay";
> +};
> +
> +&usb3_phy {
> +       vdd-supply = <&vreg_l3_1p05>;
> +       vdda1p8-supply = <&vreg_l5_1p8>;
> +       status = "okay";
> +};
> +
> +&wifi {
> +       status = "okay";
> +       vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
> +       vdd-1.8-xo-supply = <&vreg_l5_1p8>;
> +       vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
> +};
> +
> +/* PINCTRL - additions to nodes defined in qcs404.dtsi */
> +
> +&blsp1_uart2_default {
> +       rx-pins {
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       tx-pins {
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +};
> +
> +&blsp1_uart3_default {
> +       cts-pins {
> +               bias-disable;
> +       };
> +
> +       rts-tx-pins {
> +               drive-strength = <2>;
> +               bias-disable;
> +       };
> +
> +       rx-pins {
> +               bias-pull-up;
> +       };
> +};
> diff --git a/arch/arm/dts/qcs404.dtsi b/arch/arm/dts/qcs404.dtsi
> new file mode 100644
> index 000000000000..2721f32dfb71
> --- /dev/null
> +++ b/arch/arm/dts/qcs404.dtsi
> @@ -0,0 +1,1829 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-qcs404.h>
> +#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <19200000>;
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <32768>;
> +               };
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x100>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       power-domains = <&cpr>;
> +                       power-domain-names = "cpr";
> +               };
> +
> +               CPU1: cpu@101 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x101>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       power-domains = <&cpr>;
> +                       power-domain-names = "cpr";
> +               };
> +
> +               CPU2: cpu@102 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x102>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       power-domains = <&cpr>;
> +                       power-domain-names = "cpr";
> +               };
> +
> +               CPU3: cpu@103 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0x103>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&CPU_SLEEP_0>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       power-domains = <&cpr>;
> +                       power-domain-names = "cpr";
> +               };
> +
> +               L2_0: l2-cache {
> +                       compatible = "cache";
> +                       cache-level = <2>;
> +                       cache-unified;
> +               };
> +
> +               idle-states {
> +                       entry-method = "psci";
> +
> +                       CPU_SLEEP_0: cpu-sleep-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "standalone-power-collapse";
> +                               arm,psci-suspend-param = <0x40000003>;
> +                               entry-latency-us = <125>;
> +                               exit-latency-us = <180>;
> +                               min-residency-us = <595>;
> +                               local-timer-stop;
> +                       };
> +               };
> +       };
> +
> +       cpu_opp_table: opp-table-cpu {
> +               compatible = "operating-points-v2-kryo-cpu";
> +               opp-shared;
> +
> +               opp-1094400000 {
> +                       opp-hz = /bits/ 64 <1094400000>;
> +                       required-opps = <&cpr_opp1>;
> +               };
> +               opp-1248000000 {
> +                       opp-hz = /bits/ 64 <1248000000>;
> +                       required-opps = <&cpr_opp2>;
> +               };
> +               opp-1401600000 {
> +                       opp-hz = /bits/ 64 <1401600000>;
> +                       required-opps = <&cpr_opp3>;
> +               };
> +       };
> +
> +       cpr_opp_table: opp-table-cpr {
> +               compatible = "operating-points-v2-qcom-level";
> +
> +               cpr_opp1: opp1 {
> +                       opp-level = <1>;
> +                       qcom,opp-fuse-level = <1>;
> +               };
> +               cpr_opp2: opp2 {
> +                       opp-level = <2>;
> +                       qcom,opp-fuse-level = <2>;
> +               };
> +               cpr_opp3: opp3 {
> +                       opp-level = <3>;
> +                       qcom,opp-fuse-level = <3>;
> +               };
> +       };
> +
> +       firmware {
> +               scm: scm {
> +                       compatible = "qcom,scm-qcs404", "qcom,scm";
> +                       #reset-cells = <1>;
> +               };
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the size */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       rpm: remoteproc {
> +               compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
> +
> +               glink-edge {
> +                       compatible = "qcom,glink-rpm";
> +
> +                       interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> +                       qcom,rpm-msg-ram = <&rpm_msg_ram>;
> +                       mboxes = <&apcs_glb 0>;
> +
> +                       rpm_requests: rpm-requests {
> +                               compatible = "qcom,rpm-qcs404";
> +                               qcom,glink-channels = "rpm_requests";
> +
> +                               rpmcc: clock-controller {
> +                                       compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
> +                                       #clock-cells = <1>;
> +                                       clocks = <&xo_board>;
> +                                       clock-names = "xo";
> +                               };
> +
> +                               rpmpd: power-controller {
> +                                       compatible = "qcom,qcs404-rpmpd";
> +                                       #power-domain-cells = <1>;
> +                                       operating-points-v2 = <&rpmpd_opp_table>;
> +
> +                                       rpmpd_opp_table: opp-table {
> +                                               compatible = "operating-points-v2";
> +
> +                                               rpmpd_opp_ret: opp1 {
> +                                                       opp-level = <16>;
> +                                               };
> +
> +                                               rpmpd_opp_ret_plus: opp2 {
> +                                                       opp-level = <32>;
> +                                               };
> +
> +                                               rpmpd_opp_min_svs: opp3 {
> +                                                       opp-level = <48>;
> +                                               };
> +
> +                                               rpmpd_opp_low_svs: opp4 {
> +                                                       opp-level = <64>;
> +                                               };
> +
> +                                               rpmpd_opp_svs: opp5 {
> +                                                       opp-level = <128>;
> +                                               };
> +
> +                                               rpmpd_opp_svs_plus: opp6 {
> +                                                       opp-level = <192>;
> +                                               };
> +
> +                                               rpmpd_opp_nom: opp7 {
> +                                                       opp-level = <256>;
> +                                               };
> +
> +                                               rpmpd_opp_nom_plus: opp8 {
> +                                                       opp-level = <320>;
> +                                               };
> +
> +                                               rpmpd_opp_turbo: opp9 {
> +                                                       opp-level = <384>;
> +                                               };
> +
> +                                               rpmpd_opp_turbo_no_cpr: opp10 {
> +                                                       opp-level = <416>;
> +                                               };
> +
> +                                               rpmpd_opp_turbo_plus: opp11 {
> +                                                       opp-level = <512>;
> +                                               };
> +                                       };
> +                               };
> +                       };
> +               };
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               tz_apps_mem: memory@85900000 {
> +                       reg = <0 0x85900000 0 0x500000>;
> +                       no-map;
> +               };
> +
> +               xbl_mem: memory@85e00000 {
> +                       reg = <0 0x85e00000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               smem_region: memory@85f00000 {
> +                       reg = <0 0x85f00000 0 0x200000>;
> +                       no-map;
> +               };
> +
> +               tz_mem: memory@86100000 {
> +                       reg = <0 0x86100000 0 0x300000>;
> +                       no-map;
> +               };
> +
> +               wlan_fw_mem: memory@86400000 {
> +                       reg = <0 0x86400000 0 0x1100000>;
> +                       no-map;
> +               };
> +
> +               adsp_fw_mem: memory@87500000 {
> +                       reg = <0 0x87500000 0 0x1a00000>;
> +                       no-map;
> +               };
> +
> +               cdsp_fw_mem: memory@88f00000 {
> +                       reg = <0 0x88f00000 0 0x600000>;
> +                       no-map;
> +               };
> +
> +               wlan_msa_mem: memory@89500000 {
> +                       reg = <0 0x89500000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               uefi_mem: memory@9f800000 {
> +                       reg = <0 0x9f800000 0 0x800000>;
> +                       no-map;
> +               };
> +       };
> +
> +       smem {
> +               compatible = "qcom,smem";
> +
> +               memory-region = <&smem_region>;
> +               qcom,rpm-msg-ram = <&rpm_msg_ram>;
> +
> +               hwlocks = <&tcsr_mutex 3>;
> +       };
> +
> +       soc: soc@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0 0 0 0xffffffff>;
> +               compatible = "simple-bus";
> +
> +               turingcc: clock-controller@800000 {
> +                       compatible = "qcom,qcs404-turingcc";
> +                       reg = <0x00800000 0x30000>;
> +                       clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
> +
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +
> +                       status = "disabled";
> +               };
> +
> +               rpm_msg_ram: sram@60000 {
> +                       compatible = "qcom,rpm-msg-ram";
> +                       reg = <0x00060000 0x6000>;
> +               };
> +
> +               usb3_phy: phy@78000 {
> +                       compatible = "qcom,usb-ss-28nm-phy";
> +                       reg = <0x00078000 0x400>;
> +                       #phy-cells = <0>;
> +                       clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
> +                                <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> +                                <&gcc GCC_USB3_PHY_PIPE_CLK>;
> +                       clock-names = "ref", "ahb", "pipe";
> +                       resets = <&gcc GCC_USB3_PHY_BCR>,
> +                                <&gcc GCC_USB3PHY_PHY_BCR>;
> +                       reset-names = "com", "phy";
> +                       status = "disabled";
> +               };
> +
> +               usb2_phy_prim: phy@7a000 {
> +                       compatible = "qcom,usb-hs-28nm-femtophy";
> +                       reg = <0x0007a000 0x200>;
> +                       #phy-cells = <0>;
> +                       clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
> +                                <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> +                                <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> +                       clock-names = "ref", "ahb", "sleep";
> +                       resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
> +                                <&gcc GCC_USB2A_PHY_BCR>;
> +                       reset-names = "phy", "por";
> +                       status = "disabled";
> +               };
> +
> +               usb2_phy_sec: phy@7c000 {
> +                       compatible = "qcom,usb-hs-28nm-femtophy";
> +                       reg = <0x0007c000 0x200>;
> +                       #phy-cells = <0>;
> +                       clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
> +                                <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> +                                <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> +                       clock-names = "ref", "ahb", "sleep";
> +                       resets = <&gcc GCC_QUSB2_PHY_BCR>,
> +                                <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
> +                       reset-names = "phy", "por";
> +                       status = "disabled";
> +               };
> +
> +               qfprom: qfprom@a4000 {
> +                       compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
> +                       reg = <0x000a4000 0x1000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       cpr_efuse_speedbin: speedbin@13c {
> +                               reg = <0x13c 0x4>;
> +                               bits = <2 3>;
> +                       };
> +
> +                       tsens_s0_p1: s0-p1@1f8 {
> +                               reg = <0x1f8 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s0_p2: s0-p2@1f8 {
> +                               reg = <0x1f8 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_s1_p1: s1-p1@1f9 {
> +                               reg = <0x1f9 0x2>;
> +                               bits = <4 6>;
> +                       };
> +
> +                       tsens_s1_p2: s1-p2@1fa {
> +                               reg = <0x1fa 0x1>;
> +                               bits = <2 6>;
> +                       };
> +
> +                       tsens_s2_p1: s2-p1@1fb {
> +                               reg = <0x1fb 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s2_p2: s2-p2@1fb {
> +                               reg = <0x1fb 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_s3_p1: s3-p1@1fc {
> +                               reg = <0x1fc 0x2>;
> +                               bits = <4 6>;
> +                       };
> +
> +                       tsens_s3_p2: s3-p2@1fd {
> +                               reg = <0x1fd 0x1>;
> +                               bits = <2 6>;
> +                       };
> +
> +                       tsens_s4_p1: s4-p1@1fe {
> +                               reg = <0x1fe 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s4_p2: s4-p2@1fe {
> +                               reg = <0x1fe 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_s5_p1: s5-p1@200 {
> +                               reg = <0x200 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s5_p2: s5-p2@200 {
> +                               reg = <0x200 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_s6_p1: s6-p1@201 {
> +                               reg = <0x201 0x2>;
> +                               bits = <4 6>;
> +                       };
> +
> +                       tsens_s6_p2: s6-p2@202 {
> +                               reg = <0x202 0x1>;
> +                               bits = <2 6>;
> +                       };
> +
> +                       tsens_s7_p1: s7-p1@203 {
> +                               reg = <0x203 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s7_p2: s7-p2@203 {
> +                               reg = <0x203 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_s8_p1: s8-p1@204 {
> +                               reg = <0x204 0x2>;
> +                               bits = <4 6>;
> +                       };
> +
> +                       tsens_s8_p2: s8-p2@205 {
> +                               reg = <0x205 0x1>;
> +                               bits = <2 6>;
> +                       };
> +
> +                       tsens_s9_p1: s9-p1@206 {
> +                               reg = <0x206 0x1>;
> +                               bits = <0 6>;
> +                       };
> +
> +                       tsens_s9_p2: s9-p2@206 {
> +                               reg = <0x206 0x2>;
> +                               bits = <6 6>;
> +                       };
> +
> +                       tsens_mode: mode@208 {
> +                               reg = <0x208 1>;
> +                               bits = <0 3>;
> +                       };
> +
> +                       tsens_base1: base1@208 {
> +                               reg = <0x208 2>;
> +                               bits = <3 8>;
> +                       };
> +
> +                       tsens_base2: base2@208 {
> +                               reg = <0x209 2>;
> +                               bits = <3 8>;
> +                       };
> +
> +                       cpr_efuse_quot_offset1: qoffset1@231 {
> +                               reg = <0x231 0x4>;
> +                               bits = <4 7>;
> +                       };
> +                       cpr_efuse_quot_offset2: qoffset2@232 {
> +                               reg = <0x232 0x4>;
> +                               bits = <3 7>;
> +                       };
> +                       cpr_efuse_quot_offset3: qoffset3@233 {
> +                               reg = <0x233 0x4>;
> +                               bits = <2 7>;
> +                       };
> +                       cpr_efuse_init_voltage1: ivoltage1@229 {
> +                               reg = <0x229 0x4>;
> +                               bits = <4 6>;
> +                       };
> +                       cpr_efuse_init_voltage2: ivoltage2@22a {
> +                               reg = <0x22a 0x4>;
> +                               bits = <2 6>;
> +                       };
> +                       cpr_efuse_init_voltage3: ivoltage3@22b {
> +                               reg = <0x22b 0x4>;
> +                               bits = <0 6>;
> +                       };
> +                       cpr_efuse_quot1: quot1@22b {
> +                               reg = <0x22b 0x4>;
> +                               bits = <6 12>;
> +                       };
> +                       cpr_efuse_quot2: quot2@22d {
> +                               reg = <0x22d 0x4>;
> +                               bits = <2 12>;
> +                       };
> +                       cpr_efuse_quot3: quot3@230 {
> +                               reg = <0x230 0x4>;
> +                               bits = <0 12>;
> +                       };
> +                       cpr_efuse_ring1: ring1@228 {
> +                               reg = <0x228 0x4>;
> +                               bits = <0 3>;
> +                       };
> +                       cpr_efuse_ring2: ring2@228 {
> +                               reg = <0x228 0x4>;
> +                               bits = <4 3>;
> +                       };
> +                       cpr_efuse_ring3: ring3@229 {
> +                               reg = <0x229 0x4>;
> +                               bits = <0 3>;
> +                       };
> +                       cpr_efuse_revision: revision@218 {
> +                               reg = <0x218 0x4>;
> +                               bits = <3 3>;
> +                       };
> +               };
> +
> +               rng: rng@e3000 {
> +                       compatible = "qcom,prng-ee";
> +                       reg = <0x000e3000 0x1000>;
> +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
> +                       clock-names = "core";
> +               };
> +
> +               bimc: interconnect@400000 {
> +                       reg = <0x00400000 0x80000>;
> +                       compatible = "qcom,qcs404-bimc";
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
> +                               <&rpmcc RPM_SMD_BIMC_A_CLK>;
> +               };
> +
> +               tsens: thermal-sensor@4a9000 {
> +                       compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
> +                       reg = <0x004a9000 0x1000>, /* TM */
> +                             <0x004a8000 0x1000>; /* SROT */
> +                       nvmem-cells = <&tsens_mode>,
> +                                     <&tsens_base1>, <&tsens_base2>,
> +                                     <&tsens_s0_p1>, <&tsens_s0_p2>,
> +                                     <&tsens_s1_p1>, <&tsens_s1_p2>,
> +                                     <&tsens_s2_p1>, <&tsens_s2_p2>,
> +                                     <&tsens_s3_p1>, <&tsens_s3_p2>,
> +                                     <&tsens_s4_p1>, <&tsens_s4_p2>,
> +                                     <&tsens_s5_p1>, <&tsens_s5_p2>,
> +                                     <&tsens_s6_p1>, <&tsens_s6_p2>,
> +                                     <&tsens_s7_p1>, <&tsens_s7_p2>,
> +                                     <&tsens_s8_p1>, <&tsens_s8_p2>,
> +                                     <&tsens_s9_p1>, <&tsens_s9_p2>;
> +                       nvmem-cell-names = "mode",
> +                                          "base1", "base2",
> +                                          "s0_p1", "s0_p2",
> +                                          "s1_p1", "s1_p2",
> +                                          "s2_p1", "s2_p2",
> +                                          "s3_p1", "s3_p2",
> +                                          "s4_p1", "s4_p2",
> +                                          "s5_p1", "s5_p2",
> +                                          "s6_p1", "s6_p2",
> +                                          "s7_p1", "s7_p2",
> +                                          "s8_p1", "s8_p2",
> +                                          "s9_p1", "s9_p2";
> +                       #qcom,sensors = <10>;
> +                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               pcnoc: interconnect@500000 {
> +                       reg = <0x00500000 0x15080>;
> +                       compatible = "qcom,qcs404-pcnoc";
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
> +                               <&rpmcc RPM_SMD_PNOC_A_CLK>;
> +               };
> +
> +               snoc: interconnect@580000 {
> +                       reg = <0x00580000 0x23080>;
> +                       compatible = "qcom,qcs404-snoc";
> +                       #interconnect-cells = <1>;
> +                       clock-names = "bus", "bus_a";
> +                       clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
> +                               <&rpmcc RPM_SMD_SNOC_A_CLK>;
> +               };
> +
> +               remoteproc_cdsp: remoteproc@b00000 {
> +                       compatible = "qcom,qcs404-cdsp-pas";
> +                       reg = <0x00b00000 0x4040>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
> +                                             <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack";
> +
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +
> +                       /*
> +                        * If the node was using the PIL binding, then include properties:
> +                        * clocks = <&xo_board>,
> +                        *          <&gcc GCC_CDSP_CFG_AHB_CLK>,
> +                        *          <&gcc GCC_CDSP_TBU_CLK>,
> +                        *          <&gcc GCC_BIMC_CDSP_CLK>,
> +                        *          <&turingcc TURING_WRAPPER_AON_CLK>,
> +                        *          <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
> +                        *          <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
> +                        *          <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
> +                        * clock-names = "xo",
> +                        *               "sway",
> +                        *               "tbu",
> +                        *               "bimc",
> +                        *               "ahb_aon",
> +                        *               "q6ss_slave",
> +                        *               "q6ss_master",
> +                        *               "q6_axim";
> +                        * resets = <&gcc GCC_CDSP_RESTART>;
> +                        * reset-names = "restart";
> +                        * qcom,halt-regs = <&tcsr 0x19004>;
> +                        */
> +
> +                       memory-region = <&cdsp_fw_mem>;
> +
> +                       qcom,smem-states = <&cdsp_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       status = "disabled";
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> +
> +                               qcom,remote-pid = <5>;
> +                               mboxes = <&apcs_glb 12>;
> +
> +                               label = "cdsp";
> +                       };
> +               };
> +
> +               usb3: usb@7678800 {
> +                       compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
> +                       reg = <0x07678800 0x400>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       clocks = <&gcc GCC_USB30_MASTER_CLK>,
> +                                <&gcc GCC_SYS_NOC_USB3_CLK>,
> +                                <&gcc GCC_USB30_SLEEP_CLK>,
> +                                <&gcc GCC_USB30_MOCK_UTMI_CLK>;
> +                       clock-names = "core", "iface", "sleep", "mock_utmi";
> +                       assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <200000000>;
> +                       status = "disabled";
> +
> +                       usb3_dwc3: usb@7580000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x07580000 0xcd00>;
> +                               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb2_phy_prim>, <&usb3_phy>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                               snps,has-lpm-erratum;
> +                               snps,hird-threshold = /bits/ 8 <0x10>;
> +                               snps,usb3_lpm_capable;
> +                               dr_mode = "otg";
> +                       };
> +               };
> +
> +               usb2: usb@79b8800 {
> +                       compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
> +                       reg = <0x079b8800 0x400>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
> +                                <&gcc GCC_PCNOC_USB2_CLK>,
> +                                <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
> +                                <&gcc GCC_USB20_MOCK_UTMI_CLK>;
> +                       clock-names = "core", "iface", "sleep", "mock_utmi";
> +                       assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB_HS_SYSTEM_CLK>;
> +                       assigned-clock-rates = <19200000>, <133333333>;
> +                       status = "disabled";
> +
> +                       usb@78c0000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x078c0000 0xcc00>;
> +                               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb2_phy_sec>;
> +                               phy-names = "usb2-phy";
> +                               snps,has-lpm-erratum;
> +                               snps,hird-threshold = /bits/ 8 <0x10>;
> +                               snps,usb3_lpm_capable;
> +                               dr_mode = "peripheral";
> +                       };
> +               };
> +
> +               tlmm: pinctrl@1000000 {
> +                       compatible = "qcom,qcs404-pinctrl";
> +                       reg = <0x01000000 0x200000>,
> +                             <0x01300000 0x200000>,
> +                             <0x07b00000 0x200000>;
> +                       reg-names = "south", "north", "east";
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-ranges = <&tlmm 0 0 120>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +
> +                       blsp1_i2c0_default: blsp1-i2c0-default-state {
> +                               pins = "gpio32", "gpio33";
> +                               function = "blsp_i2c0";
> +                       };
> +
> +                       blsp1_i2c1_default: blsp1-i2c1-default-state {
> +                               pins = "gpio24", "gpio25";
> +                               function = "blsp_i2c1";
> +                       };
> +
> +                       blsp1_i2c2_default: blsp1-i2c2-default-state {
> +                               sda-pins {
> +                                       pins = "gpio19";
> +                                       function = "blsp_i2c_sda_a2";
> +                               };
> +
> +                               scl-pins {
> +                                       pins = "gpio20";
> +                                       function = "blsp_i2c_scl_a2";
> +                               };
> +                       };
> +
> +                       blsp1_i2c3_default: blsp1-i2c3-default-state {
> +                               pins = "gpio84", "gpio85";
> +                               function = "blsp_i2c3";
> +                       };
> +
> +                       blsp1_i2c4_default: blsp1-i2c4-default-state {
> +                               pins = "gpio117", "gpio118";
> +                               function = "blsp_i2c4";
> +                       };
> +
> +                       blsp1_uart0_default: blsp1-uart0-default-state {
> +                               pins = "gpio30", "gpio31", "gpio32", "gpio33";
> +                               function = "blsp_uart0";
> +                       };
> +
> +                       blsp1_uart1_default: blsp1-uart1-default-state {
> +                               pins = "gpio22", "gpio23";
> +                               function = "blsp_uart1";
> +                       };
> +
> +                       blsp1_uart2_default: blsp1-uart2-default-state {
> +                               rx-pins {
> +                                       pins = "gpio18";
> +                                       function = "blsp_uart_rx_a2";
> +                               };
> +
> +                               tx-pins {
> +                                       pins = "gpio17";
> +                                       function = "blsp_uart_tx_a2";
> +                               };
> +                       };
> +
> +                       blsp1_uart3_default: blsp1-uart3-default-state {
> +                               cts-pins {
> +                                       pins = "gpio84";
> +                                       function = "blsp_uart3";
> +                               };
> +
> +                               rts-tx-pins {
> +                                       pins = "gpio85", "gpio82";
> +                                       function = "blsp_uart3";
> +                               };
> +
> +                               rx-pins {
> +                                       pins = "gpio83";
> +                                       function = "blsp_uart3";
> +                               };
> +                       };
> +
> +                       blsp2_i2c0_default: blsp2-i2c0-default-state {
> +                               pins = "gpio28", "gpio29";
> +                               function = "blsp_i2c5";
> +                       };
> +
> +                       blsp1_spi0_default: blsp1-spi0-default-state {
> +                               pins = "gpio30", "gpio31", "gpio32", "gpio33";
> +                               function = "blsp_spi0";
> +                       };
> +
> +                       blsp1_spi1_default: blsp1-spi1-default-state {
> +                               mosi-pins {
> +                                       pins = "gpio22";
> +                                       function = "blsp_spi_mosi_a1";
> +                               };
> +
> +                               miso-pins {
> +                                       pins = "gpio23";
> +                                       function = "blsp_spi_miso_a1";
> +                               };
> +
> +                               cs-n-pins {
> +                                       pins = "gpio24";
> +                                       function = "blsp_spi_cs_n_a1";
> +                               };
> +
> +                               clk-pins {
> +                                       pins = "gpio25";
> +                                       function = "blsp_spi_clk_a1";
> +                               };
> +                       };
> +
> +                       blsp1_spi2_default: blsp1-spi2-default-state {
> +                               pins = "gpio17", "gpio18", "gpio19", "gpio20";
> +                               function = "blsp_spi2";
> +                       };
> +
> +                       blsp1_spi3_default: blsp1-spi3-default-state {
> +                               pins = "gpio82", "gpio83", "gpio84", "gpio85";
> +                               function = "blsp_spi3";
> +                       };
> +
> +                       blsp1_spi4_default: blsp1-spi4-default-state {
> +                               pins = "gpio37", "gpio38", "gpio117", "gpio118";
> +                               function = "blsp_spi4";
> +                       };
> +
> +                       blsp2_spi0_default: blsp2-spi0-default-state {
> +                               pins = "gpio26", "gpio27", "gpio28", "gpio29";
> +                               function = "blsp_spi5";
> +                       };
> +
> +                       blsp2_uart0_default: blsp2-uart0-default-state {
> +                               pins = "gpio26", "gpio27", "gpio28", "gpio29";
> +                               function = "blsp_uart5";
> +                       };
> +               };
> +
> +               gcc: clock-controller@1800000 {
> +                       compatible = "qcom,gcc-qcs404";
> +                       reg = <0x01800000 0x80000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +
> +                       clocks = <&xo_board>,
> +                                <&sleep_clk>,
> +                                <&pcie_phy>,
> +                                <0>,
> +                                <0>,
> +                                <0>;
> +
> +                       assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
> +                       assigned-clock-rates = <19200000>;
> +               };
> +
> +               tcsr_mutex: hwlock@1905000 {
> +                       compatible = "qcom,tcsr-mutex";
> +                       reg = <0x01905000 0x20000>;
> +                       #hwlock-cells = <1>;
> +               };
> +
> +               tcsr: syscon@1937000 {
> +                       compatible = "qcom,qcs404-tcsr", "syscon";
> +                       reg = <0x01937000 0x25000>;
> +               };
> +
> +               sram@290000 {
> +                       compatible = "qcom,rpm-stats";
> +                       reg = <0x00290000 0x10000>;
> +               };
> +
> +               spmi_bus: spmi@200f000 {
> +                       compatible = "qcom,spmi-pmic-arb";
> +                       reg = <0x0200f000 0x001000>,
> +                             <0x02400000 0x800000>,
> +                             <0x02c00000 0x800000>,
> +                             <0x03800000 0x200000>,
> +                             <0x0200a000 0x002100>;
> +                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +                       interrupt-names = "periph_irq";
> +                       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,ee = <0>;
> +                       qcom,channel = <0>;
> +                       #address-cells = <2>;
> +                       #size-cells = <0>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <4>;
> +               };
> +
> +               remoteproc_wcss: remoteproc@7400000 {
> +                       compatible = "qcom,qcs404-wcss-pas";
> +                       reg = <0x07400000 0x4040>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack";
> +
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +
> +                       memory-region = <&wlan_fw_mem>;
> +
> +                       qcom,smem-states = <&wcss_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       status = "disabled";
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
> +
> +                               qcom,remote-pid = <1>;
> +                               mboxes = <&apcs_glb 16>;
> +
> +                               label = "wcss";
> +                       };
> +               };
> +
> +               pcie_phy: phy@7786000 {
> +                       compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> +                       reg = <0x07786000 0xb8>;
> +
> +                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> +                       resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> +                                <&gcc GCC_PCIE_0_PIPE_ARES>;
> +                       reset-names = "phy", "pipe";
> +
> +                       clock-output-names = "pcie_0_pipe_clk";
> +                       #clock-cells = <0>;
> +                       #phy-cells = <0>;
> +
> +                       status = "disabled";
> +               };
> +
> +               sdcc1: mmc@7804000 {
> +                       compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
> +                       reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
> +                       reg-names = "hc", "cqhci";
> +
> +                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hc_irq", "pwr_irq";
> +
> +                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +                                <&gcc GCC_SDCC1_APPS_CLK>,
> +                                <&xo_board>;
> +                       clock-names = "iface", "core", "xo";
> +
> +                       status = "disabled";
> +               };
> +
> +               blsp1_dma: dma-controller@7884000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x07884000 0x25000>;
> +                       interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +                       status = "okay";
> +               };
> +
> +               blsp1_uart0: serial@78af000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078af000 0x200>;
> +                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_uart0_default>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_uart1: serial@78b0000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078b0000 0x200>;
> +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_uart1_default>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_uart2: serial@78b1000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078b1000 0x200>;
> +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_uart2_default>;
> +                       status = "okay";
> +               };
> +
> +               ethernet: ethernet@7a80000 {
> +                       compatible = "qcom,qcs404-ethqos";
> +                       reg = <0x07a80000 0x10000>,
> +                               <0x07a96000 0x100>;
> +                       reg-names = "stmmaceth", "rgmii";
> +                       clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
> +                       clocks = <&gcc GCC_ETH_AXI_CLK>,
> +                               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
> +                               <&gcc GCC_ETH_PTP_CLK>,
> +                               <&gcc GCC_ETH_RGMII_CLK>;
> +                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "macirq", "eth_lpi";
> +
> +                       snps,tso;
> +                       rx-fifo-depth = <4096>;
> +                       tx-fifo-depth = <4096>;
> +
> +                       status = "disabled";
> +               };
> +
> +               wifi: wifi@a000000 {
> +                       compatible = "qcom,wcn3990-wifi";
> +                       reg = <0xa000000 0x800000>;
> +                       reg-names = "membase";
> +                       memory-region = <&wlan_msa_mem>;
> +                       interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_uart3: serial@78b2000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x078b2000 0x200>;
> +                       interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_uart3_default>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c0: i2c@78b5000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b5000 0x600>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_i2c0_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi0: spi@78b5000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b5000 0x600>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_spi0_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c1: i2c@78b6000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b6000 0x600>;
> +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_i2c1_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi1: spi@78b6000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b6000 0x600>;
> +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_spi1_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c2: i2c@78b7000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b7000 0x600>;
> +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_i2c2_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi2: spi@78b7000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b7000 0x600>;
> +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_spi2_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c3: i2c@78b8000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b8000 0x600>;
> +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_i2c3_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi3: spi@78b8000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b8000 0x600>;
> +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_spi3_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_i2c4: i2c@78b9000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x078b9000 0x600>;
> +                       interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_i2c4_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp1_spi4: spi@78b9000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x078b9000 0x600>;
> +                       interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP1_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp1_spi4_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_dma: dma-controller@7ac4000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x07ac4000 0x17000>;
> +                       interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_uart0: serial@7aef000 {
> +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +                       reg = <0x07aef000 0x200>;
> +                       interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
> +                       dma-names = "tx", "rx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp2_uart0_default>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_i2c0: i2c@7af5000 {
> +                       compatible = "qcom,i2c-qup-v2.2.1";
> +                       reg = <0x07af5000 0x600>;
> +                       interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp2_i2c0_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               blsp2_spi0: spi@7af5000 {
> +                       compatible = "qcom,spi-qup-v2.2.1";
> +                       reg = <0x07af5000 0x600>;
> +                       interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
> +                                <&gcc GCC_BLSP2_AHB_CLK>;
> +                       clock-names = "core", "iface";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&blsp2_spi0_default>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               sram@8600000 {
> +                       compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
> +                       reg = <0x08600000 0x1000>;
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       ranges = <0 0x08600000 0x1000>;
> +
> +                       pil-reloc@94c {
> +                               compatible = "qcom,pil-reloc-info";
> +                               reg = <0x94c 0xc8>;
> +                       };
> +               };
> +
> +               intc: interrupt-controller@b000000 {
> +                       compatible = "qcom,msm-qgic2";
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +                       reg = <0x0b000000 0x1000>,
> +                             <0x0b002000 0x1000>;
> +               };
> +
> +               apcs_glb: mailbox@b011000 {
> +                       compatible = "qcom,qcs404-apcs-apps-global",
> +                                    "qcom,msm8916-apcs-kpss-global", "syscon";
> +                       reg = <0x0b011000 0x1000>;
> +                       #mbox-cells = <1>;
> +                       clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
> +                       clock-names = "pll", "aux";
> +                       #clock-cells = <0>;
> +               };
> +
> +               apcs_hfpll: clock-controller@b016000 {
> +                       compatible = "qcom,hfpll";
> +                       reg = <0x0b016000 0x30>;
> +                       #clock-cells = <0>;
> +                       clock-output-names = "apcs_hfpll";
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +               };
> +
> +               watchdog@b017000 {
> +                       compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
> +                       reg = <0x0b017000 0x1000>;
> +                       clocks = <&sleep_clk>;
> +               };
> +
> +               cpr: power-controller@b018000 {
> +                       compatible = "qcom,qcs404-cpr", "qcom,cpr";
> +                       reg = <0x0b018000 0x1000>;
> +                       interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> +                       clocks = <&xo_board>;
> +                       clock-names = "ref";
> +                       vdd-apc-supply = <&pms405_s3>;
> +                       #power-domain-cells = <0>;
> +                       operating-points-v2 = <&cpr_opp_table>;
> +                       acc-syscon = <&tcsr>;
> +
> +                       nvmem-cells = <&cpr_efuse_quot_offset1>,
> +                               <&cpr_efuse_quot_offset2>,
> +                               <&cpr_efuse_quot_offset3>,
> +                               <&cpr_efuse_init_voltage1>,
> +                               <&cpr_efuse_init_voltage2>,
> +                               <&cpr_efuse_init_voltage3>,
> +                               <&cpr_efuse_quot1>,
> +                               <&cpr_efuse_quot2>,
> +                               <&cpr_efuse_quot3>,
> +                               <&cpr_efuse_ring1>,
> +                               <&cpr_efuse_ring2>,
> +                               <&cpr_efuse_ring3>,
> +                               <&cpr_efuse_revision>;
> +                       nvmem-cell-names = "cpr_quotient_offset1",
> +                               "cpr_quotient_offset2",
> +                               "cpr_quotient_offset3",
> +                               "cpr_init_voltage1",
> +                               "cpr_init_voltage2",
> +                               "cpr_init_voltage3",
> +                               "cpr_quotient1",
> +                               "cpr_quotient2",
> +                               "cpr_quotient3",
> +                               "cpr_ring_osc1",
> +                               "cpr_ring_osc2",
> +                               "cpr_ring_osc3",
> +                               "cpr_fuse_revision";
> +               };
> +
> +               timer@b120000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       compatible = "arm,armv7-timer-mem";
> +                       reg = <0x0b120000 0x1000>;
> +                       clock-frequency = <19200000>;
> +
> +                       frame@b121000 {
> +                               frame-number = <0>;
> +                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b121000 0x1000>,
> +                                     <0x0b122000 0x1000>;
> +                       };
> +
> +                       frame@b123000 {
> +                               frame-number = <1>;
> +                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b123000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b124000 {
> +                               frame-number = <2>;
> +                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b124000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b125000 {
> +                               frame-number = <3>;
> +                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b125000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b126000 {
> +                               frame-number = <4>;
> +                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b126000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b127000 {
> +                               frame-number = <5>;
> +                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0xb127000 0x1000>;
> +                               status = "disabled";
> +                       };
> +
> +                       frame@b128000 {
> +                               frame-number = <6>;
> +                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +                               reg = <0x0b128000 0x1000>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               remoteproc_adsp: remoteproc@c700000 {
> +                       compatible = "qcom,qcs404-adsp-pas";
> +                       reg = <0x0c700000 0x4040>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                             <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack";
> +
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +
> +                       memory-region = <&adsp_fw_mem>;
> +
> +                       qcom,smem-states = <&adsp_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       status = "disabled";
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
> +
> +                               qcom,remote-pid = <2>;
> +                               mboxes = <&apcs_glb 8>;
> +
> +                               label = "adsp";
> +                       };
> +               };
> +
> +               pcie: pci@10000000 {
> +                       compatible = "qcom,pcie-qcs404";
> +                       reg = <0x10000000 0xf1d>,
> +                             <0x10000f20 0xa8>,
> +                             <0x07780000 0x2000>,
> +                             <0x10001000 0x2000>;
> +                       reg-names = "dbi", "elbi", "parf", "config";
> +                       device_type = "pci";
> +                       linux,pci-domain = <0>;
> +                       bus-range = <0x00 0xff>;
> +                       num-lanes = <1>;
> +                       #address-cells = <3>;
> +                       #size-cells = <2>;
> +
> +                       ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
> +                                <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
> +
> +                       interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "msi";
> +                       #interrupt-cells = <1>;
> +                       interrupt-map-mask = <0 0 0 0x7>;
> +                       interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                                       <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                                       <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                                       <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +                       clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                                <&gcc GCC_PCIE_0_AUX_CLK>,
> +                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
> +                       clock-names = "iface", "aux", "master_bus", "slave_bus";
> +
> +                       resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
> +                                <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
> +                                <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
> +                                <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
> +                                <&gcc GCC_PCIE_0_BCR>,
> +                                <&gcc GCC_PCIE_0_AHB_ARES>;
> +                       reset-names = "axi_m",
> +                                     "axi_s",
> +                                     "axi_m_sticky",
> +                                     "pipe_sticky",
> +                                     "pwr",
> +                                     "ahb";
> +
> +                       phys = <&pcie_phy>;
> +                       phy-names = "pciephy";
> +
> +                       status = "disabled";
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 2 0xff08>,
> +                            <GIC_PPI 3 0xff08>,
> +                            <GIC_PPI 4 0xff08>,
> +                            <GIC_PPI 1 0xff08>;
> +       };
> +
> +       smp2p-adsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <443>, <429>;
> +               interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&apcs_glb 10>;
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <2>;
> +
> +               adsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               adsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-cdsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <94>, <432>;
> +               interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&apcs_glb 14>;
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <5>;
> +
> +               cdsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               cdsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-wcss {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <435>, <428>;
> +               interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&apcs_glb 18>;
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <1>;
> +
> +               wcss_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               wcss_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       thermal-zones {
> +               aoss-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 0>;
> +
> +                       trips {
> +                               aoss_alert0: trip-point0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               q6-hvx-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 1>;
> +
> +                       trips {
> +                               q6_hvx_alert0: trip-point0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               lpass-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 2>;
> +
> +                       trips {
> +                               lpass_alert0: trip-point0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               wlan-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 3>;
> +
> +                       trips {
> +                               wlan_alert0: trip-point0 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               cluster-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 4>;
> +
> +                       trips {
> +                               cluster_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cluster_alert1: trip-point1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cluster_crit: cluster-crit {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cluster_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 5>;
> +
> +                       trips {
> +                               cpu0_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu0_alert1: trip-point1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu0_crit: cpu-crit {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu0_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 6>;
> +
> +                       trips {
> +                               cpu1_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu1_alert1: trip-point1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu1_crit: cpu-crit {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu1_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 7>;
> +
> +                       trips {
> +                               cpu2_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu2_alert1: trip-point1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu2_crit: cpu-crit {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu2_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu3-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 8>;
> +
> +                       trips {
> +                               cpu3_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu3_alert1: trip-point1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu3_crit: cpu-crit {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu3_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                      <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               gpu-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens 9>;
> +
> +                       trips {
> +                               gpu_alert0: trip-point0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +       };
> +};
>
> --
> 2.43.1
>

Re: [PATCH v4 39/39] MAINTAINERS: Qualcomm: add some missing paths

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Add drivers and DTS files, as well as regex matches for
> qcom/qualcomm/snapdragon.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  MAINTAINERS | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 46ba17647f3e..8b048b1faf7c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -576,18 +576,22 @@ M:        Caleb Connolly <caleb.connolly@linaro.org>
>  M:     Neil Armstrong <neil.armstrong@linaro.org>
>  R:     Sumit Garg <sumit.garg@linaro.org>
>  S:     Maintained
> -F:     arch/arm/mach-snapdragon/
> -F:     drivers/button/button-qcom-pmic.c
> -F:     drivers/clk/qcom/
> +F:     arch/arm/dts/msm8*.dtsi
> +F:     arch/arm/dts/pm8???.dtsi
> +F:     arch/arm/dts/pms405.dtsi
> +F:     arch/arm/dts/sdm845.dtsi
> +F:     drivers/*/*/pm8???-*
>  F:     drivers/gpio/msm_gpio.c
>  F:     drivers/mmc/msm_sdhci.c
>  F:     drivers/phy/msm8916-usbh-phy.c
> -F:     drivers/pinctrl/qcom/
>  F:     drivers/serial/serial_msm.c
>  F:     drivers/serial/serial_msm_geni.c
>  F:     drivers/smem/msm_smem.c
>  F:     drivers/spmi/spmi-msm.c
>  F:     drivers/usb/host/ehci-msm.c
> +N:     qcom
> +N:     snapdragon
> +N:     qualcomm
>
>  ARM STI
>  M:     Patrice Chotard <patrice.chotard@foss.st.com>
>
> --
> 2.43.1
>

Re: [PATCH v4 37/39] dt-bindings: import headers for qcs404

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import the headers needed for QCS404-evb.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
> new file mode 100644
> index 000000000000..838faef57c67
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019, Linaro Ltd
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
> +#define _DT_BINDINGS_CLK_TURING_QCS404_H
> +
> +#define TURING_Q6SS_Q6_AXIM_CLK                0
> +#define TURING_Q6SS_AHBM_AON_CLK       1
> +#define TURING_WRAPPER_AON_CLK         2
> +#define TURING_Q6SS_AHBS_AON_CLK       3
> +#define TURING_WRAPPER_QOS_AHBS_AON_CLK        4
> +
> +#endif
>
> --
> 2.43.1
>

Re: [PATCH v4 35/39] dts: dragonboard820c: use correct bindings for clocks

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be
> compatible with upstream.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/dragonboard820c.dts | 5 +++--
>  drivers/clk/qcom/clock-apq8096.c | 5 +++--
>  2 files changed, 6 insertions(+), 4 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
> index 86b7f83d36d6..282c37e28f42 100644
> --- a/arch/arm/dts/dragonboard820c.dts
> +++ b/arch/arm/dts/dragonboard820c.dts
> @@ -8,6 +8,7 @@
>  /dts-v1/;
>
>  #include "skeleton64.dtsi"
> +#include <dt-bindings/clock/qcom,gcc-msm8996.h>
>
>  / {
>         model = "Qualcomm Technologies, Inc. DB820c";
> @@ -78,7 +79,7 @@
>                 blsp2_uart2: serial@75b0000 {
>                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>                         reg = <0x75b0000 0x1000>;
> -                       clocks = <&gcc 4>;
> +                       clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
>                         clock-names = "core";
>                         pinctrl-names = "uart";
>                         pinctrl-0 = <&blsp8_uart>;
> @@ -89,7 +90,7 @@
>                         reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
>                         index = <0x0>;
>                         bus-width = <4>;
> -                       clock = <&gcc 0>;
> +                       clock = <&gcc GCC_SDCC1_APPS_CLK>;
>                         clock-frequency = <200000000>;
>                  };
>
> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> index 1e6fdb5cd42d..a4731613c5e0 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -13,6 +13,7 @@
>  #include <errno.h>
>  #include <asm/io.h>
>  #include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8996.h>
>
>  #include "clock-qcom.h"
>
> @@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
>         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>
>         switch (clk->id) {
> -       case 0: /* SDC1 */
> +       case GCC_SDCC1_APPS_CLK: /* SDC1 */
>                 return clk_init_sdc(priv, rate);
>                 break;
> -       case 4: /*UART2*/
> +       case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
>                 return clk_init_uart(priv);
>         default:
>                 return 0;
>
> --
> 2.43.1
>

Re: [PATCH v4 34/39] dts: msm8996: import PMIC dtsi files

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:23, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import PM8994 and PMI8994 DTSI files in preparation for switching
> MSM8996 boards to upstream DTS.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/pm8994.dtsi  | 152 ++++++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/dts/pmi8994.dtsi |  65 ++++++++++++++++++++
>  2 files changed, 217 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi
> new file mode 100644
> index 000000000000..d44a95caf04a
> --- /dev/null
> +++ b/arch/arm/dts/pm8994.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +/ {
> +       thermal-zones {
> +               pm8994-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&pm8994_temp>;
> +
> +                       trips {
> +                               pm8994_alert0: pm8994-alert0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               pm8994_crit: pm8994-crit {
> +                                       temperature = <125000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&spmi_bus {
> +
> +       pmic@0 {
> +               compatible = "qcom,pm8994", "qcom,spmi-pmic";
> +               reg = <0x0 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               rtc@6000 {
> +                       compatible = "qcom,pm8941-rtc";
> +                       reg = <0x6000>, <0x6100>;
> +                       reg-names = "rtc", "alarm";
> +                       interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
> +               };
> +
> +               pm8994_pon: pon@800 {
> +                       compatible = "qcom,pm8916-pon";
> +                       reg = <0x800>;
> +                       mode-bootloader = <0x2>;
> +                       mode-recovery = <0x1>;
> +
> +                       pwrkey {
> +                               compatible = "qcom,pm8941-pwrkey";
> +                               interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               linux,code = <KEY_POWER>;
> +                       };
> +
> +                       pm8994_resin: resin {
> +                               compatible = "qcom,pm8941-resin";
> +                               interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               pm8994_temp: temp-alarm@2400 {
> +                       compatible = "qcom,spmi-temp-alarm";
> +                       reg = <0x2400>;
> +                       interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
> +                       io-channel-names = "thermal";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
> +               pm8994_vadc: adc@3100 {
> +                       compatible = "qcom,spmi-vadc";
> +                       reg = <0x3100>;
> +                       interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #io-channel-cells = <1>;
> +
> +                       channel@7 {
> +                               reg = <VADC_VSYS>;
> +                               qcom,pre-scaling = <1 3>;
> +                               label = "vph_pwr";
> +                       };
> +                       channel@8 {
> +                               reg = <VADC_DIE_TEMP>;
> +                               label = "die_temp";
> +                       };
> +                       channel@9 {
> +                               reg = <VADC_REF_625MV>;
> +                               label = "ref_625mv";
> +                       };
> +                       channel@a {
> +                               reg = <VADC_REF_1250MV>;
> +                               label = "ref_1250mv";
> +                       };
> +                       channel@e {
> +                               reg = <VADC_GND_REF>;
> +                       };
> +                       channel@f {
> +                               reg = <VADC_VDD_VADC>;
> +                       };
> +               };
> +
> +               pm8994_gpios: gpio@c000 {
> +                       compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pm8994_gpios 0 0 22>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               pm8994_mpps: mpps@a000 {
> +                       compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp";
> +                       reg = <0xa000>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       gpio-ranges = <&pm8994_mpps 0 0 8>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       pmic@1 {
> +               compatible = "qcom,pm8994", "qcom,spmi-pmic";
> +               reg = <0x1 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pm8994_lpg: pwm {
> +                       compatible = "qcom,pm8994-lpg";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #pwm-cells = <2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pm8994_spmi_regulators: regulators {
> +                       compatible = "qcom,pm8994-regulators";
> +               };
> +       };
> +};
> diff --git a/arch/arm/dts/pmi8994.dtsi b/arch/arm/dts/pmi8994.dtsi
> new file mode 100644
> index 000000000000..36d6a1fb553a
> --- /dev/null
> +++ b/arch/arm/dts/pmi8994.dtsi
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> +
> +       pmic@2 {
> +               compatible = "qcom,pmi8994", "qcom,spmi-pmic";
> +               reg = <0x2 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pmi8994_gpios: gpio@c000 {
> +                       compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pmi8994_gpios 0 0 10>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               pmi8994_mpps: mpps@a000 {
> +                       compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp";
> +                       reg = <0xa000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pmi8994_mpps 0 0 4>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       pmic@3 {
> +               compatible = "qcom,pmi8994", "qcom,spmi-pmic";
> +               reg = <0x3 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pmi8994_lpg: pwm {
> +                       compatible = "qcom,pmi8994-lpg";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #pwm-cells = <2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pmi8994_spmi_regulators: regulators {
> +                       compatible = "qcom,pmi8994-regulators";
> +               };
> +
> +               pmi8994_wled: wled@d800 {
> +                       compatible = "qcom,pmi8994-wled";
> +                       reg = <0xd800>, <0xd900>;
> +                       interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
> +                                    <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "ovp", "short";
> +                       qcom,cabc;
> +                       qcom,external-pfet;
> +                       status = "disabled";
> +               };
> +       };
> +};
>
> --
> 2.43.1
>

Re: [PATCH v4 33/39] dt-bindings: import headers for MSM8996

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import dt-binding headers for MSM8996/APQ8096 from Linux.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  include/dt-bindings/clock/qcom,gcc-msm8996.h       | 362 +++++++++++++++++++++
>  include/dt-bindings/clock/qcom,mmcc-msm8996.h      | 295 +++++++++++++++++
>  .../dt-bindings/interconnect/qcom,msm8996-cbf.h    |  12 +
>  include/dt-bindings/interconnect/qcom,msm8996.h    | 163 ++++++++++
>  include/dt-bindings/sound/qcom,wcd9335.h           |  15 +
>  5 files changed, 847 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
> new file mode 100644
> index 000000000000..ddfd6fd73081
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
> @@ -0,0 +1,362 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
> +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
> +
> +#define GPLL0_EARLY                                            0
> +#define GPLL0                                                  1
> +#define GPLL1_EARLY                                            2
> +#define GPLL1                                                  3
> +#define GPLL2_EARLY                                            4
> +#define GPLL2                                                  5
> +#define GPLL3_EARLY                                            6
> +#define GPLL3                                                  7
> +#define GPLL4_EARLY                                            8
> +#define GPLL4                                                  9
> +#define SYSTEM_NOC_CLK_SRC                                     10
> +/* U-Boot: KConfig check in CI erroneously picks this up, it's unused
> + * anyway so comment it out for now
> + */
> +//#define CONFIG _NOC_CLK_SRC                                  11
> +#define PERIPH_NOC_CLK_SRC                                     12
> +#define MMSS_BIMC_GFX_CLK_SRC                                  13
> +#define USB30_MASTER_CLK_SRC                                   14
> +#define USB30_MOCK_UTMI_CLK_SRC                                        15
> +#define USB3_PHY_AUX_CLK_SRC                                   16
> +#define USB20_MASTER_CLK_SRC                                   17
> +#define USB20_MOCK_UTMI_CLK_SRC                                        18
> +#define SDCC1_APPS_CLK_SRC                                     19
> +#define SDCC1_ICE_CORE_CLK_SRC                                 20
> +#define SDCC2_APPS_CLK_SRC                                     21
> +#define SDCC3_APPS_CLK_SRC                                     22
> +#define SDCC4_APPS_CLK_SRC                                     23
> +#define BLSP1_QUP1_SPI_APPS_CLK_SRC                            24
> +#define BLSP1_QUP1_I2C_APPS_CLK_SRC                            25
> +#define BLSP1_UART1_APPS_CLK_SRC                               26
> +#define BLSP1_QUP2_SPI_APPS_CLK_SRC                            27
> +#define BLSP1_QUP2_I2C_APPS_CLK_SRC                            28
> +#define BLSP1_UART2_APPS_CLK_SRC                               29
> +#define BLSP1_QUP3_SPI_APPS_CLK_SRC                            30
> +#define BLSP1_QUP3_I2C_APPS_CLK_SRC                            31
> +#define BLSP1_UART3_APPS_CLK_SRC                               32
> +#define BLSP1_QUP4_SPI_APPS_CLK_SRC                            33
> +#define BLSP1_QUP4_I2C_APPS_CLK_SRC                            34
> +#define BLSP1_UART4_APPS_CLK_SRC                               35
> +#define BLSP1_QUP5_SPI_APPS_CLK_SRC                            36
> +#define BLSP1_QUP5_I2C_APPS_CLK_SRC                            37
> +#define BLSP1_UART5_APPS_CLK_SRC                               38
> +#define BLSP1_QUP6_SPI_APPS_CLK_SRC                            39
> +#define BLSP1_QUP6_I2C_APPS_CLK_SRC                            40
> +#define BLSP1_UART6_APPS_CLK_SRC                               41
> +#define BLSP2_QUP1_SPI_APPS_CLK_SRC                            42
> +#define BLSP2_QUP1_I2C_APPS_CLK_SRC                            43
> +#define BLSP2_UART1_APPS_CLK_SRC                               44
> +#define BLSP2_QUP2_SPI_APPS_CLK_SRC                            45
> +#define BLSP2_QUP2_I2C_APPS_CLK_SRC                            46
> +#define BLSP2_UART2_APPS_CLK_SRC                               47
> +#define BLSP2_QUP3_SPI_APPS_CLK_SRC                            48
> +#define BLSP2_QUP3_I2C_APPS_CLK_SRC                            49
> +#define BLSP2_UART3_APPS_CLK_SRC                               50
> +#define BLSP2_QUP4_SPI_APPS_CLK_SRC                            51
> +#define BLSP2_QUP4_I2C_APPS_CLK_SRC                            52
> +#define BLSP2_UART4_APPS_CLK_SRC                               53
> +#define BLSP2_QUP5_SPI_APPS_CLK_SRC                            54
> +#define BLSP2_QUP5_I2C_APPS_CLK_SRC                            55
> +#define BLSP2_UART5_APPS_CLK_SRC                               56
> +#define BLSP2_QUP6_SPI_APPS_CLK_SRC                            57
> +#define BLSP2_QUP6_I2C_APPS_CLK_SRC                            58
> +#define BLSP2_UART6_APPS_CLK_SRC                               59
> +#define PDM2_CLK_SRC                                           60
> +#define TSIF_REF_CLK_SRC                                       61
> +#define CE1_CLK_SRC                                            62
> +#define GCC_SLEEP_CLK_SRC                                      63
> +#define BIMC_CLK_SRC                                           64
> +#define HMSS_AHB_CLK_SRC                                       65
> +#define BIMC_HMSS_AXI_CLK_SRC                                  66
> +#define HMSS_RBCPR_CLK_SRC                                     67
> +#define HMSS_GPLL0_CLK_SRC                                     68
> +#define GP1_CLK_SRC                                            69
> +#define GP2_CLK_SRC                                            70
> +#define GP3_CLK_SRC                                            71
> +#define PCIE_AUX_CLK_SRC                                       72
> +#define UFS_AXI_CLK_SRC                                                73
> +#define UFS_ICE_CORE_CLK_SRC                                   74
> +#define QSPI_SER_CLK_SRC                                       75
> +#define GCC_SYS_NOC_AXI_CLK                                    76
> +#define GCC_SYS_NOC_HMSS_AHB_CLK                               77
> +#define GCC_SNOC_CNOC_AHB_CLK                                  78
> +#define GCC_SNOC_PNOC_AHB_CLK                                  79
> +#define GCC_SYS_NOC_AT_CLK                                     80
> +#define GCC_SYS_NOC_USB3_AXI_CLK                               81
> +#define GCC_SYS_NOC_UFS_AXI_CLK                                        82
> +#define GCC_CFG_NOC_AHB_CLK                                    83
> +#define GCC_PERIPH_NOC_AHB_CLK                                 84
> +#define GCC_PERIPH_NOC_USB20_AHB_CLK                           85
> +#define GCC_TIC_CLK                                            86
> +#define GCC_IMEM_AXI_CLK                                       87
> +#define GCC_MMSS_SYS_NOC_AXI_CLK                               88
> +#define GCC_MMSS_NOC_CFG_AHB_CLK                               89
> +#define GCC_MMSS_BIMC_GFX_CLK                                  90
> +#define GCC_USB30_MASTER_CLK                                   91
> +#define GCC_USB30_SLEEP_CLK                                    92
> +#define GCC_USB30_MOCK_UTMI_CLK                                        93
> +#define GCC_USB3_PHY_AUX_CLK                                   94
> +#define GCC_USB3_PHY_PIPE_CLK                                  95
> +#define GCC_USB20_MASTER_CLK                                   96
> +#define GCC_USB20_SLEEP_CLK                                    97
> +#define GCC_USB20_MOCK_UTMI_CLK                                        98
> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK                            99
> +#define GCC_SDCC1_APPS_CLK                                     100
> +#define GCC_SDCC1_AHB_CLK                                      101
> +#define GCC_SDCC1_ICE_CORE_CLK                                 102
> +#define GCC_SDCC2_APPS_CLK                                     103
> +#define GCC_SDCC2_AHB_CLK                                      104
> +#define GCC_SDCC3_APPS_CLK                                     105
> +#define GCC_SDCC3_AHB_CLK                                      106
> +#define GCC_SDCC4_APPS_CLK                                     107
> +#define GCC_SDCC4_AHB_CLK                                      108
> +#define GCC_BLSP1_AHB_CLK                                      109
> +#define GCC_BLSP1_SLEEP_CLK                                    110
> +#define GCC_BLSP1_QUP1_SPI_APPS_CLK                            111
> +#define GCC_BLSP1_QUP1_I2C_APPS_CLK                            112
> +#define GCC_BLSP1_UART1_APPS_CLK                               113
> +#define GCC_BLSP1_QUP2_SPI_APPS_CLK                            114
> +#define GCC_BLSP1_QUP2_I2C_APPS_CLK                            115
> +#define GCC_BLSP1_UART2_APPS_CLK                               116
> +#define GCC_BLSP1_QUP3_SPI_APPS_CLK                            117
> +#define GCC_BLSP1_QUP3_I2C_APPS_CLK                            118
> +#define GCC_BLSP1_UART3_APPS_CLK                               119
> +#define GCC_BLSP1_QUP4_SPI_APPS_CLK                            120
> +#define GCC_BLSP1_QUP4_I2C_APPS_CLK                            121
> +#define GCC_BLSP1_UART4_APPS_CLK                               122
> +#define GCC_BLSP1_QUP5_SPI_APPS_CLK                            123
> +#define GCC_BLSP1_QUP5_I2C_APPS_CLK                            124
> +#define GCC_BLSP1_UART5_APPS_CLK                               125
> +#define GCC_BLSP1_QUP6_SPI_APPS_CLK                            126
> +#define GCC_BLSP1_QUP6_I2C_APPS_CLK                            127
> +#define GCC_BLSP1_UART6_APPS_CLK                               128
> +#define GCC_BLSP2_AHB_CLK                                      129
> +#define GCC_BLSP2_SLEEP_CLK                                    130
> +#define GCC_BLSP2_QUP1_SPI_APPS_CLK                            131
> +#define GCC_BLSP2_QUP1_I2C_APPS_CLK                            132
> +#define GCC_BLSP2_UART1_APPS_CLK                               133
> +#define GCC_BLSP2_QUP2_SPI_APPS_CLK                            134
> +#define GCC_BLSP2_QUP2_I2C_APPS_CLK                            135
> +#define GCC_BLSP2_UART2_APPS_CLK                               136
> +#define GCC_BLSP2_QUP3_SPI_APPS_CLK                            137
> +#define GCC_BLSP2_QUP3_I2C_APPS_CLK                            138
> +#define GCC_BLSP2_UART3_APPS_CLK                               139
> +#define GCC_BLSP2_QUP4_SPI_APPS_CLK                            140
> +#define GCC_BLSP2_QUP4_I2C_APPS_CLK                            141
> +#define GCC_BLSP2_UART4_APPS_CLK                               142
> +#define GCC_BLSP2_QUP5_SPI_APPS_CLK                            143
> +#define GCC_BLSP2_QUP5_I2C_APPS_CLK                            144
> +#define GCC_BLSP2_UART5_APPS_CLK                               145
> +#define GCC_BLSP2_QUP6_SPI_APPS_CLK                            146
> +#define GCC_BLSP2_QUP6_I2C_APPS_CLK                            147
> +#define GCC_BLSP2_UART6_APPS_CLK                               148
> +#define GCC_PDM_AHB_CLK                                                149
> +#define GCC_PDM_XO4_CLK                                                150
> +#define GCC_PDM2_CLK                                           151
> +#define GCC_PRNG_AHB_CLK                                       152
> +#define GCC_TSIF_AHB_CLK                                       153
> +#define GCC_TSIF_REF_CLK                                       154
> +#define GCC_TSIF_INACTIVITY_TIMERS_CLK                         155
> +#define GCC_TCSR_AHB_CLK                                       156
> +#define GCC_BOOT_ROM_AHB_CLK                                   157
> +#define GCC_MSG_RAM_AHB_CLK                                    158
> +#define GCC_TLMM_AHB_CLK                                       159
> +#define GCC_TLMM_CLK                                           160
> +#define GCC_MPM_AHB_CLK                                                161
> +#define GCC_SPMI_SER_CLK                                       162
> +#define GCC_SPMI_CNOC_AHB_CLK                                  163
> +#define GCC_CE1_CLK                                            164
> +#define GCC_CE1_AXI_CLK                                                165
> +#define GCC_CE1_AHB_CLK                                                166
> +#define GCC_BIMC_HMSS_AXI_CLK                                  167
> +#define GCC_BIMC_GFX_CLK                                       168
> +#define GCC_HMSS_AHB_CLK                                       169
> +#define GCC_HMSS_SLV_AXI_CLK                                   170
> +#define GCC_HMSS_MSTR_AXI_CLK                                  171
> +#define GCC_HMSS_RBCPR_CLK                                     172
> +#define GCC_GP1_CLK                                            173
> +#define GCC_GP2_CLK                                            174
> +#define GCC_GP3_CLK                                            175
> +#define GCC_PCIE_0_SLV_AXI_CLK                                 176
> +#define GCC_PCIE_0_MSTR_AXI_CLK                                        177
> +#define GCC_PCIE_0_CFG_AHB_CLK                                 178
> +#define GCC_PCIE_0_AUX_CLK                                     179
> +#define GCC_PCIE_0_PIPE_CLK                                    180
> +#define GCC_PCIE_1_SLV_AXI_CLK                                 181
> +#define GCC_PCIE_1_MSTR_AXI_CLK                                        182
> +#define GCC_PCIE_1_CFG_AHB_CLK                                 183
> +#define GCC_PCIE_1_AUX_CLK                                     184
> +#define GCC_PCIE_1_PIPE_CLK                                    185
> +#define GCC_PCIE_2_SLV_AXI_CLK                                 186
> +#define GCC_PCIE_2_MSTR_AXI_CLK                                        187
> +#define GCC_PCIE_2_CFG_AHB_CLK                                 188
> +#define GCC_PCIE_2_AUX_CLK                                     189
> +#define GCC_PCIE_2_PIPE_CLK                                    190
> +#define GCC_PCIE_PHY_CFG_AHB_CLK                               191
> +#define GCC_PCIE_PHY_AUX_CLK                                   192
> +#define GCC_UFS_AXI_CLK                                                193
> +#define GCC_UFS_AHB_CLK                                                194
> +#define GCC_UFS_TX_CFG_CLK                                     195
> +#define GCC_UFS_RX_CFG_CLK                                     196
> +#define GCC_UFS_TX_SYMBOL_0_CLK                                        197
> +#define GCC_UFS_RX_SYMBOL_0_CLK                                        198
> +#define GCC_UFS_RX_SYMBOL_1_CLK                                        199
> +#define GCC_UFS_UNIPRO_CORE_CLK                                        200
> +#define GCC_UFS_ICE_CORE_CLK                                   201
> +#define GCC_UFS_SYS_CLK_CORE_CLK                               202
> +#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK                         203
> +#define GCC_AGGRE0_SNOC_AXI_CLK                                        204
> +#define GCC_AGGRE0_CNOC_AHB_CLK                                        205
> +#define GCC_SMMU_AGGRE0_AXI_CLK                                        206
> +#define GCC_SMMU_AGGRE0_AHB_CLK                                        207
> +#define GCC_AGGRE1_PNOC_AHB_CLK                                        208
> +#define GCC_AGGRE2_UFS_AXI_CLK                                 209
> +#define GCC_AGGRE2_USB3_AXI_CLK                                        210
> +#define GCC_QSPI_AHB_CLK                                       211
> +#define GCC_QSPI_SER_CLK                                       212
> +#define GCC_USB3_CLKREF_CLK                                    213
> +#define GCC_HDMI_CLKREF_CLK                                    214
> +#define GCC_UFS_CLKREF_CLK                                     215
> +#define GCC_PCIE_CLKREF_CLK                                    216
> +#define GCC_RX2_USB2_CLKREF_CLK                                        217
> +#define GCC_RX1_USB2_CLKREF_CLK                                        218
> +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK                     219
> +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK                     220
> +#define GCC_EDP_CLKREF_CLK                                     221
> +#define GCC_MSS_CFG_AHB_CLK                                    222
> +#define GCC_MSS_Q6_BIMC_AXI_CLK                                        223
> +#define GCC_MSS_SNOC_AXI_CLK                                   224
> +#define GCC_MSS_MNOC_BIMC_AXI_CLK                              225
> +#define GCC_DCC_AHB_CLK                                                226
> +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK                         227
> +#define GCC_MMSS_GPLL0_DIV_CLK                                 228
> +#define GCC_MSS_GPLL0_DIV_CLK                                  229
> +
> +#define GCC_SYSTEM_NOC_BCR                                     0
> +#define GCC_CONFIG_NOC_BCR                                     1
> +#define GCC_PERIPH_NOC_BCR                                     2
> +#define GCC_IMEM_BCR                                           3
> +#define GCC_MMSS_BCR                                           4
> +#define GCC_PIMEM_BCR                                          5
> +#define GCC_QDSS_BCR                                           6
> +#define GCC_USB_30_BCR                                         7
> +#define GCC_USB_20_BCR                                         8
> +#define GCC_QUSB2PHY_PRIM_BCR                                  9
> +#define GCC_QUSB2PHY_SEC_BCR                                   10
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR                            11
> +#define GCC_SDCC1_BCR                                          12
> +#define GCC_SDCC2_BCR                                          13
> +#define GCC_SDCC3_BCR                                          14
> +#define GCC_SDCC4_BCR                                          15
> +#define GCC_BLSP1_BCR                                          16
> +#define GCC_BLSP1_QUP1_BCR                                     17
> +#define GCC_BLSP1_UART1_BCR                                    18
> +#define GCC_BLSP1_QUP2_BCR                                     19
> +#define GCC_BLSP1_UART2_BCR                                    20
> +#define GCC_BLSP1_QUP3_BCR                                     21
> +#define GCC_BLSP1_UART3_BCR                                    22
> +#define GCC_BLSP1_QUP4_BCR                                     23
> +#define GCC_BLSP1_UART4_BCR                                    24
> +#define GCC_BLSP1_QUP5_BCR                                     25
> +#define GCC_BLSP1_UART5_BCR                                    26
> +#define GCC_BLSP1_QUP6_BCR                                     27
> +#define GCC_BLSP1_UART6_BCR                                    28
> +#define GCC_BLSP2_BCR                                          29
> +#define GCC_BLSP2_QUP1_BCR                                     30
> +#define GCC_BLSP2_UART1_BCR                                    31
> +#define GCC_BLSP2_QUP2_BCR                                     32
> +#define GCC_BLSP2_UART2_BCR                                    33
> +#define GCC_BLSP2_QUP3_BCR                                     34
> +#define GCC_BLSP2_UART3_BCR                                    35
> +#define GCC_BLSP2_QUP4_BCR                                     36
> +#define GCC_BLSP2_UART4_BCR                                    37
> +#define GCC_BLSP2_QUP5_BCR                                     38
> +#define GCC_BLSP2_UART5_BCR                                    39
> +#define GCC_BLSP2_QUP6_BCR                                     40
> +#define GCC_BLSP2_UART6_BCR                                    41
> +#define GCC_PDM_BCR                                            42
> +#define GCC_PRNG_BCR                                           43
> +#define GCC_TSIF_BCR                                           44
> +#define GCC_TCSR_BCR                                           45
> +#define GCC_BOOT_ROM_BCR                                       46
> +#define GCC_MSG_RAM_BCR                                                47
> +#define GCC_TLMM_BCR                                           48
> +#define GCC_MPM_BCR                                            49
> +#define GCC_SEC_CTRL_BCR                                       50
> +#define GCC_SPMI_BCR                                           51
> +#define GCC_SPDM_BCR                                           52
> +#define GCC_CE1_BCR                                            53
> +#define GCC_BIMC_BCR                                           54
> +#define GCC_SNOC_BUS_TIMEOUT0_BCR                              55
> +#define GCC_SNOC_BUS_TIMEOUT2_BCR                              56
> +#define GCC_SNOC_BUS_TIMEOUT1_BCR                              57
> +#define GCC_SNOC_BUS_TIMEOUT3_BCR                              58
> +#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR                                59
> +#define GCC_PNOC_BUS_TIMEOUT0_BCR                              60
> +#define GCC_PNOC_BUS_TIMEOUT1_BCR                              61
> +#define GCC_PNOC_BUS_TIMEOUT2_BCR                              62
> +#define GCC_PNOC_BUS_TIMEOUT3_BCR                              63
> +#define GCC_PNOC_BUS_TIMEOUT4_BCR                              64
> +#define GCC_CNOC_BUS_TIMEOUT0_BCR                              65
> +#define GCC_CNOC_BUS_TIMEOUT1_BCR                              66
> +#define GCC_CNOC_BUS_TIMEOUT2_BCR                              67
> +#define GCC_CNOC_BUS_TIMEOUT3_BCR                              68
> +#define GCC_CNOC_BUS_TIMEOUT4_BCR                              69
> +#define GCC_CNOC_BUS_TIMEOUT5_BCR                              70
> +#define GCC_CNOC_BUS_TIMEOUT6_BCR                              71
> +#define GCC_CNOC_BUS_TIMEOUT7_BCR                              72
> +#define GCC_CNOC_BUS_TIMEOUT8_BCR                              73
> +#define GCC_CNOC_BUS_TIMEOUT9_BCR                              74
> +#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR                                75
> +#define GCC_APB2JTAG_BCR                                       76
> +#define GCC_RBCPR_CX_BCR                                       77
> +#define GCC_RBCPR_MX_BCR                                       78
> +#define GCC_PCIE_0_BCR                                         79
> +#define GCC_PCIE_0_PHY_BCR                                     80
> +#define GCC_PCIE_1_BCR                                         81
> +#define GCC_PCIE_1_PHY_BCR                                     82
> +#define GCC_PCIE_2_BCR                                         83
> +#define GCC_PCIE_2_PHY_BCR                                     84
> +#define GCC_PCIE_PHY_BCR                                       85
> +#define GCC_DCD_BCR                                            86
> +#define GCC_OBT_ODT_BCR                                                87
> +#define GCC_UFS_BCR                                            88
> +#define GCC_SSC_BCR                                            89
> +#define GCC_VS_BCR                                             90
> +#define GCC_AGGRE0_NOC_BCR                                     91
> +#define GCC_AGGRE1_NOC_BCR                                     92
> +#define GCC_AGGRE2_NOC_BCR                                     93
> +#define GCC_DCC_BCR                                            94
> +#define GCC_IPA_BCR                                            95
> +#define GCC_QSPI_BCR                                           96
> +#define GCC_SKL_BCR                                            97
> +#define GCC_MSMPU_BCR                                          98
> +#define GCC_MSS_Q6_BCR                                         99
> +#define GCC_QREFS_VBG_CAL_BCR                                  100
> +#define GCC_PCIE_PHY_COM_BCR                                   101
> +#define GCC_PCIE_PHY_COM_NOCSR_BCR                             102
> +#define GCC_USB3_PHY_BCR                                       103
> +#define GCC_USB3PHY_PHY_BCR                                    104
> +#define GCC_MSS_RESTART                                                105
> +
> +
> +/* Indexes for GDSCs */
> +#define AGGRE0_NOC_GDSC                        0
> +#define HLOS1_VOTE_AGGRE0_NOC_GDSC     1
> +#define HLOS1_VOTE_LPASS_ADSP_GDSC     2
> +#define HLOS1_VOTE_LPASS_CORE_GDSC     3
> +#define USB30_GDSC                     4
> +#define PCIE0_GDSC                     5
> +#define PCIE1_GDSC                     6
> +#define PCIE2_GDSC                     7
> +#define UFS_GDSC                       8
> +
> +#endif
> diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
> new file mode 100644
> index 000000000000..d51f9ac70566
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
> @@ -0,0 +1,295 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
> +#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
> +
> +#define MMPLL0_EARLY                                   0
> +#define MMPLL0_PLL                                     1
> +#define MMPLL1_EARLY                                   2
> +#define MMPLL1_PLL                                     3
> +#define MMPLL2_EARLY                                   4
> +#define MMPLL2_PLL                                     5
> +#define MMPLL3_EARLY                                   6
> +#define MMPLL3_PLL                                     7
> +#define MMPLL4_EARLY                                   8
> +#define MMPLL4_PLL                                     9
> +#define MMPLL5_EARLY                                   10
> +#define MMPLL5_PLL                                     11
> +#define MMPLL8_EARLY                                   12
> +#define MMPLL8_PLL                                     13
> +#define MMPLL9_EARLY                                   14
> +#define MMPLL9_PLL                                     15
> +#define AHB_CLK_SRC                                    16
> +#define AXI_CLK_SRC                                    17
> +#define MAXI_CLK_SRC                                   18
> +#define DSA_CORE_CLK_SRC                               19
> +#define GFX3D_CLK_SRC                                  20
> +#define RBBMTIMER_CLK_SRC                              21
> +#define ISENSE_CLK_SRC                                 22
> +#define RBCPR_CLK_SRC                                  23
> +#define VIDEO_CORE_CLK_SRC                             24
> +#define VIDEO_SUBCORE0_CLK_SRC                         25
> +#define VIDEO_SUBCORE1_CLK_SRC                         26
> +#define PCLK0_CLK_SRC                                  27
> +#define PCLK1_CLK_SRC                                  28
> +#define MDP_CLK_SRC                                    29
> +#define EXTPCLK_CLK_SRC                                        30
> +#define VSYNC_CLK_SRC                                  31
> +#define HDMI_CLK_SRC                                   32
> +#define BYTE0_CLK_SRC                                  33
> +#define BYTE1_CLK_SRC                                  34
> +#define ESC0_CLK_SRC                                   35
> +#define ESC1_CLK_SRC                                   36
> +#define CAMSS_GP0_CLK_SRC                              37
> +#define CAMSS_GP1_CLK_SRC                              38
> +#define MCLK0_CLK_SRC                                  39
> +#define MCLK1_CLK_SRC                                  40
> +#define MCLK2_CLK_SRC                                  41
> +#define MCLK3_CLK_SRC                                  42
> +#define CCI_CLK_SRC                                    43
> +#define CSI0PHYTIMER_CLK_SRC                           44
> +#define CSI1PHYTIMER_CLK_SRC                           45
> +#define CSI2PHYTIMER_CLK_SRC                           46
> +#define CSIPHY0_3P_CLK_SRC                             47
> +#define CSIPHY1_3P_CLK_SRC                             48
> +#define CSIPHY2_3P_CLK_SRC                             49
> +#define JPEG0_CLK_SRC                                  50
> +#define JPEG2_CLK_SRC                                  51
> +#define JPEG_DMA_CLK_SRC                               52
> +#define VFE0_CLK_SRC                                   53
> +#define VFE1_CLK_SRC                                   54
> +#define CPP_CLK_SRC                                    55
> +#define CSI0_CLK_SRC                                   56
> +#define CSI1_CLK_SRC                                   57
> +#define CSI2_CLK_SRC                                   58
> +#define CSI3_CLK_SRC                                   59
> +#define FD_CORE_CLK_SRC                                        60
> +#define MMSS_CXO_CLK                                   61
> +#define MMSS_SLEEPCLK_CLK                              62
> +#define MMSS_MMAGIC_AHB_CLK                            63
> +#define MMSS_MMAGIC_CFG_AHB_CLK                                64
> +#define MMSS_MISC_AHB_CLK                              65
> +#define MMSS_MISC_CXO_CLK                              66
> +#define MMSS_BTO_AHB_CLK                               67
> +#define MMSS_MMAGIC_AXI_CLK                            68
> +#define MMSS_S0_AXI_CLK                                        69
> +#define MMSS_MMAGIC_MAXI_CLK                           70
> +#define DSA_CORE_CLK                                   71
> +#define DSA_NOC_CFG_AHB_CLK                            72
> +#define MMAGIC_CAMSS_AXI_CLK                           73
> +#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK                   74
> +#define THROTTLE_CAMSS_CXO_CLK                         75
> +#define THROTTLE_CAMSS_AHB_CLK                         76
> +#define THROTTLE_CAMSS_AXI_CLK                         77
> +#define SMMU_VFE_AHB_CLK                               78
> +#define SMMU_VFE_AXI_CLK                               79
> +#define SMMU_CPP_AHB_CLK                               80
> +#define SMMU_CPP_AXI_CLK                               81
> +#define SMMU_JPEG_AHB_CLK                              82
> +#define SMMU_JPEG_AXI_CLK                              83
> +#define MMAGIC_MDSS_AXI_CLK                            84
> +#define MMAGIC_MDSS_NOC_CFG_AHB_CLK                    85
> +#define THROTTLE_MDSS_CXO_CLK                          86
> +#define THROTTLE_MDSS_AHB_CLK                          87
> +#define THROTTLE_MDSS_AXI_CLK                          88
> +#define SMMU_ROT_AHB_CLK                               89
> +#define SMMU_ROT_AXI_CLK                               90
> +#define SMMU_MDP_AHB_CLK                               91
> +#define SMMU_MDP_AXI_CLK                               92
> +#define MMAGIC_VIDEO_AXI_CLK                           93
> +#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK                   94
> +#define THROTTLE_VIDEO_CXO_CLK                         95
> +#define THROTTLE_VIDEO_AHB_CLK                         96
> +#define THROTTLE_VIDEO_AXI_CLK                         97
> +#define SMMU_VIDEO_AHB_CLK                             98
> +#define SMMU_VIDEO_AXI_CLK                             99
> +#define MMAGIC_BIMC_AXI_CLK                            100
> +#define MMAGIC_BIMC_NOC_CFG_AHB_CLK                    101
> +#define GPU_GX_GFX3D_CLK                               102
> +#define GPU_GX_RBBMTIMER_CLK                           103
> +#define GPU_AHB_CLK                                    104
> +#define GPU_AON_ISENSE_CLK                             105
> +#define VMEM_MAXI_CLK                                  106
> +#define VMEM_AHB_CLK                                   107
> +#define MMSS_RBCPR_CLK                                 108
> +#define MMSS_RBCPR_AHB_CLK                             109
> +#define VIDEO_CORE_CLK                                 110
> +#define VIDEO_AXI_CLK                                  111
> +#define VIDEO_MAXI_CLK                                 112
> +#define VIDEO_AHB_CLK                                  113
> +#define VIDEO_SUBCORE0_CLK                             114
> +#define VIDEO_SUBCORE1_CLK                             115
> +#define MDSS_AHB_CLK                                   116
> +#define MDSS_HDMI_AHB_CLK                              117
> +#define MDSS_AXI_CLK                                   118
> +#define MDSS_PCLK0_CLK                                 119
> +#define MDSS_PCLK1_CLK                                 120
> +#define MDSS_MDP_CLK                                   121
> +#define MDSS_EXTPCLK_CLK                               122
> +#define MDSS_VSYNC_CLK                                 123
> +#define MDSS_HDMI_CLK                                  124
> +#define MDSS_BYTE0_CLK                                 125
> +#define MDSS_BYTE1_CLK                                 126
> +#define MDSS_ESC0_CLK                                  127
> +#define MDSS_ESC1_CLK                                  128
> +#define CAMSS_TOP_AHB_CLK                              129
> +#define CAMSS_AHB_CLK                                  130
> +#define CAMSS_MICRO_AHB_CLK                            131
> +#define CAMSS_GP0_CLK                                  132
> +#define CAMSS_GP1_CLK                                  133
> +#define CAMSS_MCLK0_CLK                                        134
> +#define CAMSS_MCLK1_CLK                                        135
> +#define CAMSS_MCLK2_CLK                                        136
> +#define CAMSS_MCLK3_CLK                                        137
> +#define CAMSS_CCI_CLK                                  138
> +#define CAMSS_CCI_AHB_CLK                              139
> +#define CAMSS_CSI0PHYTIMER_CLK                         140
> +#define CAMSS_CSI1PHYTIMER_CLK                         141
> +#define CAMSS_CSI2PHYTIMER_CLK                         142
> +#define CAMSS_CSIPHY0_3P_CLK                           143
> +#define CAMSS_CSIPHY1_3P_CLK                           144
> +#define CAMSS_CSIPHY2_3P_CLK                           145
> +#define CAMSS_JPEG0_CLK                                        146
> +#define CAMSS_JPEG2_CLK                                        147
> +#define CAMSS_JPEG_DMA_CLK                             148
> +#define CAMSS_JPEG_AHB_CLK                             149
> +#define CAMSS_JPEG_AXI_CLK                             150
> +#define CAMSS_VFE_AHB_CLK                              151
> +#define CAMSS_VFE_AXI_CLK                              152
> +#define CAMSS_VFE0_CLK                                 153
> +#define CAMSS_VFE0_STREAM_CLK                          154
> +#define CAMSS_VFE0_AHB_CLK                             155
> +#define CAMSS_VFE1_CLK                                 156
> +#define CAMSS_VFE1_STREAM_CLK                          157
> +#define CAMSS_VFE1_AHB_CLK                             158
> +#define CAMSS_CSI_VFE0_CLK                             159
> +#define CAMSS_CSI_VFE1_CLK                             160
> +#define CAMSS_CPP_VBIF_AHB_CLK                         161
> +#define CAMSS_CPP_AXI_CLK                              162
> +#define CAMSS_CPP_CLK                                  163
> +#define CAMSS_CPP_AHB_CLK                              164
> +#define CAMSS_CSI0_CLK                                 165
> +#define CAMSS_CSI0_AHB_CLK                             166
> +#define CAMSS_CSI0PHY_CLK                              167
> +#define CAMSS_CSI0RDI_CLK                              168
> +#define CAMSS_CSI0PIX_CLK                              169
> +#define CAMSS_CSI1_CLK                                 170
> +#define CAMSS_CSI1_AHB_CLK                             171
> +#define CAMSS_CSI1PHY_CLK                              172
> +#define CAMSS_CSI1RDI_CLK                              173
> +#define CAMSS_CSI1PIX_CLK                              174
> +#define CAMSS_CSI2_CLK                                 175
> +#define CAMSS_CSI2_AHB_CLK                             176
> +#define CAMSS_CSI2PHY_CLK                              177
> +#define CAMSS_CSI2RDI_CLK                              178
> +#define CAMSS_CSI2PIX_CLK                              179
> +#define CAMSS_CSI3_CLK                                 180
> +#define CAMSS_CSI3_AHB_CLK                             181
> +#define CAMSS_CSI3PHY_CLK                              182
> +#define CAMSS_CSI3RDI_CLK                              183
> +#define CAMSS_CSI3PIX_CLK                              184
> +#define CAMSS_ISPIF_AHB_CLK                            185
> +#define FD_CORE_CLK                                    186
> +#define FD_CORE_UAR_CLK                                        187
> +#define FD_AHB_CLK                                     188
> +#define MMSS_SPDM_CSI0_CLK                             189
> +#define MMSS_SPDM_JPEG_DMA_CLK                         190
> +#define MMSS_SPDM_CPP_CLK                              191
> +#define MMSS_SPDM_PCLK0_CLK                            192
> +#define MMSS_SPDM_AHB_CLK                              193
> +#define MMSS_SPDM_GFX3D_CLK                            194
> +#define MMSS_SPDM_PCLK1_CLK                            195
> +#define MMSS_SPDM_JPEG2_CLK                            196
> +#define MMSS_SPDM_DEBUG_CLK                            197
> +#define MMSS_SPDM_VFE1_CLK                             198
> +#define MMSS_SPDM_VFE0_CLK                             199
> +#define MMSS_SPDM_VIDEO_CORE_CLK                       200
> +#define MMSS_SPDM_AXI_CLK                              201
> +#define MMSS_SPDM_MDP_CLK                              202
> +#define MMSS_SPDM_JPEG0_CLK                            203
> +#define MMSS_SPDM_RM_AXI_CLK                           204
> +#define MMSS_SPDM_RM_MAXI_CLK                          205
> +
> +#define MMAGICAHB_BCR                                  0
> +#define MMAGIC_CFG_BCR                                 1
> +#define MISC_BCR                                       2
> +#define BTO_BCR                                                3
> +#define MMAGICAXI_BCR                                  4
> +#define MMAGICMAXI_BCR                                 5
> +#define DSA_BCR                                                6
> +#define MMAGIC_CAMSS_BCR                               7
> +#define THROTTLE_CAMSS_BCR                             8
> +#define SMMU_VFE_BCR                                   9
> +#define SMMU_CPP_BCR                                   10
> +#define SMMU_JPEG_BCR                                  11
> +#define MMAGIC_MDSS_BCR                                        12
> +#define THROTTLE_MDSS_BCR                              13
> +#define SMMU_ROT_BCR                                   14
> +#define SMMU_MDP_BCR                                   15
> +#define MMAGIC_VIDEO_BCR                               16
> +#define THROTTLE_VIDEO_BCR                             17
> +#define SMMU_VIDEO_BCR                                 18
> +#define MMAGIC_BIMC_BCR                                        19
> +#define GPU_GX_BCR                                     20
> +#define GPU_BCR                                                21
> +#define GPU_AON_BCR                                    22
> +#define VMEM_BCR                                       23
> +#define MMSS_RBCPR_BCR                                 24
> +#define VIDEO_BCR                                      25
> +#define MDSS_BCR                                       26
> +#define CAMSS_TOP_BCR                                  27
> +#define CAMSS_AHB_BCR                                  28
> +#define CAMSS_MICRO_BCR                                        29
> +#define CAMSS_CCI_BCR                                  30
> +#define CAMSS_PHY0_BCR                                 31
> +#define CAMSS_PHY1_BCR                                 32
> +#define CAMSS_PHY2_BCR                                 33
> +#define CAMSS_CSIPHY0_3P_BCR                           34
> +#define CAMSS_CSIPHY1_3P_BCR                           35
> +#define CAMSS_CSIPHY2_3P_BCR                           36
> +#define CAMSS_JPEG_BCR                                 37
> +#define CAMSS_VFE_BCR                                  38
> +#define CAMSS_VFE0_BCR                                 39
> +#define CAMSS_VFE1_BCR                                 40
> +#define CAMSS_CSI_VFE0_BCR                             41
> +#define CAMSS_CSI_VFE1_BCR                             42
> +#define CAMSS_CPP_TOP_BCR                              43
> +#define CAMSS_CPP_BCR                                  44
> +#define CAMSS_CSI0_BCR                                 45
> +#define CAMSS_CSI0RDI_BCR                              46
> +#define CAMSS_CSI0PIX_BCR                              47
> +#define CAMSS_CSI1_BCR                                 48
> +#define CAMSS_CSI1RDI_BCR                              49
> +#define CAMSS_CSI1PIX_BCR                              50
> +#define CAMSS_CSI2_BCR                                 51
> +#define CAMSS_CSI2RDI_BCR                              52
> +#define CAMSS_CSI2PIX_BCR                              53
> +#define CAMSS_CSI3_BCR                                 54
> +#define CAMSS_CSI3RDI_BCR                              55
> +#define CAMSS_CSI3PIX_BCR                              56
> +#define CAMSS_ISPIF_BCR                                        57
> +#define FD_BCR                                         58
> +#define MMSS_SPDM_RM_BCR                               59
> +
> +/* Indexes for GDSCs */
> +#define MMAGIC_VIDEO_GDSC      0
> +#define MMAGIC_MDSS_GDSC       1
> +#define MMAGIC_CAMSS_GDSC      2
> +#define GPU_GDSC               3
> +#define VENUS_GDSC             4
> +#define VENUS_CORE0_GDSC       5
> +#define VENUS_CORE1_GDSC       6
> +#define CAMSS_GDSC             7
> +#define VFE0_GDSC              8
> +#define VFE1_GDSC              9
> +#define JPEG_GDSC              10
> +#define CPP_GDSC               11
> +#define FD_GDSC                        12
> +#define MDSS_GDSC              13
> +#define GPU_GX_GDSC            14
> +#define MMAGIC_BIMC_GDSC       15
> +
> +#endif
> diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
> new file mode 100644
> index 000000000000..aac5e69f6bd5
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
> +
> +#define MASTER_CBF_M4M         0
> +#define SLAVE_CBF_M4M          1
> +
> +#endif
> diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h
> new file mode 100644
> index 000000000000..a0b7c0ec7bed
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,msm8996.h
> @@ -0,0 +1,163 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
> +/*
> + * Qualcomm MSM8996 interconnect IDs
> + *
> + * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
> +
> +/* A0NOC */
> +#define MASTER_PCIE_0                  0
> +#define MASTER_PCIE_1                  1
> +#define MASTER_PCIE_2                  2
> +
> +/* A1NOC */
> +#define MASTER_CNOC_A1NOC              0
> +#define MASTER_CRYPTO_CORE0            1
> +#define MASTER_PNOC_A1NOC              2
> +
> +/* A2NOC */
> +#define MASTER_USB3                    0
> +#define MASTER_IPA                     1
> +#define MASTER_UFS                     2
> +
> +/* BIMC */
> +#define MASTER_AMPSS_M0                        0
> +#define MASTER_GRAPHICS_3D             1
> +#define MASTER_MNOC_BIMC               2
> +#define MASTER_SNOC_BIMC               3
> +#define SLAVE_EBI_CH0                  4
> +#define SLAVE_HMSS_L3                  5
> +#define SLAVE_BIMC_SNOC_0              6
> +#define SLAVE_BIMC_SNOC_1              7
> +
> +/* CNOC */
> +#define MASTER_SNOC_CNOC               0
> +#define MASTER_QDSS_DAP                        1
> +#define SLAVE_CNOC_A1NOC               2
> +#define SLAVE_CLK_CTL                  3
> +#define SLAVE_TCSR                     4
> +#define SLAVE_TLMM                     5
> +#define SLAVE_CRYPTO_0_CFG             6
> +#define SLAVE_MPM                      7
> +#define SLAVE_PIMEM_CFG                        8
> +#define SLAVE_IMEM_CFG                 9
> +#define SLAVE_MESSAGE_RAM              10
> +#define SLAVE_BIMC_CFG                 11
> +#define SLAVE_PMIC_ARB                 12
> +#define SLAVE_PRNG                     13
> +#define SLAVE_DCC_CFG                  14
> +#define SLAVE_RBCPR_MX                 15
> +#define SLAVE_QDSS_CFG                 16
> +#define SLAVE_RBCPR_CX                 17
> +#define SLAVE_QDSS_RBCPR_APU           18
> +#define SLAVE_CNOC_MNOC_CFG            19
> +#define SLAVE_SNOC_CFG                 20
> +#define SLAVE_SNOC_MPU_CFG             21
> +#define SLAVE_EBI1_PHY_CFG             22
> +#define SLAVE_A0NOC_CFG                        23
> +#define SLAVE_PCIE_1_CFG               24
> +#define SLAVE_PCIE_2_CFG               25
> +#define SLAVE_PCIE_0_CFG               26
> +#define SLAVE_PCIE20_AHB2PHY           27
> +#define SLAVE_A0NOC_MPU_CFG            28
> +#define SLAVE_UFS_CFG                  29
> +#define SLAVE_A1NOC_CFG                        30
> +#define SLAVE_A1NOC_MPU_CFG            31
> +#define SLAVE_A2NOC_CFG                        32
> +#define SLAVE_A2NOC_MPU_CFG            33
> +#define SLAVE_SSC_CFG                  34
> +#define SLAVE_A0NOC_SMMU_CFG           35
> +#define SLAVE_A1NOC_SMMU_CFG           36
> +#define SLAVE_A2NOC_SMMU_CFG           37
> +#define SLAVE_LPASS_SMMU_CFG           38
> +#define SLAVE_CNOC_MNOC_MMSS_CFG       39
> +
> +/* MNOC */
> +#define MASTER_CNOC_MNOC_CFG           0
> +#define MASTER_CPP                     1
> +#define MASTER_JPEG                    2
> +#define MASTER_MDP_PORT0               3
> +#define MASTER_MDP_PORT1               4
> +#define MASTER_ROTATOR                 5
> +#define MASTER_VIDEO_P0                        6
> +#define MASTER_VFE                     7
> +#define MASTER_SNOC_VMEM               8
> +#define MASTER_VIDEO_P0_OCMEM          9
> +#define MASTER_CNOC_MNOC_MMSS_CFG      10
> +#define SLAVE_MNOC_BIMC                        11
> +#define SLAVE_VMEM                     12
> +#define SLAVE_SERVICE_MNOC             13
> +#define SLAVE_MMAGIC_CFG               14
> +#define SLAVE_CPR_CFG                  15
> +#define SLAVE_MISC_CFG                 16
> +#define SLAVE_VENUS_THROTTLE_CFG       17
> +#define SLAVE_VENUS_CFG                        18
> +#define SLAVE_VMEM_CFG                 19
> +#define SLAVE_DSA_CFG                  20
> +#define SLAVE_MMSS_CLK_CFG             21
> +#define SLAVE_DSA_MPU_CFG              22
> +#define SLAVE_MNOC_MPU_CFG             23
> +#define SLAVE_DISPLAY_CFG              24
> +#define SLAVE_DISPLAY_THROTTLE_CFG     25
> +#define SLAVE_CAMERA_CFG               26
> +#define SLAVE_CAMERA_THROTTLE_CFG      27
> +#define SLAVE_GRAPHICS_3D_CFG          28
> +#define SLAVE_SMMU_MDP_CFG             29
> +#define SLAVE_SMMU_ROT_CFG             30
> +#define SLAVE_SMMU_VENUS_CFG           31
> +#define SLAVE_SMMU_CPP_CFG             32
> +#define SLAVE_SMMU_JPEG_CFG            33
> +#define SLAVE_SMMU_VFE_CFG             34
> +
> +/* PNOC */
> +#define MASTER_SNOC_PNOC               0
> +#define MASTER_SDCC_1                  1
> +#define MASTER_SDCC_2                  2
> +#define MASTER_SDCC_4                  3
> +#define MASTER_USB_HS                  4
> +#define MASTER_BLSP_1                  5
> +#define MASTER_BLSP_2                  6
> +#define MASTER_TSIF                    7
> +#define SLAVE_PNOC_A1NOC               8
> +#define SLAVE_USB_HS                   9
> +#define SLAVE_SDCC_2                   10
> +#define SLAVE_SDCC_4                   11
> +#define SLAVE_TSIF                     12
> +#define SLAVE_BLSP_2                   13
> +#define SLAVE_SDCC_1                   14
> +#define SLAVE_BLSP_1                   15
> +#define SLAVE_PDM                      16
> +#define SLAVE_AHB2PHY                  17
> +
> +/* SNOC */
> +#define MASTER_HMSS                    0
> +#define MASTER_QDSS_BAM                        1
> +#define MASTER_SNOC_CFG                        2
> +#define MASTER_BIMC_SNOC_0             3
> +#define MASTER_BIMC_SNOC_1             4
> +#define MASTER_A0NOC_SNOC              5
> +#define MASTER_A1NOC_SNOC              6
> +#define MASTER_A2NOC_SNOC              7
> +#define MASTER_QDSS_ETR                        8
> +#define SLAVE_A0NOC_SNOC               9
> +#define SLAVE_A1NOC_SNOC               10
> +#define SLAVE_A2NOC_SNOC               11
> +#define SLAVE_HMSS                     12
> +#define SLAVE_LPASS                    13
> +#define SLAVE_USB3                     14
> +#define SLAVE_SNOC_BIMC                        15
> +#define SLAVE_SNOC_CNOC                        16
> +#define SLAVE_IMEM                     17
> +#define SLAVE_PIMEM                    18
> +#define SLAVE_SNOC_VMEM                        19
> +#define SLAVE_SNOC_PNOC                        20
> +#define SLAVE_QDSS_STM                 21
> +#define SLAVE_PCIE_0                   22
> +#define SLAVE_PCIE_1                   23
> +#define SLAVE_PCIE_2                   24
> +#define SLAVE_SERVICE_SNOC             25
> +
> +#endif
> diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h
> new file mode 100644
> index 000000000000..f5e9f1db091e
> --- /dev/null
> +++ b/include/dt-bindings/sound/qcom,wcd9335.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +
> +#ifndef __DT_SOUND_QCOM_WCD9335_H
> +#define __DT_SOUND_QCOM_WCD9335_H
> +
> +#define AIF1_PB                 0
> +#define AIF1_CAP                1
> +#define AIF2_PB                 2
> +#define AIF2_CAP                3
> +#define AIF3_PB                 4
> +#define AIF3_CAP                5
> +#define AIF4_PB                 6
> +#define NUM_CODEC_DAIS          7
> +
> +#endif
>
> --
> 2.43.1
>

Re: [PATCH v4 31/39] dts: msm8916: import PMIC dtsi files

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import the supporting pm8916.dtsi and msm8916-pm8916.dtsi files from
> upstream in preparation for switching boards over.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  arch/arm/dts/msm8916-pm8916.dtsi | 157 ++++++++++++++++++++++++++++++++++
>  arch/arm/dts/pm8916.dtsi         | 178 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 335 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi
> new file mode 100644
> index 000000000000..b1a7eafbee31
> --- /dev/null
> +++ b/arch/arm/dts/msm8916-pm8916.dtsi
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
> + * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
> + * Many regulators have a fixed purpose in the original reference design and
> + * were rarely re-used for different purposes. Devices that deviate from the
> + * typical reference design should not make use of this include and instead add
> + * the necessary properties in the board-specific device tree.
> + */
> +
> +#include "msm8916.dtsi"
> +#include "pm8916.dtsi"
> +
> +&camss {
> +       vdda-supply = <&pm8916_l2>;
> +};
> +
> +&mdss_dsi0 {
> +       vdda-supply = <&pm8916_l2>;
> +       vddio-supply = <&pm8916_l6>;
> +};
> +
> +&mdss_dsi0_phy {
> +       vddio-supply = <&pm8916_l6>;
> +};
> +
> +&mpss {
> +       pll-supply = <&pm8916_l7>;
> +};
> +
> +&pm8916_codec {
> +       vdd-cdc-io-supply = <&pm8916_l5>;
> +       vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
> +       vdd-micbias-supply = <&pm8916_l13>;
> +};
> +
> +&sdhc_1 {
> +       vmmc-supply = <&pm8916_l8>;
> +       vqmmc-supply = <&pm8916_l5>;
> +};
> +
> +&sdhc_2 {
> +       vmmc-supply = <&pm8916_l11>;
> +       vqmmc-supply = <&pm8916_l12>;
> +};
> +
> +&usb_hs_phy {
> +       v1p8-supply = <&pm8916_l7>;
> +       v3p3-supply = <&pm8916_l13>;
> +};
> +
> +&wcnss {
> +       vddpx-supply = <&pm8916_l7>;
> +};
> +
> +&wcnss_iris {
> +       vddxo-supply = <&pm8916_l7>;
> +       vddrfa-supply = <&pm8916_s3>;
> +       vddpa-supply = <&pm8916_l9>;
> +       vdddig-supply = <&pm8916_l5>;
> +};
> +
> +&rpm_requests {
> +       pm8916_rpm_regulators: regulators {
> +               compatible = "qcom,rpm-pm8916-regulators";
> +               vdd_l1_l2_l3-supply = <&pm8916_s3>;
> +               vdd_l4_l5_l6-supply = <&pm8916_s4>;
> +               vdd_l7-supply = <&pm8916_s4>;
> +
> +               /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
> +
> +               pm8916_s3: s3 {
> +                       regulator-min-microvolt = <1250000>;
> +                       regulator-max-microvolt = <1350000>;
> +                       regulator-always-on; /* Needed for L2 */
> +               };
> +
> +               pm8916_s4: s4 {
> +                       regulator-min-microvolt = <1850000>;
> +                       regulator-max-microvolt = <2150000>;
> +                       regulator-always-on; /* Needed for L5/L7 */
> +               };
> +
> +               /*
> +                * Some of the regulators are unused or managed by another
> +                * processor (e.g. the modem). We should still define nodes for
> +                * them to ensure the vote from the application processor can be
> +                * dropped in case the regulators are already on during boot.
> +                *
> +                * The labels for these nodes are omitted on purpose because
> +                * boards should configure a proper voltage before using them.
> +                */
> +               l1 {};
> +
> +               pm8916_l2: l2 {
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <1200000>;
> +                       regulator-always-on; /* Needed for LPDDR RAM */
> +               };
> +
> +               /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
> +
> +               l4 {};
> +
> +               pm8916_l5: l5 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on; /* Needed for most digital I/O */
> +               };
> +
> +               pm8916_l6: l6 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +               };
> +
> +               pm8916_l7: l7 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <1800000>;
> +                       regulator-always-on; /* Needed for CPU PLL */
> +               };
> +
> +               pm8916_l8: l8 {
> +                       regulator-min-microvolt = <2900000>;
> +                       regulator-max-microvolt = <2900000>;
> +               };
> +
> +               pm8916_l9: l9 {
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3300000>;
> +               };
> +
> +               l10 {};
> +
> +               pm8916_l11: l11 {
> +                       regulator-min-microvolt = <2950000>;
> +                       regulator-max-microvolt = <2950000>;
> +                       regulator-allow-set-load;
> +                       regulator-system-load = <200000>;
> +               };
> +
> +               pm8916_l12: l12 {
> +                       regulator-min-microvolt = <1800000>;
> +                       regulator-max-microvolt = <2950000>;
> +               };
> +
> +               pm8916_l13: l13 {
> +                       regulator-min-microvolt = <3075000>;
> +                       regulator-max-microvolt = <3075000>;
> +               };
> +
> +               l14 {};
> +               l15 {};
> +               l16 {};
> +               l17 {};
> +               l18 {};
> +       };
> +};
> diff --git a/arch/arm/dts/pm8916.dtsi b/arch/arm/dts/pm8916.dtsi
> new file mode 100644
> index 000000000000..f4de86787743
> --- /dev/null
> +++ b/arch/arm/dts/pm8916.dtsi
> @@ -0,0 +1,178 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> +
> +       pm8916_0: pmic@0 {
> +               compatible = "qcom,pm8916", "qcom,spmi-pmic";
> +               reg = <0x0 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pon@800 {
> +                       compatible = "qcom,pm8916-pon";
> +                       reg = <0x800>;
> +                       mode-bootloader = <0x2>;
> +                       mode-recovery = <0x1>;
> +
> +                       pwrkey {
> +                               compatible = "qcom,pm8941-pwrkey";
> +                               interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               linux,code = <KEY_POWER>;
> +                       };
> +
> +                       pm8916_resin: resin {
> +                               compatible = "qcom,pm8941-resin";
> +                               interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               status = "disabled";
> +                       };
> +
> +                       watchdog {
> +                               compatible = "qcom,pm8916-wdt";
> +                               interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
> +                               timeout-sec = <60>;
> +                       };
> +               };
> +
> +               pm8916_usbin: usb-detect@1300 {
> +                       compatible = "qcom,pm8941-misc";
> +                       reg = <0x1300>;
> +                       interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
> +                       interrupt-names = "usb_vbus";
> +                       status = "disabled";
> +               };
> +
> +               pm8916_temp: temp-alarm@2400 {
> +                       compatible = "qcom,spmi-temp-alarm";
> +                       reg = <0x2400>;
> +                       interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
> +                       io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
> +                       io-channel-names = "thermal";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
> +               pm8916_vadc: adc@3100 {
> +                       compatible = "qcom,spmi-vadc";
> +                       reg = <0x3100>;
> +                       interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #io-channel-cells = <1>;
> +
> +                       channel@0 {
> +                               reg = <VADC_USBIN>;
> +                               qcom,pre-scaling = <1 10>;
> +                       };
> +                       channel@7 {
> +                               reg = <VADC_VSYS>;
> +                               qcom,pre-scaling = <1 3>;
> +                       };
> +                       channel@8 {
> +                               reg = <VADC_DIE_TEMP>;
> +                       };
> +                       channel@9 {
> +                               reg = <VADC_REF_625MV>;
> +                       };
> +                       channel@a {
> +                               reg = <VADC_REF_1250MV>;
> +                       };
> +                       channel@e {
> +                               reg = <VADC_GND_REF>;
> +                       };
> +                       channel@f {
> +                               reg = <VADC_VDD_VADC>;
> +                       };
> +               };
> +
> +               rtc@6000 {
> +                       compatible = "qcom,pm8941-rtc";
> +                       reg = <0x6000>, <0x6100>;
> +                       reg-names = "rtc", "alarm";
> +                       interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
> +               };
> +
> +               pm8916_mpps: mpps@a000 {
> +                       compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp";
> +                       reg = <0xa000>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       gpio-ranges = <&pm8916_mpps 0 0 4>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               pm8916_gpios: gpio@c000 {
> +                       compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000>;
> +                       gpio-controller;
> +                       gpio-ranges = <&pm8916_gpios 0 0 4>;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       pm8916_1: pmic@1 {
> +               compatible = "qcom,pm8916", "qcom,spmi-pmic";
> +               reg = <0x1 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pm8916_pwm: pwm {
> +                       compatible = "qcom,pm8916-pwm";
> +
> +                       #pwm-cells = <2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               pm8916_vib: vibrator@c000 {
> +                       compatible = "qcom,pm8916-vib";
> +                       reg = <0xc000>;
> +                       status = "disabled";
> +               };
> +
> +               pm8916_codec: audio-codec@f000 {
> +                       compatible = "qcom,pm8916-wcd-analog-codec";
> +                       reg = <0xf000>;
> +                       interrupt-parent = <&spmi_bus>;
> +                       interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
> +                                    <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
> +                       interrupt-names = "cdc_spk_cnp_int",
> +                                         "cdc_spk_clip_int",
> +                                         "cdc_spk_ocp_int",
> +                                         "mbhc_ins_rem_det1",
> +                                         "mbhc_but_rel_det",
> +                                         "mbhc_but_press_det",
> +                                         "mbhc_ins_rem_det",
> +                                         "mbhc_switch_int",
> +                                         "cdc_ear_ocp_int",
> +                                         "cdc_hphr_ocp_int",
> +                                         "cdc_hphl_ocp_det",
> +                                         "cdc_ear_cnp_int",
> +                                         "cdc_hphr_cnp_int",
> +                                         "cdc_hphl_cnp_int";
> +                       #sound-dai-cells = <1>;
> +                       status = "disabled";
> +               };
> +       };
> +};
>
> --
> 2.43.1
>

Re: [PATCH v4 30/39] dt-bindings: import headers for MSM8916

[Sumit Garg]

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Import the dt-bindings headers in preparation for switching to upstream
> DTS for MSM8916.
>
> Taken from kernel tag v6.7
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  include/dt-bindings/arm/coresight-cti-dt.h      |  37 +++++
>  include/dt-bindings/clock/qcom,rpmcc.h          | 174 ++++++++++++++++++++++++
>  include/dt-bindings/interconnect/qcom,msm8916.h | 100 ++++++++++++++
>  include/dt-bindings/pinctrl/qcom,pmic-mpp.h     | 106 +++++++++++++++
>  include/dt-bindings/reset/qcom,gcc-msm8916.h    | 100 ++++++++++++++
>  include/dt-bindings/sound/apq8016-lpass.h       |   9 ++
>  include/dt-bindings/sound/qcom,lpass.h          |  46 +++++++
>  7 files changed, 572 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>


-Sumit

> diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h
> new file mode 100644
> index 000000000000..61e7bdf8ea6e
> --- /dev/null
> +++ b/include/dt-bindings/arm/coresight-cti-dt.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for the defined trigger signal
> + * types on CoreSight CTI.
> + */
> +
> +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
> +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
> +
> +#define GEN_IO         0
> +#define GEN_INTREQ     1
> +#define GEN_INTACK     2
> +#define GEN_HALTREQ    3
> +#define GEN_RESTARTREQ 4
> +#define PE_EDBGREQ     5
> +#define PE_DBGRESTART  6
> +#define PE_CTIIRQ      7
> +#define PE_PMUIRQ      8
> +#define PE_DBGTRIGGER  9
> +#define ETM_EXTOUT     10
> +#define ETM_EXTIN      11
> +#define SNK_FULL       12
> +#define SNK_ACQCOMP    13
> +#define SNK_FLUSHCOMP  14
> +#define SNK_FLUSHIN    15
> +#define SNK_TRIGIN     16
> +#define STM_ASYNCOUT   17
> +#define STM_TOUT_SPTE  18
> +#define STM_TOUT_SW    19
> +#define STM_TOUT_HETE  20
> +#define STM_HWEVENT    21
> +#define ELA_TSTART     22
> +#define ELA_TSTOP      23
> +#define ELA_DBGREQ     24
> +#define CTI_TRIG_MAX   25
> +
> +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */
> diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
> new file mode 100644
> index 000000000000..46309c9953b2
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,rpmcc.h
> @@ -0,0 +1,174 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2015 Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
> +#define _DT_BINDINGS_CLK_MSM_RPMCC_H
> +
> +/* RPM clocks */
> +#define RPM_PXO_CLK                            0
> +#define RPM_PXO_A_CLK                          1
> +#define RPM_CXO_CLK                            2
> +#define RPM_CXO_A_CLK                          3
> +#define RPM_APPS_FABRIC_CLK                    4
> +#define RPM_APPS_FABRIC_A_CLK                  5
> +#define RPM_CFPB_CLK                           6
> +#define RPM_CFPB_A_CLK                         7
> +#define RPM_QDSS_CLK                           8
> +#define RPM_QDSS_A_CLK                         9
> +#define RPM_DAYTONA_FABRIC_CLK                 10
> +#define RPM_DAYTONA_FABRIC_A_CLK               11
> +#define RPM_EBI1_CLK                           12
> +#define RPM_EBI1_A_CLK                         13
> +#define RPM_MM_FABRIC_CLK                      14
> +#define RPM_MM_FABRIC_A_CLK                    15
> +#define RPM_MMFPB_CLK                          16
> +#define RPM_MMFPB_A_CLK                                17
> +#define RPM_SYS_FABRIC_CLK                     18
> +#define RPM_SYS_FABRIC_A_CLK                   19
> +#define RPM_SFPB_CLK                           20
> +#define RPM_SFPB_A_CLK                         21
> +#define RPM_SMI_CLK                            22
> +#define RPM_SMI_A_CLK                          23
> +#define RPM_PLL4_CLK                           24
> +#define RPM_XO_D0                              25
> +#define RPM_XO_D1                              26
> +#define RPM_XO_A0                              27
> +#define RPM_XO_A1                              28
> +#define RPM_XO_A2                              29
> +#define RPM_NSS_FABRIC_0_CLK                   30
> +#define RPM_NSS_FABRIC_0_A_CLK                 31
> +#define RPM_NSS_FABRIC_1_CLK                   32
> +#define RPM_NSS_FABRIC_1_A_CLK                 33
> +
> +/* SMD RPM clocks */
> +#define RPM_SMD_XO_CLK_SRC                             0
> +#define RPM_SMD_XO_A_CLK_SRC                   1
> +#define RPM_SMD_PCNOC_CLK                              2
> +#define RPM_SMD_PCNOC_A_CLK                            3
> +#define RPM_SMD_SNOC_CLK                               4
> +#define RPM_SMD_SNOC_A_CLK                             5
> +#define RPM_SMD_BIMC_CLK                               6
> +#define RPM_SMD_BIMC_A_CLK                             7
> +#define RPM_SMD_QDSS_CLK                               8
> +#define RPM_SMD_QDSS_A_CLK                             9
> +#define RPM_SMD_BB_CLK1                                10
> +#define RPM_SMD_BB_CLK1_A                              11
> +#define RPM_SMD_BB_CLK2                                12
> +#define RPM_SMD_BB_CLK2_A                              13
> +#define RPM_SMD_RF_CLK1                                14
> +#define RPM_SMD_RF_CLK1_A                              15
> +#define RPM_SMD_RF_CLK2                                16
> +#define RPM_SMD_RF_CLK2_A                              17
> +#define RPM_SMD_BB_CLK1_PIN                            18
> +#define RPM_SMD_BB_CLK1_A_PIN                  19
> +#define RPM_SMD_BB_CLK2_PIN                            20
> +#define RPM_SMD_BB_CLK2_A_PIN                  21
> +#define RPM_SMD_RF_CLK1_PIN                            22
> +#define RPM_SMD_RF_CLK1_A_PIN                  23
> +#define RPM_SMD_RF_CLK2_PIN                            24
> +#define RPM_SMD_RF_CLK2_A_PIN                  25
> +#define RPM_SMD_PNOC_CLK                       26
> +#define RPM_SMD_PNOC_A_CLK                     27
> +#define RPM_SMD_CNOC_CLK                       28
> +#define RPM_SMD_CNOC_A_CLK                     29
> +#define RPM_SMD_MMSSNOC_AHB_CLK                        30
> +#define RPM_SMD_MMSSNOC_AHB_A_CLK              31
> +#define RPM_SMD_GFX3D_CLK_SRC                  32
> +#define RPM_SMD_GFX3D_A_CLK_SRC                        33
> +#define RPM_SMD_OCMEMGX_CLK                    34
> +#define RPM_SMD_OCMEMGX_A_CLK                  35
> +#define RPM_SMD_CXO_D0                         36
> +#define RPM_SMD_CXO_D0_A                       37
> +#define RPM_SMD_CXO_D1                         38
> +#define RPM_SMD_CXO_D1_A                       39
> +#define RPM_SMD_CXO_A0                         40
> +#define RPM_SMD_CXO_A0_A                       41
> +#define RPM_SMD_CXO_A1                         42
> +#define RPM_SMD_CXO_A1_A                       43
> +#define RPM_SMD_CXO_A2                         44
> +#define RPM_SMD_CXO_A2_A                       45
> +#define RPM_SMD_DIV_CLK1                       46
> +#define RPM_SMD_DIV_A_CLK1                     47
> +#define RPM_SMD_DIV_CLK2                       48
> +#define RPM_SMD_DIV_A_CLK2                     49
> +#define RPM_SMD_DIFF_CLK                       50
> +#define RPM_SMD_DIFF_A_CLK                     51
> +#define RPM_SMD_CXO_D0_PIN                     52
> +#define RPM_SMD_CXO_D0_A_PIN                   53
> +#define RPM_SMD_CXO_D1_PIN                     54
> +#define RPM_SMD_CXO_D1_A_PIN                   55
> +#define RPM_SMD_CXO_A0_PIN                     56
> +#define RPM_SMD_CXO_A0_A_PIN                   57
> +#define RPM_SMD_CXO_A1_PIN                     58
> +#define RPM_SMD_CXO_A1_A_PIN                   59
> +#define RPM_SMD_CXO_A2_PIN                     60
> +#define RPM_SMD_CXO_A2_A_PIN                   61
> +#define RPM_SMD_AGGR1_NOC_CLK                  62
> +#define RPM_SMD_AGGR1_NOC_A_CLK                        63
> +#define RPM_SMD_AGGR2_NOC_CLK                  64
> +#define RPM_SMD_AGGR2_NOC_A_CLK                        65
> +#define RPM_SMD_MMAXI_CLK                      66
> +#define RPM_SMD_MMAXI_A_CLK                    67
> +#define RPM_SMD_IPA_CLK                                68
> +#define RPM_SMD_IPA_A_CLK                      69
> +#define RPM_SMD_CE1_CLK                                70
> +#define RPM_SMD_CE1_A_CLK                      71
> +#define RPM_SMD_DIV_CLK3                       72
> +#define RPM_SMD_DIV_A_CLK3                     73
> +#define RPM_SMD_LN_BB_CLK                      74
> +#define RPM_SMD_LN_BB_A_CLK                    75
> +#define RPM_SMD_BIMC_GPU_CLK                   76
> +#define RPM_SMD_BIMC_GPU_A_CLK                 77
> +#define RPM_SMD_QPIC_CLK                       78
> +#define RPM_SMD_QPIC_CLK_A                     79
> +#define RPM_SMD_LN_BB_CLK1                     80
> +#define RPM_SMD_LN_BB_CLK1_A                   81
> +#define RPM_SMD_LN_BB_CLK2                     82
> +#define RPM_SMD_LN_BB_CLK2_A                   83
> +#define RPM_SMD_LN_BB_CLK3_PIN                 84
> +#define RPM_SMD_LN_BB_CLK3_A_PIN               85
> +#define RPM_SMD_RF_CLK3                                86
> +#define RPM_SMD_RF_CLK3_A                      87
> +#define RPM_SMD_RF_CLK3_PIN                    88
> +#define RPM_SMD_RF_CLK3_A_PIN                  89
> +#define RPM_SMD_MMSSNOC_AXI_CLK                        90
> +#define RPM_SMD_MMSSNOC_AXI_CLK_A              91
> +#define RPM_SMD_CNOC_PERIPH_CLK                        92
> +#define RPM_SMD_CNOC_PERIPH_A_CLK              93
> +#define RPM_SMD_LN_BB_CLK3                     94
> +#define RPM_SMD_LN_BB_CLK3_A                   95
> +#define RPM_SMD_LN_BB_CLK1_PIN                 96
> +#define RPM_SMD_LN_BB_CLK1_A_PIN               97
> +#define RPM_SMD_LN_BB_CLK2_PIN                 98
> +#define RPM_SMD_LN_BB_CLK2_A_PIN               99
> +#define RPM_SMD_SYSMMNOC_CLK                   100
> +#define RPM_SMD_SYSMMNOC_A_CLK                 101
> +#define RPM_SMD_CE2_CLK                                102
> +#define RPM_SMD_CE2_A_CLK                      103
> +#define RPM_SMD_CE3_CLK                                104
> +#define RPM_SMD_CE3_A_CLK                      105
> +#define RPM_SMD_QUP_CLK                                106
> +#define RPM_SMD_QUP_A_CLK                      107
> +#define RPM_SMD_MMRT_CLK                       108
> +#define RPM_SMD_MMRT_A_CLK                     109
> +#define RPM_SMD_MMNRT_CLK                      110
> +#define RPM_SMD_MMNRT_A_CLK                    111
> +#define RPM_SMD_SNOC_PERIPH_CLK                        112
> +#define RPM_SMD_SNOC_PERIPH_A_CLK              113
> +#define RPM_SMD_SNOC_LPASS_CLK                 114
> +#define RPM_SMD_SNOC_LPASS_A_CLK               115
> +#define RPM_SMD_HWKM_CLK                       116
> +#define RPM_SMD_HWKM_A_CLK                     117
> +#define RPM_SMD_PKA_CLK                                118
> +#define RPM_SMD_PKA_A_CLK                      119
> +#define RPM_SMD_CPUSS_GNOC_CLK                 120
> +#define RPM_SMD_CPUSS_GNOC_A_CLK               121
> +#define RPM_SMD_MSS_CFG_AHB_CLK                122
> +#define RPM_SMD_MSS_CFG_AHB_A_CLK              123
> +#define RPM_SMD_BIMC_FREQ_LOG                  124
> +#define RPM_SMD_LN_BB_CLK_PIN                  125
> +#define RPM_SMD_LN_BB_A_CLK_PIN                        126
> +
> +#endif
> diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h
> new file mode 100644
> index 000000000000..359a75feb198
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,msm8916.h
> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Qualcomm interconnect IDs
> + *
> + * Copyright (c) 2019, Linaro Ltd.
> + * Author: Georgi Djakov <georgi.djakov@linaro.org>
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
> +
> +#define BIMC_SNOC_SLV                  0
> +#define MASTER_JPEG                    1
> +#define MASTER_MDP_PORT0               2
> +#define MASTER_QDSS_BAM                        3
> +#define MASTER_QDSS_ETR                        4
> +#define MASTER_SNOC_CFG                        5
> +#define MASTER_VFE                     6
> +#define MASTER_VIDEO_P0                        7
> +#define SNOC_MM_INT_0                  8
> +#define SNOC_MM_INT_1                  9
> +#define SNOC_MM_INT_2                  10
> +#define SNOC_MM_INT_BIMC               11
> +#define PCNOC_SNOC_SLV                 12
> +#define SLAVE_APSS                     13
> +#define SLAVE_CATS_128                 14
> +#define SLAVE_OCMEM_64                 15
> +#define SLAVE_IMEM                     16
> +#define SLAVE_QDSS_STM                 17
> +#define SLAVE_SRVC_SNOC                        18
> +#define SNOC_BIMC_0_MAS                        19
> +#define SNOC_BIMC_1_MAS                        20
> +#define SNOC_INT_0                     21
> +#define SNOC_INT_1                     22
> +#define SNOC_INT_BIMC                  23
> +#define SNOC_PCNOC_MAS                 24
> +#define SNOC_QDSS_INT                  25
> +
> +#define BIMC_SNOC_MAS                  0
> +#define MASTER_AMPSS_M0                        1
> +#define MASTER_GRAPHICS_3D             2
> +#define MASTER_TCU0                    3
> +#define MASTER_TCU1                    4
> +#define SLAVE_AMPSS_L2                 5
> +#define SLAVE_EBI_CH0                  6
> +#define SNOC_BIMC_0_SLV                        7
> +#define SNOC_BIMC_1_SLV                        8
> +
> +#define MASTER_BLSP_1                  0
> +#define MASTER_DEHR                    1
> +#define MASTER_LPASS                   2
> +#define MASTER_CRYPTO_CORE0            3
> +#define MASTER_SDCC_1                  4
> +#define MASTER_SDCC_2                  5
> +#define MASTER_SPDM                    6
> +#define MASTER_USB_HS                  7
> +#define PCNOC_INT_0                    8
> +#define PCNOC_INT_1                    9
> +#define PCNOC_MAS_0                    10
> +#define PCNOC_MAS_1                    11
> +#define PCNOC_SLV_0                    12
> +#define PCNOC_SLV_1                    13
> +#define PCNOC_SLV_2                    14
> +#define PCNOC_SLV_3                    15
> +#define PCNOC_SLV_4                    16
> +#define PCNOC_SLV_8                    17
> +#define PCNOC_SLV_9                    18
> +#define PCNOC_SNOC_MAS                 19
> +#define SLAVE_BIMC_CFG                 20
> +#define SLAVE_BLSP_1                   21
> +#define SLAVE_BOOT_ROM                 22
> +#define SLAVE_CAMERA_CFG               23
> +#define SLAVE_CLK_CTL                  24
> +#define SLAVE_CRYPTO_0_CFG             25
> +#define SLAVE_DEHR_CFG                 26
> +#define SLAVE_DISPLAY_CFG              27
> +#define SLAVE_GRAPHICS_3D_CFG          28
> +#define SLAVE_IMEM_CFG                 29
> +#define SLAVE_LPASS                    30
> +#define SLAVE_MPM                      31
> +#define SLAVE_MSG_RAM                  32
> +#define SLAVE_MSS                      33
> +#define SLAVE_PDM                      34
> +#define SLAVE_PMIC_ARB                 35
> +#define SLAVE_PCNOC_CFG                        36
> +#define SLAVE_PRNG                     37
> +#define SLAVE_QDSS_CFG                 38
> +#define SLAVE_RBCPR_CFG                        39
> +#define SLAVE_SDCC_1                   40
> +#define SLAVE_SDCC_2                   41
> +#define SLAVE_SECURITY                 42
> +#define SLAVE_SNOC_CFG                 43
> +#define SLAVE_SPDM                     44
> +#define SLAVE_TCSR                     45
> +#define SLAVE_TLMM                     46
> +#define SLAVE_USB_HS                   47
> +#define SLAVE_VENUS_CFG                        48
> +#define SNOC_PCNOC_SLV                 49
> +
> +#endif
> diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
> new file mode 100644
> index 000000000000..32e66ee7e830
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for the Qualcomm PMIC's
> + * Multi-Purpose Pin binding.
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
> +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
> +
> +/* power-source */
> +
> +/* Digital Input/Output: level [PM8058] */
> +#define PM8058_MPP_VPH                 0
> +#define PM8058_MPP_S3                  1
> +#define PM8058_MPP_L2                  2
> +#define PM8058_MPP_L3                  3
> +
> +/* Digital Input/Output: level [PM8901] */
> +#define PM8901_MPP_MSMIO               0
> +#define PM8901_MPP_DIG                 1
> +#define PM8901_MPP_L5                  2
> +#define PM8901_MPP_S4                  3
> +#define PM8901_MPP_VPH                 4
> +
> +/* Digital Input/Output: level [PM8921] */
> +#define PM8921_MPP_S4                  1
> +#define PM8921_MPP_L15                 3
> +#define PM8921_MPP_L17                 4
> +#define PM8921_MPP_VPH                 7
> +
> +/* Digital Input/Output: level [PM8821] */
> +#define PM8821_MPP_1P8                 0
> +#define PM8821_MPP_VPH                 7
> +
> +/* Digital Input/Output: level [PM8018] */
> +#define PM8018_MPP_L4                  0
> +#define PM8018_MPP_L14                 1
> +#define PM8018_MPP_S3                  2
> +#define PM8018_MPP_L6                  3
> +#define PM8018_MPP_L2                  4
> +#define PM8018_MPP_L5                  5
> +#define PM8018_MPP_VPH                 7
> +
> +/* Digital Input/Output: level [PM8038] */
> +#define PM8038_MPP_L20                 0
> +#define PM8038_MPP_L11                 1
> +#define PM8038_MPP_L5                  2
> +#define PM8038_MPP_L15                 3
> +#define PM8038_MPP_L17                 4
> +#define PM8038_MPP_VPH                 7
> +
> +#define PM8841_MPP_VPH                 0
> +#define PM8841_MPP_S3                  2
> +
> +#define PM8916_MPP_VPH                 0
> +#define PM8916_MPP_L2                  2
> +#define PM8916_MPP_L5                  3
> +
> +#define PM8941_MPP_VPH                 0
> +#define PM8941_MPP_L1                  1
> +#define PM8941_MPP_S3                  2
> +#define PM8941_MPP_L6                  3
> +
> +#define PMA8084_MPP_VPH                        0
> +#define PMA8084_MPP_L1                 1
> +#define PMA8084_MPP_S4                 2
> +#define PMA8084_MPP_L6                 3
> +
> +#define PM8994_MPP_VPH                 0
> +/* Only supported for MPP_05-MPP_08 */
> +#define PM8994_MPP_L19                 1
> +#define PM8994_MPP_S4                  2
> +#define PM8994_MPP_L12                 3
> +
> +/*
> + * Analog Input - Set the source for analog input.
> + * To be used with "qcom,amux-route" property
> + */
> +#define PMIC_MPP_AMUX_ROUTE_CH5                0
> +#define PMIC_MPP_AMUX_ROUTE_CH6                1
> +#define PMIC_MPP_AMUX_ROUTE_CH7                2
> +#define PMIC_MPP_AMUX_ROUTE_CH8                3
> +#define PMIC_MPP_AMUX_ROUTE_ABUS1      4
> +#define PMIC_MPP_AMUX_ROUTE_ABUS2      5
> +#define PMIC_MPP_AMUX_ROUTE_ABUS3      6
> +#define PMIC_MPP_AMUX_ROUTE_ABUS4      7
> +
> +/* Analog Output: level */
> +#define PMIC_MPP_AOUT_LVL_1V25         0
> +#define PMIC_MPP_AOUT_LVL_1V25_2       1
> +#define PMIC_MPP_AOUT_LVL_0V625                2
> +#define PMIC_MPP_AOUT_LVL_0V3125       3
> +#define PMIC_MPP_AOUT_LVL_MPP          4
> +#define PMIC_MPP_AOUT_LVL_ABUS1                5
> +#define PMIC_MPP_AOUT_LVL_ABUS2                6
> +#define PMIC_MPP_AOUT_LVL_ABUS3                7
> +
> +/* To be used with "function" */
> +#define PMIC_MPP_FUNC_NORMAL           "normal"
> +#define PMIC_MPP_FUNC_PAIRED           "paired"
> +#define PMIC_MPP_FUNC_DTEST1           "dtest1"
> +#define PMIC_MPP_FUNC_DTEST2           "dtest2"
> +#define PMIC_MPP_FUNC_DTEST3           "dtest3"
> +#define PMIC_MPP_FUNC_DTEST4           "dtest4"
> +
> +#endif
> diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
> new file mode 100644
> index 000000000000..1f9be10872df
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h
> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2015 Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
> +#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
> +
> +#define GCC_BLSP1_BCR                  0
> +#define GCC_BLSP1_QUP1_BCR             1
> +#define GCC_BLSP1_UART1_BCR            2
> +#define GCC_BLSP1_QUP2_BCR             3
> +#define GCC_BLSP1_UART2_BCR            4
> +#define GCC_BLSP1_QUP3_BCR             5
> +#define GCC_BLSP1_QUP4_BCR             6
> +#define GCC_BLSP1_QUP5_BCR             7
> +#define GCC_BLSP1_QUP6_BCR             8
> +#define GCC_IMEM_BCR                   9
> +#define GCC_SMMU_BCR                   10
> +#define GCC_APSS_TCU_BCR               11
> +#define GCC_SMMU_XPU_BCR               12
> +#define GCC_PCNOC_TBU_BCR              13
> +#define GCC_PRNG_BCR                   14
> +#define GCC_BOOT_ROM_BCR               15
> +#define GCC_CRYPTO_BCR                 16
> +#define GCC_SEC_CTRL_BCR               17
> +#define GCC_AUDIO_CORE_BCR             18
> +#define GCC_ULT_AUDIO_BCR              19
> +#define GCC_DEHR_BCR                   20
> +#define GCC_SYSTEM_NOC_BCR             21
> +#define GCC_PCNOC_BCR                  22
> +#define GCC_TCSR_BCR                   23
> +#define GCC_QDSS_BCR                   24
> +#define GCC_DCD_BCR                    25
> +#define GCC_MSG_RAM_BCR                        26
> +#define GCC_MPM_BCR                    27
> +#define GCC_SPMI_BCR                   28
> +#define GCC_SPDM_BCR                   29
> +#define GCC_MM_SPDM_BCR                        30
> +#define GCC_BIMC_BCR                   31
> +#define GCC_RBCPR_BCR                  32
> +#define GCC_TLMM_BCR                   33
> +#define GCC_USB_HS_BCR                 34
> +#define GCC_USB2A_PHY_BCR              35
> +#define GCC_SDCC1_BCR                  36
> +#define GCC_SDCC2_BCR                  37
> +#define GCC_PDM_BCR                    38
> +#define GCC_SNOC_BUS_TIMEOUT0_BCR      39
> +#define GCC_PCNOC_BUS_TIMEOUT0_BCR     40
> +#define GCC_PCNOC_BUS_TIMEOUT1_BCR     41
> +#define GCC_PCNOC_BUS_TIMEOUT2_BCR     42
> +#define GCC_PCNOC_BUS_TIMEOUT3_BCR     43
> +#define GCC_PCNOC_BUS_TIMEOUT4_BCR     44
> +#define GCC_PCNOC_BUS_TIMEOUT5_BCR     45
> +#define GCC_PCNOC_BUS_TIMEOUT6_BCR     46
> +#define GCC_PCNOC_BUS_TIMEOUT7_BCR     47
> +#define GCC_PCNOC_BUS_TIMEOUT8_BCR     48
> +#define GCC_PCNOC_BUS_TIMEOUT9_BCR     49
> +#define GCC_MMSS_BCR                   50
> +#define GCC_VENUS0_BCR                 51
> +#define GCC_MDSS_BCR                   52
> +#define GCC_CAMSS_PHY0_BCR             53
> +#define GCC_CAMSS_CSI0_BCR             54
> +#define GCC_CAMSS_CSI0PHY_BCR          55
> +#define GCC_CAMSS_CSI0RDI_BCR          56
> +#define GCC_CAMSS_CSI0PIX_BCR          57
> +#define GCC_CAMSS_PHY1_BCR             58
> +#define GCC_CAMSS_CSI1_BCR             59
> +#define GCC_CAMSS_CSI1PHY_BCR          60
> +#define GCC_CAMSS_CSI1RDI_BCR          61
> +#define GCC_CAMSS_CSI1PIX_BCR          62
> +#define GCC_CAMSS_ISPIF_BCR            63
> +#define GCC_CAMSS_CCI_BCR              64
> +#define GCC_CAMSS_MCLK0_BCR            65
> +#define GCC_CAMSS_MCLK1_BCR            66
> +#define GCC_CAMSS_GP0_BCR              67
> +#define GCC_CAMSS_GP1_BCR              68
> +#define GCC_CAMSS_TOP_BCR              69
> +#define GCC_CAMSS_MICRO_BCR            70
> +#define GCC_CAMSS_JPEG_BCR             71
> +#define GCC_CAMSS_VFE_BCR              72
> +#define GCC_CAMSS_CSI_VFE0_BCR         73
> +#define GCC_OXILI_BCR                  74
> +#define GCC_GMEM_BCR                   75
> +#define GCC_CAMSS_AHB_BCR              76
> +#define GCC_MDP_TBU_BCR                        77
> +#define GCC_GFX_TBU_BCR                        78
> +#define GCC_GFX_TCU_BCR                        79
> +#define GCC_MSS_TBU_AXI_BCR            80
> +#define GCC_MSS_TBU_GSS_AXI_BCR                81
> +#define GCC_MSS_TBU_Q6_AXI_BCR         82
> +#define GCC_GTCU_AHB_BCR               83
> +#define GCC_SMMU_CFG_BCR               84
> +#define GCC_VFE_TBU_BCR                        85
> +#define GCC_VENUS_TBU_BCR              86
> +#define GCC_JPEG_TBU_BCR               87
> +#define GCC_PRONTO_TBU_BCR             88
> +#define GCC_SMMU_CATS_BCR              89
> +
> +#endif
> diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h
> new file mode 100644
> index 000000000000..dc605c4bc224
> --- /dev/null
> +++ b/include/dt-bindings/sound/apq8016-lpass.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_APQ8016_LPASS_H
> +#define __DT_APQ8016_LPASS_H
> +
> +#include <dt-bindings/sound/qcom,lpass.h>
> +
> +/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */
> +
> +#endif /* __DT_APQ8016_LPASS_H */
> diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h
> new file mode 100644
> index 000000000000..a9404c3b8884
> --- /dev/null
> +++ b/include/dt-bindings/sound/qcom,lpass.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __DT_QCOM_LPASS_H
> +#define __DT_QCOM_LPASS_H
> +
> +#define MI2S_PRIMARY   0
> +#define MI2S_SECONDARY 1
> +#define MI2S_TERTIARY  2
> +#define MI2S_QUATERNARY        3
> +#define MI2S_QUINARY   4
> +
> +#define LPASS_DP_RX    5
> +
> +#define LPASS_CDC_DMA_RX0 6
> +#define LPASS_CDC_DMA_RX1 7
> +#define LPASS_CDC_DMA_RX2 8
> +#define LPASS_CDC_DMA_RX3 9
> +#define LPASS_CDC_DMA_RX4 10
> +#define LPASS_CDC_DMA_RX5 11
> +#define LPASS_CDC_DMA_RX6 12
> +#define LPASS_CDC_DMA_RX7 13
> +#define LPASS_CDC_DMA_RX8 14
> +#define LPASS_CDC_DMA_RX9 15
> +
> +#define LPASS_CDC_DMA_TX0 16
> +#define LPASS_CDC_DMA_TX1 17
> +#define LPASS_CDC_DMA_TX2 18
> +#define LPASS_CDC_DMA_TX3 19
> +#define LPASS_CDC_DMA_TX4 20
> +#define LPASS_CDC_DMA_TX5 21
> +#define LPASS_CDC_DMA_TX6 22
> +#define LPASS_CDC_DMA_TX7 23
> +#define LPASS_CDC_DMA_TX8 24
> +
> +#define LPASS_CDC_DMA_VA_TX0 25
> +#define LPASS_CDC_DMA_VA_TX1 26
> +#define LPASS_CDC_DMA_VA_TX2 27
> +#define LPASS_CDC_DMA_VA_TX3 28
> +#define LPASS_CDC_DMA_VA_TX4 29
> +#define LPASS_CDC_DMA_VA_TX5 30
> +#define LPASS_CDC_DMA_VA_TX6 31
> +#define LPASS_CDC_DMA_VA_TX7 32
> +#define LPASS_CDC_DMA_VA_TX8 33
> +
> +#define LPASS_MCLK0    0
> +
> +#endif /* __DT_QCOM_LPASS_H */
>
> --
> 2.43.1
>

Re: [PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment

[Peter Robinson]

On Thu, 15 Feb 2024 at 21:03, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Add a config fragment for building U-Boot such that it can be
> chainloaded by aboot/LK rather than being flashed directly to the aboot
> partition.

How does this work in practice? I think a lot of devices, one example
I see is signed vs unsigned, or emmc vs other storage, have to
configs, how would a user choose with LK vs the other option here?

> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config
> new file mode 100644
> index 000000000000..3fd064924a1f
> --- /dev/null
> +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config
> @@ -0,0 +1,7 @@
> +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
> +CONFIG_TEXT_BASE=0x0
> +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set
> +# CONFIG_REMAKE_ELF is not set
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_INIT_SP_RELATIVE=y
> +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
>
> --
> 2.43.1
>

Re: [PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment

[Caleb Connolly]

On 20/02/2024 14:19, Peter Robinson wrote:
> On Thu, 15 Feb 2024 at 21:03, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>>
>> Add a config fragment for building U-Boot such that it can be
>> chainloaded by aboot/LK rather than being flashed directly to the aboot
>> partition.
> 
> How does this work in practice? I think a lot of devices, one example
> I see is signed vs unsigned, or emmc vs other storage, have to
> configs, how would a user choose with LK vs the other option here?

I'm not sure I understand, maybe the commit message wording was a bit
vague... There is only the default mode where U-Boot is flashed to the
aboot partition, and then the chainloaded usecase where it's wrapped in
an Android boot image and flashed to the boot partition.
> 
>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
>> ---
>>  board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config
>> new file mode 100644
>> index 000000000000..3fd064924a1f
>> --- /dev/null
>> +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config
>> @@ -0,0 +1,7 @@
>> +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
>> +CONFIG_TEXT_BASE=0x0
>> +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set
>> +# CONFIG_REMAKE_ELF is not set
>> +CONFIG_POSITION_INDEPENDENT=y
>> +CONFIG_INIT_SP_RELATIVE=y
>> +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
>>
>> --
>> 2.43.1
>>

-- 
// Caleb (they/them)

Re: [PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration

[Neil Armstrong]

On 20/02/2024 06:56, Sumit Garg wrote:
> On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>>
>> Some platforms hard reset when attempting to configure PMIC GPIOs. Add
>> support for quirks specified in match data with a single quirk to skip
>> this configuration. We rely on the GPIO already be configured correctly,
>> which is always the case for volume up (the only current user of these
>> GPIOs).
> 
> I can't find a similar quirk in the counterpart Linux driver
> (drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are
> missing in the U-Boot driver?

It's not ideal, it's fine to have it at first but at some point a proper
solution should be found.

Neil

> 
> -Sumit
> 
>>
>> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
>> ---
>>   drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++--
>>   1 file changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
>> index 2a4fef8d28cb..198cd84bc31e 100644
>> --- a/drivers/gpio/qcom_pmic_gpio.c
>> +++ b/drivers/gpio/qcom_pmic_gpio.c
>> @@ -64,6 +64,15 @@
>>   #define REG_EN_CTL             0x46
>>   #define REG_EN_CTL_ENABLE      (1 << 7)
>>
>> +/**
>> + * pmic_gpio_match_data - platform specific configuration
>> + *
>> + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
>> + */
>> +enum pmic_gpio_quirks {
>> +       QCOM_PMIC_QUIRK_READONLY = (1 << 0),
>> +};
>> +
>>   struct qcom_gpio_bank {
>>          uint32_t pid; /* Peripheral ID on SPMI bus */
>>          bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
>> @@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
>>          struct qcom_gpio_bank *priv = dev_get_priv(dev);
>>          uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
>>          uint32_t reg_ctl_val;
>> -       int ret;
>> +       ulong quirks = dev_get_driver_data(dev);
>> +       int ret = 0;
>> +
>> +       /* Some PMICs don't like their GPIOs being configured */
>> +       if (quirks & QCOM_PMIC_QUIRK_READONLY)
>> +               return 0;
>>
>>          /* Disable the GPIO */
>>          ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
>> @@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
>>   static const struct udevice_id qcom_gpio_ids[] = {
>>          { .compatible = "qcom,pm8916-gpio" },
>>          { .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
>> -       { .compatible = "qcom,pm8998-gpio" },
>> +       { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
>>          { .compatible = "qcom,pms405-gpio" },
>>          { }
>>   };
>>
>> --
>> 2.43.1
>>

Re: [PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration

[Sumit Garg]

On Wed, 21 Feb 2024 at 14:19, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 20/02/2024 06:56, Sumit Garg wrote:
> > On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
> >>
> >> Some platforms hard reset when attempting to configure PMIC GPIOs. Add
> >> support for quirks specified in match data with a single quirk to skip
> >> this configuration. We rely on the GPIO already be configured correctly,
> >> which is always the case for volume up (the only current user of these
> >> GPIOs).
> >
> > I can't find a similar quirk in the counterpart Linux driver
> > (drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are
> > missing in the U-Boot driver?
>
> It's not ideal, it's fine to have it at first but at some point a proper
> solution should be found.

Then at least let's add code comments to say that it is just a
workaround for the time being until a proper solution is found.

-Sumit

>
> Neil
>
> >
> > -Sumit
> >
> >>
> >> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> >> ---
> >>   drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++--
> >>   1 file changed, 16 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> >> index 2a4fef8d28cb..198cd84bc31e 100644
> >> --- a/drivers/gpio/qcom_pmic_gpio.c
> >> +++ b/drivers/gpio/qcom_pmic_gpio.c
> >> @@ -64,6 +64,15 @@
> >>   #define REG_EN_CTL             0x46
> >>   #define REG_EN_CTL_ENABLE      (1 << 7)
> >>
> >> +/**
> >> + * pmic_gpio_match_data - platform specific configuration
> >> + *
> >> + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
> >> + */
> >> +enum pmic_gpio_quirks {
> >> +       QCOM_PMIC_QUIRK_READONLY = (1 << 0),
> >> +};
> >> +
> >>   struct qcom_gpio_bank {
> >>          uint32_t pid; /* Peripheral ID on SPMI bus */
> >>          bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
> >> @@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
> >>          struct qcom_gpio_bank *priv = dev_get_priv(dev);
> >>          uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> >>          uint32_t reg_ctl_val;
> >> -       int ret;
> >> +       ulong quirks = dev_get_driver_data(dev);
> >> +       int ret = 0;
> >> +
> >> +       /* Some PMICs don't like their GPIOs being configured */
> >> +       if (quirks & QCOM_PMIC_QUIRK_READONLY)
> >> +               return 0;
> >>
> >>          /* Disable the GPIO */
> >>          ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
> >> @@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
> >>   static const struct udevice_id qcom_gpio_ids[] = {
> >>          { .compatible = "qcom,pm8916-gpio" },
> >>          { .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
> >> -       { .compatible = "qcom,pm8998-gpio" },
> >> +       { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
> >>          { .compatible = "qcom,pms405-gpio" },
> >>          { }
> >>   };
> >>
> >> --
> >> 2.43.1
> >>