* [U-Boot] [PATCH] samsung: move DRAM parameters
@ 2009-11-04 8:22 "Seunghyeon Rhee (이승현)"
2009-11-05 0:46 ` Minkyu Kang
0 siblings, 1 reply; 4+ messages in thread
From: "Seunghyeon Rhee (이승현)" @ 2009-11-04 8:22 UTC (permalink / raw)
To: u-boot
Move the definitions of DRAM parameters from SoC description
(s3c6400.h) to board description (smdk6400.h). DRAM parameters
are rather board-specific than SoC specific. According to the
current source, one may have to change the definitions in
s3c6400.h in addition to creating the new board description
whenever he wants to add support for a new board based on
s3c6400. I don't think this meets the U-Boot policy of
separating SoC description and board description.
There will be no observable changes in operation. It's just
to make it easier to add support for new boards.
Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
---
include/configs/smdk6400.h | 21 +++++++++++++++++++++
include/s3c6400.h | 21 ---------------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f6e1221..a2b46fd 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -309,4 +309,25 @@
# error "usb_ohci.c is currently broken with MMU enabled."
#endif
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2 0xB45
+#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
+#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH 7800 /* ns */
+#define DDR_tRAS 45 /* ns (min: 45ns)*/
+#define DDR_tRC 68 /* ns (min: 67.5ns)*/
+#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
+#define DDR_tRFC 80 /* ns (min: 80ns)*/
+#define DDR_tRP 23 /* ns (min: 22.5ns)*/
+#define DDR_tRRD 15 /* ns (min: 15ns)*/
+#define DDR_tWR 15 /* ns (min: 15ns)*/
+#define DDR_tXSR 120 /* ns (min: 120ns)*/
+#define DDR_CASL 3 /* CAS Latency 3 */
+
#endif /* __CONFIG_H */
diff --git a/include/s3c6400.h b/include/s3c6400.h
index e527c08..34d0d15 100644
--- a/include/s3c6400.h
+++ b/include/s3c6400.h
@@ -814,27 +814,6 @@
#endif
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
/*
* mDDR memory configuration
*/
--
1.6.2.5
--
Seunghyeon Rhee, Ph.D. / Director
LPM Technology Inc.
T +82-70-8255-6007 F +82-2-6442-6462
M +82-10-2790-0657
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] samsung: move DRAM parameters
2009-11-04 8:22 [U-Boot] [PATCH] samsung: move DRAM parameters "Seunghyeon Rhee (이승현)"
@ 2009-11-05 0:46 ` Minkyu Kang
2009-11-05 1:51 ` "Seunghyeon Rhee (이승현)"
0 siblings, 1 reply; 4+ messages in thread
From: Minkyu Kang @ 2009-11-05 0:46 UTC (permalink / raw)
To: u-boot
Dear Seunghyeon Rhee,
2009/11/4 "Seunghyeon Rhee (???)" <seunghyeon@lpmtec.com>:
> Move the definitions of DRAM parameters from SoC description
> (s3c6400.h) to board description (smdk6400.h). DRAM parameters
> are rather board-specific than SoC specific. According to the
> current source, one may have to change the definitions in
> s3c6400.h in addition to creating the new board description
> whenever he wants to add support for a new board based on
> s3c6400. I don't think this meets the U-Boot policy of
> separating SoC description and board description.
> There will be no observable changes in operation. It's just
> to make it easier to add support for new boards.
>
> Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
> ---
> ?include/configs/smdk6400.h | ? 21 +++++++++++++++++++++
> ?include/s3c6400.h ? ? ? ? ?| ? 21 ---------------------
> ?2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
> index f6e1221..a2b46fd 100644
> --- a/include/configs/smdk6400.h
> +++ b/include/configs/smdk6400.h
> @@ -309,4 +309,25 @@
> ?# error "usb_ohci.c is currently broken with MMU enabled."
> ?#endif
>
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define DMC1_MEM_CFG ? 0x80010012 ? ? ?/* Chip1, Burst4, Row/Column bit */
> +#define DMC1_MEM_CFG2 ?0xB45
> +#define DMC1_CHIP0_CFG 0x150F8 ? ? ? ? /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
> +#define DMC_DDR_32_CFG 0x0 ? ? ? ? ? ? /* 32bit, DDR */
> +
> +/* Memory Parameters */
> +/* DDR Parameters */
> +#define DDR_tREFRESH ? ? ? ? ? 7800 ? ?/* ns */
> +#define DDR_tRAS ? ? ? ? ? ? ? 45 ? ? ?/* ns (min: 45ns)*/
> +#define DDR_tRC ? ? ? ? ? ? ? ?68 ? ? ?/* ns (min: 67.5ns)*/
> +#define DDR_tRCD ? ? ? ? ? ? ? 23 ? ? ?/* ns (min: 22.5ns)*/
> +#define DDR_tRFC ? ? ? ? ? ? ? 80 ? ? ?/* ns (min: 80ns)*/
> +#define DDR_tRP ? ? ? ? ? ? ? ?23 ? ? ?/* ns (min: 22.5ns)*/
> +#define DDR_tRRD ? ? ? ? ? ? ? 15 ? ? ?/* ns (min: 15ns)*/
> +#define DDR_tWR ? ? ? ? ? ? ? ?15 ? ? ?/* ns (min: 15ns)*/
> +#define DDR_tXSR ? ? ? ? ? ? ? 120 ? ? /* ns (min: 120ns)*/
> +#define DDR_CASL ? ? ? ? ? ? ? 3 ? ? ? /* CAS Latency 3 */
> +
> ?#endif /* __CONFIG_H */
> diff --git a/include/s3c6400.h b/include/s3c6400.h
> index e527c08..34d0d15 100644
> --- a/include/s3c6400.h
> +++ b/include/s3c6400.h
> @@ -814,27 +814,6 @@
> ?#endif
>
>
> -/*-----------------------------------------------------------------------
> - * Physical Memory Map
> - */
> -#define DMC1_MEM_CFG ? 0x80010012 ? ? ?/* Chip1, Burst4, Row/Column bit */
> -#define DMC1_MEM_CFG2 ?0xB45
> -#define DMC1_CHIP0_CFG 0x150F8 ? ? ? ? /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
> -#define DMC_DDR_32_CFG 0x0 ? ? ? ? ? ? /* 32bit, DDR */
> -
> -/* Memory Parameters */
> -/* DDR Parameters */
> -#define DDR_tREFRESH ? ? ? ? ? 7800 ? ?/* ns */
> -#define DDR_tRAS ? ? ? ? ? ? ? 45 ? ? ?/* ns (min: 45ns)*/
> -#define DDR_tRC ? ? ? ? ? ? ? ?68 ? ? ?/* ns (min: 67.5ns)*/
> -#define DDR_tRCD ? ? ? ? ? ? ? 23 ? ? ?/* ns (min: 22.5ns)*/
> -#define DDR_tRFC ? ? ? ? ? ? ? 80 ? ? ?/* ns (min: 80ns)*/
> -#define DDR_tRP ? ? ? ? ? ? ? ?23 ? ? ?/* ns (min: 22.5ns)*/
> -#define DDR_tRRD ? ? ? ? ? ? ? 15 ? ? ?/* ns (min: 15ns)*/
> -#define DDR_tWR ? ? ? ? ? ? ? ?15 ? ? ?/* ns (min: 15ns)*/
> -#define DDR_tXSR ? ? ? ? ? ? ? 120 ? ? /* ns (min: 120ns)*/
> -#define DDR_CASL ? ? ? ? ? ? ? 3 ? ? ? /* CAS Latency 3 */
> -
> ?/*
> ?* mDDR memory configuration
> ?*/
> --
> 1.6.2.5
>
>
> --
> Seunghyeon Rhee, Ph.D. / Director
> LPM Technology Inc.
> T +82-70-8255-6007 ?F +82-2-6442-6462
> M +82-10-2790-0657
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
yes,
DRAM parameters are board specific.
But I think it is not good way to move DRAM parameters to board
configuration file.
At first, we need to move cpu/arm1176/s3c64xx/cpu_init.S to board
directory. (please see smdkc100/mem_setup.S)
And.. let's think about where to move DRAM parameters.
Please give your opinion.
Thanks
Minkyu Kang
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] samsung: move DRAM parameters
2009-11-05 0:46 ` Minkyu Kang
@ 2009-11-05 1:51 ` "Seunghyeon Rhee (이승현)"
2009-11-05 11:24 ` Minkyu Kang
0 siblings, 1 reply; 4+ messages in thread
From: "Seunghyeon Rhee (이승현)" @ 2009-11-05 1:51 UTC (permalink / raw)
To: u-boot
Dear Minkyu Kang,
What causes the current ambiguity is, in my opinion, the "parameters"
themselves and "the way of setting them." As you know, DRAM controller
is integrated in the SoC while the parameters required to set them are
dependent on the external components, DRAM chips.
In this respect, cpu_init.S - I don't like the name because all it does is
set up the memory controller. mem_setup.S is more appropriate - don't
need to be moved to board description stuffs. The memory controller (the
hardware logic in the SoC) is not changeable according to the board design.
Neither does the way of setting it, which is in charge of cpu_init.S.
What is
changed from board to board is not cpu_init.S but the parameters. If we
move it to board directory, we have to add redundant code - actually
several copies of the same file - every time we add support for a new board
with the same SoC.
Thererfore, I think cpu_init.S(or mem_setup.S) would better be placed with
SoC stuffs like it is now while DRAM parameters be moved to board
description stuffs. We can make the function for setting up the DRAM
controller completely independent of board design by introducing more
macro definitions if necessary. All we have to do for adding support for
new boards then will be reduced to creating the new board's description.
No redundant codes, no repeated modification of the SoC description will
be required.
Best regards,
Seunghyeon
Seunghyeon Rhee, Ph.D. / Director
LPM Technology Inc.
T +82-70-8255-6007 F +82-2-6442-6462
M +82-10-2790-0657
Minkyu Kang ? ?:
> Dear Seunghyeon Rhee,
>
> 2009/11/4 "Seunghyeon Rhee (???)" <seunghyeon@lpmtec.com>:
>
>> Move the definitions of DRAM parameters from SoC description
>> (s3c6400.h) to board description (smdk6400.h). DRAM parameters
>> are rather board-specific than SoC specific. According to the
>> current source, one may have to change the definitions in
>> s3c6400.h in addition to creating the new board description
>> whenever he wants to add support for a new board based on
>> s3c6400. I don't think this meets the U-Boot policy of
>> separating SoC description and board description.
>> There will be no observable changes in operation. It's just
>> to make it easier to add support for new boards.
>>
>> Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
>> ---
>> include/configs/smdk6400.h | 21 +++++++++++++++++++++
>> include/s3c6400.h | 21 ---------------------
>> 2 files changed, 21 insertions(+), 21 deletions(-)
>>
>> diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
>> index f6e1221..a2b46fd 100644
>> --- a/include/configs/smdk6400.h
>> +++ b/include/configs/smdk6400.h
>> @@ -309,4 +309,25 @@
>> # error "usb_ohci.c is currently broken with MMU enabled."
>> #endif
>>
>> +/*-----------------------------------------------------------------------
>> + * Physical Memory Map
>> + */
>> +#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
>> +#define DMC1_MEM_CFG2 0xB45
>> +#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
>> +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
>> +
>> +/* Memory Parameters */
>> +/* DDR Parameters */
>> +#define DDR_tREFRESH 7800 /* ns */
>> +#define DDR_tRAS 45 /* ns (min: 45ns)*/
>> +#define DDR_tRC 68 /* ns (min: 67.5ns)*/
>> +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
>> +#define DDR_tRFC 80 /* ns (min: 80ns)*/
>> +#define DDR_tRP 23 /* ns (min: 22.5ns)*/
>> +#define DDR_tRRD 15 /* ns (min: 15ns)*/
>> +#define DDR_tWR 15 /* ns (min: 15ns)*/
>> +#define DDR_tXSR 120 /* ns (min: 120ns)*/
>> +#define DDR_CASL 3 /* CAS Latency 3 */
>> +
>> #endif /* __CONFIG_H */
>> diff --git a/include/s3c6400.h b/include/s3c6400.h
>> index e527c08..34d0d15 100644
>> --- a/include/s3c6400.h
>> +++ b/include/s3c6400.h
>> @@ -814,27 +814,6 @@
>> #endif
>>
>>
>> -/*-----------------------------------------------------------------------
>> - * Physical Memory Map
>> - */
>> -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
>> -#define DMC1_MEM_CFG2 0xB45
>> -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
>> -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
>> -
>> -/* Memory Parameters */
>> -/* DDR Parameters */
>> -#define DDR_tREFRESH 7800 /* ns */
>> -#define DDR_tRAS 45 /* ns (min: 45ns)*/
>> -#define DDR_tRC 68 /* ns (min: 67.5ns)*/
>> -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
>> -#define DDR_tRFC 80 /* ns (min: 80ns)*/
>> -#define DDR_tRP 23 /* ns (min: 22.5ns)*/
>> -#define DDR_tRRD 15 /* ns (min: 15ns)*/
>> -#define DDR_tWR 15 /* ns (min: 15ns)*/
>> -#define DDR_tXSR 120 /* ns (min: 120ns)*/
>> -#define DDR_CASL 3 /* CAS Latency 3 */
>> -
>> /*
>> * mDDR memory configuration
>> */
>> --
>> 1.6.2.5
>>
>>
>> --
>> Seunghyeon Rhee, Ph.D. / Director
>> LPM Technology Inc.
>> T +82-70-8255-6007 F +82-2-6442-6462
>> M +82-10-2790-0657
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>>
>
> yes,
> DRAM parameters are board specific.
> But I think it is not good way to move DRAM parameters to board
> configuration file.
> At first, we need to move cpu/arm1176/s3c64xx/cpu_init.S to board
> directory. (please see smdkc100/mem_setup.S)
> And.. let's think about where to move DRAM parameters.
> Please give your opinion.
>
> Thanks
> Minkyu Kang
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] samsung: move DRAM parameters
2009-11-05 1:51 ` "Seunghyeon Rhee (이승현)"
@ 2009-11-05 11:24 ` Minkyu Kang
0 siblings, 0 replies; 4+ messages in thread
From: Minkyu Kang @ 2009-11-05 11:24 UTC (permalink / raw)
To: u-boot
Dear Seunghyeon Rhee,
please do not top posting.
2009/11/5 "Seunghyeon Rhee (???)" <seunghyeon@lpmtec.com>:
> Dear Minkyu Kang,
>
> What causes the current ambiguity is, in my opinion, the "parameters"
> themselves and "the way of setting them." As you know, DRAM controller
> is integrated in the SoC while the parameters required to set them are
> dependent on the external components, DRAM chips.
>
> In this respect, cpu_init.S - I don't like the name because all it does is
> set up the memory controller. mem_setup.S is more appropriate - don't
> need to be moved to board description stuffs. The memory controller (the
> hardware logic in the SoC) is not changeable according to the board design.
> Neither does the way of setting it, which is in charge of cpu_init.S.
> What is
> changed from board to board is not cpu_init.S but the parameters. If we
> move it to board directory, we have to add redundant code - actually
> several copies of the same file - every time we add support for a new board
> with the same SoC.
>
> Thererfore, I think cpu_init.S(or mem_setup.S) would better be placed with
> SoC stuffs like it is now while DRAM parameters be moved to board
> description stuffs. We can make the function for setting up the DRAM
> controller completely independent of board design by introducing more
> macro definitions if necessary. All we have to do for adding support for
> new boards then will be reduced to creating the new board's description.
> No redundant codes, no repeated modification of the SoC description will
> be required.
Agreed.
But, I'm not sure that move it to board configuration file.
let's figure out and discuss.. including regard your suggestion.
>
> Best regards,
> Seunghyeon
>
> Seunghyeon Rhee, Ph.D. / Director
> LPM Technology Inc.
> T +82-70-8255-6007 F +82-2-6442-6462
> M +82-10-2790-0657
>
>
>
> Minkyu Kang ? ?:
>> Dear Seunghyeon Rhee,
>>
>> 2009/11/4 "Seunghyeon Rhee (???)" <seunghyeon@lpmtec.com>:
>>
>>> Move the definitions of DRAM parameters from SoC description
>>> (s3c6400.h) to board description (smdk6400.h). DRAM parameters
>>> are rather board-specific than SoC specific. According to the
>>> current source, one may have to change the definitions in
>>> s3c6400.h in addition to creating the new board description
>>> whenever he wants to add support for a new board based on
>>> s3c6400. I don't think this meets the U-Boot policy of
>>> separating SoC description and board description.
>>> There will be no observable changes in operation. It's just
>>> to make it easier to add support for new boards.
>>>
>>> Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
>>> ---
>>> include/configs/smdk6400.h | 21 +++++++++++++++++++++
>>> include/s3c6400.h | 21 ---------------------
>>> 2 files changed, 21 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
>>> index f6e1221..a2b46fd 100644
>>> --- a/include/configs/smdk6400.h
>>> +++ b/include/configs/smdk6400.h
>>> @@ -309,4 +309,25 @@
>>> # error "usb_ohci.c is currently broken with MMU enabled."
>>> #endif
>>>
>>> +/*-----------------------------------------------------------------------
>>> + * Physical Memory Map
>>> + */
>>> +#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
>>> +#define DMC1_MEM_CFG2 0xB45
>>> +#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
>>> +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
>>> +
>>> +/* Memory Parameters */
>>> +/* DDR Parameters */
>>> +#define DDR_tREFRESH 7800 /* ns */
>>> +#define DDR_tRAS 45 /* ns (min: 45ns)*/
>>> +#define DDR_tRC 68 /* ns (min: 67.5ns)*/
>>> +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
>>> +#define DDR_tRFC 80 /* ns (min: 80ns)*/
>>> +#define DDR_tRP 23 /* ns (min: 22.5ns)*/
>>> +#define DDR_tRRD 15 /* ns (min: 15ns)*/
>>> +#define DDR_tWR 15 /* ns (min: 15ns)*/
>>> +#define DDR_tXSR 120 /* ns (min: 120ns)*/
>>> +#define DDR_CASL 3 /* CAS Latency 3 */
>>> +
>>> #endif /* __CONFIG_H */
>>> diff --git a/include/s3c6400.h b/include/s3c6400.h
>>> index e527c08..34d0d15 100644
>>> --- a/include/s3c6400.h
>>> +++ b/include/s3c6400.h
>>> @@ -814,27 +814,6 @@
>>> #endif
>>>
>>>
>>> -/*-----------------------------------------------------------------------
>>> - * Physical Memory Map
>>> - */
>>> -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
>>> -#define DMC1_MEM_CFG2 0xB45
>>> -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
>>> -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
>>> -
>>> -/* Memory Parameters */
>>> -/* DDR Parameters */
>>> -#define DDR_tREFRESH 7800 /* ns */
>>> -#define DDR_tRAS 45 /* ns (min: 45ns)*/
>>> -#define DDR_tRC 68 /* ns (min: 67.5ns)*/
>>> -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
>>> -#define DDR_tRFC 80 /* ns (min: 80ns)*/
>>> -#define DDR_tRP 23 /* ns (min: 22.5ns)*/
>>> -#define DDR_tRRD 15 /* ns (min: 15ns)*/
>>> -#define DDR_tWR 15 /* ns (min: 15ns)*/
>>> -#define DDR_tXSR 120 /* ns (min: 120ns)*/
>>> -#define DDR_CASL 3 /* CAS Latency 3 */
>>> -
>>> /*
>>> * mDDR memory configuration
>>> */
>>> --
>>> 1.6.2.5
>>>
>>>
>>> --
>>> Seunghyeon Rhee, Ph.D. / Director
>>> LPM Technology Inc.
>>> T +82-70-8255-6007 F +82-2-6442-6462
>>> M +82-10-2790-0657
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>>>
>>>
>>
>> yes,
>> DRAM parameters are board specific.
>> But I think it is not good way to move DRAM parameters to board
>> configuration file.
>> At first, we need to move cpu/arm1176/s3c64xx/cpu_init.S to board
>> directory. (please see smdkc100/mem_setup.S)
>> And.. let's think about where to move DRAM parameters.
>> Please give your opinion.
>>
>> Thanks
>> Minkyu Kang
>>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks
Minkyu Kang
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2009-11-05 11:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-11-04 8:22 [U-Boot] [PATCH] samsung: move DRAM parameters "Seunghyeon Rhee (이승현)"
2009-11-05 0:46 ` Minkyu Kang
2009-11-05 1:51 ` "Seunghyeon Rhee (이승현)"
2009-11-05 11:24 ` Minkyu Kang
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