DTS file PCI / i8259 for Xilinx ML510

DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

Hi,

I'm working on adding PCI support for the Xilinx ML510 FPGA board. The board contains a Virtex-5 FPGA (containing two PPC440 cores), a ALI M1533 pci south bridge, pci slots and more.

I have written code (inspired by the powermac pci code) which initializes the pci soft-core which is in my FPGA. Linux now sees all my pci devices in /proc/bus/pci/devices and the kernel assigned io memory / io port ranges for each device.

Right now I'm working on irq assignment. The FPGA contains a xilinx interrupt controller to which a uart, ethernet, pci slots (inta/b/c/d) and my ALI south bridge (it has its own irq input on the xilinx intc) are connected. The ALI south bridge itself contains a i8259 interrupt controller to which internal USB, IDE and other peripherals are connected.

The problems I'm having are with the DTS file. I'm not fully sure what to put in there and what the kernel is doing with the PCI info. As a start point I looked at mpc8641_hpcn.dts / mpc8572.dts and other freescale files as their boards also contain a i8259 south bridge but this time connected to a ULI M1575 south bridge (it is the successor to the ALI M1533).

The freescale boards define the pci bus like below and connect ULI M1575 peripherals to the i8259 controller. Regarding the entries in the pci interrupt-map what does the fourth column mean? According to source code it means 'interrupt specifier' but what does it mean? In a lot of cases it is 1. Further I believe in this case the entries behind 'mpic' correspond to the inta/b/c/d lines, is that correct? On my board inta is connected to interrupt 5 (intb=4, intc=3, intd=2) of the xilinx intc, so I would need to use those numbers there for my board?

	pci0: pcie@f8008000
	{
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		..
		..
		interrupt-map-mask = <0xff00 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0 0 1 &mpic 2 1
			0x8800 0 0 2 &mpic 3 1
			0x8800 0 0 3 &mpic 4 1
			0x8800 0 0 4 &mpic 1 1
			..
			..
			// IDSEL 0x1c  USB
			0xe000 0 0 1 &i8259 12 2
			0xe100 0 0 2 &i8259 9 2
		>;

At some point in the file they create some (dummy?) pcie section in which they define a uli1575, an isa bus and attached to that isa bus a i8259. Is this the correct way of doing things? The i8259 driver seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined below but how are those mapped to the south bridge? I have seen some code in kernel/isa-bridge, is that code indeed responsible for setting up these ports?

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0x80000000
					  0x02000000 0x0 0x80000000
					  0x0 0x20000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <1 0x20 2
						       1 0xa0 2
						       1 0x4d0 2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};
				};
			};
		};

Thanks,
Roderick Colenbrander


-- 
Nur bis 16.03.! DSL-Komplettanschluss inkl. WLAN-Modem für nur 
17,95 ¿/mtl. + 1 Monat gratis!* http://dsl.gmx.de/?ac=OM.AD.PD003K11308T4569a

Re: DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

-------- Original-Nachricht --------
> Datum: Mon, 16 Mar 2009 09:18:54 +0100
> Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> An: "Gerhard Pircher" <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
> Betreff: Re: DTS file PCI / i8259 for Xilinx ML510

> 
> -------- Original-Nachricht --------
> > Datum: Sun, 15 Mar 2009 11:43:13 +0100
> > Von: "Gerhard Pircher" <gerhard_pircher@gmx.net>
> > An: "Roderick Colenbrander" <thunderbird2k@gmx.net>,
> linuxppc-dev@ozlabs.org
> > Betreff: Re: DTS file PCI / i8259 for Xilinx ML510
> 
> > 
> > -------- Original-Nachricht --------
> > > Datum: Sun, 15 Mar 2009 09:38:26 +0100
> > > Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> > > An: "Gerhard Pircher" <gerhard_pircher@gmx.net>,
> linuxppc-dev@ozlabs.org
> > > Betreff: Re: DTS file PCI / i8259 for Xilinx ML510
> > 
> > > > > At some point in the file they create some (dummy?) pcie section
> in
> > > > > which they define a uli1575, an isa bus and attached to that isa
> bus
> > > > > a i8259. Is this the correct way of doing things? The i8259 driver
> > > > > seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also
> > > > > defined below but how are those mapped to the south bridge? I have
> > > > > seen some code in kernel/isa-bridge, is that code indeed
> responsible
> > > > > for setting up these ports?
> > > > Yes, the pcie node is the PCI host bridge node and the uli1571 node
> > > > acts as PCI2ISA bridge node. AFAIK their ranges properties are
> parsed
> > > > by pci_process_bridge_OF_ranges().
> > > > IIRC the code in kernel/isa-bridge is used for 64bit PPC machines
> only
> > > > for now. The I/O addresses for the i8259 PIC are currently hardcoded
> > > > and setup (request_resource()) in sysdev/i8259.c.
> > > 
> > > I got the i8259 south bridge working now after adding an io_base_virt
> > > offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> > > the troubles to add ppc32 support to isa-bridge.c? The whole point of
> > > the code is basically to remap the io memory to low addresses for
> these
> > > 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> > > systems with a i8259).
> > pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
> > if your board has only one PCI I/O space. It also sets isa_io_base to
> > io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
> > PCI I/O address 0x0. Isn't that the case for your board?
> > 
> > > As far as I have seen it is only needed for i8259 interrupt
> controllers.
> > > Personally I think it would be better to pass a io base offset to
> > > i8259_setup or so. Or perhaps do some dts file parsing in i8259.c.
> > > I'm not sure what the proper layout would be for this in the dts file
> > > though.
> > I think adding an io base offset parameter to i8259_setup isn't the
> > right way to do it. I would expect other problems too, if ISA I/O space
> > isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more
> > experienced kernel developer can comment on this?
> 
> I'm now back behind my ML510 board and have been doing some tests. As I
> mentioned before I was doing inb(isa_io_base + port) / outb(val, isa_io_base
> + port) which worked fine. As far as I see it the problem is the definition
> of inb/outb on ppc32 they don't take isa_io_base into account. They are:
> __do_in_asm(_rec_inb, "lbzx")
> __do_out_asm(_rec_outb, "stbx")
> #define __do_outb(val, port)    _rec_outb(val, port)
> #define __do_inb(port)          _rec_inb(port)
> 
> While on 64-bit ppc they are:
> #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
> #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
> 
> (On ppc32 _IO_BASE is isa_io_base but on 64-bit it is set to pci_io_base)
> 
> Am I correct that inb/outb are broken on ppc32? If so what is the right
> way to fix them?
> 
> Regards,
> Roderick

I just talked about this on IRC with Benjamin Herrenschmidt and I misunderstood the inb/outb command. the commands are using _IO_PORTS and I must be doing something wrong.

Roderick
-- 
Nur bis 16.03.! DSL-Komplettanschluss inkl. WLAN-Modem für nur 
17,95 ¿/mtl. + 1 Monat gratis!* http://dsl.gmx.de/?ac=OM.AD.PD003K11308T4569a

Re: DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

-------- Original-Nachricht --------
> Datum: Sun, 15 Mar 2009 11:43:13 +0100
> Von: "Gerhard Pircher" <gerhard_pircher@gmx.net>
> An: "Roderick Colenbrander" <thunderbird2k@gmx.net>, linuxppc-dev@ozlabs.org
> Betreff: Re: DTS file PCI / i8259 for Xilinx ML510

> 
> -------- Original-Nachricht --------
> > Datum: Sun, 15 Mar 2009 09:38:26 +0100
> > Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> > An: "Gerhard Pircher" <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
> > Betreff: Re: DTS file PCI / i8259 for Xilinx ML510
> 
> > > > At some point in the file they create some (dummy?) pcie section in
> > > > which they define a uli1575, an isa bus and attached to that isa bus
> > > > a i8259. Is this the correct way of doing things? The i8259 driver
> > > > seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also
> > > > defined below but how are those mapped to the south bridge? I have
> > > > seen some code in kernel/isa-bridge, is that code indeed responsible
> > > > for setting up these ports?
> > > Yes, the pcie node is the PCI host bridge node and the uli1571 node
> > > acts as PCI2ISA bridge node. AFAIK their ranges properties are parsed
> > > by pci_process_bridge_OF_ranges().
> > > IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only
> > > for now. The I/O addresses for the i8259 PIC are currently hardcoded
> > > and setup (request_resource()) in sysdev/i8259.c.
> > 
> > I got the i8259 south bridge working now after adding an io_base_virt
> > offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> > the troubles to add ppc32 support to isa-bridge.c? The whole point of
> > the code is basically to remap the io memory to low addresses for these
> > 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> > systems with a i8259).
> pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
> if your board has only one PCI I/O space. It also sets isa_io_base to
> io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
> PCI I/O address 0x0. Isn't that the case for your board?
> 
> > As far as I have seen it is only needed for i8259 interrupt controllers.
> > Personally I think it would be better to pass a io base offset to
> > i8259_setup or so. Or perhaps do some dts file parsing in i8259.c.
> > I'm not sure what the proper layout would be for this in the dts file
> > though.
> I think adding an io base offset parameter to i8259_setup isn't the
> right way to do it. I would expect other problems too, if ISA I/O space
> isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more
> experienced kernel developer can comment on this?

I'm now back behind my ML510 board and have been doing some tests. As I mentioned before I was doing inb(isa_io_base + port) / outb(val, isa_io_base + port) which worked fine. As far as I see it the problem is the definition of inb/outb on ppc32 they don't take isa_io_base into account. They are:
__do_in_asm(_rec_inb, "lbzx")
__do_out_asm(_rec_outb, "stbx")
#define __do_outb(val, port)    _rec_outb(val, port)
#define __do_inb(port)          _rec_inb(port)

While on 64-bit ppc they are:
#define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
#define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);

(On ppc32 _IO_BASE is isa_io_base but on 64-bit it is set to pci_io_base)

Am I correct that inb/outb are broken on ppc32? If so what is the right way to fix them?

Regards,
Roderick
-- 
Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01

Re: DTS file PCI / i8259 for Xilinx ML510

[Gerhard Pircher]

-------- Original-Nachricht --------
> Datum: Sun, 15 Mar 2009 12:00:17 +0100
> Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> An: "Gerhard Pircher" <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
> Betreff: Re: DTS file PCI / i8259 for Xilinx ML510

> > > I got the i8259 south bridge working now after adding an io_base_virt
> > > offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> > > the troubles to add ppc32 support to isa-bridge.c? The whole point of
> > > the code is basically to remap the io memory to low addresses for
> > > these 64-bit ppc systems (mainly freescale boards with a i8259 and
> > > pseries systems with a i8259).
> > pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
> > if your board has only one PCI I/O space. It also sets isa_io_base to
> > io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
> > PCI I/O address 0x0. Isn't that the case for your board?
> > 
> 
> Ah then perhaps that is my problem. I'm using my own pci implementation
> for Xilinx their plbv46 soft core. The soft core might be compatible
> with a generic ibm plb-pci bridge (sysdev/ppc44x_pci.c). Basically I'm
> doing something like which is done in powermac/pci.c e.g. creating the
> pci_controller and filling it with cfg_addr / cfg_data pointers, io
> ranges, resource ranges and so on. The data is obtained from the dts
> file but from some xilinx generated fields and doesn't have the generic
> ranges fields and some others. I guess it is time to fix this part of
> the DTS file.
I don't know much about this plb2pci bridge, but if you take a look at ppc4xx_probe_pci_bridge() in sysdev/ppc4xx_pci.c, you'll see that it
calls pci_process_bridge_OF_ranges() too. Thus the "ranges" properties
are required to setup PCI correctly.

> Some other issue I had which might be related to my DTS file bugs is
> some i/o port conflict. The M1553 south bridge is just a peripheral on
> the ML510 primary pci bus there are no PCI slots connected to it. There
> are four other pci slots of which two are directly connected to the fpga
> (they are on the same bus as the M1553) and two are connected using a
> pci-to-pci bridge because they use 5V instead of 3.3V. The bridge chip
> wanted 0x0-0xfff while some south bridge devices wanted low addresses
> (if I remember correctly the IDE controller wants 0x1f0-0x1f1 and some
> 0x3** ports). This generated some "Cannot allocate resource region ..
The I/O ports within 0x0-0xfff are somehow reserved for legacy ISA
devices (in the M1553 southbridge), if I remember the PCI spec correctly.
That will conflict with the PCI2PCI bridge anyway, if both claim PCI I/O
transactions for this range. I guess you have to relocate the PCI I/O
window of the PCI2PCI bridge.

> will remap" messages from kernel/pci-common.c. This remapping didn't
> happen. Should a proper DTS file prevent this issue? If not where is the
> remapping done (I didn't see it). For that reason I'm ignoring the
> pci-to-pci bridge for now.
AFAIK bridge windows are not relocated. The firmware should setup them
correctly. Also, you don't have to add the PCI2PCI bridge to the DTS,
if the bridge uses the standardized register set to define the I/O and
memory windows. A general rule (for PCI) is to only define the
information that cannot be probed by the kernel itself.

regards,

Gerhard
-- 
Nur bis 16.03.! DSL-Komplettanschluss inkl. WLAN-Modem für nur 
17,95 ¿/mtl. + 1 Monat gratis!* http://dsl.gmx.de/?ac=OM.AD.PD003K11308T4569a

Re: DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

> > I got the i8259 south bridge working now after adding an io_base_virt
> > offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> > the troubles to add ppc32 support to isa-bridge.c? The whole point of
> > the code is basically to remap the io memory to low addresses for these
> > 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> > systems with a i8259).
> pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
> if your board has only one PCI I/O space. It also sets isa_io_base to
> io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
> PCI I/O address 0x0. Isn't that the case for your board?
> 

Ah then perhaps that is my problem. I'm using my own pci implementation for Xilinx their plbv46 soft core. The soft core might be compatible with a generic ibm plb-pci bridge (sysdev/ppc44x_pci.c). Basically I'm doing something like which is done in powermac/pci.c e.g. creating the pci_controller and filling it with cfg_addr / cfg_data pointers, io ranges, resource ranges and so on. The data is obtained from the dts file but from some xilinx generated fields and doesn't have the generic ranges fields and some others. I guess it is time to fix this part of the DTS file.

Some other issue I had which might be related to my DTS file bugs is some i/o port conflict. The M1553 south bridge is just a peripheral on the ML510 primary pci bus there are no PCI slots connected to it. There are four other pci slots of which two are directly connected to the fpga (they are on the same bus as the M1553) and two are connected using a pci-to-pci bridge because they use 5V instead of 3.3V. The bridge chip wanted 0x0-0xfff while some south bridge devices wanted low addresses (if I remember correctly the IDE controller wants 0x1f0-0x1f1 and some 0x3** ports). This generated some "Cannot allocate resource region .. will remap" messages from kernel/pci-common.c. This remapping didn't happen. Should a proper DTS file prevent this issue? If not where is the remapping done (I didn't see it). For that reason I'm ignoring the pci-to-pci bridge for now.

Thanks,
Roderick Colenbrander
-- 
Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01

Re: DTS file PCI / i8259 for Xilinx ML510

[Gerhard Pircher]

-------- Original-Nachricht --------
> Datum: Sun, 15 Mar 2009 09:38:26 +0100
> Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> An: "Gerhard Pircher" <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
> Betreff: Re: DTS file PCI / i8259 for Xilinx ML510

> > > At some point in the file they create some (dummy?) pcie section in
> > > which they define a uli1575, an isa bus and attached to that isa bus
> > > a i8259. Is this the correct way of doing things? The i8259 driver
> > > seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also
> > > defined below but how are those mapped to the south bridge? I have
> > > seen some code in kernel/isa-bridge, is that code indeed responsible
> > > for setting up these ports?
> > Yes, the pcie node is the PCI host bridge node and the uli1571 node
> > acts as PCI2ISA bridge node. AFAIK their ranges properties are parsed
> > by pci_process_bridge_OF_ranges().
> > IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only
> > for now. The I/O addresses for the i8259 PIC are currently hardcoded
> > and setup (request_resource()) in sysdev/i8259.c.
> 
> I got the i8259 south bridge working now after adding an io_base_virt
> offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> the troubles to add ppc32 support to isa-bridge.c? The whole point of
> the code is basically to remap the io memory to low addresses for these
> 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> systems with a i8259).
pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
if your board has only one PCI I/O space. It also sets isa_io_base to
io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
PCI I/O address 0x0. Isn't that the case for your board?

> As far as I have seen it is only needed for i8259 interrupt controllers.
> Personally I think it would be better to pass a io base offset to
> i8259_setup or so. Or perhaps do some dts file parsing in i8259.c.
> I'm not sure what the proper layout would be for this in the dts file
> though.
I think adding an io base offset parameter to i8259_setup isn't the
right way to do it. I would expect other problems too, if ISA I/O space
isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more
experienced kernel developer can comment on this?

> With those changes I mentioned to i8259.c I got some PCI devices of my
> ali m1553 south bridge working. The code is ugly and I need to do
> cleanups. When it is done I will submit some patches.
IMHO that doesn't matter, as long as it helps people to understand your
problem. :-)

regards,

Gerhard

-- 
Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01

Re: DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

> > At some point in the file they create some (dummy?) pcie section in
> > which they define a uli1575, an isa bus and attached to that isa bus a
> > i8259. Is this the correct way of doing things? The i8259 driver seems
> > to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined
> > below but how are those mapped to the south bridge? I have seen some
> > code in kernel/isa-bridge, is that code indeed responsible for setting
> > up these ports?
> Yes, the pcie node is the PCI host bridge node and the uli1571 node acts
> as PCI2ISA bridge node. AFAIK their ranges properties are parsed by
> pci_process_bridge_OF_ranges().
> IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only
> for now. The I/O addresses for the i8259 PIC are currently hardcoded and
> setup (request_resource()) in sysdev/i8259.c.

I got the i8259 south bridge working now after adding an io_base_virt offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all the troubles to add ppc32 support to isa-bridge.c? The whole point of the code is basically to remap the io memory to low addresses for these 64-bit ppc systems (mainly freescale boards with a i8259 and pseries systems with a i8259). As far as I have seen it is only needed for i8259 interrupt controllers. Personally I think it would be better to pass a io base offset to i8259_setup or so. Or perhaps do some dts file parsing in i8259.c. I'm not sure what the proper layout would be for this in the dts file though.

With those changes I mentioned to i8259.c I got some PCI devices of my ali m1553 south bridge working. The code is ugly and I need to do cleanups. When it is done I will submit some patches.

Regards,
Roderick Colenbrander
-- 
Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01

Re: DTS file PCI / i8259 for Xilinx ML510

[Gerhard Pircher]

-------- Original-Nachricht --------
> Datum: Thu, 12 Mar 2009 11:32:19 +0100
> Von: "Roderick Colenbrander" <thunderbird2k@gmx.net>
> An: linuxppc-dev@ozlabs.org
> Betreff: DTS file PCI / i8259 for Xilinx ML510

> ...
> The freescale boards define the pci bus like below and connect ULI M1575
> peripherals to the i8259 controller. Regarding the entries in the pci
> interrupt-map what does the fourth column mean? According to source code
> it means 'interrupt specifier' but what does it mean? In a lot of cases
> it is 1.
IIRC the fourth column is the PCI interrupt line (INTA..D = 1..4). The
Freescale boards may have a number of onboard PCI devices, which are
usually connected to a single PCI interrupt line only (INTA). In this
case a PCI unit address (1. column) is specified only once within the
interrupt-map table and the corresponding interrupt specifier is set
to 1 for INTA.
On the other side PCI slots can have up to four entries (INTA..D) for a
specific PCI unit address.

Please take a look at this document here:
http://playground.sun.com/1275/practice/imap/imap0_9d.html

> Further I believe in this case the entries behind 'mpic' correspond to
> the inta/b/c/d lines, is that correct? On my board inta is connected to
> interrupt 5 (intb=4, intc=3, intd=2) of the xilinx intc, so I would need
> to use those numbers there for my board?
No, the last two columns specify the real interrupt (IRQ line, level or
edge triggered). They're values depend on the type of interrupt
controller and its #interrupt-cells property.

> 	pci0: pcie@f8008000
> 	{
> 		device_type = "pci";
> 		#interrupt-cells = <1>;
> 		#size-cells = <2>;
> 		#address-cells = <3>;
> 		..
> 		..
> 		interrupt-map-mask = <0xff00 0 0 7>;
> 		interrupt-map = <
> 			/* IDSEL 0x11 func 0 - PCI slot 1 */
> 			0x8800 0 0 1 &mpic 2 1
> 			0x8800 0 0 2 &mpic 3 1
> 			0x8800 0 0 3 &mpic 4 1
> 			0x8800 0 0 4 &mpic 1 1
> 			..
> 			..
> 			// IDSEL 0x1c  USB
> 			0xe000 0 0 1 &i8259 12 2
> 			0xe100 0 0 2 &i8259 9 2
> 		>;
> 
> At some point in the file they create some (dummy?) pcie section in
> which they define a uli1575, an isa bus and attached to that isa bus a
> i8259. Is this the correct way of doing things? The i8259 driver seems
> to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined
> below but how are those mapped to the south bridge? I have seen some
> code in kernel/isa-bridge, is that code indeed responsible for setting
> up these ports?
Yes, the pcie node is the PCI host bridge node and the uli1571 node acts
as PCI2ISA bridge node. AFAIK their ranges properties are parsed by
pci_process_bridge_OF_ranges().
IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only
for now. The I/O addresses for the i8259 PIC are currently hardcoded and
setup (request_resource()) in sysdev/i8259.c.

> 		pcie@0 {
> 			reg = <0 0 0 0 0>;
> 			#size-cells = <2>;
> 			#address-cells = <3>;
> 			device_type = "pci";
> 			ranges = <0x02000000 0x0 0x80000000
> 				  0x02000000 0x0 0x80000000
> 				  0x0 0x20000000
> 
> 				  0x01000000 0x0 0x00000000
> 				  0x01000000 0x0 0x00000000
> 				  0x0 0x00100000>;
> 			uli1575@0 {
> 				reg = <0 0 0 0 0>;
> 				#size-cells = <2>;
> 				#address-cells = <3>;
> 				ranges = <0x02000000 0x0 0x80000000
> 					  0x02000000 0x0 0x80000000
> 					  0x0 0x20000000
> 					  0x01000000 0x0 0x00000000
> 					  0x01000000 0x0 0x00000000
> 					  0x0 0x00100000>;
> 				isa@1e {
> 					device_type = "isa";
> 					#interrupt-cells = <2>;
> 					#size-cells = <1>;
> 					#address-cells = <2>;
> 					reg = <0xf000 0 0 0 0>;
> 					ranges = <1 0 0x01000000 0 0
> 						  0x00001000>;
> 					interrupt-parent = <&i8259>;
> 
> 					i8259: interrupt-controller@20 {
> 						reg = <1 0x20 2
> 						       1 0xa0 2
> 						       1 0x4d0 2>;
> 						interrupt-controller;
> 						device_type = "interrupt-controller";
> 						#address-cells = <0>;
> 						#interrupt-cells = <2>;
> 						compatible = "chrp,iic";
> 						interrupts = <9 2>;
> 						interrupt-parent = <&mpic>;
> 					};
> 				};
> 			};
> 		};
> 
> Thanks,
> Roderick Colenbrander

best regards,

Gerhard
-- 
Nur bis 16.03.! DSL-Komplettanschluss inkl. WLAN-Modem für nur 
17,95 ¿/mtl. + 1 Monat gratis!* http://dsl.gmx.de/?ac=OM.AD.PD003K11308T4569a

DTS file PCI / i8259 for Xilinx ML510

[Roderick Colenbrander]

Hi,

I'm working on adding PCI support for the Xilinx ML510 FPGA board. The board contains a Virtex-5 FPGA (containing two PPC440 cores), a ALI M1533 pci south bridge, pci slots and more.

I have written code (inspired by the powermac pci code) which initializes the pci soft-core which is in my FPGA. Linux now sees all my pci devices in /proc/bus/pci/devices and the kernel assigned io memory / io port ranges for each device.

Right now I'm working on irq assignment. The FPGA contains a xilinx interrupt controller to which a uart, ethernet, pci slots (inta/b/c/d) and my ALI south bridge (it has its own irq input on the xilinx intc) are connected. The ALI south bridge itself contains a i8259 interrupt controller to which internal USB, IDE and other peripherals are connected.

The problems I'm having are with the DTS file. I'm not fully sure what to put in there and what the kernel is doing with the PCI info. As a start point I looked at mpc8641_hpcn.dts / mpc8572.dts and other freescale files as their boards also contain a i8259 south bridge but this time connected to a ULI M1575 south bridge (it is the successor to the ALI M1533).

The freescale boards define the pci bus like below and connect ULI M1575 peripherals to the i8259 controller. Regarding the entries in the pci interrupt-map what does the fourth column mean? According to source code it means 'interrupt specifier' but what does it mean? In a lot of cases it is 1. Further I believe in this case the entries behind 'mpic' correspond to the inta/b/c/d lines, is that correct? On my board inta is connected to interrupt 5 (intb=4, intc=3, intd=2) of the xilinx intc, so I would need to use those numbers there for my board?

	pci0: pcie@f8008000
	{
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		..
		..
		interrupt-map-mask = <0xff00 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0 0 1 &mpic 2 1
			0x8800 0 0 2 &mpic 3 1
			0x8800 0 0 3 &mpic 4 1
			0x8800 0 0 4 &mpic 1 1
			..
			..
			// IDSEL 0x1c  USB
			0xe000 0 0 1 &i8259 12 2
			0xe100 0 0 2 &i8259 9 2
		>;

At some point in the file they create some (dummy?) pcie section in which they define a uli1575, an isa bus and attached to that isa bus a i8259. Is this the correct way of doing things? The i8259 driver seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined below but how are those mapped to the south bridge? I have seen some code in kernel/isa-bridge, is that code indeed responsible for setting up these ports?

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0x80000000
					  0x02000000 0x0 0x80000000
					  0x0 0x20000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <1 0x20 2
						       1 0xa0 2
						       1 0x4d0 2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};
				};
			};
		};

Thanks,
Roderick Colenbrander
-- 
Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01