[git-pull -tip][PATCH 0/10] few cpufeature additions and users

[git-pull -tip][PATCH 0/10] few cpufeature additions and users

[Jaswinder Singh Rajput]

Here is first patchset of cpufeatures I will release another cpufeature
patchset after these are applied.

The following changes since commit 3e0c373749d7eb5b354ac0b043f2b2cdf84eefef:
  Yinghai Lu (1):
        x86: clean up and fix setup_clear/force_cpu_cap handling

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/jaswinder/linux-2.6-cpu.git x86/cpufeature

Jaswinder Singh Rajput (10):
      x86: Add cpufeature for Processor Name
      x86: get_model_name() user of X86_FEATURE_PNAME
      x86: Add cpufeatures for Advanced Power Management
      x86: check_powernow() for K7 user of Advanced Power Management features
      x86: check_powernow() for K8 and later user of Advanced Power Management features
      x86: early_init_intel() user of Advanced Power Management features
      x86: early_init_amd() user of Advanced Power Management features
      x86: Add cpufeature for Microcode update
      x86 : collect_cpu_info() of Intel user of Microcode feature
      x86 : collect_cpu_info() of AMD user of Microcode feature

 arch/x86/include/asm/cpufeature.h         |   20 ++++++++++++++++----
 arch/x86/kernel/cpu/amd.c                 |   21 ++++++++++++++++-----
 arch/x86/kernel/cpu/common.c              |   22 +++++++++++++++++-----
 arch/x86/kernel/cpu/cpufreq/powernow-k7.c |   16 ++++++----------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.c |   16 ++++++++--------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.h |    4 ----
 arch/x86/kernel/cpu/intel.c               |   19 +++++++++++++++----
 arch/x86/kernel/microcode_amd.c           |    3 ++-
 arch/x86/kernel/microcode_intel.c         |    4 ++--
 9 files changed, 82 insertions(+), 43 deletions(-)

Complete diff:

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..1fd6770 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS		10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,6 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -153,8 +152,10 @@
  * Auxiliary flags: Linux defined - For features scattered in various
  * CPUID levels like 0x6, 0xA etc
  */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
+#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
+#define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -163,6 +164,17 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx			*/
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperatue sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7e4a459..ca133a0 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -334,13 +334,12 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 	early_init_amd_mc(c);
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-	}
 
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
@@ -353,6 +352,15 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 #endif
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	if (c->x86 >= 0x10) {				/* fam10h+	*/
+		/* setting microcode update feature			*/
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+	}
+}
+
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
@@ -372,6 +380,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 	}
 #endif
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_amd(c);
 
 	/*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e7fd5c4..a428b36 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -352,7 +352,7 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 	unsigned int *v;
 	char *p, *q;
 
-	if (c->extended_cpuid_level < 0x80000004)
+	if (!cpu_has(c, X86_FEATURE_PNAME))
 		return;
 
 	v = (unsigned int *)c->x86_model_id;
@@ -563,6 +563,22 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * Processor Name / Brand String
+	 * (Function 8000_0002h, 8000_0003h, 8000_0004h)
+	 * Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to
+	 * 16 ASCII bytes of the processor name in the EAX, EBX, ECX and EDX
+	 * registers.
+	 */
+	if (c->extended_cpuid_level >= 0x80000004)
+		set_cpu_cap(c, X86_FEATURE_PNAME);
+
+	/* Advanced Power Management (Function 8000_0007h), edx */
+	if (c->extended_cpuid_level >= 0x80000007){
+		c->x86_capability[9] = cpuid_edx(0x80000007);
+		c->x86_power = cpuid_edx(0x80000007);
+	}
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		u32 eax = cpuid_eax(0x80000008);
 
@@ -573,10 +589,6 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
 		c->x86_phys_bits = 36;
 #endif
-
-	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
-
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index 3c28ccd..1f35474 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -118,7 +118,6 @@ static int check_fsb(unsigned int fsbspeed)
 static int check_powernow(void)
 {
 	struct cpuinfo_x86 *c = &cpu_data(0);
-	unsigned int maxei, eax, ebx, ecx, edx;
 
 	if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
 #ifdef MODULE
@@ -128,9 +127,8 @@ static int check_powernow(void)
 		return 0;
 	}
 
-	/* Get maximum capabilities */
-	maxei = cpuid_eax(0x80000000);
-	if (maxei < 0x80000007) {	/* Any powernow info ? */
+	/* Advanced Power Management capabilities */
+	if (c->x86_capability[9]) {	/* Any powernow info ? */
 #ifdef MODULE
 		printk(KERN_INFO PFX "No powernow capabilities detected\n");
 #endif
@@ -143,23 +141,21 @@ static int check_powernow(void)
 		have_a0 = 1;
 	}
 
-	cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
-
 	/* Check we can actually do something before we say anything.*/
-	if (!(edx & (1 << 1 | 1 << 2)))
+	if (!cpu_has(c, X86_FEATURE_FID) && !cpu_has(c, X86_FEATURE_VID))
 		return 0;
 
 	printk(KERN_INFO PFX "PowerNOW! Technology present. Can scale: ");
 
-	if (edx & 1 << 1) {
+	if (cpu_has(c, X86_FEATURE_FID)) {
 		printk("frequency");
 		can_scale_bus = 1;
 	}
 
-	if ((edx & (1 << 1 | 1 << 2)) == 0x6)
+	if (cpu_has(c, X86_FEATURE_FID) && cpu_has(c, X86_FEATURE_VID))
 		printk(" and ");
 
-	if (edx & 1 << 2) {
+	if (cpu_has(c, X86_FEATURE_VID)) {
 		printk("voltage");
 		can_scale_vid = 1;
 	}
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 4709ead..b3f4ec8 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -512,8 +512,9 @@ static int core_voltage_post_transition(struct powernow_k8_data *data,
 
 static int check_supported_cpu(unsigned int cpu)
 {
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	cpumask_t oldmask;
-	u32 eax, ebx, ecx, edx;
+	u32 eax;
 	unsigned int rc = 0;
 
 	oldmask = current->cpus_allowed;
@@ -540,23 +541,22 @@ static int check_supported_cpu(unsigned int cpu)
 			goto out;
 		}
 
-		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
-		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
+		/* Advanced Power Management capabilities */
+		if (c->x86_capability[9]) {
 			printk(KERN_INFO PFX
 			       "No frequency change capabilities detected\n");
 			goto out;
 		}
 
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & P_STATE_TRANSITION_CAPABLE)
-			!= P_STATE_TRANSITION_CAPABLE) {
+		/* check for frequncy and volatage ID control support */
+		if (!cpu_has(c, X86_FEATURE_FID) &&
+			!cpu_has(c, X86_FEATURE_VID)) {
 			printk(KERN_INFO PFX
 				"Power state transitions not supported\n");
 			goto out;
 		}
 	} else { /* must be a HW Pstate capable processor */
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
+		if (cpu_has(c, X86_FEATURE_HWPSTATE))
 			cpu_family = CPU_HW_PSTATE;
 		else
 			goto out;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698f..4dfe414 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -64,9 +64,6 @@ struct powernow_k8_data {
 #define CPUID_XMOD_REV_MASK		0x000c0000
 #define CPUID_XFAM_10H			0x00100000	/* family 0x10 */
 #define CPUID_USE_XFAM_XMOD		0x00000f00
-#define CPUID_GET_MAX_CAPABILITIES	0x80000000
-#define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
-#define P_STATE_TRANSITION_CAPABLE	6
 
 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
@@ -101,7 +98,6 @@ struct powernow_k8_data {
 
 
 /* Hardware Pstate _PSS and MSR definitions */
-#define USE_HW_PSTATE		0x00000080
 #define HW_PSTATE_MASK 		0x00000007
 #define HW_PSTATE_VALID_MASK 	0x80000000
 #define HW_PSTATE_MAX_MASK	0x000000f0
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7437fa1..ddb26f2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,14 +61,14 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states.
 	 *
 	 * It is also reliable across cores and sockets. (but not across
 	 * cabinets - we turn it off in that case explicitly.)
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
 		sched_clock_stable = 1;
@@ -303,10 +303,21 @@ static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 	}
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	/* setting microcode update feature				*/
+	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+}
+
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_intel(c);
 
 	intel_workarounds(c);
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 453b579..1178638 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -90,7 +90,8 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 	u32 dummy;
 
 	memset(csig, 0, sizeof(*csig));
-	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+	if (c->x86_vendor != X86_VENDOR_AMD ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not "
 		       "supported\n", cpu, c->x86);
 		return -1;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 149b9ec..c2e128e 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,8 +161,8 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 
 	memset(csig, 0, sizeof(*csig));
 
-	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
-	    cpu_has(c, X86_FEATURE_IA64)) {
+	if (c->x86_vendor != X86_VENDOR_INTEL ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_ERR "microcode: CPU%d not a capable Intel "
 			"processor\n", cpu_num);
 		return -1;

[PATCH 1/10 -tip] x86: Add cpufeature for Processor Name

[Jaswinder Singh Rajput]

Processor Name / Brand String (Function 8000_0002h, 8000_0003h, 8000_0004h)
Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to 16 ASCII
bytes of the processor name in the EAX, EBX, ECX and EDX registers.

X86_FEATURE_PNAME will be useful for displaying MSRs like AMD:
MSRC001_00[35:30] Processor Name String Registers

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    5 +++--
 arch/x86/kernel/cpu/common.c      |   10 ++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..e1a4cc4 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -153,8 +153,9 @@
  * Auxiliary flags: Linux defined - For features scattered in various
  * CPUID levels like 0x6, 0xA etc
  */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
+#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e7fd5c4..542684c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -563,6 +563,16 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * Processor Name / Brand String
+	 * (Function 8000_0002h, 8000_0003h, 8000_0004h)
+	 * Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to
+	 * 16 ASCII bytes of the processor name in the EAX, EBX, ECX and EDX
+	 * registers.
+	 */
+	if (c->extended_cpuid_level >= 0x80000004)
+		set_cpu_cap(c, X86_FEATURE_PNAME);
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		u32 eax = cpuid_eax(0x80000008);
 
-- 
1.6.0.6

[PATCH 2/10 -tip] x86: get_model_name() user of X86_FEATURE_PNAME

[Jaswinder Singh Rajput]

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 542684c..3994feb 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -352,7 +352,7 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 	unsigned int *v;
 	char *p, *q;
 
-	if (c->extended_cpuid_level < 0x80000004)
+	if (!cpu_has(c, X86_FEATURE_PNAME))
 		return;
 
 	v = (unsigned int *)c->x86_model_id;
-- 
1.6.0.6

[PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

Add Advanced Power Management (Function 8000_0007h), edx

/proc/cpuinfo (before)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname

/proc/cpuinfo (after)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
ts ttp htc stc 100mhzsteps hwpstate constant_tsc

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |   14 ++++++++++++--
 arch/x86/kernel/cpu/common.c      |   10 ++++++----
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e1a4cc4..d37ab0f 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS		10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,6 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -164,6 +163,17 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx			*/
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperatue sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3994feb..a428b36 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -573,6 +573,12 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	if (c->extended_cpuid_level >= 0x80000004)
 		set_cpu_cap(c, X86_FEATURE_PNAME);
 
+	/* Advanced Power Management (Function 8000_0007h), edx */
+	if (c->extended_cpuid_level >= 0x80000007){
+		c->x86_capability[9] = cpuid_edx(0x80000007);
+		c->x86_power = cpuid_edx(0x80000007);
+	}
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		u32 eax = cpuid_eax(0x80000008);
 
@@ -583,10 +589,6 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
 		c->x86_phys_bits = 36;
 #endif
-
-	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
-
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
-- 
1.6.0.6

[PATCH 4/10 -tip] x86: check_powernow() for K7 user of Advanced Power Management features

[Jaswinder Singh Rajput]

use X86_FEATURE_FID and X86_FEATURE_VID to determine K7 PowerNOW.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/cpufreq/powernow-k7.c |   16 ++++++----------
 1 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index 3c28ccd..1f35474 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -118,7 +118,6 @@ static int check_fsb(unsigned int fsbspeed)
 static int check_powernow(void)
 {
 	struct cpuinfo_x86 *c = &cpu_data(0);
-	unsigned int maxei, eax, ebx, ecx, edx;
 
 	if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
 #ifdef MODULE
@@ -128,9 +127,8 @@ static int check_powernow(void)
 		return 0;
 	}
 
-	/* Get maximum capabilities */
-	maxei = cpuid_eax(0x80000000);
-	if (maxei < 0x80000007) {	/* Any powernow info ? */
+	/* Advanced Power Management capabilities */
+	if (c->x86_capability[9]) {	/* Any powernow info ? */
 #ifdef MODULE
 		printk(KERN_INFO PFX "No powernow capabilities detected\n");
 #endif
@@ -143,23 +141,21 @@ static int check_powernow(void)
 		have_a0 = 1;
 	}
 
-	cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
-
 	/* Check we can actually do something before we say anything.*/
-	if (!(edx & (1 << 1 | 1 << 2)))
+	if (!cpu_has(c, X86_FEATURE_FID) && !cpu_has(c, X86_FEATURE_VID))
 		return 0;
 
 	printk(KERN_INFO PFX "PowerNOW! Technology present. Can scale: ");
 
-	if (edx & 1 << 1) {
+	if (cpu_has(c, X86_FEATURE_FID)) {
 		printk("frequency");
 		can_scale_bus = 1;
 	}
 
-	if ((edx & (1 << 1 | 1 << 2)) == 0x6)
+	if (cpu_has(c, X86_FEATURE_FID) && cpu_has(c, X86_FEATURE_VID))
 		printk(" and ");
 
-	if (edx & 1 << 2) {
+	if (cpu_has(c, X86_FEATURE_VID)) {
 		printk("voltage");
 		can_scale_vid = 1;
 	}
-- 
1.6.0.6

[PATCH 5/10 -tip] x86: check_powernow() for K8 and later user of Advanced Power Management features

[Jaswinder Singh Rajput]

use X86_FEATURE_FID, X86_FEATURE_VID and X86_FEATURE_HWPSTATE
to determine K8 and later PowerNOW.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/cpufreq/powernow-k8.c |   16 ++++++++--------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.h |    4 ----
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 4709ead..b3f4ec8 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -512,8 +512,9 @@ static int core_voltage_post_transition(struct powernow_k8_data *data,
 
 static int check_supported_cpu(unsigned int cpu)
 {
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	cpumask_t oldmask;
-	u32 eax, ebx, ecx, edx;
+	u32 eax;
 	unsigned int rc = 0;
 
 	oldmask = current->cpus_allowed;
@@ -540,23 +541,22 @@ static int check_supported_cpu(unsigned int cpu)
 			goto out;
 		}
 
-		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
-		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
+		/* Advanced Power Management capabilities */
+		if (c->x86_capability[9]) {
 			printk(KERN_INFO PFX
 			       "No frequency change capabilities detected\n");
 			goto out;
 		}
 
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & P_STATE_TRANSITION_CAPABLE)
-			!= P_STATE_TRANSITION_CAPABLE) {
+		/* check for frequncy and volatage ID control support */
+		if (!cpu_has(c, X86_FEATURE_FID) &&
+			!cpu_has(c, X86_FEATURE_VID)) {
 			printk(KERN_INFO PFX
 				"Power state transitions not supported\n");
 			goto out;
 		}
 	} else { /* must be a HW Pstate capable processor */
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
+		if (cpu_has(c, X86_FEATURE_HWPSTATE))
 			cpu_family = CPU_HW_PSTATE;
 		else
 			goto out;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698f..4dfe414 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -64,9 +64,6 @@ struct powernow_k8_data {
 #define CPUID_XMOD_REV_MASK		0x000c0000
 #define CPUID_XFAM_10H			0x00100000	/* family 0x10 */
 #define CPUID_USE_XFAM_XMOD		0x00000f00
-#define CPUID_GET_MAX_CAPABILITIES	0x80000000
-#define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
-#define P_STATE_TRANSITION_CAPABLE	6
 
 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
@@ -101,7 +98,6 @@ struct powernow_k8_data {
 
 
 /* Hardware Pstate _PSS and MSR definitions */
-#define USE_HW_PSTATE		0x00000080
 #define HW_PSTATE_MASK 		0x00000007
 #define HW_PSTATE_VALID_MASK 	0x80000000
 #define HW_PSTATE_MAX_MASK	0x000000f0
-- 
1.6.0.6

[PATCH 6/10 -tip] x86: early_init_intel() user of Advanced Power Management features

[Jaswinder Singh Rajput]

use X86_FEATURE_CONSTANT_TSC to determine TSC Invariance

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/intel.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7437fa1..62130a0 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,14 +61,14 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states.
 	 *
 	 * It is also reliable across cores and sockets. (but not across
 	 * cabinets - we turn it off in that case explicitly.)
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
 		sched_clock_stable = 1;
-- 
1.6.0.6

[PATCH 7/10 -tip] x86: early_init_amd() user of Advanced Power Management features

[Jaswinder Singh Rajput]

use X86_FEATURE_CONSTANT_TSC to determine TSC Invariant

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/amd.c |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7e4a459..1d36ac4 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -334,13 +334,12 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 	early_init_amd_mc(c);
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-	}
 
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
-- 
1.6.0.6

[PATCH 8/10 -tip] x86: Add cpufeature for Microcode update

[Jaswinder Singh Rajput]

Setting microcode update feature to friendly access of UCODE MSRs like:
1. IA32_PLATFORM_ID (Intel)
2. IA32_UCODE_WRITE (Intel)
3. IA32_UCODE_REV (Intel)
4. MSR_AMD64_PATCH_LEVEL (AMD)
5. MSR_AMD64_PATCH_LOADER (AMD)

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |   12 ++++++++++++
 arch/x86/kernel/cpu/intel.c       |   11 +++++++++++
 3 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index d37ab0f..1fd6770 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -155,6 +155,7 @@
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
 #define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
 #define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
+#define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1d36ac4..ca133a0 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,15 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 #endif
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	if (c->x86 >= 0x10) {				/* fam10h+	*/
+		/* setting microcode update feature			*/
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+	}
+}
+
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
@@ -371,6 +380,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 	}
 #endif
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_amd(c);
 
 	/*
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 62130a0..ddb26f2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -303,10 +303,21 @@ static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 	}
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	/* setting microcode update feature				*/
+	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+}
+
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_intel(c);
 
 	intel_workarounds(c);
-- 
1.6.0.6

[PATCH 9/10 -tip] x86: collect_cpu_info() of Intel user of Microcode feature

[Jaswinder Singh Rajput]

use X86_FEATURE_MICROCODE to determine microcode update

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/microcode_intel.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 149b9ec..c2e128e 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,8 +161,8 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 
 	memset(csig, 0, sizeof(*csig));
 
-	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
-	    cpu_has(c, X86_FEATURE_IA64)) {
+	if (c->x86_vendor != X86_VENDOR_INTEL ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_ERR "microcode: CPU%d not a capable Intel "
 			"processor\n", cpu_num);
 		return -1;
-- 
1.6.0.6

[PATCH 10/10 -tip] x86: collect_cpu_info() of AMD user of Microcode feature

[Jaswinder Singh Rajput]

use X86_FEATURE_MICROCODE to determine microcode update

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/microcode_amd.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 453b579..1178638 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -90,7 +90,8 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 	u32 dummy;
 
 	memset(csig, 0, sizeof(*csig));
-	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+	if (c->x86_vendor != X86_VENDOR_AMD ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not "
 		       "supported\n", cpu, c->x86);
 		return -1;
-- 
1.6.0.6

Re: [PATCH 5/10 -tip] x86: check_powernow() for K8 and later user of Advanced Power Management features

[Ingo Molnar]

* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> -		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
> -		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
> +		/* Advanced Power Management capabilities */
> +		if (c->x86_capability[9]) {
>  			printk(KERN_INFO PFX
>  			       "No frequency change capabilities detected\n");
>  			goto out;
>  		}

How is the new check equivalent to the old one? It isnt and this is 
a bug.

Also, open-coding x86_capability[9] like that is quite unclean. Were 
we ever to reorder those bits internally, this could would break.

But i see what you are trying to do. A better method might be to add 
a new helper:

+#define X86_FEATURE_TS         (9*32+ 0) /* Temperatue sensor          */
+#define X86_FEATURE_FID                (9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID                (9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP                (9*32+ 3) /* Thermal trip   	*/
+#define X86_FEATURE_HTC                (9*32+ 4) /* Hardware thermal control   */
+#define X86_FEATURE_STC                (9*32+ 5) /* Software thermal control   */
+#define X86_FEATURE_100MHZSTEPS        (9*32+ 6) /* 100 MHz multiplier control */
+#define X86_FEATURE_HWPSTATE   (9*32+ 7) /* Hardware P-State control   */
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks  */

... to represent the 'is any of these set' property.

[ btw., there's a typo in the X86_FEATURE_TS comment above ]

	Ingo

Re: [PATCH 5/10 -tip] x86: check_powernow() for K8 and later user of Advanced Power Management features

[Jaswinder Singh Rajput]

On Tue, 2009-05-12 at 19:48 +0200, Ingo Molnar wrote:
> * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:
> 
> > -		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
> > -		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
> > +		/* Advanced Power Management capabilities */
> > +		if (c->x86_capability[9]) {
> >  			printk(KERN_INFO PFX
> >  			       "No frequency change capabilities detected\n");
> >  			goto out;
> >  		}
> 
> How is the new check equivalent to the old one? It isnt and this is 
> a bug.
> 
> Also, open-coding x86_capability[9] like that is quite unclean. Were 
> we ever to reorder those bits internally, this could would break.
> 
> But i see what you are trying to do. A better method might be to add 
> a new helper:
> 
> +#define X86_FEATURE_TS         (9*32+ 0) /* Temperatue sensor          */
> +#define X86_FEATURE_FID                (9*32+ 1) /* Frequency ID control	*/
> +#define X86_FEATURE_VID                (9*32+ 2) /* Voltage ID control		*/
> +#define X86_FEATURE_TTP                (9*32+ 3) /* Thermal trip   	*/
> +#define X86_FEATURE_HTC                (9*32+ 4) /* Hardware thermal control   */
> +#define X86_FEATURE_STC                (9*32+ 5) /* Software thermal control   */
> +#define X86_FEATURE_100MHZSTEPS        (9*32+ 6) /* 100 MHz multiplier control */
> +#define X86_FEATURE_HWPSTATE   (9*32+ 7) /* Hardware P-State control   */
> +#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks  */
> 
> ... to represent the 'is any of these set' property.
> 

Yes, I was also thinking about adding this helper cpufeature, may be
that's why I made above mistake ;-)

> [ btw., there's a typo in the X86_FEATURE_TS comment above ]
> 

Ok I will send updated patches and new pull request :-)


[PATCH-tip] x86: check_powernow() for K8 and later user of Advanced Power Management features

use X86_FEATURE_POWER_MGMT, X86_FEATURE_FID, X86_FEATURE_VID and
X86_FEATURE_HWPSTATE to determine K8 and later PowerNOW.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/cpufreq/powernow-k8.c |   16 ++++++++--------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.h |    4 ----
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 4709ead..c9869fd 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -512,8 +512,9 @@ static int core_voltage_post_transition(struct powernow_k8_data *data,
 
 static int check_supported_cpu(unsigned int cpu)
 {
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	cpumask_t oldmask;
-	u32 eax, ebx, ecx, edx;
+	u32 eax;
 	unsigned int rc = 0;
 
 	oldmask = current->cpus_allowed;
@@ -540,23 +541,22 @@ static int check_supported_cpu(unsigned int cpu)
 			goto out;
 		}
 
-		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
-		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
+		/* Advanced Power Management capabilities */
+		if (!cpu_has(c, X86_FEATURE_POWER_MGMT)) {
 			printk(KERN_INFO PFX
 			       "No frequency change capabilities detected\n");
 			goto out;
 		}
 
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & P_STATE_TRANSITION_CAPABLE)
-			!= P_STATE_TRANSITION_CAPABLE) {
+		/* check for frequncy and volatage ID control support */
+		if (!cpu_has(c, X86_FEATURE_FID) &&
+			!cpu_has(c, X86_FEATURE_VID)) {
 			printk(KERN_INFO PFX
 				"Power state transitions not supported\n");
 			goto out;
 		}
 	} else { /* must be a HW Pstate capable processor */
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
+		if (cpu_has(c, X86_FEATURE_HWPSTATE))
 			cpu_family = CPU_HW_PSTATE;
 		else
 			goto out;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698f..4dfe414 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -64,9 +64,6 @@ struct powernow_k8_data {
 #define CPUID_XMOD_REV_MASK		0x000c0000
 #define CPUID_XFAM_10H			0x00100000	/* family 0x10 */
 #define CPUID_USE_XFAM_XMOD		0x00000f00
-#define CPUID_GET_MAX_CAPABILITIES	0x80000000
-#define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
-#define P_STATE_TRANSITION_CAPABLE	6
 
 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
@@ -101,7 +98,6 @@ struct powernow_k8_data {
 
 
 /* Hardware Pstate _PSS and MSR definitions */
-#define USE_HW_PSTATE		0x00000080
 #define HW_PSTATE_MASK 		0x00000007
 #define HW_PSTATE_VALID_MASK 	0x80000000
 #define HW_PSTATE_MAX_MASK	0x000000f0
-- 
1.6.0.6

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Tue, 2009-05-12 at 21:09 +0530, Jaswinder Singh Rajput wrote:
> Add Advanced Power Management (Function 8000_0007h), edx
> 
> /proc/cpuinfo (before)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> 
> /proc/cpuinfo (after)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> ts ttp htc stc 100mhzsteps hwpstate constant_tsc
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> ---

New patch after adding helper cpufeature for Advanced Power Management
availability and fixing typo.

[PATCH -tip] x86: Add cpufeatures for Advanced Power Management

Add Advanced Power Management (Function 8000_0007h), edx

/proc/cpuinfo (before)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname

/proc/cpuinfo (after)
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
ts ttp htc stc 100mhzsteps hwpstate constant_tsc

Also added helper cpufeature to check Advanced Power Management is available.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/include/asm/cpufeature.h |   15 +++++++++++++--
 arch/x86/kernel/cpu/common.c      |   16 ++++++++++++----
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e1a4cc4..c4e2e39 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS		10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,7 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
+#define X86_FEATURE_POWER_MGMT	(3*32+ 8) /* Advanced Power Management */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -164,6 +164,17 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx			*/
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperature sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3994feb..c98ade3 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -573,6 +573,18 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	if (c->extended_cpuid_level >= 0x80000004)
 		set_cpu_cap(c, X86_FEATURE_PNAME);
 
+	/* Advanced Power Management (Function 8000_0007h), edx */
+	if (c->extended_cpuid_level >= 0x80000007) {
+		c->x86_capability[9] = cpuid_edx(0x80000007);
+		c->x86_power = cpuid_edx(0x80000007);
+
+		/*
+		 * Adding helper cpufeature to check the availability of
+		 * Advanced Power Management (Function 8000_0007h), edx
+		 */
+		set_cpu_cap(c, X86_FEATURE_POWER_MGMT);
+	}
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		u32 eax = cpuid_eax(0x80000008);
 
@@ -583,10 +595,6 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
 		c->x86_phys_bits = 36;
 #endif
-
-	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
-
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
-- 
1.6.0.6

Re: [PATCH 4/10 -tip] x86: check_powernow() for K7 user of Advanced Power Management features

[Jaswinder Singh Rajput]

On Tue, 2009-05-12 at 21:10 +0530, Jaswinder Singh Rajput wrote:
> use X86_FEATURE_FID and X86_FEATURE_VID to determine K7 PowerNOW.
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> ---
>  arch/x86/kernel/cpu/cpufreq/powernow-k7.c |   16 ++++++----------
>  1 files changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
> index 3c28ccd..1f35474 100644
> --- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
> +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
> @@ -118,7 +118,6 @@ static int check_fsb(unsigned int fsbspeed)
>  static int check_powernow(void)
>  {
>  	struct cpuinfo_x86 *c = &cpu_data(0);
> -	unsigned int maxei, eax, ebx, ecx, edx;
>  
>  	if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
>  #ifdef MODULE
> @@ -128,9 +127,8 @@ static int check_powernow(void)
>  		return 0;
>  	}
>  
> -	/* Get maximum capabilities */
> -	maxei = cpuid_eax(0x80000000);
> -	if (maxei < 0x80000007) {	/* Any powernow info ? */
> +	/* Advanced Power Management capabilities */
> +	if (c->x86_capability[9]) {	/* Any powernow info ? */

[PATCH -tip] x86: check_powernow() for K7 user of Advanced Power Management features

use X86_FEATURE_POWER_MGMT, X86_FEATURE_FID and X86_FEATURE_VID
to determine K7 PowerNOW.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/cpufreq/powernow-k7.c |   16 ++++++----------
 1 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index 3c28ccd..965f235 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -118,7 +118,6 @@ static int check_fsb(unsigned int fsbspeed)
 static int check_powernow(void)
 {
 	struct cpuinfo_x86 *c = &cpu_data(0);
-	unsigned int maxei, eax, ebx, ecx, edx;
 
 	if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
 #ifdef MODULE
@@ -128,9 +127,8 @@ static int check_powernow(void)
 		return 0;
 	}
 
-	/* Get maximum capabilities */
-	maxei = cpuid_eax(0x80000000);
-	if (maxei < 0x80000007) {	/* Any powernow info ? */
+	/* Advanced Power Management capabilities */
+	if (!cpu_has(c, X86_FEATURE_POWER_MGMT)) {	/* Any powernow info */
 #ifdef MODULE
 		printk(KERN_INFO PFX "No powernow capabilities detected\n");
 #endif
@@ -143,23 +141,21 @@ static int check_powernow(void)
 		have_a0 = 1;
 	}
 
-	cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
-
 	/* Check we can actually do something before we say anything.*/
-	if (!(edx & (1 << 1 | 1 << 2)))
+	if (!cpu_has(c, X86_FEATURE_FID) && !cpu_has(c, X86_FEATURE_VID))
 		return 0;
 
 	printk(KERN_INFO PFX "PowerNOW! Technology present. Can scale: ");
 
-	if (edx & 1 << 1) {
+	if (cpu_has(c, X86_FEATURE_FID)) {
 		printk("frequency");
 		can_scale_bus = 1;
 	}
 
-	if ((edx & (1 << 1 | 1 << 2)) == 0x6)
+	if (cpu_has(c, X86_FEATURE_FID) && cpu_has(c, X86_FEATURE_VID))
 		printk(" and ");
 
-	if (edx & 1 << 2) {
+	if (cpu_has(c, X86_FEATURE_VID)) {
 		printk("voltage");
 		can_scale_vid = 1;
 	}
-- 
1.6.0.6

Re: [git-pull -tip][PATCH 0/10] few cpufeature additions and users

[Jaswinder Singh Rajput]

On Tue, 2009-05-12 at 21:05 +0530, Jaswinder Singh Rajput wrote:
> Here is first patchset of cpufeatures I will release another cpufeature
> patchset after these are applied.
> 
> The following changes since commit 3e0c373749d7eb5b354ac0b043f2b2cdf84eefef:
>   Yinghai Lu (1):
>         x86: clean up and fix setup_clear/force_cpu_cap handling
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/jaswinder/linux-2.6-cpu.git x86/cpufeature
> 

Here is new pull request:

The following changes since commit 3e0c373749d7eb5b354ac0b043f2b2cdf84eefef:
  Yinghai Lu (1):
        x86: clean up and fix setup_clear/force_cpu_cap handling

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/jaswinder/linux-2.6-cpu.git x86/cpufeature

Jaswinder Singh Rajput (10):
      x86: Add cpufeature for Processor Name
      x86: get_model_name() user of X86_FEATURE_PNAME
      x86: Add cpufeatures for Advanced Power Management
      x86: check_powernow() for K7 user of Advanced Power Management features
      x86: check_powernow() for K8 and later user of Advanced Power Management features
      x86: early_init_intel() user of Advanced Power Management features
      x86: early_init_amd() user of Advanced Power Management features
      x86: Add cpufeature for Microcode update
      x86: collect_cpu_info() of Intel user of Microcode feature
      x86: collect_cpu_info() of AMD user of Microcode feature

 arch/x86/include/asm/cpufeature.h         |   21 +++++++++++++++++----
 arch/x86/kernel/cpu/amd.c                 |   21 ++++++++++++++++-----
 arch/x86/kernel/cpu/common.c              |   28 +++++++++++++++++++++++-----
 arch/x86/kernel/cpu/cpufreq/powernow-k7.c |   16 ++++++----------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.c |   16 ++++++++--------
 arch/x86/kernel/cpu/cpufreq/powernow-k8.h |    4 ----
 arch/x86/kernel/cpu/intel.c               |   19 +++++++++++++++----
 arch/x86/kernel/microcode_amd.c           |    3 ++-
 arch/x86/kernel/microcode_intel.c         |    4 ++--
 9 files changed, 89 insertions(+), 43 deletions(-)

Complete diff:
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..659cdaa 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	9	/* N 32-bit words worth of info */
+#define NCAPINTS		10	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -76,7 +76,7 @@
 #define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
 #define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
 #define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
+#define X86_FEATURE_POWER_MGMT	(3*32+ 8) /* Advanced Power Management */
 #define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
@@ -153,8 +153,10 @@
  * Auxiliary flags: Linux defined - For features scattered in various
  * CPUID levels like 0x6, 0xA etc
  */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration	*/
+#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer	*/
+#define X86_FEATURE_PNAME	(7*32+ 2) /* Processor Name		*/
+#define X86_FEATURE_MICROCODE	(7*32+ 3) /* Microcode update		*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -163,6 +165,17 @@
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 
+/* Advanced Power Management (Function 8000_0007h), edx			*/
+#define X86_FEATURE_TS		(9*32+ 0) /* Temperature sensor		*/
+#define X86_FEATURE_FID		(9*32+ 1) /* Frequency ID control	*/
+#define X86_FEATURE_VID		(9*32+ 2) /* Voltage ID control		*/
+#define X86_FEATURE_TTP		(9*32+ 3) /* Thermal trip		*/
+#define X86_FEATURE_HTC		(9*32+ 4) /* Hardware thermal control	*/
+#define X86_FEATURE_STC		(9*32+ 5) /* Software thermal control	*/
+#define X86_FEATURE_100MHZSTEPS	(9*32+ 6) /* 100 MHz multiplier control	*/
+#define X86_FEATURE_HWPSTATE	(9*32+ 7) /* Hardware P-State control	*/
+#define X86_FEATURE_CONSTANT_TSC (9*32+ 8) /* Constant rate TSC ticks	*/
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7e4a459..ca133a0 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -334,13 +334,12 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 	early_init_amd_mc(c);
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-	}
 
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
@@ -353,6 +352,15 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 #endif
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	if (c->x86 >= 0x10) {				/* fam10h+	*/
+		/* setting microcode update feature			*/
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+	}
+}
+
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
@@ -372,6 +380,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 	}
 #endif
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_amd(c);
 
 	/*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e7fd5c4..c98ade3 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -352,7 +352,7 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 	unsigned int *v;
 	char *p, *q;
 
-	if (c->extended_cpuid_level < 0x80000004)
+	if (!cpu_has(c, X86_FEATURE_PNAME))
 		return;
 
 	v = (unsigned int *)c->x86_model_id;
@@ -563,6 +563,28 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * Processor Name / Brand String
+	 * (Function 8000_0002h, 8000_0003h, 8000_0004h)
+	 * Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to
+	 * 16 ASCII bytes of the processor name in the EAX, EBX, ECX and EDX
+	 * registers.
+	 */
+	if (c->extended_cpuid_level >= 0x80000004)
+		set_cpu_cap(c, X86_FEATURE_PNAME);
+
+	/* Advanced Power Management (Function 8000_0007h), edx */
+	if (c->extended_cpuid_level >= 0x80000007) {
+		c->x86_capability[9] = cpuid_edx(0x80000007);
+		c->x86_power = cpuid_edx(0x80000007);
+
+		/*
+		 * Adding helper cpufeature to check the availability of
+		 * Advanced Power Management (Function 8000_0007h), edx
+		 */
+		set_cpu_cap(c, X86_FEATURE_POWER_MGMT);
+	}
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		u32 eax = cpuid_eax(0x80000008);
 
@@ -573,10 +595,6 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
 		c->x86_phys_bits = 36;
 #endif
-
-	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
-
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index 3c28ccd..965f235 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -118,7 +118,6 @@ static int check_fsb(unsigned int fsbspeed)
 static int check_powernow(void)
 {
 	struct cpuinfo_x86 *c = &cpu_data(0);
-	unsigned int maxei, eax, ebx, ecx, edx;
 
 	if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
 #ifdef MODULE
@@ -128,9 +127,8 @@ static int check_powernow(void)
 		return 0;
 	}
 
-	/* Get maximum capabilities */
-	maxei = cpuid_eax(0x80000000);
-	if (maxei < 0x80000007) {	/* Any powernow info ? */
+	/* Advanced Power Management capabilities */
+	if (!cpu_has(c, X86_FEATURE_POWER_MGMT)) {	/* Any powernow info */
 #ifdef MODULE
 		printk(KERN_INFO PFX "No powernow capabilities detected\n");
 #endif
@@ -143,23 +141,21 @@ static int check_powernow(void)
 		have_a0 = 1;
 	}
 
-	cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
-
 	/* Check we can actually do something before we say anything.*/
-	if (!(edx & (1 << 1 | 1 << 2)))
+	if (!cpu_has(c, X86_FEATURE_FID) && !cpu_has(c, X86_FEATURE_VID))
 		return 0;
 
 	printk(KERN_INFO PFX "PowerNOW! Technology present. Can scale: ");
 
-	if (edx & 1 << 1) {
+	if (cpu_has(c, X86_FEATURE_FID)) {
 		printk("frequency");
 		can_scale_bus = 1;
 	}
 
-	if ((edx & (1 << 1 | 1 << 2)) == 0x6)
+	if (cpu_has(c, X86_FEATURE_FID) && cpu_has(c, X86_FEATURE_VID))
 		printk(" and ");
 
-	if (edx & 1 << 2) {
+	if (cpu_has(c, X86_FEATURE_VID)) {
 		printk("voltage");
 		can_scale_vid = 1;
 	}
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 4709ead..c9869fd 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -512,8 +512,9 @@ static int core_voltage_post_transition(struct powernow_k8_data *data,
 
 static int check_supported_cpu(unsigned int cpu)
 {
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	cpumask_t oldmask;
-	u32 eax, ebx, ecx, edx;
+	u32 eax;
 	unsigned int rc = 0;
 
 	oldmask = current->cpus_allowed;
@@ -540,23 +541,22 @@ static int check_supported_cpu(unsigned int cpu)
 			goto out;
 		}
 
-		eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
-		if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
+		/* Advanced Power Management capabilities */
+		if (!cpu_has(c, X86_FEATURE_POWER_MGMT)) {
 			printk(KERN_INFO PFX
 			       "No frequency change capabilities detected\n");
 			goto out;
 		}
 
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & P_STATE_TRANSITION_CAPABLE)
-			!= P_STATE_TRANSITION_CAPABLE) {
+		/* check for frequncy and volatage ID control support */
+		if (!cpu_has(c, X86_FEATURE_FID) &&
+			!cpu_has(c, X86_FEATURE_VID)) {
 			printk(KERN_INFO PFX
 				"Power state transitions not supported\n");
 			goto out;
 		}
 	} else { /* must be a HW Pstate capable processor */
-		cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-		if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
+		if (cpu_has(c, X86_FEATURE_HWPSTATE))
 			cpu_family = CPU_HW_PSTATE;
 		else
 			goto out;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698f..4dfe414 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -64,9 +64,6 @@ struct powernow_k8_data {
 #define CPUID_XMOD_REV_MASK		0x000c0000
 #define CPUID_XFAM_10H			0x00100000	/* family 0x10 */
 #define CPUID_USE_XFAM_XMOD		0x00000f00
-#define CPUID_GET_MAX_CAPABILITIES	0x80000000
-#define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
-#define P_STATE_TRANSITION_CAPABLE	6
 
 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
@@ -101,7 +98,6 @@ struct powernow_k8_data {
 
 
 /* Hardware Pstate _PSS and MSR definitions */
-#define USE_HW_PSTATE		0x00000080
 #define HW_PSTATE_MASK 		0x00000007
 #define HW_PSTATE_VALID_MASK 	0x80000000
 #define HW_PSTATE_MAX_MASK	0x000000f0
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7437fa1..ddb26f2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,14 +61,14 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
+	 * Advanced power management is 8000_0007 edx.
+	 * Bit 8 is TSC runs at constant rate with P/T states
+	 * and does not stop in deep C-states.
 	 *
 	 * It is also reliable across cores and sockets. (but not across
 	 * cabinets - we turn it off in that case explicitly.)
 	 */
-	if (c->x86_power & (1 << 8)) {
-		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
 		sched_clock_stable = 1;
@@ -303,10 +303,21 @@ static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 	}
 }
 
+/* Set cpufeatures to friendly access miscellaneous MSRs		*/
+static void __cpuinit set_soft_cpufeatures(struct cpuinfo_x86 *c)
+{
+	/* setting microcode update feature				*/
+	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
+		set_cpu_cap(c, X86_FEATURE_MICROCODE);
+}
+
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
 
+	/* setting early so that other functions can take advantage */
+	set_soft_cpufeatures(c);
+
 	early_init_intel(c);
 
 	intel_workarounds(c);
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 453b579..1178638 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -90,7 +90,8 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 	u32 dummy;
 
 	memset(csig, 0, sizeof(*csig));
-	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+	if (c->x86_vendor != X86_VENDOR_AMD ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not "
 		       "supported\n", cpu, c->x86);
 		return -1;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 149b9ec..c2e128e 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,8 +161,8 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 
 	memset(csig, 0, sizeof(*csig));
 
-	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
-	    cpu_has(c, X86_FEATURE_IA64)) {
+	if (c->x86_vendor != X86_VENDOR_INTEL ||
+	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
 		printk(KERN_ERR "microcode: CPU%d not a capable Intel "
 			"processor\n", cpu_num);
 		return -1;

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Thomas Gleixner]

Jaswinder,

On Wed, 13 May 2009, Jaswinder Singh Rajput wrote:
> +	/* Advanced Power Management (Function 8000_0007h), edx */
> +	if (c->extended_cpuid_level >= 0x80000007) {
> +		c->x86_capability[9] = cpuid_edx(0x80000007);

In the reply to [Patch 5/10] Ingo wrote:
>> Also, open-coding x86_capability[9] like that is quite unclean. Were 
>> we ever to reorder those bits internally, this could would break.

Do you really believe that open-coding x86_capability[9] in .../common.c
is better than the open-coding in ../powernow-k8.c ?

Again, open-coding is wrong and error prone. Ingo explicitely asked for a
helper function. All you did is moving the open-coded hard wired array
reference to a different place.

Please start to listen to the review comments as long as people are
willing to look at your patches. Seriously, the noise/useful ratio of
your patches is annoying and adds an unjustified burden to the
maintainers of that code.

Thanks,

	tglx

Re: [PATCH 8/10 -tip] x86: Add cpufeature for Microcode update

[Andreas Herrmann]

On Tue, May 12, 2009 at 09:13:16PM +0530, Jaswinder Singh Rajput wrote:
> 
> Setting microcode update feature to friendly access of UCODE MSRs like:
> 1. IA32_PLATFORM_ID (Intel)
> 2. IA32_UCODE_WRITE (Intel)
> 3. IA32_UCODE_REV (Intel)
> 4. MSR_AMD64_PATCH_LEVEL (AMD)
> 5. MSR_AMD64_PATCH_LOADER (AMD)
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>

NAK! There is absolutely no point in moving the CPU
family/model/revision checks from the microcode drivers into generic
setup code.

Please explain what's the benefit of this?

>  arch/x86/include/asm/cpufeature.h |    1 +
>  arch/x86/kernel/cpu/amd.c         |   12 ++++++++++++
>  arch/x86/kernel/cpu/intel.c       |   11 +++++++++++
>  3 files changed, 24 insertions(+), 0 deletions(-)

I just see that it adds additional lines of code without any benefit.
You don't even check for this flag in microcode_core code which would
have introduced a "minor use case" of this.

Instead of checking CPU family/model/revision in those drivers (that
are really requiring this information and really know what to check
for) you disperse the handling of it over the kernel.

Last not least. The check in the AMD microcode loader driver ensures
that only AMD CPU families >= 0x10 are handled by the driver. It's a
mystery to me how this information is useful to set a generic
microcode feature flag "to friendly access of UCODE MSRs".

Maybe you wanted to introduce a generic flag to indicate that certain
MSRs are available. Then this check is just bogus.

Please, if you want to access microcode related MSRs in other parts of
the kernel, introduce the right CPU family and revision checks at the new
respective places.


Regards,
Andreas

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  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: [PATCH 10/10 -tip] x86: collect_cpu_info() of AMD user of Microcode feature

[Andreas Herrmann]

On Tue, May 12, 2009 at 09:14:38PM +0530, Jaswinder Singh Rajput wrote:
> 
> use X86_FEATURE_MICROCODE to determine microcode update
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>

NAK.

>  arch/x86/kernel/microcode_amd.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
> index 453b579..1178638 100644
> --- a/arch/x86/kernel/microcode_amd.c
> +++ b/arch/x86/kernel/microcode_amd.c
> @@ -90,7 +90,8 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
>  	u32 dummy;
>  
>  	memset(csig, 0, sizeof(*csig));
> -	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
> +	if (c->x86_vendor != X86_VENDOR_AMD ||
> +	    !cpu_has(c, X86_FEATURE_MICROCODE)) {
>  		printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not "
>  		       "supported\n", cpu, c->x86);
>  		return -1;
> -- 
> 1.6.0.6


Regards,
Andreas

-- 
Operating | Advanced Micro Devices GmbH
  System  | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. München, Germany
 Research | Geschäftsführer: Thomas M. McCoy, Giuliano Meroni
  Center  | Sitz: Dornach, Gemeinde Aschheim, Landkreis München
  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: [PATCH 6/10 -tip] x86: early_init_intel() user of Advanced Power Management features

[Andreas Herrmann]

On Tue, May 12, 2009 at 09:11:48PM +0530, Jaswinder Singh Rajput wrote:
> 
> use X86_FEATURE_CONSTANT_TSC to determine TSC Invariance
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>

I'd like to NAK this as well.

You didn't get to the point what's the difference between
X86_FEATURE_CONSTANT_TSC and X86_FEATURE_NONSTOP_TSC, did you?
I guess you never checked the related commit messages. (I.e. using git
blame to see how code evolved over time and _why_ was it changed.)
In this case it would have been commit 40fb17152c50a69dc304dd632131c2f41281ce44
(x86: support always running TSC on Intel CPUs), see
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=40fb17152c50a69dc304dd632131c2f41281ce44

>  arch/x86/kernel/cpu/intel.c |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 7437fa1..62130a0 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -61,14 +61,14 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
>  		c->x86_phys_bits = 36;
>  
>  	/*
> -	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
> -	 * with P/T states and does not stop in deep C-states.
> +	 * Advanced power management is 8000_0007 edx.
> +	 * Bit 8 is TSC runs at constant rate with P/T states
> +	 * and does not stop in deep C-states.
>  	 *
>  	 * It is also reliable across cores and sockets. (but not across
>  	 * cabinets - we turn it off in that case explicitly.)
>  	 */
> -	if (c->x86_power & (1 << 8)) {
> -		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> +	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
>  		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
>  		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
>  		sched_clock_stable = 1;

This code would mark some Intel CPUs as having
X86_FEATURE_NONSTOP_TSC which is certainly wrong in some cases.

You missed this snippet.

        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

in early_init_intel().


Regards,
Andreas

-- 
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 Research | Geschäftsführer: Thomas M. McCoy, Giuliano Meroni
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  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Andreas Herrmann]

On Wed, May 13, 2009 at 12:36:30AM +0530, Jaswinder Singh Rajput wrote:
> On Tue, 2009-05-12 at 21:09 +0530, Jaswinder Singh Rajput wrote:
> > Add Advanced Power Management (Function 8000_0007h), edx
> > 
> > /proc/cpuinfo (before)
> > flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> > mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> > rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
> > lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> > 
> > /proc/cpuinfo (after)
> > flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> > mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> > rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
> > lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> > ts ttp htc stc 100mhzsteps hwpstate constant_tsc
> > 
> > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> > ---
> 
> New patch after adding helper cpufeature for Advanced Power Management
> availability and fixing typo.
> 
> [PATCH -tip] x86: Add cpufeatures for Advanced Power Management
> 
> Add Advanced Power Management (Function 8000_0007h), edx
> 
> /proc/cpuinfo (before)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> 
> /proc/cpuinfo (after)
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good tsc_reliable nonstop_tsc pni cx16
> lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch osvw skinit pname
> ts ttp htc stc 100mhzsteps hwpstate constant_tsc

What's the point of adding power managment flags twice?
Most of it is already displayed in /proc/cpuinfo under
"power management".


Regards,
Andreas

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 Research | Geschäftsführer: Thomas M. McCoy, Giuliano Meroni
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  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: [PATCH 5/10 -tip] x86: check_powernow() for K8 and later user of Advanced Power Management features

[Andreas Herrmann]

You should involve the maintainer of powernow-k8 when submitting patches for this driver.
It's Mark Langsdorf (mark.langsdorf@amd.com).

Regards,
Andreas

-- 
Operating | Advanced Micro Devices GmbH
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 Research | Geschäftsführer: Thomas M. McCoy, Giuliano Meroni
  Center  | Sitz: Dornach, Gemeinde Aschheim, Landkreis München
  (OSRC)  | Registergericht München, HRB Nr. 43632

Re: [PATCH 8/10 -tip] x86: Add cpufeature for Microcode update

[Jaswinder Singh Rajput]

On Wed, 2009-05-13 at 07:46 +0200, Andreas Herrmann wrote:
> On Tue, May 12, 2009 at 09:13:16PM +0530, Jaswinder Singh Rajput wrote:
> > 
> > Setting microcode update feature to friendly access of UCODE MSRs like:
> > 1. IA32_PLATFORM_ID (Intel)
> > 2. IA32_UCODE_WRITE (Intel)
> > 3. IA32_UCODE_REV (Intel)
> > 4. MSR_AMD64_PATCH_LEVEL (AMD)
> > 5. MSR_AMD64_PATCH_LOADER (AMD)
> > 
> > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> 
> NAK! There is absolutely no point in moving the CPU
> family/model/revision checks from the microcode drivers into generic
> setup code.

Thanks, trashed.

--
JSR

Re: [PATCH 10/10 -tip] x86: collect_cpu_info() of AMD user of Microcode feature

[Jaswinder Singh Rajput]

On Wed, 2009-05-13 at 07:47 +0200, Andreas Herrmann wrote:
> On Tue, May 12, 2009 at 09:14:38PM +0530, Jaswinder Singh Rajput wrote:
> > 
> > use X86_FEATURE_MICROCODE to determine microcode update
> > 
> > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> 
> NAK.

Thanks, trashed.

--
JSR

Re: [PATCH 6/10 -tip] x86: early_init_intel() user of Advanced Power Management features

[Jaswinder Singh Rajput]

On Wed, 2009-05-13 at 08:18 +0200, Andreas Herrmann wrote:
> On Tue, May 12, 2009 at 09:11:48PM +0530, Jaswinder Singh Rajput wrote:
> > 
> > use X86_FEATURE_CONSTANT_TSC to determine TSC Invariance
> > 
> > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> 
> I'd like to NAK this as well.

Thanks, trashed.

--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Tue, 2009-05-12 at 23:04 +0200, Thomas Gleixner wrote:
> Jaswinder,
> 
> On Wed, 13 May 2009, Jaswinder Singh Rajput wrote:
> > +	/* Advanced Power Management (Function 8000_0007h), edx */
> > +	if (c->extended_cpuid_level >= 0x80000007) {
> > +		c->x86_capability[9] = cpuid_edx(0x80000007);
> 
> In the reply to [Patch 5/10] Ingo wrote:
> >> Also, open-coding x86_capability[9] like that is quite unclean. Were 
> >> we ever to reorder those bits internally, this could would break.
> 
> Do you really believe that open-coding x86_capability[9] in .../common.c
> is better than the open-coding in ../powernow-k8.c ?
> 
> Again, open-coding is wrong and error prone. Ingo explicitely asked for a
> helper function. All you did is moving the open-coded hard wired array
> reference to a different place.
> 
> Please start to listen to the review comments as long as people are
> willing to look at your patches. Seriously, the noise/useful ratio of
> your patches is annoying and adds an unjustified burden to the
> maintainers of that code.
> 

Ok, trashed complete cpu_debug and cpufeature patches, I hope it will
makes maintainers happy and save their precious time.

Anyway thanks for being so helpful and making my task easier :-)

--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

Hello Thomas,

On Tue, 2009-05-12 at 23:04 +0200, Thomas Gleixner wrote:
> Jaswinder,
> 
> On Wed, 13 May 2009, Jaswinder Singh Rajput wrote:
> > +	/* Advanced Power Management (Function 8000_0007h), edx */
> > +	if (c->extended_cpuid_level >= 0x80000007) {
> > +		c->x86_capability[9] = cpuid_edx(0x80000007);
> 
> In the reply to [Patch 5/10] Ingo wrote:
> >> Also, open-coding x86_capability[9] like that is quite unclean. Were 
> >> we ever to reorder those bits internally, this could would break.
> 
> Do you really believe that open-coding x86_capability[9] in .../common.c
> is better than the open-coding in ../powernow-k8.c ?
> 

BTW, then how you can set x86_capability[9] in one shot ? do you want me
to set each bit with set_cpu_cap() ?

> Again, open-coding is wrong and error prone. Ingo explicitely asked for a
> helper function. All you did is moving the open-coded hard wired array
> reference to a different place.

I am sorry I did not get you, if possible can you please explain your
comment.

I made x86_capability[9] as Advanced Power Management (Function
8000_0007h), edx.
And I moved to X86_FEATURE_CONSTANT_TSC to Advanced Power Management
group as it is the part of it.

I added helper cpufeature for Advanced Power Management availability
so I set in software cpufeature array in vacuum created by
X86_FEATURE_CONSTANT_TSC.

If you have some better suggestion, please let me know.

Thanks for your guidance,
--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Thomas Gleixner]

On Fri, 15 May 2009, Jaswinder Singh Rajput wrote:
> > Do you really believe that open-coding x86_capability[9] in .../common.c
> > is better than the open-coding in ../powernow-k8.c ?
> > 
> 
> BTW, then how you can set x86_capability[9] in one shot ? do you want me
> to set each bit with set_cpu_cap() ?

Using "9" as an array index is the point. This needs to be a constant
near the other constants which describe the bits and a big fat comment.

Thanks,

	tglx

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Sun, 2009-05-17 at 14:17 +0200, Thomas Gleixner wrote:
> On Fri, 15 May 2009, Jaswinder Singh Rajput wrote:
> > > Do you really believe that open-coding x86_capability[9] in .../common.c
> > > is better than the open-coding in ../powernow-k8.c ?
> > > 
> > 
> > BTW, then how you can set x86_capability[9] in one shot ? do you want me
> > to set each bit with set_cpu_cap() ?
> 
> Using "9" as an array index is the point. This needs to be a constant
> near the other constants which describe the bits and a big fat comment.
> 

Sure, I will do it. And hoping that I will get ACK from you ;-)

Thanks,
--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

Hello Thomas,

On Sun, 2009-05-17 at 14:17 +0200, Thomas Gleixner wrote:
> On Fri, 15 May 2009, Jaswinder Singh Rajput wrote:
> > > Do you really believe that open-coding x86_capability[9] in .../common.c
> > > is better than the open-coding in ../powernow-k8.c ?
> > > 
> > 
> > BTW, then how you can set x86_capability[9] in one shot ? do you want me
> > to set each bit with set_cpu_cap() ?
> 
> Using "9" as an array index is the point. This needs to be a constant
> near the other constants which describe the bits and a big fat comment.
> 

You mean these should also use constant and big fat comment :

arch/x86/include/asm/elf.h:#define ELF_HWCAP            (boot_cpu_data.x86_capability[0])
arch/x86/kernel/cpu/centaur.c:          c->x86_capability[5] = cpuid_edx(0xC0000001);
arch/x86/kernel/cpu/common.c:           c->x86_capability[0] = capability;
arch/x86/kernel/cpu/common.c:           c->x86_capability[4] = excap;
arch/x86/kernel/cpu/common.c:                   c->x86_capability[1] = cpuid_edx(0x80000001);
arch/x86/kernel/cpu/common.c:                   c->x86_capability[6] = cpuid_ecx(0x80000001);
arch/x86/kernel/cpu/transmeta.c:                        c->x86_capability[2] = cpuid_edx(0x80860001);
arch/x86/kernel/cpu/transmeta.c:        c->x86_capability[0] = cpuid_edx(0x00000001);
arch/x86/kernel/mpparse.c:      processor.featureflag = boot_cpu_data.x86_capability[0];
arch/x86/lguest/boot.c: new_cpu_data.x86_capability[0] = cpuid_edx(1);
arch/x86/xen/enlighten.c:       new_cpu_data.x86_capability[0] = cpuid_edx(1);

So should I also make constant for all x86_capability.

Peter, Ingo:
Do you think we need to arrange x86_capability in some order, currently
we are using x86_capability numbering in random order.

Thanks,
--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> 
> Peter, Ingo:
> Do you think we need to arrange x86_capability in some order, currently
> we are using x86_capability numbering in random order.
> 

No.

	-hpa

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Tue, 2009-05-19 at 09:41 -0700, H. Peter Anvin wrote:
> Jaswinder Singh Rajput wrote:
> > 
> > Peter, Ingo:
> > Do you think we need to arrange x86_capability in some order, currently
> > we are using x86_capability numbering in random order.
> > 
> 
> No.
> 

I think better I will show with the coding to get the clear picture.

Currently we are using hardcoded x86_capability as [0], [2], [4], [5].

Thomas prefer to use constant so may be we can define current system as:

enum {
	CPUID_0000_0001_EDX = 0,	/* 0x00000001 edx */
	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
	CPUID_SOFT_MISC1,		/* Software Misc1 */
	CPUID_0000_0001_ECX,		/* 0x00000001 ecx */
	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */
	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
	CPUID_SOFT_MISC2,		/* Software Misc2 */
	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */
};

I was suggesting to also sort it out based on address and register like this:

enum {
	/* Hardware CPUIDs */
	CPUID_0000_0001_ECX = 0,	/* 0x00000001 ecx */
	CPUID_0000_0001_EDX,		/* 0x00000001 edx */
	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */

	/* Software/Miscellaneous CPUIDs */
	CPUID_SOFT_MISC1,		/* Software Misc1 */
	CPUID_SOFT_MISC2,		/* Software Misc2 */
	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */
};

Do you have some better suggestion.

Thanks,

--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Wed, 2009-05-20 at 12:45 +0530, Jaswinder Singh Rajput wrote:
> On Tue, 2009-05-19 at 09:41 -0700, H. Peter Anvin wrote:
> > Jaswinder Singh Rajput wrote:
> > > 
> > > Peter, Ingo:
> > > Do you think we need to arrange x86_capability in some order, currently
> > > we are using x86_capability numbering in random order.
> > > 
> > 
> > No.
> > 
> 
> I think better I will show with the coding to get the clear picture.
> 
> Currently we are using hardcoded x86_capability as [0], [2], [4], [5].
> 
> Thomas prefer to use constant so may be we can define current system as:
> 
> enum {
> 	CPUID_0000_0001_EDX = 0,	/* 0x00000001 edx */
> 	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
> 	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
> 	CPUID_SOFT_MISC1,		/* Software Misc1 */
> 	CPUID_0000_0001_ECX,		/* 0x00000001 ecx */
> 	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */
> 	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
> 	CPUID_SOFT_MISC2,		/* Software Misc2 */
> 	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */
> };
> 
> I was suggesting to also sort it out based on address and register like this:
> 
> enum {
> 	/* Hardware CPUIDs */
> 	CPUID_0000_0001_ECX = 0,	/* 0x00000001 ecx */
> 	CPUID_0000_0001_EDX,		/* 0x00000001 edx */
> 	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
> 	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
> 	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
> 	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */
> 
> 	/* Software/Miscellaneous CPUIDs */
> 	CPUID_SOFT_MISC1,		/* Software Misc1 */
> 	CPUID_SOFT_MISC2,		/* Software Misc2 */
> 	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */

	/* End of CPUIDs */
	NCAPINTS,			/* N 32-bit words worth of info */
};

This will also take care of max x86_capability CPUID limit.

--
JSR

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> 
> I think better I will show with the coding to get the clear picture.
> 
> Currently we are using hardcoded x86_capability as [0], [2], [4], [5].
> 
> Thomas prefer to use constant so may be we can define current system as:
> 
> enum {
> 	CPUID_0000_0001_EDX = 0,	/* 0x00000001 edx */
> 	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
> 	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
> 	CPUID_SOFT_MISC1,		/* Software Misc1 */
> 	CPUID_0000_0001_ECX,		/* 0x00000001 ecx */
> 	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */
> 	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
> 	CPUID_SOFT_MISC2,		/* Software Misc2 */
> 	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */
> };
> 

This really seems clumsy to me.  We don't refer to the individual words
all that often; and more importantly, I think it'd be hard to get rid of
all the places where the words are referenced.

I do NOT want to renumber them; therein lie madness.

	-hpa

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[Jaswinder Singh Rajput]

On Wed, 2009-05-20 at 11:30 -0700, H. Peter Anvin wrote:
> Jaswinder Singh Rajput wrote:
> > 
> > I think better I will show with the coding to get the clear picture.
> > 
> > Currently we are using hardcoded x86_capability as [0], [2], [4], [5].
> > 
> > Thomas prefer to use constant so may be we can define current system as:
> > 
> > enum {
> > 	CPUID_0000_0001_EDX = 0,	/* 0x00000001 edx */
> > 	CPUID_8000_0001_EDX,		/* 0x80000001 edx */
> > 	CPUID_8086_0001_EDX,		/* 0x80860001 edx */
> > 	CPUID_SOFT_MISC1,		/* Software Misc1 */
> > 	CPUID_0000_0001_ECX,		/* 0x00000001 ecx */
> > 	CPUID_C000_0001_EDX,		/* 0xC0000001 edx */
> > 	CPUID_8000_0001_ECX,		/* 0x80000001 ecx */
> > 	CPUID_SOFT_MISC2,		/* Software Misc2 */
> > 	CPUID_SOFT_VIRTUAL,		/* Software Virtualization */
> > };
> > 
> 
> This really seems clumsy to me.  We don't refer to the individual words
> all that often; and more importantly, I think it'd be hard to get rid of
> all the places where the words are referenced.
> 

OK. It was thomas request. I hope this explanation will be enough and
thomas have no objection in Advanced Power Management's cpufeatures
series.

Ingo: should I resend new cpufeatures series, or you can use this one.

Thanks,
--
JSR

Re: [PATCH 1/10 -tip] x86: Add cpufeature for Processor Name

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
> Processor Name / Brand String (Function 8000_0002h, 8000_0003h, 8000_0004h)
> Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to 16 ASCII
> bytes of the processor name in the EAX, EBX, ECX and EDX registers.
> 
> X86_FEATURE_PNAME will be useful for displaying MSRs like AMD:
> MSRC001_00[35:30] Processor Name String Registers
> 

Pointless and wrong.  The presence of the processor name is not the same
thing as the presence of specific MSRs, which are model-specific.

	-hpa

Re: [PATCH 3/10 -tip] x86: Add cpufeatures for Advanced Power Management

[H. Peter Anvin]

Andreas Herrmann wrote:
> 
> What's the point of adding power managment flags twice?
> Most of it is already displayed in /proc/cpuinfo under
> "power management".
> 

And that is user-space visible, so even if we unify the array (which may
be worthwhile) we cannot change the way they're presented to userspace.

	-hpa

Re: [PATCH 1/10 -tip] x86: Add cpufeature for Processor Name

[Jaswinder Singh Rajput]

On Wed, 2009-05-20 at 23:11 -0700, H. Peter Anvin wrote:
> Jaswinder Singh Rajput wrote:
> > Processor Name / Brand String (Function 8000_0002h, 8000_0003h, 8000_0004h)
> > Functions 8000_0002h, 8000_0003h, and 8000_0004h each return up to 16 ASCII
> > bytes of the processor name in the EAX, EBX, ECX and EDX registers.
> > 
> > X86_FEATURE_PNAME will be useful for displaying MSRs like AMD:
> > MSRC001_00[35:30] Processor Name String Registers
> > 
> 
> Pointless and wrong.  The presence of the processor name is not the same
> thing as the presence of specific MSRs, which are model-specific.
> 

>From AMD's BIOS and Kernel Developer’s Guide(BKDG) Manual :

 MSRC001_00[35:30] Processor Name String Registers
Reset: 0000 0000 0000 0000h. These registers holds the CPUID name string in ASCII. The state of these regis-
ters are returned by CPUID instructions, CPUID Fn8000_000[4:2]. BIOS should set these registers to the
AMD-provided product name for the processor. Each register contains a block of 8 ASCII characters; the least
byte corresponds to the first ASCII character of the block; the most-significant byte corresponds to the last
character of the block. MSRC001_0030 contains the first block of the name string; MSRC001_0035 contains
the last block of the name string.

  Bits    Description
  63:0 CpuNameString. Read-write.

--
JSR

Re: [PATCH 1/10 -tip] x86: Add cpufeature for Processor Name

[H. Peter Anvin]

Jaswinder Singh Rajput wrote:
>>>
>> Pointless and wrong.  The presence of the processor name is not the same
>> thing as the presence of specific MSRs, which are model-specific.
>>
> 
>>From AMD's BIOS and Kernel Developer’s Guide(BKDG) Manual :
> 
>  MSRC001_00[35:30] Processor Name String Registers
> Reset: 0000 0000 0000 0000h. These registers holds the CPUID name string in ASCII. The state of these regis-
> ters are returned by CPUID instructions, CPUID Fn8000_000[4:2]. BIOS should set these registers to the
> AMD-provided product name for the processor. Each register contains a block of 8 ASCII characters; the least
> byte corresponds to the first ASCII character of the block; the most-significant byte corresponds to the last
> character of the block. MSRC001_0030 contains the first block of the name string; MSRC001_0035 contains
> the last block of the name string.
> 
>   Bits    Description
>   63:0 CpuNameString. Read-write.
> 

Yes.  Non-AMD processors also have the brand name string in CPUID, but
set them though other means.

	-hpa