* [PATCH 01/16] tda18271c2dd: Initial check-in
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
@ 2011-07-03 16:36 ` Oliver Endriss
2011-07-03 16:37 ` [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes Oliver Endriss
` (16 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:36 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
From: Ralph Metzler <rjkm@metzlerbros.de>
Driver for the NXP TDA18271c2 silicon tuner.
Signed-off-by: Ralph Metzler <rjkm@metzlerbros.de>
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/frontends/tda18271c2dd.c | 1063 +++++++++++++++++++++++
drivers/media/dvb/frontends/tda18271c2dd.h | 5 +
drivers/media/dvb/frontends/tda18271c2dd_maps.h | 810 +++++++++++++++++
3 files changed, 1878 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/tda18271c2dd.c
create mode 100644 drivers/media/dvb/frontends/tda18271c2dd.h
create mode 100644 drivers/media/dvb/frontends/tda18271c2dd_maps.h
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.c b/drivers/media/dvb/frontends/tda18271c2dd.c
new file mode 100644
index 0000000..b4a23bf
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd.c
@@ -0,0 +1,1063 @@
+/*
+ * tda18271c2dd: Driver for the TDA18271C2 tuner
+ *
+ * Copyright (C) 2010 Digital Devices GmbH
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/firmware.h>
+#include <linux/i2c.h>
+#include <linux/version.h>
+#include <asm/div64.h>
+
+#include "dvb_frontend.h"
+
+struct SStandardParam {
+ s32 m_IFFrequency;
+ u32 m_BandWidth;
+ u8 m_EP3_4_0;
+ u8 m_EB22;
+};
+
+struct SMap {
+ u32 m_Frequency;
+ u8 m_Param;
+};
+
+struct SMapI {
+ u32 m_Frequency;
+ s32 m_Param;
+};
+
+struct SMap2 {
+ u32 m_Frequency;
+ u8 m_Param1;
+ u8 m_Param2;
+};
+
+struct SRFBandMap {
+ u32 m_RF_max;
+ u32 m_RF1_Default;
+ u32 m_RF2_Default;
+ u32 m_RF3_Default;
+};
+
+enum ERegister
+{
+ ID = 0,
+ TM,
+ PL,
+ EP1, EP2, EP3, EP4, EP5,
+ CPD, CD1, CD2, CD3,
+ MPD, MD1, MD2, MD3,
+ EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
+ EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
+ EB21, EB22, EB23,
+ NUM_REGS
+};
+
+struct tda_state {
+ struct i2c_adapter *i2c;
+ u8 adr;
+
+ u32 m_Frequency;
+ u32 IF;
+
+ u8 m_IFLevelAnalog;
+ u8 m_IFLevelDigital;
+ u8 m_IFLevelDVBC;
+ u8 m_IFLevelDVBT;
+
+ u8 m_EP4;
+ u8 m_EP3_Standby;
+
+ bool m_bMaster;
+
+ s32 m_SettlingTime;
+
+ u8 m_Regs[NUM_REGS];
+
+ /* Tracking filter settings for band 0..6 */
+ u32 m_RF1[7];
+ s32 m_RF_A1[7];
+ s32 m_RF_B1[7];
+ u32 m_RF2[7];
+ s32 m_RF_A2[7];
+ s32 m_RF_B2[7];
+ u32 m_RF3[7];
+
+ u8 m_TMValue_RFCal; /* Calibration temperatur */
+
+ bool m_bFMInput; /* true to use Pin 8 for FM Radio */
+
+};
+
+static int PowerScan(struct tda_state *state,
+ u8 RFBand,u32 RF_in,
+ u32 * pRF_Out, bool *pbcal);
+
+static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
+{
+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
+ .buf = data, .len = len}};
+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
+}
+
+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
+{
+ struct i2c_msg msg = {.addr = adr, .flags = 0,
+ .buf = data, .len = len};
+
+ if (i2c_transfer(adap, &msg, 1) != 1) {
+ printk("i2c_write error\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int WriteRegs(struct tda_state *state,
+ u8 SubAddr, u8 *Regs, u16 nRegs)
+{
+ u8 data[nRegs+1];
+
+ data[0] = SubAddr;
+ memcpy(data + 1, Regs, nRegs);
+ return i2c_write(state->i2c, state->adr, data, nRegs+1);
+}
+
+static int WriteReg(struct tda_state *state, u8 SubAddr,u8 Reg)
+{
+ u8 msg[2] = {SubAddr, Reg};
+
+ return i2c_write(state->i2c, state->adr, msg, 2);
+}
+
+static int Read(struct tda_state *state, u8 * Regs)
+{
+ return i2c_readn(state->i2c, state->adr, Regs, 16);
+}
+
+static int ReadExtented(struct tda_state *state, u8 * Regs)
+{
+ return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
+}
+
+static int UpdateRegs(struct tda_state *state, u8 RegFrom,u8 RegTo)
+{
+ return WriteRegs(state, RegFrom,
+ &state->m_Regs[RegFrom], RegTo-RegFrom+1);
+}
+static int UpdateReg(struct tda_state *state, u8 Reg)
+{
+ return WriteReg(state, Reg,state->m_Regs[Reg]);
+}
+
+#include "tda18271c2dd_maps.h"
+
+#undef CHK_ERROR
+#define CHK_ERROR(s) if ((status = s) < 0) break
+
+static void reset(struct tda_state *state)
+{
+ u32 ulIFLevelAnalog = 0;
+ u32 ulIFLevelDigital = 2;
+ u32 ulIFLevelDVBC = 7;
+ u32 ulIFLevelDVBT = 6;
+ u32 ulXTOut = 0;
+ u32 ulStandbyMode = 0x06; // Send in stdb, but leave osc on
+ u32 ulSlave = 0;
+ u32 ulFMInput = 0;
+ u32 ulSettlingTime = 100;
+
+ state->m_Frequency = 0;
+ state->m_SettlingTime = 100;
+ state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
+ state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
+ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
+ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
+
+ state->m_EP4 = 0x20;
+ if( ulXTOut != 0 ) state->m_EP4 |= 0x40;
+
+ state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
+ state->m_bMaster = (ulSlave == 0);
+
+ state->m_SettlingTime = ulSettlingTime;
+
+ state->m_bFMInput = (ulFMInput == 2);
+}
+
+static bool SearchMap1(struct SMap Map[],
+ u32 Frequency, u8 *pParam)
+{
+ int i = 0;
+
+ while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency) )
+ i += 1;
+ if (Map[i].m_Frequency == 0)
+ return false;
+ *pParam = Map[i].m_Param;
+ return true;
+}
+
+static bool SearchMap2(struct SMapI Map[],
+ u32 Frequency, s32 *pParam)
+{
+ int i = 0;
+
+ while ((Map[i].m_Frequency != 0) &&
+ (Frequency > Map[i].m_Frequency) )
+ i += 1;
+ if (Map[i].m_Frequency == 0)
+ return false;
+ *pParam = Map[i].m_Param;
+ return true;
+}
+
+static bool SearchMap3(struct SMap2 Map[],u32 Frequency,
+ u8 *pParam1, u8 *pParam2)
+{
+ int i = 0;
+
+ while ((Map[i].m_Frequency != 0) &&
+ (Frequency > Map[i].m_Frequency) )
+ i += 1;
+ if (Map[i].m_Frequency == 0)
+ return false;
+ *pParam1 = Map[i].m_Param1;
+ *pParam2 = Map[i].m_Param2;
+ return true;
+}
+
+static bool SearchMap4(struct SRFBandMap Map[],
+ u32 Frequency, u8 *pRFBand)
+{
+ int i = 0;
+
+ while (i < 7 && (Frequency > Map[i].m_RF_max))
+ i += 1;
+ if (i == 7)
+ return false;
+ *pRFBand = i;
+ return true;
+}
+
+static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
+{
+ int status = 0;
+
+ do {
+ u8 Regs[16];
+ state->m_Regs[TM] |= 0x10;
+ CHK_ERROR(UpdateReg(state,TM));
+ CHK_ERROR(Read(state,Regs));
+ if( ( (Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20 ) ||
+ ( (Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00 ) ) {
+ state->m_Regs[TM] ^= 0x20;
+ CHK_ERROR(UpdateReg(state,TM));
+ msleep(10);
+ CHK_ERROR(Read(state,Regs));
+ }
+ *pTM_Value = (Regs[TM] & 0x20 ) ? m_Thermometer_Map_2[Regs[TM] & 0x0F] :
+ m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
+ state->m_Regs[TM] &= ~0x10; // Thermometer off
+ CHK_ERROR(UpdateReg(state,TM));
+ state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0 ?????????
+ CHK_ERROR(UpdateReg(state,EP4));
+ } while(0);
+
+ return status;
+}
+
+static int StandBy(struct tda_state *state)
+{
+ int status = 0;
+ do {
+ state->m_Regs[EB12] &= ~0x20; // PD_AGC1_Det = 0
+ CHK_ERROR(UpdateReg(state,EB12));
+ state->m_Regs[EB18] &= ~0x83; // AGC1_loop_off = 0, AGC1_Gain = 6 dB
+ CHK_ERROR(UpdateReg(state,EB18));
+ state->m_Regs[EB21] |= 0x03; // AGC2_Gain = -6 dB
+ state->m_Regs[EP3] = state->m_EP3_Standby;
+ CHK_ERROR(UpdateReg(state,EP3));
+ state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LP_Fc[2] = 0
+ CHK_ERROR(UpdateRegs(state,EB21,EB23));
+ } while(0);
+ return status;
+}
+
+static int CalcMainPLL(struct tda_state *state, u32 freq)
+{
+
+ u8 PostDiv;
+ u8 Div;
+ u64 OscFreq;
+ u32 MainDiv;
+
+ if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) {
+ return -EINVAL;
+ }
+
+ OscFreq = (u64) freq * (u64) Div;
+ OscFreq *= (u64) 16384;
+ do_div(OscFreq, (u64)16000000);
+ MainDiv = OscFreq;
+
+ state->m_Regs[MPD] = PostDiv & 0x77;
+ state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
+ state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
+ state->m_Regs[MD3] = ((MainDiv ) & 0xFF);
+
+ return UpdateRegs(state, MPD, MD3);
+}
+
+static int CalcCalPLL(struct tda_state *state, u32 freq)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",freq));
+
+ u8 PostDiv;
+ u8 Div;
+ u64 OscFreq;
+ u32 CalDiv;
+
+ if( !SearchMap3(m_Cal_PLL_Map,freq,&PostDiv,&Div) )
+ {
+ return -EINVAL;
+ }
+
+ OscFreq = (u64)freq * (u64)Div;
+ //CalDiv = u32( OscFreq * 16384 / 16000000 );
+ OscFreq*=(u64)16384;
+ do_div(OscFreq, (u64)16000000);
+ CalDiv=OscFreq;
+
+ state->m_Regs[CPD] = PostDiv;
+ state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
+ state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
+ state->m_Regs[CD3] = ((CalDiv ) & 0xFF);
+
+ return UpdateRegs(state,CPD,CD3);
+}
+
+static int CalibrateRF(struct tda_state *state,
+ u8 RFBand,u32 freq, s32 * pCprog)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " ID = %02x\n",state->m_Regs[ID]));
+ int status = 0;
+ u8 Regs[NUM_REGS];
+ do {
+ u8 BP_Filter=0;
+ u8 GainTaper=0;
+ u8 RFC_K=0;
+ u8 RFC_M=0;
+
+ state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0
+ CHK_ERROR(UpdateReg(state,EP4));
+ state->m_Regs[EB18] |= 0x03; // AGC1_Gain = 3
+ CHK_ERROR(UpdateReg(state,EB18));
+
+ // Switching off LT (as datasheet says) causes calibration on C1 to fail
+ // (Readout of Cprog is allways 255)
+ if( state->m_Regs[ID] != 0x83 ) // C1: ID == 83, C2: ID == 84
+ {
+ state->m_Regs[EP3] |= 0x40; // SM_LT = 1
+ }
+
+ if( ! ( SearchMap1(m_BP_Filter_Map,freq,&BP_Filter) &&
+ SearchMap1(m_GainTaper_Map,freq,&GainTaper) &&
+ SearchMap3(m_KM_Map,freq,&RFC_K,&RFC_M)) )
+ {
+ return -EINVAL;
+ }
+
+ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
+ state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
+
+ state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
+
+ CHK_ERROR(UpdateRegs(state,EP1,EP3));
+ CHK_ERROR(UpdateReg(state,EB13));
+
+ state->m_Regs[EB4] |= 0x20; // LO_ForceSrce = 1
+ CHK_ERROR(UpdateReg(state,EB4));
+
+ state->m_Regs[EB7] |= 0x20; // CAL_ForceSrce = 1
+ CHK_ERROR(UpdateReg(state,EB7));
+
+ state->m_Regs[EB14] = 0; // RFC_Cprog = 0
+ CHK_ERROR(UpdateReg(state,EB14));
+
+ state->m_Regs[EB20] &= ~0x20; // ForceLock = 0;
+ CHK_ERROR(UpdateReg(state,EB20));
+
+ state->m_Regs[EP4] |= 0x03; // CAL_Mode = 3
+ CHK_ERROR(UpdateRegs(state,EP4,EP5));
+
+ CHK_ERROR(CalcCalPLL(state,freq));
+ CHK_ERROR(CalcMainPLL(state,freq + 1000000));
+
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state,EP1));
+
+ state->m_Regs[EB4] &= ~0x20; // LO_ForceSrce = 0
+ CHK_ERROR(UpdateReg(state,EB4));
+
+ state->m_Regs[EB7] &= ~0x20; // CAL_ForceSrce = 0
+ CHK_ERROR(UpdateReg(state,EB7));
+ msleep(10);
+
+ state->m_Regs[EB20] |= 0x20; // ForceLock = 1;
+ CHK_ERROR(UpdateReg(state,EB20));
+ msleep(60);
+
+ state->m_Regs[EP4] &= ~0x03; // CAL_Mode = 0
+ state->m_Regs[EP3] &= ~0x40; // SM_LT = 0
+ state->m_Regs[EB18] &= ~0x03; // AGC1_Gain = 0
+ CHK_ERROR(UpdateReg(state,EB18));
+ CHK_ERROR(UpdateRegs(state,EP3,EP4));
+ CHK_ERROR(UpdateReg(state,EP1));
+
+ CHK_ERROR(ReadExtented(state,Regs));
+
+ *pCprog = Regs[EB14];
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Cprog = %d\n",Regs[EB14]));
+
+ } while(0);
+ return status;
+}
+
+static int RFTrackingFiltersInit(struct tda_state *state,
+ u8 RFBand)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
+ int status = 0;
+
+ u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
+ u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
+ u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
+ bool bcal = false;
+
+ s32 Cprog_cal1 = 0;
+ s32 Cprog_table1 = 0;
+ s32 Cprog_cal2 = 0;
+ s32 Cprog_table2 = 0;
+ s32 Cprog_cal3 = 0;
+ s32 Cprog_table3 = 0;
+
+ state->m_RF_A1[RFBand] = 0;
+ state->m_RF_B1[RFBand] = 0;
+ state->m_RF_A2[RFBand] = 0;
+ state->m_RF_B2[RFBand] = 0;
+
+ do {
+ CHK_ERROR(PowerScan(state,RFBand,RF1,&RF1,&bcal));
+ if( bcal ) {
+ CHK_ERROR(CalibrateRF(state,RFBand,RF1,&Cprog_cal1));
+ }
+ SearchMap2(m_RF_Cal_Map,RF1,&Cprog_table1);
+ if( !bcal ) {
+ Cprog_cal1 = Cprog_table1;
+ }
+ state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
+ //state->m_RF_A1[RF_Band] = ????
+
+ if( RF2 == 0 ) break;
+
+ CHK_ERROR(PowerScan(state,RFBand,RF2,&RF2,&bcal));
+ if( bcal ) {
+ CHK_ERROR(CalibrateRF(state,RFBand,RF2,&Cprog_cal2));
+ }
+ SearchMap2(m_RF_Cal_Map,RF2,&Cprog_table2);
+ if( !bcal )
+ {
+ Cprog_cal2 = Cprog_table2;
+ }
+
+ state->m_RF_A1[RFBand] =
+ (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
+ ((s32)(RF2)-(s32)(RF1));
+
+ if( RF3 == 0 ) break;
+
+ CHK_ERROR(PowerScan(state,RFBand,RF3,&RF3,&bcal));
+ if( bcal )
+ {
+ CHK_ERROR(CalibrateRF(state,RFBand,RF3,&Cprog_cal3));
+ }
+ SearchMap2(m_RF_Cal_Map,RF3,&Cprog_table3);
+ if( !bcal )
+ {
+ Cprog_cal3 = Cprog_table3;
+ }
+ state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3)-(s32)(RF2));
+ state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
+
+ } while(0);
+
+ state->m_RF1[RFBand] = RF1;
+ state->m_RF2[RFBand] = RF2;
+ state->m_RF3[RFBand] = RF3;
+
+#if 0
+ printk("%s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __FUNCTION__,
+ RFBand,RF1,state->m_RF_A1[RFBand],state->m_RF_B1[RFBand],RF2,
+ state->m_RF_A2[RFBand],state->m_RF_B2[RFBand],RF3);
+#endif
+
+ return status;
+}
+
+static int PowerScan(struct tda_state *state,
+ u8 RFBand,u32 RF_in, u32 * pRF_Out, bool *pbcal)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d,%d)\n",RFBand,RF_in));
+ int status = 0;
+ do {
+ u8 Gain_Taper=0;
+ s32 RFC_Cprog=0;
+ u8 CID_Target=0;
+ u8 CountLimit=0;
+ u32 freq_MainPLL;
+ u8 Regs[NUM_REGS];
+ u8 CID_Gain;
+ s32 Count = 0;
+ int sign = 1;
+ bool wait = false;
+
+ if( ! (SearchMap2(m_RF_Cal_Map,RF_in,&RFC_Cprog) &&
+ SearchMap1(m_GainTaper_Map,RF_in,&Gain_Taper) &&
+ SearchMap3(m_CID_Target_Map,RF_in,&CID_Target,&CountLimit) )) {
+ printk("%s Search map failed\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
+ state->m_Regs[EB14] = (RFC_Cprog);
+ CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state,EB14));
+
+ freq_MainPLL = RF_in + 1000000;
+ CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
+ msleep(5);
+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; // CAL_mode = 1
+ CHK_ERROR(UpdateReg(state,EP4));
+ CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
+ CHK_ERROR(ReadExtented(state,Regs));
+ CID_Gain = Regs[EB10] & 0x3F;
+ state->m_Regs[ID] = Regs[ID]; // Chip version, (needed for C1 workarround in CalibrateRF )
+
+ *pRF_Out = RF_in;
+
+ while( CID_Gain < CID_Target ) {
+ freq_MainPLL = RF_in + sign * Count + 1000000;
+ CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
+ msleep( wait ? 5 : 1 );
+ wait = false;
+ CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
+ CHK_ERROR(ReadExtented(state,Regs));
+ CID_Gain = Regs[EB10] & 0x3F;
+ Count += 200000;
+
+ if( Count < CountLimit * 100000 ) continue;
+ if( sign < 0 ) break;
+
+ sign = -sign;
+ Count = 200000;
+ wait = true;
+ }
+ CHK_ERROR(status);
+ if( CID_Gain >= CID_Target )
+ {
+ *pbcal = true;
+ *pRF_Out = freq_MainPLL - 1000000;
+ }
+ else
+ {
+ *pbcal = false;
+ }
+ } while(0);
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Found = %d RF = %d\n",*pbcal,*pRF_Out));
+ return status;
+}
+
+static int PowerScanInit(struct tda_state *state)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
+ int status = 0;
+ do
+ {
+ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); // If level = 0, Cal mode = 0
+ CHK_ERROR(UpdateRegs(state,EP3,EP4));
+ state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03 ); // AGC 1 Gain = 0
+ CHK_ERROR(UpdateReg(state,EB18));
+ state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03 ); // AGC 2 Gain = 0 (Datasheet = 3)
+ state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06 ); // ForceLP_Fc2_En = 1, LPFc[2] = 1
+ CHK_ERROR(UpdateRegs(state,EB21,EB23));
+ } while(0);
+ return status;
+}
+
+static int CalcRFFilterCurve(struct tda_state *state)
+{
+ //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
+ int status = 0;
+ do
+ {
+ msleep(200); // Temperature stabilisation
+ CHK_ERROR(PowerScanInit(state));
+ CHK_ERROR(RFTrackingFiltersInit(state,0));
+ CHK_ERROR(RFTrackingFiltersInit(state,1));
+ CHK_ERROR(RFTrackingFiltersInit(state,2));
+ CHK_ERROR(RFTrackingFiltersInit(state,3));
+ CHK_ERROR(RFTrackingFiltersInit(state,4));
+ CHK_ERROR(RFTrackingFiltersInit(state,5));
+ CHK_ERROR(RFTrackingFiltersInit(state,6));
+ CHK_ERROR(ThermometerRead(state,&state->m_TMValue_RFCal)); // also switches off Cal mode !!!
+ } while(0);
+
+ return status;
+}
+
+static int FixedContentsI2CUpdate(struct tda_state *state)
+{
+ static u8 InitRegs[] = {
+ 0x08,0x80,0xC6,
+ 0xDF,0x16,0x60,0x80,
+ 0x80,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,
+ 0xFC,0x01,0x84,0x41,
+ 0x01,0x84,0x40,0x07,
+ 0x00,0x00,0x96,0x3F,
+ 0xC1,0x00,0x8F,0x00,
+ 0x00,0x8C,0x00,0x20,
+ 0xB3,0x48,0xB0,
+ };
+ int status = 0;
+ memcpy(&state->m_Regs[TM],InitRegs,EB23-TM+1);
+ do {
+ CHK_ERROR(UpdateRegs(state,TM,EB23));
+
+ // AGC1 gain setup
+ state->m_Regs[EB17] = 0x00;
+ CHK_ERROR(UpdateReg(state,EB17));
+ state->m_Regs[EB17] = 0x03;
+ CHK_ERROR(UpdateReg(state,EB17));
+ state->m_Regs[EB17] = 0x43;
+ CHK_ERROR(UpdateReg(state,EB17));
+ state->m_Regs[EB17] = 0x4C;
+ CHK_ERROR(UpdateReg(state,EB17));
+
+ // IRC Cal Low band
+ state->m_Regs[EP3] = 0x1F;
+ state->m_Regs[EP4] = 0x66;
+ state->m_Regs[EP5] = 0x81;
+ state->m_Regs[CPD] = 0xCC;
+ state->m_Regs[CD1] = 0x6C;
+ state->m_Regs[CD2] = 0x00;
+ state->m_Regs[CD3] = 0x00;
+ state->m_Regs[MPD] = 0xC5;
+ state->m_Regs[MD1] = 0x77;
+ state->m_Regs[MD2] = 0x08;
+ state->m_Regs[MD3] = 0x00;
+ CHK_ERROR(UpdateRegs(state,EP2,MD3)); // diff between sw and datasheet (ep3-md3)
+
+ //state->m_Regs[EB4] = 0x61; // missing in sw
+ //CHK_ERROR(UpdateReg(state,EB4));
+ //msleep(1);
+ //state->m_Regs[EB4] = 0x41;
+ //CHK_ERROR(UpdateReg(state,EB4));
+
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP1));
+ msleep(5);
+
+ state->m_Regs[EP5] = 0x85;
+ state->m_Regs[CPD] = 0xCB;
+ state->m_Regs[CD1] = 0x66;
+ state->m_Regs[CD2] = 0x70;
+ CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP2));
+ msleep(30);
+
+ // IRC Cal mid band
+ state->m_Regs[EP5] = 0x82;
+ state->m_Regs[CPD] = 0xA8;
+ state->m_Regs[CD2] = 0x00;
+ state->m_Regs[MPD] = 0xA1; // Datasheet = 0xA9
+ state->m_Regs[MD1] = 0x73;
+ state->m_Regs[MD2] = 0x1A;
+ CHK_ERROR(UpdateRegs(state,EP3,MD3));
+
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP1));
+ msleep(5);
+
+ state->m_Regs[EP5] = 0x86;
+ state->m_Regs[CPD] = 0xA8;
+ state->m_Regs[CD1] = 0x66;
+ state->m_Regs[CD2] = 0xA0;
+ CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP2));
+ msleep(30);
+
+ // IRC Cal high band
+ state->m_Regs[EP5] = 0x83;
+ state->m_Regs[CPD] = 0x98;
+ state->m_Regs[CD1] = 0x65;
+ state->m_Regs[CD2] = 0x00;
+ state->m_Regs[MPD] = 0x91; // Datasheet = 0x91
+ state->m_Regs[MD1] = 0x71;
+ state->m_Regs[MD2] = 0xCD;
+ CHK_ERROR(UpdateRegs(state,EP3,MD3));
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP1));
+ msleep(5);
+ state->m_Regs[EP5] = 0x87;
+ state->m_Regs[CD1] = 0x65;
+ state->m_Regs[CD2] = 0x50;
+ CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ msleep(5);
+ CHK_ERROR(UpdateReg(state,EP2));
+ msleep(30);
+
+ // Back to normal
+ state->m_Regs[EP4] = 0x64;
+ CHK_ERROR(UpdateReg(state,EP4));
+ CHK_ERROR(UpdateReg(state,EP1));
+
+ } while(0);
+ return status;
+}
+
+static int InitCal(struct tda_state *state)
+{
+ int status = 0;
+
+ do
+ {
+ CHK_ERROR(FixedContentsI2CUpdate(state));
+ CHK_ERROR(CalcRFFilterCurve(state));
+ CHK_ERROR(StandBy(state));
+ //m_bInitDone = true;
+ } while(0);
+ return status;
+};
+
+static int RFTrackingFiltersCorrection(struct tda_state *state,
+ u32 Frequency)
+{
+ int status = 0;
+ s32 Cprog_table;
+ u8 RFBand;
+ u8 dCoverdT;
+
+ if( !SearchMap2(m_RF_Cal_Map,Frequency,&Cprog_table) ||
+ !SearchMap4(m_RF_Band_Map,Frequency,&RFBand) ||
+ !SearchMap1(m_RF_Cal_DC_Over_DT_Map,Frequency,&dCoverdT) )
+ {
+ return -EINVAL;
+ }
+
+ do
+ {
+ u8 TMValue_Current;
+ u32 RF1 = state->m_RF1[RFBand];
+ u32 RF2 = state->m_RF1[RFBand];
+ u32 RF3 = state->m_RF1[RFBand];
+ s32 RF_A1 = state->m_RF_A1[RFBand];
+ s32 RF_B1 = state->m_RF_B1[RFBand];
+ s32 RF_A2 = state->m_RF_A2[RFBand];
+ s32 RF_B2 = state->m_RF_B2[RFBand];
+ s32 Capprox = 0;
+ int TComp;
+
+ state->m_Regs[EP3] &= ~0xE0; // Power up
+ CHK_ERROR(UpdateReg(state,EP3));
+
+ CHK_ERROR(ThermometerRead(state,&TMValue_Current));
+
+ if( RF3 == 0 || Frequency < RF2 )
+ {
+ Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
+ }
+ else
+ {
+ Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
+ }
+
+ TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
+
+ Capprox += TComp;
+
+ if( Capprox < 0 ) Capprox = 0;
+ else if( Capprox > 255 ) Capprox = 255;
+
+
+ // TODO Temperature compensation. There is defenitely a scale factor
+ // missing in the datasheet, so leave it out for now.
+ state->m_Regs[EB14] = (Capprox );
+
+ CHK_ERROR(UpdateReg(state,EB14));
+
+ } while(0);
+ return status;
+}
+
+static int ChannelConfiguration(struct tda_state *state,
+ u32 Frequency, int Standard)
+{
+
+ s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
+ int status = 0;
+
+ u8 BP_Filter = 0;
+ u8 RF_Band = 0;
+ u8 GainTaper = 0;
+ u8 IR_Meas;
+
+ state->IF=IntermediateFrequency;
+ //printk("%s Freq = %d Standard = %d IF = %d\n",__FUNCTION__,Frequency,Standard,IntermediateFrequency);
+ // get values from tables
+
+ if(! ( SearchMap1(m_BP_Filter_Map,Frequency,&BP_Filter) &&
+ SearchMap1(m_GainTaper_Map,Frequency,&GainTaper) &&
+ SearchMap1(m_IR_Meas_Map,Frequency,&IR_Meas) &&
+ SearchMap4(m_RF_Band_Map,Frequency,&RF_Band) ) )
+ {
+ printk("%s SearchMap failed\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ do
+ {
+ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
+ state->m_Regs[EP3] &= ~0x04; // switch RFAGC to high speed mode
+
+ // m_EP4 default for XToutOn, CAL_Mode (0)
+ state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax )? state->m_IFLevelDigital : state->m_IFLevelAnalog );
+ //state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
+ if( Standard <= HF_AnalogMax ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
+ else if( Standard <= HF_ATSC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
+ else if( Standard <= HF_DVBC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
+ else state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
+
+ if( (Standard == HF_FM_Radio) && state->m_bFMInput ) state->m_Regs[EP4] |= 80;
+
+ state->m_Regs[MPD] &= ~0x80;
+ if( Standard > HF_AnalogMax ) state->m_Regs[MPD] |= 0x80; // Add IF_notch for digital
+
+ state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
+
+ // Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM )
+ if( Standard == HF_FM_Radio ) state->m_Regs[EB23] |= 0x06; // ForceLP_Fc2_En = 1, LPFc[2] = 1
+ else state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LPFc[2] = 0
+
+ CHK_ERROR(UpdateRegs(state,EB22,EB23));
+
+ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; // Dis_Power_level = 1, Filter
+ state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
+ state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
+
+ state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
+ (state->m_bMaster ? 0x04 : 0x00); // CALVCO_FortLOn = MS
+ // AGC1_always_master = 0
+ // AGC_firstn = 0
+ CHK_ERROR(UpdateReg(state,EB1));
+
+ if( state->m_bMaster )
+ {
+ CHK_ERROR(CalcMainPLL(state,Frequency + IntermediateFrequency));
+ CHK_ERROR(UpdateRegs(state,TM,EP5));
+ state->m_Regs[EB4] |= 0x20; // LO_forceSrce = 1
+ CHK_ERROR(UpdateReg(state,EB4));
+ msleep(1);
+ state->m_Regs[EB4] &= ~0x20; // LO_forceSrce = 0
+ CHK_ERROR(UpdateReg(state,EB4));
+ }
+ else
+ {
+ u8 PostDiv;
+ u8 Div;
+ CHK_ERROR(CalcCalPLL(state,Frequency + IntermediateFrequency));
+
+ SearchMap3(m_Cal_PLL_Map,Frequency + IntermediateFrequency,&PostDiv,&Div);
+ state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
+ CHK_ERROR(UpdateReg(state,MPD));
+ CHK_ERROR(UpdateRegs(state,TM,EP5));
+
+ state->m_Regs[EB7] |= 0x20; // CAL_forceSrce = 1
+ CHK_ERROR(UpdateReg(state,EB7));
+ msleep(1);
+ state->m_Regs[EB7] &= ~0x20; // CAL_forceSrce = 0
+ CHK_ERROR(UpdateReg(state,EB7));
+ }
+ msleep(20);
+ if( Standard != HF_FM_Radio )
+ {
+ state->m_Regs[EP3] |= 0x04; // RFAGC to normal mode
+ }
+ CHK_ERROR(UpdateReg(state,EP3));
+
+ } while(0);
+ return status;
+}
+
+static int sleep(struct dvb_frontend* fe)
+{
+ struct tda_state *state = fe->tuner_priv;
+
+ StandBy(state);
+ return 0;
+}
+
+static int init(struct dvb_frontend* fe)
+{
+ //struct tda_state *state = fe->tuner_priv;
+ return 0;
+}
+
+static int release(struct dvb_frontend* fe)
+{
+ kfree(fe->tuner_priv);
+ fe->tuner_priv = NULL;
+ return 0;
+}
+
+static int set_params(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct tda_state *state = fe->tuner_priv;
+ int status = 0;
+ int Standard;
+
+ state->m_Frequency = params->frequency;
+
+ if (fe->ops.info.type == FE_OFDM)
+ switch (params->u.ofdm.bandwidth) {
+ case BANDWIDTH_6_MHZ:
+ Standard = HF_DVBT_6MHZ;
+ break;
+ case BANDWIDTH_7_MHZ:
+ Standard = HF_DVBT_7MHZ;
+ break;
+ default:
+ case BANDWIDTH_8_MHZ:
+ Standard = HF_DVBT_8MHZ;
+ break;
+ }
+ else if (fe->ops.info.type == FE_QAM) {
+ Standard = HF_DVBC_8MHZ;
+ } else
+ return -EINVAL;
+ do {
+ CHK_ERROR(RFTrackingFiltersCorrection(state,params->frequency));
+ CHK_ERROR(ChannelConfiguration(state,params->frequency,Standard));
+
+ msleep(state->m_SettlingTime); // Allow AGC's to settle down
+ } while(0);
+ return status;
+}
+
+#if 0
+static int GetSignalStrength(s32 * pSignalStrength,u32 RFAgc,u32 IFAgc)
+{
+ if( IFAgc < 500 ) {
+ // Scale this from 0 to 50000
+ *pSignalStrength = IFAgc * 100;
+ } else {
+ // Scale range 500-1500 to 50000-80000
+ *pSignalStrength = 50000 + (IFAgc - 500) * 30;
+ }
+
+ return 0;
+}
+#endif
+
+static int get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+ struct tda_state *state = fe->tuner_priv;
+
+ *frequency = state->IF;
+ return 0;
+}
+
+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+ //struct tda_state *state = fe->tuner_priv;
+ //*bandwidth = priv->bandwidth;
+ return 0;
+}
+
+
+static struct dvb_tuner_ops tuner_ops = {
+ .info = {
+ .name = "NXP TDA18271C2D",
+ .frequency_min = 47125000,
+ .frequency_max = 865000000,
+ .frequency_step = 62500
+ },
+ .init = init,
+ .sleep = sleep,
+ .set_params = set_params,
+ .release = release,
+ .get_frequency = get_frequency,
+ .get_bandwidth = get_bandwidth,
+};
+
+struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, u8 adr)
+{
+ struct tda_state *state;
+
+ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
+ if (!state)
+ return NULL;
+
+ fe->tuner_priv = state;
+ state->adr = adr;
+ state->i2c = i2c;
+ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
+ reset(state);
+ InitCal(state);
+
+ return fe;
+}
+
+EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
+MODULE_DESCRIPTION("TDA18271C2 driver");
+MODULE_AUTHOR("DD");
+MODULE_LICENSE("GPL");
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.h b/drivers/media/dvb/frontends/tda18271c2dd.h
new file mode 100644
index 0000000..492badd
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd.h
@@ -0,0 +1,5 @@
+#ifndef _TDA18271C2DD_H_
+#define _TDA18271C2DD_H_
+struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, u8 adr);
+#endif
diff --git a/drivers/media/dvb/frontends/tda18271c2dd_maps.h b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
new file mode 100644
index 0000000..21fa4e1
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
@@ -0,0 +1,810 @@
+enum HF_S {
+ HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
+ HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ,
+ HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ,
+ HF_DVBC_8MHZ, HF_DVBC
+};
+
+struct SStandardParam m_StandardTable[] =
+{
+ { 0, 0, 0x00, 0x00 }, // HF_None
+ { 6000000, 7000000, 0x1D, 0x2C }, // HF_B,
+ { 6900000, 8000000, 0x1E, 0x2C }, // HF_DK,
+ { 7100000, 8000000, 0x1E, 0x2C }, // HF_G,
+ { 7250000, 8000000, 0x1E, 0x2C }, // HF_I,
+ { 6900000, 8000000, 0x1E, 0x2C }, // HF_L,
+ { 1250000, 8000000, 0x1E, 0x2C }, // HF_L1,
+ { 5400000, 6000000, 0x1C, 0x2C }, // HF_MN,
+ { 1250000, 500000, 0x18, 0x2C }, // HF_FM_Radio,
+ { 0, 0, 0x00, 0x00 }, // HF_AnalogMax (Unused)
+ { 3300000, 6000000, 0x1C, 0x58 }, // HF_DVBT_6MHZ
+ { 3500000, 7000000, 0x1C, 0x37 }, // HF_DVBT_7MHZ
+ { 4000000, 8000000, 0x1D, 0x37 }, // HF_DVBT_8MHZ
+ { 0, 0, 0x00, 0x00 }, // HF_DVBT (Unused)
+ { 5000000, 6000000, 0x1C, 0x37 }, // HF_ATSC (center = 3.25 MHz)
+ { 4000000, 6000000, 0x1D, 0x58 }, // HF_DVBC_6MHZ (Chicago)
+ { 4500000, 7000000, 0x1E, 0x37 }, // HF_DVBC_7MHZ (not documented by NXP)
+ { 5000000, 8000000, 0x1F, 0x37 }, // HF_DVBC_8MHZ
+ { 0, 0, 0x00, 0x00 }, // HF_DVBC (Unused)
+};
+
+struct SMap m_BP_Filter_Map[] = {
+ { 62000000, 0x00 },
+ { 84000000, 0x01 },
+ { 100000000, 0x02 },
+ { 140000000, 0x03 },
+ { 170000000, 0x04 },
+ { 180000000, 0x05 },
+ { 865000000, 0x06 },
+ { 0, 0x00 }, // Table End
+};
+
+static struct SMapI m_RF_Cal_Map[] = {
+ { 41000000, 0x0F },
+ { 43000000, 0x1C },
+ { 45000000, 0x2F },
+ { 46000000, 0x39 },
+ { 47000000, 0x40 },
+ { 47900000, 0x50 },
+ { 49100000, 0x16 },
+ { 50000000, 0x18 },
+ { 51000000, 0x20 },
+ { 53000000, 0x28 },
+ { 55000000, 0x2B },
+ { 56000000, 0x32 },
+ { 57000000, 0x35 },
+ { 58000000, 0x3E },
+ { 59000000, 0x43 },
+ { 60000000, 0x4E },
+ { 61100000, 0x55 },
+ { 63000000, 0x0F },
+ { 64000000, 0x11 },
+ { 65000000, 0x12 },
+ { 66000000, 0x15 },
+ { 67000000, 0x16 },
+ { 68000000, 0x17 },
+ { 70000000, 0x19 },
+ { 71000000, 0x1C },
+ { 72000000, 0x1D },
+ { 73000000, 0x1F },
+ { 74000000, 0x20 },
+ { 75000000, 0x21 },
+ { 76000000, 0x24 },
+ { 77000000, 0x25 },
+ { 78000000, 0x27 },
+ { 80000000, 0x28 },
+ { 81000000, 0x29 },
+ { 82000000, 0x2D },
+ { 83000000, 0x2E },
+ { 84000000, 0x2F },
+ { 85000000, 0x31 },
+ { 86000000, 0x33 },
+ { 87000000, 0x34 },
+ { 88000000, 0x35 },
+ { 89000000, 0x37 },
+ { 90000000, 0x38 },
+ { 91000000, 0x39 },
+ { 93000000, 0x3C },
+ { 94000000, 0x3E },
+ { 95000000, 0x3F },
+ { 96000000, 0x40 },
+ { 97000000, 0x42 },
+ { 99000000, 0x45 },
+ { 100000000, 0x46 },
+ { 102000000, 0x48 },
+ { 103000000, 0x4A },
+ { 105000000, 0x4D },
+ { 106000000, 0x4E },
+ { 107000000, 0x50 },
+ { 108000000, 0x51 },
+ { 110000000, 0x54 },
+ { 111000000, 0x56 },
+ { 112000000, 0x57 },
+ { 113000000, 0x58 },
+ { 114000000, 0x59 },
+ { 115000000, 0x5C },
+ { 116000000, 0x5D },
+ { 117000000, 0x5F },
+ { 119000000, 0x60 },
+ { 120000000, 0x64 },
+ { 121000000, 0x65 },
+ { 122000000, 0x66 },
+ { 123000000, 0x68 },
+ { 124000000, 0x69 },
+ { 125000000, 0x6C },
+ { 126000000, 0x6D },
+ { 127000000, 0x6E },
+ { 128000000, 0x70 },
+ { 129000000, 0x71 },
+ { 130000000, 0x75 },
+ { 131000000, 0x77 },
+ { 132000000, 0x78 },
+ { 133000000, 0x7B },
+ { 134000000, 0x7E },
+ { 135000000, 0x81 },
+ { 136000000, 0x82 },
+ { 137000000, 0x87 },
+ { 138000000, 0x88 },
+ { 139000000, 0x8D },
+ { 140000000, 0x8E },
+ { 141000000, 0x91 },
+ { 142000000, 0x95 },
+ { 143000000, 0x9A },
+ { 144000000, 0x9D },
+ { 145000000, 0xA1 },
+ { 146000000, 0xA2 },
+ { 147000000, 0xA4 },
+ { 148000000, 0xA9 },
+ { 149000000, 0xAE },
+ { 150000000, 0xB0 },
+ { 151000000, 0xB1 },
+ { 152000000, 0xB7 },
+ { 152600000, 0xBD },
+ { 154000000, 0x20 },
+ { 155000000, 0x22 },
+ { 156000000, 0x24 },
+ { 157000000, 0x25 },
+ { 158000000, 0x27 },
+ { 159000000, 0x29 },
+ { 160000000, 0x2C },
+ { 161000000, 0x2D },
+ { 163000000, 0x2E },
+ { 164000000, 0x2F },
+ { 164700000, 0x30 },
+ { 166000000, 0x11 },
+ { 167000000, 0x12 },
+ { 168000000, 0x13 },
+ { 169000000, 0x14 },
+ { 170000000, 0x15 },
+ { 172000000, 0x16 },
+ { 173000000, 0x17 },
+ { 174000000, 0x18 },
+ { 175000000, 0x1A },
+ { 176000000, 0x1B },
+ { 178000000, 0x1D },
+ { 179000000, 0x1E },
+ { 180000000, 0x1F },
+ { 181000000, 0x20 },
+ { 182000000, 0x21 },
+ { 183000000, 0x22 },
+ { 184000000, 0x24 },
+ { 185000000, 0x25 },
+ { 186000000, 0x26 },
+ { 187000000, 0x27 },
+ { 188000000, 0x29 },
+ { 189000000, 0x2A },
+ { 190000000, 0x2C },
+ { 191000000, 0x2D },
+ { 192000000, 0x2E },
+ { 193000000, 0x2F },
+ { 194000000, 0x30 },
+ { 195000000, 0x33 },
+ { 196000000, 0x35 },
+ { 198000000, 0x36 },
+ { 200000000, 0x38 },
+ { 201000000, 0x3C },
+ { 202000000, 0x3D },
+ { 203500000, 0x3E },
+ { 206000000, 0x0E },
+ { 208000000, 0x0F },
+ { 212000000, 0x10 },
+ { 216000000, 0x11 },
+ { 217000000, 0x12 },
+ { 218000000, 0x13 },
+ { 220000000, 0x14 },
+ { 222000000, 0x15 },
+ { 225000000, 0x16 },
+ { 228000000, 0x17 },
+ { 231000000, 0x18 },
+ { 234000000, 0x19 },
+ { 235000000, 0x1A },
+ { 236000000, 0x1B },
+ { 237000000, 0x1C },
+ { 240000000, 0x1D },
+ { 242000000, 0x1E },
+ { 244000000, 0x1F },
+ { 247000000, 0x20 },
+ { 249000000, 0x21 },
+ { 252000000, 0x22 },
+ { 253000000, 0x23 },
+ { 254000000, 0x24 },
+ { 256000000, 0x25 },
+ { 259000000, 0x26 },
+ { 262000000, 0x27 },
+ { 264000000, 0x28 },
+ { 267000000, 0x29 },
+ { 269000000, 0x2A },
+ { 271000000, 0x2B },
+ { 273000000, 0x2C },
+ { 275000000, 0x2D },
+ { 277000000, 0x2E },
+ { 279000000, 0x2F },
+ { 282000000, 0x30 },
+ { 284000000, 0x31 },
+ { 286000000, 0x32 },
+ { 287000000, 0x33 },
+ { 290000000, 0x34 },
+ { 293000000, 0x35 },
+ { 295000000, 0x36 },
+ { 297000000, 0x37 },
+ { 300000000, 0x38 },
+ { 303000000, 0x39 },
+ { 305000000, 0x3A },
+ { 306000000, 0x3B },
+ { 307000000, 0x3C },
+ { 310000000, 0x3D },
+ { 312000000, 0x3E },
+ { 315000000, 0x3F },
+ { 318000000, 0x40 },
+ { 320000000, 0x41 },
+ { 323000000, 0x42 },
+ { 324000000, 0x43 },
+ { 325000000, 0x44 },
+ { 327000000, 0x45 },
+ { 331000000, 0x46 },
+ { 334000000, 0x47 },
+ { 337000000, 0x48 },
+ { 339000000, 0x49 },
+ { 340000000, 0x4A },
+ { 341000000, 0x4B },
+ { 343000000, 0x4C },
+ { 345000000, 0x4D },
+ { 349000000, 0x4E },
+ { 352000000, 0x4F },
+ { 353000000, 0x50 },
+ { 355000000, 0x51 },
+ { 357000000, 0x52 },
+ { 359000000, 0x53 },
+ { 361000000, 0x54 },
+ { 362000000, 0x55 },
+ { 364000000, 0x56 },
+ { 368000000, 0x57 },
+ { 370000000, 0x58 },
+ { 372000000, 0x59 },
+ { 375000000, 0x5A },
+ { 376000000, 0x5B },
+ { 377000000, 0x5C },
+ { 379000000, 0x5D },
+ { 382000000, 0x5E },
+ { 384000000, 0x5F },
+ { 385000000, 0x60 },
+ { 386000000, 0x61 },
+ { 388000000, 0x62 },
+ { 390000000, 0x63 },
+ { 393000000, 0x64 },
+ { 394000000, 0x65 },
+ { 396000000, 0x66 },
+ { 397000000, 0x67 },
+ { 398000000, 0x68 },
+ { 400000000, 0x69 },
+ { 402000000, 0x6A },
+ { 403000000, 0x6B },
+ { 407000000, 0x6C },
+ { 408000000, 0x6D },
+ { 409000000, 0x6E },
+ { 410000000, 0x6F },
+ { 411000000, 0x70 },
+ { 412000000, 0x71 },
+ { 413000000, 0x72 },
+ { 414000000, 0x73 },
+ { 417000000, 0x74 },
+ { 418000000, 0x75 },
+ { 420000000, 0x76 },
+ { 422000000, 0x77 },
+ { 423000000, 0x78 },
+ { 424000000, 0x79 },
+ { 427000000, 0x7A },
+ { 428000000, 0x7B },
+ { 429000000, 0x7D },
+ { 432000000, 0x7F },
+ { 434000000, 0x80 },
+ { 435000000, 0x81 },
+ { 436000000, 0x83 },
+ { 437000000, 0x84 },
+ { 438000000, 0x85 },
+ { 439000000, 0x86 },
+ { 440000000, 0x87 },
+ { 441000000, 0x88 },
+ { 442000000, 0x89 },
+ { 445000000, 0x8A },
+ { 446000000, 0x8B },
+ { 447000000, 0x8C },
+ { 448000000, 0x8E },
+ { 449000000, 0x8F },
+ { 450000000, 0x90 },
+ { 452000000, 0x91 },
+ { 453000000, 0x93 },
+ { 454000000, 0x94 },
+ { 456000000, 0x96 },
+ { 457800000, 0x98 },
+ { 461000000, 0x11 },
+ { 468000000, 0x12 },
+ { 472000000, 0x13 },
+ { 473000000, 0x14 },
+ { 474000000, 0x15 },
+ { 481000000, 0x16 },
+ { 486000000, 0x17 },
+ { 491000000, 0x18 },
+ { 498000000, 0x19 },
+ { 499000000, 0x1A },
+ { 501000000, 0x1B },
+ { 506000000, 0x1C },
+ { 511000000, 0x1D },
+ { 516000000, 0x1E },
+ { 520000000, 0x1F },
+ { 521000000, 0x20 },
+ { 525000000, 0x21 },
+ { 529000000, 0x22 },
+ { 533000000, 0x23 },
+ { 539000000, 0x24 },
+ { 541000000, 0x25 },
+ { 547000000, 0x26 },
+ { 549000000, 0x27 },
+ { 551000000, 0x28 },
+ { 556000000, 0x29 },
+ { 561000000, 0x2A },
+ { 563000000, 0x2B },
+ { 565000000, 0x2C },
+ { 569000000, 0x2D },
+ { 571000000, 0x2E },
+ { 577000000, 0x2F },
+ { 580000000, 0x30 },
+ { 582000000, 0x31 },
+ { 584000000, 0x32 },
+ { 588000000, 0x33 },
+ { 591000000, 0x34 },
+ { 596000000, 0x35 },
+ { 598000000, 0x36 },
+ { 603000000, 0x37 },
+ { 604000000, 0x38 },
+ { 606000000, 0x39 },
+ { 612000000, 0x3A },
+ { 615000000, 0x3B },
+ { 617000000, 0x3C },
+ { 621000000, 0x3D },
+ { 622000000, 0x3E },
+ { 625000000, 0x3F },
+ { 632000000, 0x40 },
+ { 633000000, 0x41 },
+ { 634000000, 0x42 },
+ { 642000000, 0x43 },
+ { 643000000, 0x44 },
+ { 647000000, 0x45 },
+ { 650000000, 0x46 },
+ { 652000000, 0x47 },
+ { 657000000, 0x48 },
+ { 661000000, 0x49 },
+ { 662000000, 0x4A },
+ { 665000000, 0x4B },
+ { 667000000, 0x4C },
+ { 670000000, 0x4D },
+ { 673000000, 0x4E },
+ { 676000000, 0x4F },
+ { 677000000, 0x50 },
+ { 681000000, 0x51 },
+ { 683000000, 0x52 },
+ { 686000000, 0x53 },
+ { 688000000, 0x54 },
+ { 689000000, 0x55 },
+ { 691000000, 0x56 },
+ { 695000000, 0x57 },
+ { 698000000, 0x58 },
+ { 703000000, 0x59 },
+ { 704000000, 0x5A },
+ { 705000000, 0x5B },
+ { 707000000, 0x5C },
+ { 710000000, 0x5D },
+ { 712000000, 0x5E },
+ { 717000000, 0x5F },
+ { 718000000, 0x60 },
+ { 721000000, 0x61 },
+ { 722000000, 0x62 },
+ { 723000000, 0x63 },
+ { 725000000, 0x64 },
+ { 727000000, 0x65 },
+ { 730000000, 0x66 },
+ { 732000000, 0x67 },
+ { 735000000, 0x68 },
+ { 740000000, 0x69 },
+ { 741000000, 0x6A },
+ { 742000000, 0x6B },
+ { 743000000, 0x6C },
+ { 745000000, 0x6D },
+ { 747000000, 0x6E },
+ { 748000000, 0x6F },
+ { 750000000, 0x70 },
+ { 752000000, 0x71 },
+ { 754000000, 0x72 },
+ { 757000000, 0x73 },
+ { 758000000, 0x74 },
+ { 760000000, 0x75 },
+ { 763000000, 0x76 },
+ { 764000000, 0x77 },
+ { 766000000, 0x78 },
+ { 767000000, 0x79 },
+ { 768000000, 0x7A },
+ { 773000000, 0x7B },
+ { 774000000, 0x7C },
+ { 776000000, 0x7D },
+ { 777000000, 0x7E },
+ { 778000000, 0x7F },
+ { 779000000, 0x80 },
+ { 781000000, 0x81 },
+ { 783000000, 0x82 },
+ { 784000000, 0x83 },
+ { 785000000, 0x84 },
+ { 786000000, 0x85 },
+ { 793000000, 0x86 },
+ { 794000000, 0x87 },
+ { 795000000, 0x88 },
+ { 797000000, 0x89 },
+ { 799000000, 0x8A },
+ { 801000000, 0x8B },
+ { 802000000, 0x8C },
+ { 803000000, 0x8D },
+ { 804000000, 0x8E },
+ { 810000000, 0x90 },
+ { 811000000, 0x91 },
+ { 812000000, 0x92 },
+ { 814000000, 0x93 },
+ { 816000000, 0x94 },
+ { 817000000, 0x96 },
+ { 818000000, 0x97 },
+ { 820000000, 0x98 },
+ { 821000000, 0x99 },
+ { 822000000, 0x9A },
+ { 828000000, 0x9B },
+ { 829000000, 0x9D },
+ { 830000000, 0x9F },
+ { 831000000, 0xA0 },
+ { 833000000, 0xA1 },
+ { 835000000, 0xA2 },
+ { 836000000, 0xA3 },
+ { 837000000, 0xA4 },
+ { 838000000, 0xA6 },
+ { 840000000, 0xA8 },
+ { 842000000, 0xA9 },
+ { 845000000, 0xAA },
+ { 846000000, 0xAB },
+ { 847000000, 0xAD },
+ { 848000000, 0xAE },
+ { 852000000, 0xAF },
+ { 853000000, 0xB0 },
+ { 858000000, 0xB1 },
+ { 860000000, 0xB2 },
+ { 861000000, 0xB3 },
+ { 862000000, 0xB4 },
+ { 863000000, 0xB6 },
+ { 864000000, 0xB8 },
+ { 865000000, 0xB9 },
+ { 0, 0x00 }, // Table End
+};
+
+
+static struct SMap2 m_KM_Map[] = {
+ { 47900000, 3, 2 },
+ { 61100000, 3, 1 },
+ { 350000000, 3, 0 },
+ { 720000000, 2, 1 },
+ { 865000000, 3, 3 },
+ { 0, 0x00 }, // Table End
+};
+
+static struct SMap2 m_Main_PLL_Map[] = {
+ { 33125000, 0x57, 0xF0 },
+ { 35500000, 0x56, 0xE0 },
+ { 38188000, 0x55, 0xD0 },
+ { 41375000, 0x54, 0xC0 },
+ { 45125000, 0x53, 0xB0 },
+ { 49688000, 0x52, 0xA0 },
+ { 55188000, 0x51, 0x90 },
+ { 62125000, 0x50, 0x80 },
+ { 66250000, 0x47, 0x78 },
+ { 71000000, 0x46, 0x70 },
+ { 76375000, 0x45, 0x68 },
+ { 82750000, 0x44, 0x60 },
+ { 90250000, 0x43, 0x58 },
+ { 99375000, 0x42, 0x50 },
+ { 110375000, 0x41, 0x48 },
+ { 124250000, 0x40, 0x40 },
+ { 132500000, 0x37, 0x3C },
+ { 142000000, 0x36, 0x38 },
+ { 152750000, 0x35, 0x34 },
+ { 165500000, 0x34, 0x30 },
+ { 180500000, 0x33, 0x2C },
+ { 198750000, 0x32, 0x28 },
+ { 220750000, 0x31, 0x24 },
+ { 248500000, 0x30, 0x20 },
+ { 265000000, 0x27, 0x1E },
+ { 284000000, 0x26, 0x1C },
+ { 305500000, 0x25, 0x1A },
+ { 331000000, 0x24, 0x18 },
+ { 361000000, 0x23, 0x16 },
+ { 397500000, 0x22, 0x14 },
+ { 441500000, 0x21, 0x12 },
+ { 497000000, 0x20, 0x10 },
+ { 530000000, 0x17, 0x0F },
+ { 568000000, 0x16, 0x0E },
+ { 611000000, 0x15, 0x0D },
+ { 662000000, 0x14, 0x0C },
+ { 722000000, 0x13, 0x0B },
+ { 795000000, 0x12, 0x0A },
+ { 883000000, 0x11, 0x09 },
+ { 994000000, 0x10, 0x08 },
+ { 0, 0x00, 0x00 }, // Table End
+};
+
+static struct SMap2 m_Cal_PLL_Map[] = {
+ { 33813000, 0xDD, 0xD0 },
+ { 36625000, 0xDC, 0xC0 },
+ { 39938000, 0xDB, 0xB0 },
+ { 43938000, 0xDA, 0xA0 },
+ { 48813000, 0xD9, 0x90 },
+ { 54938000, 0xD8, 0x80 },
+ { 62813000, 0xD3, 0x70 },
+ { 67625000, 0xCD, 0x68 },
+ { 73250000, 0xCC, 0x60 },
+ { 79875000, 0xCB, 0x58 },
+ { 87875000, 0xCA, 0x50 },
+ { 97625000, 0xC9, 0x48 },
+ { 109875000, 0xC8, 0x40 },
+ { 125625000, 0xC3, 0x38 },
+ { 135250000, 0xBD, 0x34 },
+ { 146500000, 0xBC, 0x30 },
+ { 159750000, 0xBB, 0x2C },
+ { 175750000, 0xBA, 0x28 },
+ { 195250000, 0xB9, 0x24 },
+ { 219750000, 0xB8, 0x20 },
+ { 251250000, 0xB3, 0x1C },
+ { 270500000, 0xAD, 0x1A },
+ { 293000000, 0xAC, 0x18 },
+ { 319500000, 0xAB, 0x16 },
+ { 351500000, 0xAA, 0x14 },
+ { 390500000, 0xA9, 0x12 },
+ { 439500000, 0xA8, 0x10 },
+ { 502500000, 0xA3, 0x0E },
+ { 541000000, 0x9D, 0x0D },
+ { 586000000, 0x9C, 0x0C },
+ { 639000000, 0x9B, 0x0B },
+ { 703000000, 0x9A, 0x0A },
+ { 781000000, 0x99, 0x09 },
+ { 879000000, 0x98, 0x08 },
+ { 0, 0x00, 0x00 }, // Table End
+};
+
+static struct SMap m_GainTaper_Map[] = {
+ { 45400000, 0x1F },
+ { 45800000, 0x1E },
+ { 46200000, 0x1D },
+ { 46700000, 0x1C },
+ { 47100000, 0x1B },
+ { 47500000, 0x1A },
+ { 47900000, 0x19 },
+ { 49600000, 0x17 },
+ { 51200000, 0x16 },
+ { 52900000, 0x15 },
+ { 54500000, 0x14 },
+ { 56200000, 0x13 },
+ { 57800000, 0x12 },
+ { 59500000, 0x11 },
+ { 61100000, 0x10 },
+ { 67600000, 0x0D },
+ { 74200000, 0x0C },
+ { 80700000, 0x0B },
+ { 87200000, 0x0A },
+ { 93800000, 0x09 },
+ { 100300000, 0x08 },
+ { 106900000, 0x07 },
+ { 113400000, 0x06 },
+ { 119900000, 0x05 },
+ { 126500000, 0x04 },
+ { 133000000, 0x03 },
+ { 139500000, 0x02 },
+ { 146100000, 0x01 },
+ { 152600000, 0x00 },
+ { 154300000, 0x1F },
+ { 156100000, 0x1E },
+ { 157800000, 0x1D },
+ { 159500000, 0x1C },
+ { 161200000, 0x1B },
+ { 163000000, 0x1A },
+ { 164700000, 0x19 },
+ { 170200000, 0x17 },
+ { 175800000, 0x16 },
+ { 181300000, 0x15 },
+ { 186900000, 0x14 },
+ { 192400000, 0x13 },
+ { 198000000, 0x12 },
+ { 203500000, 0x11 },
+ { 216200000, 0x14 },
+ { 228900000, 0x13 },
+ { 241600000, 0x12 },
+ { 254400000, 0x11 },
+ { 267100000, 0x10 },
+ { 279800000, 0x0F },
+ { 292500000, 0x0E },
+ { 305200000, 0x0D },
+ { 317900000, 0x0C },
+ { 330700000, 0x0B },
+ { 343400000, 0x0A },
+ { 356100000, 0x09 },
+ { 368800000, 0x08 },
+ { 381500000, 0x07 },
+ { 394200000, 0x06 },
+ { 406900000, 0x05 },
+ { 419700000, 0x04 },
+ { 432400000, 0x03 },
+ { 445100000, 0x02 },
+ { 457800000, 0x01 },
+ { 476300000, 0x19 },
+ { 494800000, 0x18 },
+ { 513300000, 0x17 },
+ { 531800000, 0x16 },
+ { 550300000, 0x15 },
+ { 568900000, 0x14 },
+ { 587400000, 0x13 },
+ { 605900000, 0x12 },
+ { 624400000, 0x11 },
+ { 642900000, 0x10 },
+ { 661400000, 0x0F },
+ { 679900000, 0x0E },
+ { 698400000, 0x0D },
+ { 716900000, 0x0C },
+ { 735400000, 0x0B },
+ { 753900000, 0x0A },
+ { 772500000, 0x09 },
+ { 791000000, 0x08 },
+ { 809500000, 0x07 },
+ { 828000000, 0x06 },
+ { 846500000, 0x05 },
+ { 865000000, 0x04 },
+ { 0, 0x00 }, // Table End
+};
+
+static struct SMap m_RF_Cal_DC_Over_DT_Map[] = {
+ { 47900000, 0x00 },
+ { 55000000, 0x00 },
+ { 61100000, 0x0A },
+ { 64000000, 0x0A },
+ { 82000000, 0x14 },
+ { 84000000, 0x19 },
+ { 119000000, 0x1C },
+ { 124000000, 0x20 },
+ { 129000000, 0x2A },
+ { 134000000, 0x32 },
+ { 139000000, 0x39 },
+ { 144000000, 0x3E },
+ { 149000000, 0x3F },
+ { 152600000, 0x40 },
+ { 154000000, 0x40 },
+ { 164700000, 0x41 },
+ { 203500000, 0x32 },
+ { 353000000, 0x19 },
+ { 356000000, 0x1A },
+ { 359000000, 0x1B },
+ { 363000000, 0x1C },
+ { 366000000, 0x1D },
+ { 369000000, 0x1E },
+ { 373000000, 0x1F },
+ { 376000000, 0x20 },
+ { 379000000, 0x21 },
+ { 383000000, 0x22 },
+ { 386000000, 0x23 },
+ { 389000000, 0x24 },
+ { 393000000, 0x25 },
+ { 396000000, 0x26 },
+ { 399000000, 0x27 },
+ { 402000000, 0x28 },
+ { 404000000, 0x29 },
+ { 407000000, 0x2A },
+ { 409000000, 0x2B },
+ { 412000000, 0x2C },
+ { 414000000, 0x2D },
+ { 417000000, 0x2E },
+ { 419000000, 0x2F },
+ { 422000000, 0x30 },
+ { 424000000, 0x31 },
+ { 427000000, 0x32 },
+ { 429000000, 0x33 },
+ { 432000000, 0x34 },
+ { 434000000, 0x35 },
+ { 437000000, 0x36 },
+ { 439000000, 0x37 },
+ { 442000000, 0x38 },
+ { 444000000, 0x39 },
+ { 447000000, 0x3A },
+ { 449000000, 0x3B },
+ { 457800000, 0x3C },
+ { 465000000, 0x0F },
+ { 477000000, 0x12 },
+ { 483000000, 0x14 },
+ { 502000000, 0x19 },
+ { 508000000, 0x1B },
+ { 519000000, 0x1C },
+ { 522000000, 0x1D },
+ { 524000000, 0x1E },
+ { 534000000, 0x1F },
+ { 549000000, 0x20 },
+ { 554000000, 0x22 },
+ { 584000000, 0x24 },
+ { 589000000, 0x26 },
+ { 658000000, 0x27 },
+ { 664000000, 0x2C },
+ { 669000000, 0x2D },
+ { 699000000, 0x2E },
+ { 704000000, 0x30 },
+ { 709000000, 0x31 },
+ { 714000000, 0x32 },
+ { 724000000, 0x33 },
+ { 729000000, 0x36 },
+ { 739000000, 0x38 },
+ { 744000000, 0x39 },
+ { 749000000, 0x3B },
+ { 754000000, 0x3C },
+ { 759000000, 0x3D },
+ { 764000000, 0x3E },
+ { 769000000, 0x3F },
+ { 774000000, 0x40 },
+ { 779000000, 0x41 },
+ { 784000000, 0x43 },
+ { 789000000, 0x46 },
+ { 794000000, 0x48 },
+ { 799000000, 0x4B },
+ { 804000000, 0x4F },
+ { 809000000, 0x54 },
+ { 814000000, 0x59 },
+ { 819000000, 0x5D },
+ { 824000000, 0x61 },
+ { 829000000, 0x68 },
+ { 834000000, 0x6E },
+ { 839000000, 0x75 },
+ { 844000000, 0x7E },
+ { 849000000, 0x82 },
+ { 854000000, 0x84 },
+ { 859000000, 0x8F },
+ { 865000000, 0x9A },
+ { 0, 0x00 }, // Table End
+};
+
+
+static struct SMap m_IR_Meas_Map[] = {
+ { 200000000, 0x05 },
+ { 400000000, 0x06 },
+ { 865000000, 0x07 },
+ { 0, 0x00 }, // Table End
+};
+
+static struct SMap2 m_CID_Target_Map[] = {
+ { 46000000, 0x04, 18 },
+ { 52200000, 0x0A, 15 },
+ { 70100000, 0x01, 40 },
+ { 136800000, 0x18, 40 },
+ { 156700000, 0x18, 40 },
+ { 186250000, 0x0A, 40 },
+ { 230000000, 0x0A, 40 },
+ { 345000000, 0x18, 40 },
+ { 426000000, 0x0E, 40 },
+ { 489500000, 0x1E, 40 },
+ { 697500000, 0x32, 40 },
+ { 842000000, 0x3A, 40 },
+ { 0, 0x00, 0 }, // Table End
+};
+
+static struct SRFBandMap m_RF_Band_Map[7] = {
+ { 47900000, 46000000, 0, 0},
+ { 61100000, 52200000, 0, 0},
+ { 152600000, 70100000, 136800000, 0},
+ { 164700000, 156700000, 0, 0},
+ { 203500000, 186250000, 0, 0},
+ { 457800000, 230000000, 345000000, 426000000},
+ { 865000000, 489500000, 697500000, 842000000},
+};
+
+u8 m_Thermometer_Map_1[16] = {
+ 60,62,66,64, 74,72,68,70, 90,88,84,86, 76,78,82,80,
+};
+
+u8 m_Thermometer_Map_2[16] = {
+ 92,94,98,96, 106,104,100,102, 122,120,116,118, 108,110,114,112,
+};
+
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
2011-07-03 16:36 ` [PATCH 01/16] tda18271c2dd: Initial check-in Oliver Endriss
@ 2011-07-03 16:37 ` Oliver Endriss
2011-07-03 16:49 ` [PATCH 05/16] DRX-K: Tons " Oliver Endriss
` (15 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:37 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/frontends/tda18271c2dd.c | 727 +++++------
drivers/media/dvb/frontends/tda18271c2dd_maps.h | 1534 ++++++++++++-----------
2 files changed, 1118 insertions(+), 1143 deletions(-)
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.c b/drivers/media/dvb/frontends/tda18271c2dd.c
index b4a23bf..a8afc22 100644
--- a/drivers/media/dvb/frontends/tda18271c2dd.c
+++ b/drivers/media/dvb/frontends/tda18271c2dd.c
@@ -64,8 +64,7 @@ struct SRFBandMap {
u32 m_RF3_Default;
};
-enum ERegister
-{
+enum ERegister {
ID = 0,
TM,
PL,
@@ -115,13 +114,13 @@ struct tda_state {
};
static int PowerScan(struct tda_state *state,
- u8 RFBand,u32 RF_in,
- u32 * pRF_Out, bool *pbcal);
+ u8 RFBand, u32 RF_in,
+ u32 *pRF_Out, bool *pbcal);
static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
{
struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
- .buf = data, .len = len}};
+ .buf = data, .len = len} };
return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
}
@@ -131,7 +130,7 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
- printk("i2c_write error\n");
+ printk(KERN_ERR "i2c_write error\n");
return -1;
}
return 0;
@@ -147,7 +146,7 @@ static int WriteRegs(struct tda_state *state,
return i2c_write(state->i2c, state->adr, data, nRegs+1);
}
-static int WriteReg(struct tda_state *state, u8 SubAddr,u8 Reg)
+static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg)
{
u8 msg[2] = {SubAddr, Reg};
@@ -164,14 +163,14 @@ static int ReadExtented(struct tda_state *state, u8 * Regs)
return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
}
-static int UpdateRegs(struct tda_state *state, u8 RegFrom,u8 RegTo)
+static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo)
{
return WriteRegs(state, RegFrom,
&state->m_Regs[RegFrom], RegTo-RegFrom+1);
}
static int UpdateReg(struct tda_state *state, u8 Reg)
{
- return WriteReg(state, Reg,state->m_Regs[Reg]);
+ return WriteReg(state, Reg, state->m_Regs[Reg]);
}
#include "tda18271c2dd_maps.h"
@@ -186,7 +185,7 @@ static void reset(struct tda_state *state)
u32 ulIFLevelDVBC = 7;
u32 ulIFLevelDVBT = 6;
u32 ulXTOut = 0;
- u32 ulStandbyMode = 0x06; // Send in stdb, but leave osc on
+ u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */
u32 ulSlave = 0;
u32 ulFMInput = 0;
u32 ulSettlingTime = 100;
@@ -199,7 +198,8 @@ static void reset(struct tda_state *state)
state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
state->m_EP4 = 0x20;
- if( ulXTOut != 0 ) state->m_EP4 |= 0x40;
+ if (ulXTOut != 0)
+ state->m_EP4 |= 0x40;
state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
state->m_bMaster = (ulSlave == 0);
@@ -214,7 +214,7 @@ static bool SearchMap1(struct SMap Map[],
{
int i = 0;
- while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency) )
+ while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency))
i += 1;
if (Map[i].m_Frequency == 0)
return false;
@@ -228,7 +228,7 @@ static bool SearchMap2(struct SMapI Map[],
int i = 0;
while ((Map[i].m_Frequency != 0) &&
- (Frequency > Map[i].m_Frequency) )
+ (Frequency > Map[i].m_Frequency))
i += 1;
if (Map[i].m_Frequency == 0)
return false;
@@ -236,13 +236,13 @@ static bool SearchMap2(struct SMapI Map[],
return true;
}
-static bool SearchMap3(struct SMap2 Map[],u32 Frequency,
+static bool SearchMap3(struct SMap2 Map[], u32 Frequency,
u8 *pParam1, u8 *pParam2)
{
int i = 0;
while ((Map[i].m_Frequency != 0) &&
- (Frequency > Map[i].m_Frequency) )
+ (Frequency > Map[i].m_Frequency))
i += 1;
if (Map[i].m_Frequency == 0)
return false;
@@ -271,22 +271,23 @@ static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
do {
u8 Regs[16];
state->m_Regs[TM] |= 0x10;
- CHK_ERROR(UpdateReg(state,TM));
- CHK_ERROR(Read(state,Regs));
- if( ( (Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20 ) ||
- ( (Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00 ) ) {
+ CHK_ERROR(UpdateReg(state, TM));
+ CHK_ERROR(Read(state, Regs));
+ if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) ||
+ ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) {
state->m_Regs[TM] ^= 0x20;
- CHK_ERROR(UpdateReg(state,TM));
+ CHK_ERROR(UpdateReg(state, TM));
msleep(10);
- CHK_ERROR(Read(state,Regs));
+ CHK_ERROR(Read(state, Regs));
}
- *pTM_Value = (Regs[TM] & 0x20 ) ? m_Thermometer_Map_2[Regs[TM] & 0x0F] :
- m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
- state->m_Regs[TM] &= ~0x10; // Thermometer off
- CHK_ERROR(UpdateReg(state,TM));
- state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0 ?????????
- CHK_ERROR(UpdateReg(state,EP4));
- } while(0);
+ *pTM_Value = (Regs[TM] & 0x20)
+ ? m_Thermometer_Map_2[Regs[TM] & 0x0F]
+ : m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
+ state->m_Regs[TM] &= ~0x10; /* Thermometer off */
+ CHK_ERROR(UpdateReg(state, TM));
+ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
+ CHK_ERROR(UpdateReg(state, EP4));
+ } while (0);
return status;
}
@@ -295,16 +296,16 @@ static int StandBy(struct tda_state *state)
{
int status = 0;
do {
- state->m_Regs[EB12] &= ~0x20; // PD_AGC1_Det = 0
- CHK_ERROR(UpdateReg(state,EB12));
- state->m_Regs[EB18] &= ~0x83; // AGC1_loop_off = 0, AGC1_Gain = 6 dB
- CHK_ERROR(UpdateReg(state,EB18));
- state->m_Regs[EB21] |= 0x03; // AGC2_Gain = -6 dB
+ state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */
+ CHK_ERROR(UpdateReg(state, EB12));
+ state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */
+ CHK_ERROR(UpdateReg(state, EB18));
+ state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */
state->m_Regs[EP3] = state->m_EP3_Standby;
- CHK_ERROR(UpdateReg(state,EP3));
- state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LP_Fc[2] = 0
- CHK_ERROR(UpdateRegs(state,EB21,EB23));
- } while(0);
+ CHK_ERROR(UpdateReg(state, EP3));
+ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */
+ CHK_ERROR(UpdateRegs(state, EB21, EB23));
+ } while (0);
return status;
}
@@ -316,9 +317,8 @@ static int CalcMainPLL(struct tda_state *state, u32 freq)
u64 OscFreq;
u32 MainDiv;
- if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) {
+ if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div))
return -EINVAL;
- }
OscFreq = (u64) freq * (u64) Div;
OscFreq *= (u64) 16384;
@@ -328,133 +328,122 @@ static int CalcMainPLL(struct tda_state *state, u32 freq)
state->m_Regs[MPD] = PostDiv & 0x77;
state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
- state->m_Regs[MD3] = ((MainDiv ) & 0xFF);
+ state->m_Regs[MD3] = (MainDiv & 0xFF);
return UpdateRegs(state, MPD, MD3);
}
static int CalcCalPLL(struct tda_state *state, u32 freq)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",freq));
-
u8 PostDiv;
u8 Div;
u64 OscFreq;
u32 CalDiv;
- if( !SearchMap3(m_Cal_PLL_Map,freq,&PostDiv,&Div) )
- {
+ if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div))
return -EINVAL;
- }
OscFreq = (u64)freq * (u64)Div;
- //CalDiv = u32( OscFreq * 16384 / 16000000 );
- OscFreq*=(u64)16384;
+ /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */
+ OscFreq *= (u64)16384;
do_div(OscFreq, (u64)16000000);
- CalDiv=OscFreq;
+ CalDiv = OscFreq;
state->m_Regs[CPD] = PostDiv;
state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
- state->m_Regs[CD3] = ((CalDiv ) & 0xFF);
+ state->m_Regs[CD3] = (CalDiv & 0xFF);
- return UpdateRegs(state,CPD,CD3);
+ return UpdateRegs(state, CPD, CD3);
}
static int CalibrateRF(struct tda_state *state,
- u8 RFBand,u32 freq, s32 * pCprog)
+ u8 RFBand, u32 freq, s32 *pCprog)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " ID = %02x\n",state->m_Regs[ID]));
int status = 0;
u8 Regs[NUM_REGS];
do {
- u8 BP_Filter=0;
- u8 GainTaper=0;
- u8 RFC_K=0;
- u8 RFC_M=0;
-
- state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0
- CHK_ERROR(UpdateReg(state,EP4));
- state->m_Regs[EB18] |= 0x03; // AGC1_Gain = 3
- CHK_ERROR(UpdateReg(state,EB18));
-
- // Switching off LT (as datasheet says) causes calibration on C1 to fail
- // (Readout of Cprog is allways 255)
- if( state->m_Regs[ID] != 0x83 ) // C1: ID == 83, C2: ID == 84
- {
- state->m_Regs[EP3] |= 0x40; // SM_LT = 1
- }
-
- if( ! ( SearchMap1(m_BP_Filter_Map,freq,&BP_Filter) &&
- SearchMap1(m_GainTaper_Map,freq,&GainTaper) &&
- SearchMap3(m_KM_Map,freq,&RFC_K,&RFC_M)) )
- {
+ u8 BP_Filter = 0;
+ u8 GainTaper = 0;
+ u8 RFC_K = 0;
+ u8 RFC_M = 0;
+
+ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
+ CHK_ERROR(UpdateReg(state, EP4));
+ state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */
+ CHK_ERROR(UpdateReg(state, EB18));
+
+ /* Switching off LT (as datasheet says) causes calibration on C1 to fail */
+ /* (Readout of Cprog is allways 255) */
+ if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */
+ state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */
+
+ if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) &&
+ SearchMap1(m_GainTaper_Map, freq, &GainTaper) &&
+ SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M)))
return -EINVAL;
- }
state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
- CHK_ERROR(UpdateRegs(state,EP1,EP3));
- CHK_ERROR(UpdateReg(state,EB13));
+ CHK_ERROR(UpdateRegs(state, EP1, EP3));
+ CHK_ERROR(UpdateReg(state, EB13));
- state->m_Regs[EB4] |= 0x20; // LO_ForceSrce = 1
- CHK_ERROR(UpdateReg(state,EB4));
+ state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */
+ CHK_ERROR(UpdateReg(state, EB4));
- state->m_Regs[EB7] |= 0x20; // CAL_ForceSrce = 1
- CHK_ERROR(UpdateReg(state,EB7));
+ state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */
+ CHK_ERROR(UpdateReg(state, EB7));
- state->m_Regs[EB14] = 0; // RFC_Cprog = 0
- CHK_ERROR(UpdateReg(state,EB14));
+ state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */
+ CHK_ERROR(UpdateReg(state, EB14));
- state->m_Regs[EB20] &= ~0x20; // ForceLock = 0;
- CHK_ERROR(UpdateReg(state,EB20));
+ state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */
+ CHK_ERROR(UpdateReg(state, EB20));
- state->m_Regs[EP4] |= 0x03; // CAL_Mode = 3
- CHK_ERROR(UpdateRegs(state,EP4,EP5));
+ state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
+ CHK_ERROR(UpdateRegs(state, EP4, EP5));
- CHK_ERROR(CalcCalPLL(state,freq));
- CHK_ERROR(CalcMainPLL(state,freq + 1000000));
+ CHK_ERROR(CalcCalPLL(state, freq));
+ CHK_ERROR(CalcMainPLL(state, freq + 1000000));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP2));
- CHK_ERROR(UpdateReg(state,EP1));
- CHK_ERROR(UpdateReg(state,EP2));
- CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state, EP2));
+ CHK_ERROR(UpdateReg(state, EP1));
+ CHK_ERROR(UpdateReg(state, EP2));
+ CHK_ERROR(UpdateReg(state, EP1));
- state->m_Regs[EB4] &= ~0x20; // LO_ForceSrce = 0
- CHK_ERROR(UpdateReg(state,EB4));
+ state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */
+ CHK_ERROR(UpdateReg(state, EB4));
- state->m_Regs[EB7] &= ~0x20; // CAL_ForceSrce = 0
- CHK_ERROR(UpdateReg(state,EB7));
+ state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */
+ CHK_ERROR(UpdateReg(state, EB7));
msleep(10);
- state->m_Regs[EB20] |= 0x20; // ForceLock = 1;
- CHK_ERROR(UpdateReg(state,EB20));
+ state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */
+ CHK_ERROR(UpdateReg(state, EB20));
msleep(60);
- state->m_Regs[EP4] &= ~0x03; // CAL_Mode = 0
- state->m_Regs[EP3] &= ~0x40; // SM_LT = 0
- state->m_Regs[EB18] &= ~0x03; // AGC1_Gain = 0
- CHK_ERROR(UpdateReg(state,EB18));
- CHK_ERROR(UpdateRegs(state,EP3,EP4));
- CHK_ERROR(UpdateReg(state,EP1));
+ state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
+ state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */
+ state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */
+ CHK_ERROR(UpdateReg(state, EB18));
+ CHK_ERROR(UpdateRegs(state, EP3, EP4));
+ CHK_ERROR(UpdateReg(state, EP1));
- CHK_ERROR(ReadExtented(state,Regs));
+ CHK_ERROR(ReadExtented(state, Regs));
*pCprog = Regs[EB14];
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Cprog = %d\n",Regs[EB14]));
- } while(0);
+ } while (0);
return status;
}
static int RFTrackingFiltersInit(struct tda_state *state,
u8 RFBand)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
int status = 0;
u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
@@ -475,171 +464,161 @@ static int RFTrackingFiltersInit(struct tda_state *state,
state->m_RF_B2[RFBand] = 0;
do {
- CHK_ERROR(PowerScan(state,RFBand,RF1,&RF1,&bcal));
- if( bcal ) {
- CHK_ERROR(CalibrateRF(state,RFBand,RF1,&Cprog_cal1));
+ CHK_ERROR(PowerScan(state, RFBand, RF1, &RF1, &bcal));
+ if (bcal) {
+ CHK_ERROR(CalibrateRF(state, RFBand, RF1, &Cprog_cal1));
}
- SearchMap2(m_RF_Cal_Map,RF1,&Cprog_table1);
- if( !bcal ) {
+ SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1);
+ if (!bcal)
Cprog_cal1 = Cprog_table1;
- }
state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
- //state->m_RF_A1[RF_Band] = ????
+ /* state->m_RF_A1[RF_Band] = ???? */
- if( RF2 == 0 ) break;
+ if (RF2 == 0)
+ break;
- CHK_ERROR(PowerScan(state,RFBand,RF2,&RF2,&bcal));
- if( bcal ) {
- CHK_ERROR(CalibrateRF(state,RFBand,RF2,&Cprog_cal2));
+ CHK_ERROR(PowerScan(state, RFBand, RF2, &RF2, &bcal));
+ if (bcal) {
+ CHK_ERROR(CalibrateRF(state, RFBand, RF2, &Cprog_cal2));
}
- SearchMap2(m_RF_Cal_Map,RF2,&Cprog_table2);
- if( !bcal )
- {
+ SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2);
+ if (!bcal)
Cprog_cal2 = Cprog_table2;
- }
state->m_RF_A1[RFBand] =
(Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
- ((s32)(RF2)-(s32)(RF1));
+ ((s32)(RF2) - (s32)(RF1));
- if( RF3 == 0 ) break;
+ if (RF3 == 0)
+ break;
- CHK_ERROR(PowerScan(state,RFBand,RF3,&RF3,&bcal));
- if( bcal )
- {
- CHK_ERROR(CalibrateRF(state,RFBand,RF3,&Cprog_cal3));
+ CHK_ERROR(PowerScan(state, RFBand, RF3, &RF3, &bcal));
+ if (bcal) {
+ CHK_ERROR(CalibrateRF(state, RFBand, RF3, &Cprog_cal3));
}
- SearchMap2(m_RF_Cal_Map,RF3,&Cprog_table3);
- if( !bcal )
- {
+ SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3);
+ if (!bcal)
Cprog_cal3 = Cprog_table3;
- }
- state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3)-(s32)(RF2));
+ state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2));
state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
- } while(0);
+ } while (0);
state->m_RF1[RFBand] = RF1;
state->m_RF2[RFBand] = RF2;
state->m_RF3[RFBand] = RF3;
#if 0
- printk("%s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __FUNCTION__,
- RFBand,RF1,state->m_RF_A1[RFBand],state->m_RF_B1[RFBand],RF2,
- state->m_RF_A2[RFBand],state->m_RF_B2[RFBand],RF3);
+ printk(KERN_ERR "%s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__,
+ RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2,
+ state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3);
#endif
return status;
}
static int PowerScan(struct tda_state *state,
- u8 RFBand,u32 RF_in, u32 * pRF_Out, bool *pbcal)
+ u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d,%d)\n",RFBand,RF_in));
- int status = 0;
- do {
- u8 Gain_Taper=0;
- s32 RFC_Cprog=0;
- u8 CID_Target=0;
- u8 CountLimit=0;
- u32 freq_MainPLL;
- u8 Regs[NUM_REGS];
- u8 CID_Gain;
- s32 Count = 0;
- int sign = 1;
- bool wait = false;
-
- if( ! (SearchMap2(m_RF_Cal_Map,RF_in,&RFC_Cprog) &&
- SearchMap1(m_GainTaper_Map,RF_in,&Gain_Taper) &&
- SearchMap3(m_CID_Target_Map,RF_in,&CID_Target,&CountLimit) )) {
- printk("%s Search map failed\n", __FUNCTION__);
- return -EINVAL;
- }
-
- state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
- state->m_Regs[EB14] = (RFC_Cprog);
- CHK_ERROR(UpdateReg(state,EP2));
- CHK_ERROR(UpdateReg(state,EB14));
-
- freq_MainPLL = RF_in + 1000000;
- CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
- msleep(5);
- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; // CAL_mode = 1
- CHK_ERROR(UpdateReg(state,EP4));
- CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
- CHK_ERROR(ReadExtented(state,Regs));
- CID_Gain = Regs[EB10] & 0x3F;
- state->m_Regs[ID] = Regs[ID]; // Chip version, (needed for C1 workarround in CalibrateRF )
-
- *pRF_Out = RF_in;
-
- while( CID_Gain < CID_Target ) {
- freq_MainPLL = RF_in + sign * Count + 1000000;
- CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
- msleep( wait ? 5 : 1 );
- wait = false;
- CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
- CHK_ERROR(ReadExtented(state,Regs));
- CID_Gain = Regs[EB10] & 0x3F;
- Count += 200000;
-
- if( Count < CountLimit * 100000 ) continue;
- if( sign < 0 ) break;
-
- sign = -sign;
- Count = 200000;
- wait = true;
- }
- CHK_ERROR(status);
- if( CID_Gain >= CID_Target )
- {
- *pbcal = true;
- *pRF_Out = freq_MainPLL - 1000000;
- }
- else
- {
- *pbcal = false;
- }
- } while(0);
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Found = %d RF = %d\n",*pbcal,*pRF_Out));
- return status;
+ int status = 0;
+ do {
+ u8 Gain_Taper = 0;
+ s32 RFC_Cprog = 0;
+ u8 CID_Target = 0;
+ u8 CountLimit = 0;
+ u32 freq_MainPLL;
+ u8 Regs[NUM_REGS];
+ u8 CID_Gain;
+ s32 Count = 0;
+ int sign = 1;
+ bool wait = false;
+
+ if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) &&
+ SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) &&
+ SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) {
+
+ printk(KERN_ERR "%s Search map failed\n", __func__);
+ return -EINVAL;
+ }
+
+ state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
+ state->m_Regs[EB14] = (RFC_Cprog);
+ CHK_ERROR(UpdateReg(state, EP2));
+ CHK_ERROR(UpdateReg(state, EB14));
+
+ freq_MainPLL = RF_in + 1000000;
+ CHK_ERROR(CalcMainPLL(state, freq_MainPLL));
+ msleep(5);
+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
+ CHK_ERROR(UpdateReg(state, EP4));
+ CHK_ERROR(UpdateReg(state, EP2)); /* Launch power measurement */
+ CHK_ERROR(ReadExtented(state, Regs));
+ CID_Gain = Regs[EB10] & 0x3F;
+ state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */
+
+ *pRF_Out = RF_in;
+
+ while (CID_Gain < CID_Target) {
+ freq_MainPLL = RF_in + sign * Count + 1000000;
+ CHK_ERROR(CalcMainPLL(state, freq_MainPLL));
+ msleep(wait ? 5 : 1);
+ wait = false;
+ CHK_ERROR(UpdateReg(state, EP2)); /* Launch power measurement */
+ CHK_ERROR(ReadExtented(state, Regs));
+ CID_Gain = Regs[EB10] & 0x3F;
+ Count += 200000;
+
+ if (Count < CountLimit * 100000)
+ continue;
+ if (sign < 0)
+ break;
+
+ sign = -sign;
+ Count = 200000;
+ wait = true;
+ }
+ CHK_ERROR(status);
+ if (CID_Gain >= CID_Target) {
+ *pbcal = true;
+ *pRF_Out = freq_MainPLL - 1000000;
+ } else
+ *pbcal = false;
+ } while (0);
+
+ return status;
}
static int PowerScanInit(struct tda_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
int status = 0;
- do
- {
+ do {
state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); // If level = 0, Cal mode = 0
- CHK_ERROR(UpdateRegs(state,EP3,EP4));
- state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03 ); // AGC 1 Gain = 0
- CHK_ERROR(UpdateReg(state,EB18));
- state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03 ); // AGC 2 Gain = 0 (Datasheet = 3)
- state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06 ); // ForceLP_Fc2_En = 1, LPFc[2] = 1
- CHK_ERROR(UpdateRegs(state,EB21,EB23));
- } while(0);
+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
+ CHK_ERROR(UpdateRegs(state, EP3, EP4));
+ state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */
+ CHK_ERROR(UpdateReg(state, EB18));
+ state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */
+ state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
+ CHK_ERROR(UpdateRegs(state, EB21, EB23));
+ } while (0);
return status;
}
static int CalcRFFilterCurve(struct tda_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
int status = 0;
- do
- {
- msleep(200); // Temperature stabilisation
+ do {
+ msleep(200); /* Temperature stabilisation */
CHK_ERROR(PowerScanInit(state));
- CHK_ERROR(RFTrackingFiltersInit(state,0));
- CHK_ERROR(RFTrackingFiltersInit(state,1));
- CHK_ERROR(RFTrackingFiltersInit(state,2));
- CHK_ERROR(RFTrackingFiltersInit(state,3));
- CHK_ERROR(RFTrackingFiltersInit(state,4));
- CHK_ERROR(RFTrackingFiltersInit(state,5));
- CHK_ERROR(RFTrackingFiltersInit(state,6));
- CHK_ERROR(ThermometerRead(state,&state->m_TMValue_RFCal)); // also switches off Cal mode !!!
- } while(0);
+ CHK_ERROR(RFTrackingFiltersInit(state, 0));
+ CHK_ERROR(RFTrackingFiltersInit(state, 1));
+ CHK_ERROR(RFTrackingFiltersInit(state, 2));
+ CHK_ERROR(RFTrackingFiltersInit(state, 3));
+ CHK_ERROR(RFTrackingFiltersInit(state, 4));
+ CHK_ERROR(RFTrackingFiltersInit(state, 5));
+ CHK_ERROR(RFTrackingFiltersInit(state, 6));
+ CHK_ERROR(ThermometerRead(state, &state->m_TMValue_RFCal)); /* also switches off Cal mode !!! */
+ } while (0);
return status;
}
@@ -647,33 +626,33 @@ static int CalcRFFilterCurve(struct tda_state *state)
static int FixedContentsI2CUpdate(struct tda_state *state)
{
static u8 InitRegs[] = {
- 0x08,0x80,0xC6,
- 0xDF,0x16,0x60,0x80,
- 0x80,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,
- 0xFC,0x01,0x84,0x41,
- 0x01,0x84,0x40,0x07,
- 0x00,0x00,0x96,0x3F,
- 0xC1,0x00,0x8F,0x00,
- 0x00,0x8C,0x00,0x20,
- 0xB3,0x48,0xB0,
+ 0x08, 0x80, 0xC6,
+ 0xDF, 0x16, 0x60, 0x80,
+ 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xFC, 0x01, 0x84, 0x41,
+ 0x01, 0x84, 0x40, 0x07,
+ 0x00, 0x00, 0x96, 0x3F,
+ 0xC1, 0x00, 0x8F, 0x00,
+ 0x00, 0x8C, 0x00, 0x20,
+ 0xB3, 0x48, 0xB0,
};
int status = 0;
- memcpy(&state->m_Regs[TM],InitRegs,EB23-TM+1);
+ memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1);
do {
- CHK_ERROR(UpdateRegs(state,TM,EB23));
+ CHK_ERROR(UpdateRegs(state, TM, EB23));
- // AGC1 gain setup
+ /* AGC1 gain setup */
state->m_Regs[EB17] = 0x00;
- CHK_ERROR(UpdateReg(state,EB17));
+ CHK_ERROR(UpdateReg(state, EB17));
state->m_Regs[EB17] = 0x03;
- CHK_ERROR(UpdateReg(state,EB17));
+ CHK_ERROR(UpdateReg(state, EB17));
state->m_Regs[EB17] = 0x43;
- CHK_ERROR(UpdateReg(state,EB17));
+ CHK_ERROR(UpdateReg(state, EB17));
state->m_Regs[EB17] = 0x4C;
- CHK_ERROR(UpdateReg(state,EB17));
+ CHK_ERROR(UpdateReg(state, EB17));
- // IRC Cal Low band
+ /* IRC Cal Low band */
state->m_Regs[EP3] = 0x1F;
state->m_Regs[EP4] = 0x66;
state->m_Regs[EP5] = 0x81;
@@ -685,75 +664,77 @@ static int FixedContentsI2CUpdate(struct tda_state *state)
state->m_Regs[MD1] = 0x77;
state->m_Regs[MD2] = 0x08;
state->m_Regs[MD3] = 0x00;
- CHK_ERROR(UpdateRegs(state,EP2,MD3)); // diff between sw and datasheet (ep3-md3)
+ CHK_ERROR(UpdateRegs(state, EP2, MD3)); /* diff between sw and datasheet (ep3-md3) */
- //state->m_Regs[EB4] = 0x61; // missing in sw
- //CHK_ERROR(UpdateReg(state,EB4));
- //msleep(1);
- //state->m_Regs[EB4] = 0x41;
- //CHK_ERROR(UpdateReg(state,EB4));
+#if 0
+ state->m_Regs[EB4] = 0x61; /* missing in sw */
+ CHK_ERROR(UpdateReg(state, EB4));
+ msleep(1);
+ state->m_Regs[EB4] = 0x41;
+ CHK_ERROR(UpdateReg(state, EB4));
+#endif
msleep(5);
- CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state, EP1));
msleep(5);
state->m_Regs[EP5] = 0x85;
state->m_Regs[CPD] = 0xCB;
state->m_Regs[CD1] = 0x66;
state->m_Regs[CD2] = 0x70;
- CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ CHK_ERROR(UpdateRegs(state, EP3, CD3));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state, EP2));
msleep(30);
- // IRC Cal mid band
+ /* IRC Cal mid band */
state->m_Regs[EP5] = 0x82;
state->m_Regs[CPD] = 0xA8;
state->m_Regs[CD2] = 0x00;
- state->m_Regs[MPD] = 0xA1; // Datasheet = 0xA9
+ state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */
state->m_Regs[MD1] = 0x73;
state->m_Regs[MD2] = 0x1A;
- CHK_ERROR(UpdateRegs(state,EP3,MD3));
+ CHK_ERROR(UpdateRegs(state, EP3, MD3));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state, EP1));
msleep(5);
state->m_Regs[EP5] = 0x86;
state->m_Regs[CPD] = 0xA8;
state->m_Regs[CD1] = 0x66;
state->m_Regs[CD2] = 0xA0;
- CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ CHK_ERROR(UpdateRegs(state, EP3, CD3));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state, EP2));
msleep(30);
- // IRC Cal high band
+ /* IRC Cal high band */
state->m_Regs[EP5] = 0x83;
state->m_Regs[CPD] = 0x98;
state->m_Regs[CD1] = 0x65;
state->m_Regs[CD2] = 0x00;
- state->m_Regs[MPD] = 0x91; // Datasheet = 0x91
+ state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */
state->m_Regs[MD1] = 0x71;
state->m_Regs[MD2] = 0xCD;
- CHK_ERROR(UpdateRegs(state,EP3,MD3));
+ CHK_ERROR(UpdateRegs(state, EP3, MD3));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state, EP1));
msleep(5);
state->m_Regs[EP5] = 0x87;
state->m_Regs[CD1] = 0x65;
state->m_Regs[CD2] = 0x50;
- CHK_ERROR(UpdateRegs(state,EP3,CD3));
+ CHK_ERROR(UpdateRegs(state, EP3, CD3));
msleep(5);
- CHK_ERROR(UpdateReg(state,EP2));
+ CHK_ERROR(UpdateReg(state, EP2));
msleep(30);
- // Back to normal
+ /* Back to normal */
state->m_Regs[EP4] = 0x64;
- CHK_ERROR(UpdateReg(state,EP4));
- CHK_ERROR(UpdateReg(state,EP1));
+ CHK_ERROR(UpdateReg(state, EP4));
+ CHK_ERROR(UpdateReg(state, EP1));
- } while(0);
+ } while (0);
return status;
}
@@ -761,13 +742,12 @@ static int InitCal(struct tda_state *state)
{
int status = 0;
- do
- {
+ do {
CHK_ERROR(FixedContentsI2CUpdate(state));
CHK_ERROR(CalcRFFilterCurve(state));
CHK_ERROR(StandBy(state));
- //m_bInitDone = true;
- } while(0);
+ /* m_bInitDone = true; */
+ } while (0);
return status;
};
@@ -779,15 +759,13 @@ static int RFTrackingFiltersCorrection(struct tda_state *state,
u8 RFBand;
u8 dCoverdT;
- if( !SearchMap2(m_RF_Cal_Map,Frequency,&Cprog_table) ||
- !SearchMap4(m_RF_Band_Map,Frequency,&RFBand) ||
- !SearchMap1(m_RF_Cal_DC_Over_DT_Map,Frequency,&dCoverdT) )
- {
+ if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) ||
+ !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) ||
+ !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT))
+
return -EINVAL;
- }
- do
- {
+ do {
u8 TMValue_Current;
u32 RF1 = state->m_RF1[RFBand];
u32 RF2 = state->m_RF1[RFBand];
@@ -799,35 +777,33 @@ static int RFTrackingFiltersCorrection(struct tda_state *state,
s32 Capprox = 0;
int TComp;
- state->m_Regs[EP3] &= ~0xE0; // Power up
- CHK_ERROR(UpdateReg(state,EP3));
+ state->m_Regs[EP3] &= ~0xE0; /* Power up */
+ CHK_ERROR(UpdateReg(state, EP3));
- CHK_ERROR(ThermometerRead(state,&TMValue_Current));
+ CHK_ERROR(ThermometerRead(state, &TMValue_Current));
- if( RF3 == 0 || Frequency < RF2 )
- {
+ if (RF3 == 0 || Frequency < RF2)
Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
- }
else
- {
Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
- }
TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
Capprox += TComp;
- if( Capprox < 0 ) Capprox = 0;
- else if( Capprox > 255 ) Capprox = 255;
+ if (Capprox < 0)
+ Capprox = 0;
+ else if (Capprox > 255)
+ Capprox = 255;
- // TODO Temperature compensation. There is defenitely a scale factor
- // missing in the datasheet, so leave it out for now.
- state->m_Regs[EB14] = (Capprox );
+ /* TODO Temperature compensation. There is defenitely a scale factor */
+ /* missing in the datasheet, so leave it out for now. */
+ state->m_Regs[EB14] = Capprox;
- CHK_ERROR(UpdateReg(state,EB14));
+ CHK_ERROR(UpdateReg(state, EB14));
- } while(0);
+ } while (0);
return status;
}
@@ -843,94 +819,96 @@ static int ChannelConfiguration(struct tda_state *state,
u8 GainTaper = 0;
u8 IR_Meas;
- state->IF=IntermediateFrequency;
- //printk("%s Freq = %d Standard = %d IF = %d\n",__FUNCTION__,Frequency,Standard,IntermediateFrequency);
- // get values from tables
+ state->IF = IntermediateFrequency;
+ /* printk("%s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
+ /* get values from tables */
- if(! ( SearchMap1(m_BP_Filter_Map,Frequency,&BP_Filter) &&
- SearchMap1(m_GainTaper_Map,Frequency,&GainTaper) &&
- SearchMap1(m_IR_Meas_Map,Frequency,&IR_Meas) &&
- SearchMap4(m_RF_Band_Map,Frequency,&RF_Band) ) )
- {
- printk("%s SearchMap failed\n", __FUNCTION__);
+ if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
+ SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) &&
+ SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) &&
+ SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) {
+
+ printk(KERN_ERR "%s SearchMap failed\n", __func__);
return -EINVAL;
}
- do
- {
+ do {
state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
- state->m_Regs[EP3] &= ~0x04; // switch RFAGC to high speed mode
-
- // m_EP4 default for XToutOn, CAL_Mode (0)
- state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax )? state->m_IFLevelDigital : state->m_IFLevelAnalog );
- //state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
- if( Standard <= HF_AnalogMax ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
- else if( Standard <= HF_ATSC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
- else if( Standard <= HF_DVBC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
- else state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
+ state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */
+
+ /* m_EP4 default for XToutOn, CAL_Mode (0) */
+ state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);
+ /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */
+ if (Standard <= HF_AnalogMax)
+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
+ else if (Standard <= HF_ATSC)
+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
+ else if (Standard <= HF_DVBC)
+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
+ else
+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
- if( (Standard == HF_FM_Radio) && state->m_bFMInput ) state->m_Regs[EP4] |= 80;
+ if ((Standard == HF_FM_Radio) && state->m_bFMInput)
+ state->m_Regs[EP4] |= 80;
state->m_Regs[MPD] &= ~0x80;
- if( Standard > HF_AnalogMax ) state->m_Regs[MPD] |= 0x80; // Add IF_notch for digital
+ if (Standard > HF_AnalogMax)
+ state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */
state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
- // Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM )
- if( Standard == HF_FM_Radio ) state->m_Regs[EB23] |= 0x06; // ForceLP_Fc2_En = 1, LPFc[2] = 1
- else state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LPFc[2] = 0
+ /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */
+ if (Standard == HF_FM_Radio)
+ state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
+ else
+ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */
- CHK_ERROR(UpdateRegs(state,EB22,EB23));
+ CHK_ERROR(UpdateRegs(state, EB22, EB23));
- state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; // Dis_Power_level = 1, Filter
+ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */
state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
- (state->m_bMaster ? 0x04 : 0x00); // CALVCO_FortLOn = MS
- // AGC1_always_master = 0
- // AGC_firstn = 0
- CHK_ERROR(UpdateReg(state,EB1));
-
- if( state->m_bMaster )
- {
- CHK_ERROR(CalcMainPLL(state,Frequency + IntermediateFrequency));
- CHK_ERROR(UpdateRegs(state,TM,EP5));
- state->m_Regs[EB4] |= 0x20; // LO_forceSrce = 1
- CHK_ERROR(UpdateReg(state,EB4));
+ (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */
+ /* AGC1_always_master = 0 */
+ /* AGC_firstn = 0 */
+ CHK_ERROR(UpdateReg(state, EB1));
+
+ if (state->m_bMaster) {
+ CHK_ERROR(CalcMainPLL(state, Frequency + IntermediateFrequency));
+ CHK_ERROR(UpdateRegs(state, TM, EP5));
+ state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */
+ CHK_ERROR(UpdateReg(state, EB4));
msleep(1);
- state->m_Regs[EB4] &= ~0x20; // LO_forceSrce = 0
- CHK_ERROR(UpdateReg(state,EB4));
- }
- else
- {
+ state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
+ CHK_ERROR(UpdateReg(state, EB4));
+ } else {
u8 PostDiv;
u8 Div;
- CHK_ERROR(CalcCalPLL(state,Frequency + IntermediateFrequency));
+ CHK_ERROR(CalcCalPLL(state, Frequency + IntermediateFrequency));
- SearchMap3(m_Cal_PLL_Map,Frequency + IntermediateFrequency,&PostDiv,&Div);
+ SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div);
state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
- CHK_ERROR(UpdateReg(state,MPD));
- CHK_ERROR(UpdateRegs(state,TM,EP5));
+ CHK_ERROR(UpdateReg(state, MPD));
+ CHK_ERROR(UpdateRegs(state, TM, EP5));
- state->m_Regs[EB7] |= 0x20; // CAL_forceSrce = 1
- CHK_ERROR(UpdateReg(state,EB7));
+ state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */
+ CHK_ERROR(UpdateReg(state, EB7));
msleep(1);
- state->m_Regs[EB7] &= ~0x20; // CAL_forceSrce = 0
- CHK_ERROR(UpdateReg(state,EB7));
+ state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */
+ CHK_ERROR(UpdateReg(state, EB7));
}
msleep(20);
- if( Standard != HF_FM_Radio )
- {
- state->m_Regs[EP3] |= 0x04; // RFAGC to normal mode
- }
- CHK_ERROR(UpdateReg(state,EP3));
+ if (Standard != HF_FM_Radio)
+ state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */
+ CHK_ERROR(UpdateReg(state, EP3));
- } while(0);
+ } while (0);
return status;
}
-static int sleep(struct dvb_frontend* fe)
+static int sleep(struct dvb_frontend *fe)
{
struct tda_state *state = fe->tuner_priv;
@@ -938,13 +916,12 @@ static int sleep(struct dvb_frontend* fe)
return 0;
}
-static int init(struct dvb_frontend* fe)
+static int init(struct dvb_frontend *fe)
{
- //struct tda_state *state = fe->tuner_priv;
return 0;
}
-static int release(struct dvb_frontend* fe)
+static int release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
@@ -978,22 +955,22 @@ static int set_params(struct dvb_frontend *fe,
} else
return -EINVAL;
do {
- CHK_ERROR(RFTrackingFiltersCorrection(state,params->frequency));
- CHK_ERROR(ChannelConfiguration(state,params->frequency,Standard));
+ CHK_ERROR(RFTrackingFiltersCorrection(state, params->frequency));
+ CHK_ERROR(ChannelConfiguration(state, params->frequency, Standard));
- msleep(state->m_SettlingTime); // Allow AGC's to settle down
- } while(0);
+ msleep(state->m_SettlingTime); /* Allow AGC's to settle down */
+ } while (0);
return status;
}
#if 0
-static int GetSignalStrength(s32 * pSignalStrength,u32 RFAgc,u32 IFAgc)
+static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc)
{
- if( IFAgc < 500 ) {
- // Scale this from 0 to 50000
+ if (IFAgc < 500) {
+ /* Scale this from 0 to 50000 */
*pSignalStrength = IFAgc * 100;
} else {
- // Scale range 500-1500 to 50000-80000
+ /* Scale range 500-1500 to 50000-80000 */
*pSignalStrength = 50000 + (IFAgc - 500) * 30;
}
@@ -1011,8 +988,8 @@ static int get_frequency(struct dvb_frontend *fe, u32 *frequency)
static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
- //struct tda_state *state = fe->tuner_priv;
- //*bandwidth = priv->bandwidth;
+ /* struct tda_state *state = fe->tuner_priv; */
+ /* *bandwidth = priv->bandwidth; */
return 0;
}
@@ -1050,14 +1027,8 @@ struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
return fe;
}
-
EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
+
MODULE_DESCRIPTION("TDA18271C2 driver");
MODULE_AUTHOR("DD");
MODULE_LICENSE("GPL");
-
-/*
- * Local variables:
- * c-basic-offset: 8
- * End:
- */
diff --git a/drivers/media/dvb/frontends/tda18271c2dd_maps.h b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
index 21fa4e1..b87661b 100644
--- a/drivers/media/dvb/frontends/tda18271c2dd_maps.h
+++ b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
@@ -1,810 +1,814 @@
enum HF_S {
- HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
+ HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ,
HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ,
HF_DVBC_8MHZ, HF_DVBC
};
-struct SStandardParam m_StandardTable[] =
-{
- { 0, 0, 0x00, 0x00 }, // HF_None
- { 6000000, 7000000, 0x1D, 0x2C }, // HF_B,
- { 6900000, 8000000, 0x1E, 0x2C }, // HF_DK,
- { 7100000, 8000000, 0x1E, 0x2C }, // HF_G,
- { 7250000, 8000000, 0x1E, 0x2C }, // HF_I,
- { 6900000, 8000000, 0x1E, 0x2C }, // HF_L,
- { 1250000, 8000000, 0x1E, 0x2C }, // HF_L1,
- { 5400000, 6000000, 0x1C, 0x2C }, // HF_MN,
- { 1250000, 500000, 0x18, 0x2C }, // HF_FM_Radio,
- { 0, 0, 0x00, 0x00 }, // HF_AnalogMax (Unused)
- { 3300000, 6000000, 0x1C, 0x58 }, // HF_DVBT_6MHZ
- { 3500000, 7000000, 0x1C, 0x37 }, // HF_DVBT_7MHZ
- { 4000000, 8000000, 0x1D, 0x37 }, // HF_DVBT_8MHZ
- { 0, 0, 0x00, 0x00 }, // HF_DVBT (Unused)
- { 5000000, 6000000, 0x1C, 0x37 }, // HF_ATSC (center = 3.25 MHz)
- { 4000000, 6000000, 0x1D, 0x58 }, // HF_DVBC_6MHZ (Chicago)
- { 4500000, 7000000, 0x1E, 0x37 }, // HF_DVBC_7MHZ (not documented by NXP)
- { 5000000, 8000000, 0x1F, 0x37 }, // HF_DVBC_8MHZ
- { 0, 0, 0x00, 0x00 }, // HF_DVBC (Unused)
+struct SStandardParam m_StandardTable[] = {
+ { 0, 0, 0x00, 0x00 }, /* HF_None */
+ { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */
+ { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */
+ { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */
+ { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */
+ { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */
+ { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */
+ { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */
+ { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */
+ { 0, 0, 0x00, 0x00 }, /* HF_AnalogMax (Unused) */
+ { 3300000, 6000000, 0x1C, 0x58 }, /* HF_DVBT_6MHZ */
+ { 3500000, 7000000, 0x1C, 0x37 }, /* HF_DVBT_7MHZ */
+ { 4000000, 8000000, 0x1D, 0x37 }, /* HF_DVBT_8MHZ */
+ { 0, 0, 0x00, 0x00 }, /* HF_DVBT (Unused) */
+ { 5000000, 6000000, 0x1C, 0x37 }, /* HF_ATSC (center = 3.25 MHz) */
+ { 4000000, 6000000, 0x1D, 0x58 }, /* HF_DVBC_6MHZ (Chicago) */
+ { 4500000, 7000000, 0x1E, 0x37 }, /* HF_DVBC_7MHZ (not documented by NXP) */
+ { 5000000, 8000000, 0x1F, 0x37 }, /* HF_DVBC_8MHZ */
+ { 0, 0, 0x00, 0x00 }, /* HF_DVBC (Unused) */
};
struct SMap m_BP_Filter_Map[] = {
- { 62000000, 0x00 },
- { 84000000, 0x01 },
- { 100000000, 0x02 },
- { 140000000, 0x03 },
- { 170000000, 0x04 },
- { 180000000, 0x05 },
- { 865000000, 0x06 },
- { 0, 0x00 }, // Table End
+ { 62000000, 0x00 },
+ { 84000000, 0x01 },
+ { 100000000, 0x02 },
+ { 140000000, 0x03 },
+ { 170000000, 0x04 },
+ { 180000000, 0x05 },
+ { 865000000, 0x06 },
+ { 0, 0x00 }, /* Table End */
};
static struct SMapI m_RF_Cal_Map[] = {
- { 41000000, 0x0F },
- { 43000000, 0x1C },
- { 45000000, 0x2F },
- { 46000000, 0x39 },
- { 47000000, 0x40 },
- { 47900000, 0x50 },
- { 49100000, 0x16 },
- { 50000000, 0x18 },
- { 51000000, 0x20 },
- { 53000000, 0x28 },
- { 55000000, 0x2B },
- { 56000000, 0x32 },
- { 57000000, 0x35 },
- { 58000000, 0x3E },
- { 59000000, 0x43 },
- { 60000000, 0x4E },
- { 61100000, 0x55 },
- { 63000000, 0x0F },
- { 64000000, 0x11 },
- { 65000000, 0x12 },
- { 66000000, 0x15 },
- { 67000000, 0x16 },
- { 68000000, 0x17 },
- { 70000000, 0x19 },
- { 71000000, 0x1C },
- { 72000000, 0x1D },
- { 73000000, 0x1F },
- { 74000000, 0x20 },
- { 75000000, 0x21 },
- { 76000000, 0x24 },
- { 77000000, 0x25 },
- { 78000000, 0x27 },
- { 80000000, 0x28 },
- { 81000000, 0x29 },
- { 82000000, 0x2D },
- { 83000000, 0x2E },
- { 84000000, 0x2F },
- { 85000000, 0x31 },
- { 86000000, 0x33 },
- { 87000000, 0x34 },
- { 88000000, 0x35 },
- { 89000000, 0x37 },
- { 90000000, 0x38 },
- { 91000000, 0x39 },
- { 93000000, 0x3C },
- { 94000000, 0x3E },
- { 95000000, 0x3F },
- { 96000000, 0x40 },
- { 97000000, 0x42 },
- { 99000000, 0x45 },
- { 100000000, 0x46 },
- { 102000000, 0x48 },
- { 103000000, 0x4A },
- { 105000000, 0x4D },
- { 106000000, 0x4E },
- { 107000000, 0x50 },
- { 108000000, 0x51 },
- { 110000000, 0x54 },
- { 111000000, 0x56 },
- { 112000000, 0x57 },
- { 113000000, 0x58 },
- { 114000000, 0x59 },
- { 115000000, 0x5C },
- { 116000000, 0x5D },
- { 117000000, 0x5F },
- { 119000000, 0x60 },
- { 120000000, 0x64 },
- { 121000000, 0x65 },
- { 122000000, 0x66 },
- { 123000000, 0x68 },
- { 124000000, 0x69 },
- { 125000000, 0x6C },
- { 126000000, 0x6D },
- { 127000000, 0x6E },
- { 128000000, 0x70 },
- { 129000000, 0x71 },
- { 130000000, 0x75 },
- { 131000000, 0x77 },
- { 132000000, 0x78 },
- { 133000000, 0x7B },
- { 134000000, 0x7E },
- { 135000000, 0x81 },
- { 136000000, 0x82 },
- { 137000000, 0x87 },
- { 138000000, 0x88 },
- { 139000000, 0x8D },
- { 140000000, 0x8E },
- { 141000000, 0x91 },
- { 142000000, 0x95 },
- { 143000000, 0x9A },
- { 144000000, 0x9D },
- { 145000000, 0xA1 },
- { 146000000, 0xA2 },
- { 147000000, 0xA4 },
- { 148000000, 0xA9 },
- { 149000000, 0xAE },
- { 150000000, 0xB0 },
- { 151000000, 0xB1 },
- { 152000000, 0xB7 },
- { 152600000, 0xBD },
- { 154000000, 0x20 },
- { 155000000, 0x22 },
- { 156000000, 0x24 },
- { 157000000, 0x25 },
- { 158000000, 0x27 },
- { 159000000, 0x29 },
- { 160000000, 0x2C },
- { 161000000, 0x2D },
- { 163000000, 0x2E },
- { 164000000, 0x2F },
- { 164700000, 0x30 },
- { 166000000, 0x11 },
- { 167000000, 0x12 },
- { 168000000, 0x13 },
- { 169000000, 0x14 },
- { 170000000, 0x15 },
- { 172000000, 0x16 },
- { 173000000, 0x17 },
- { 174000000, 0x18 },
- { 175000000, 0x1A },
- { 176000000, 0x1B },
- { 178000000, 0x1D },
- { 179000000, 0x1E },
- { 180000000, 0x1F },
- { 181000000, 0x20 },
- { 182000000, 0x21 },
- { 183000000, 0x22 },
- { 184000000, 0x24 },
- { 185000000, 0x25 },
- { 186000000, 0x26 },
- { 187000000, 0x27 },
- { 188000000, 0x29 },
- { 189000000, 0x2A },
- { 190000000, 0x2C },
- { 191000000, 0x2D },
- { 192000000, 0x2E },
- { 193000000, 0x2F },
- { 194000000, 0x30 },
- { 195000000, 0x33 },
- { 196000000, 0x35 },
- { 198000000, 0x36 },
- { 200000000, 0x38 },
- { 201000000, 0x3C },
- { 202000000, 0x3D },
- { 203500000, 0x3E },
- { 206000000, 0x0E },
- { 208000000, 0x0F },
- { 212000000, 0x10 },
- { 216000000, 0x11 },
- { 217000000, 0x12 },
- { 218000000, 0x13 },
- { 220000000, 0x14 },
- { 222000000, 0x15 },
- { 225000000, 0x16 },
- { 228000000, 0x17 },
- { 231000000, 0x18 },
- { 234000000, 0x19 },
- { 235000000, 0x1A },
- { 236000000, 0x1B },
- { 237000000, 0x1C },
- { 240000000, 0x1D },
- { 242000000, 0x1E },
- { 244000000, 0x1F },
- { 247000000, 0x20 },
- { 249000000, 0x21 },
- { 252000000, 0x22 },
- { 253000000, 0x23 },
- { 254000000, 0x24 },
- { 256000000, 0x25 },
- { 259000000, 0x26 },
- { 262000000, 0x27 },
- { 264000000, 0x28 },
- { 267000000, 0x29 },
- { 269000000, 0x2A },
- { 271000000, 0x2B },
- { 273000000, 0x2C },
- { 275000000, 0x2D },
- { 277000000, 0x2E },
- { 279000000, 0x2F },
- { 282000000, 0x30 },
- { 284000000, 0x31 },
- { 286000000, 0x32 },
- { 287000000, 0x33 },
- { 290000000, 0x34 },
- { 293000000, 0x35 },
- { 295000000, 0x36 },
- { 297000000, 0x37 },
- { 300000000, 0x38 },
- { 303000000, 0x39 },
- { 305000000, 0x3A },
- { 306000000, 0x3B },
- { 307000000, 0x3C },
- { 310000000, 0x3D },
- { 312000000, 0x3E },
- { 315000000, 0x3F },
- { 318000000, 0x40 },
- { 320000000, 0x41 },
- { 323000000, 0x42 },
- { 324000000, 0x43 },
- { 325000000, 0x44 },
- { 327000000, 0x45 },
- { 331000000, 0x46 },
- { 334000000, 0x47 },
- { 337000000, 0x48 },
- { 339000000, 0x49 },
- { 340000000, 0x4A },
- { 341000000, 0x4B },
- { 343000000, 0x4C },
- { 345000000, 0x4D },
- { 349000000, 0x4E },
- { 352000000, 0x4F },
- { 353000000, 0x50 },
- { 355000000, 0x51 },
- { 357000000, 0x52 },
- { 359000000, 0x53 },
- { 361000000, 0x54 },
- { 362000000, 0x55 },
- { 364000000, 0x56 },
- { 368000000, 0x57 },
- { 370000000, 0x58 },
- { 372000000, 0x59 },
- { 375000000, 0x5A },
- { 376000000, 0x5B },
- { 377000000, 0x5C },
- { 379000000, 0x5D },
- { 382000000, 0x5E },
- { 384000000, 0x5F },
- { 385000000, 0x60 },
- { 386000000, 0x61 },
- { 388000000, 0x62 },
- { 390000000, 0x63 },
- { 393000000, 0x64 },
- { 394000000, 0x65 },
- { 396000000, 0x66 },
- { 397000000, 0x67 },
- { 398000000, 0x68 },
- { 400000000, 0x69 },
- { 402000000, 0x6A },
- { 403000000, 0x6B },
- { 407000000, 0x6C },
- { 408000000, 0x6D },
- { 409000000, 0x6E },
- { 410000000, 0x6F },
- { 411000000, 0x70 },
- { 412000000, 0x71 },
- { 413000000, 0x72 },
- { 414000000, 0x73 },
- { 417000000, 0x74 },
- { 418000000, 0x75 },
- { 420000000, 0x76 },
- { 422000000, 0x77 },
- { 423000000, 0x78 },
- { 424000000, 0x79 },
- { 427000000, 0x7A },
- { 428000000, 0x7B },
- { 429000000, 0x7D },
- { 432000000, 0x7F },
- { 434000000, 0x80 },
- { 435000000, 0x81 },
- { 436000000, 0x83 },
- { 437000000, 0x84 },
- { 438000000, 0x85 },
- { 439000000, 0x86 },
- { 440000000, 0x87 },
- { 441000000, 0x88 },
- { 442000000, 0x89 },
- { 445000000, 0x8A },
- { 446000000, 0x8B },
- { 447000000, 0x8C },
- { 448000000, 0x8E },
- { 449000000, 0x8F },
- { 450000000, 0x90 },
- { 452000000, 0x91 },
- { 453000000, 0x93 },
- { 454000000, 0x94 },
- { 456000000, 0x96 },
- { 457800000, 0x98 },
- { 461000000, 0x11 },
- { 468000000, 0x12 },
- { 472000000, 0x13 },
- { 473000000, 0x14 },
- { 474000000, 0x15 },
- { 481000000, 0x16 },
- { 486000000, 0x17 },
- { 491000000, 0x18 },
- { 498000000, 0x19 },
- { 499000000, 0x1A },
- { 501000000, 0x1B },
- { 506000000, 0x1C },
- { 511000000, 0x1D },
- { 516000000, 0x1E },
- { 520000000, 0x1F },
- { 521000000, 0x20 },
- { 525000000, 0x21 },
- { 529000000, 0x22 },
- { 533000000, 0x23 },
- { 539000000, 0x24 },
- { 541000000, 0x25 },
- { 547000000, 0x26 },
- { 549000000, 0x27 },
- { 551000000, 0x28 },
- { 556000000, 0x29 },
- { 561000000, 0x2A },
- { 563000000, 0x2B },
- { 565000000, 0x2C },
- { 569000000, 0x2D },
- { 571000000, 0x2E },
- { 577000000, 0x2F },
- { 580000000, 0x30 },
- { 582000000, 0x31 },
- { 584000000, 0x32 },
- { 588000000, 0x33 },
- { 591000000, 0x34 },
- { 596000000, 0x35 },
- { 598000000, 0x36 },
- { 603000000, 0x37 },
- { 604000000, 0x38 },
- { 606000000, 0x39 },
- { 612000000, 0x3A },
- { 615000000, 0x3B },
- { 617000000, 0x3C },
- { 621000000, 0x3D },
- { 622000000, 0x3E },
- { 625000000, 0x3F },
- { 632000000, 0x40 },
- { 633000000, 0x41 },
- { 634000000, 0x42 },
- { 642000000, 0x43 },
- { 643000000, 0x44 },
- { 647000000, 0x45 },
- { 650000000, 0x46 },
- { 652000000, 0x47 },
- { 657000000, 0x48 },
- { 661000000, 0x49 },
- { 662000000, 0x4A },
- { 665000000, 0x4B },
- { 667000000, 0x4C },
- { 670000000, 0x4D },
- { 673000000, 0x4E },
- { 676000000, 0x4F },
- { 677000000, 0x50 },
- { 681000000, 0x51 },
- { 683000000, 0x52 },
- { 686000000, 0x53 },
- { 688000000, 0x54 },
- { 689000000, 0x55 },
- { 691000000, 0x56 },
- { 695000000, 0x57 },
- { 698000000, 0x58 },
- { 703000000, 0x59 },
- { 704000000, 0x5A },
- { 705000000, 0x5B },
- { 707000000, 0x5C },
- { 710000000, 0x5D },
- { 712000000, 0x5E },
- { 717000000, 0x5F },
- { 718000000, 0x60 },
- { 721000000, 0x61 },
- { 722000000, 0x62 },
- { 723000000, 0x63 },
- { 725000000, 0x64 },
- { 727000000, 0x65 },
- { 730000000, 0x66 },
- { 732000000, 0x67 },
- { 735000000, 0x68 },
- { 740000000, 0x69 },
- { 741000000, 0x6A },
- { 742000000, 0x6B },
- { 743000000, 0x6C },
- { 745000000, 0x6D },
- { 747000000, 0x6E },
- { 748000000, 0x6F },
- { 750000000, 0x70 },
- { 752000000, 0x71 },
- { 754000000, 0x72 },
- { 757000000, 0x73 },
- { 758000000, 0x74 },
- { 760000000, 0x75 },
- { 763000000, 0x76 },
- { 764000000, 0x77 },
- { 766000000, 0x78 },
- { 767000000, 0x79 },
- { 768000000, 0x7A },
- { 773000000, 0x7B },
- { 774000000, 0x7C },
- { 776000000, 0x7D },
- { 777000000, 0x7E },
- { 778000000, 0x7F },
- { 779000000, 0x80 },
- { 781000000, 0x81 },
- { 783000000, 0x82 },
- { 784000000, 0x83 },
- { 785000000, 0x84 },
- { 786000000, 0x85 },
- { 793000000, 0x86 },
- { 794000000, 0x87 },
- { 795000000, 0x88 },
- { 797000000, 0x89 },
- { 799000000, 0x8A },
- { 801000000, 0x8B },
- { 802000000, 0x8C },
- { 803000000, 0x8D },
- { 804000000, 0x8E },
- { 810000000, 0x90 },
- { 811000000, 0x91 },
- { 812000000, 0x92 },
- { 814000000, 0x93 },
- { 816000000, 0x94 },
- { 817000000, 0x96 },
- { 818000000, 0x97 },
- { 820000000, 0x98 },
- { 821000000, 0x99 },
- { 822000000, 0x9A },
- { 828000000, 0x9B },
- { 829000000, 0x9D },
- { 830000000, 0x9F },
- { 831000000, 0xA0 },
- { 833000000, 0xA1 },
- { 835000000, 0xA2 },
- { 836000000, 0xA3 },
- { 837000000, 0xA4 },
- { 838000000, 0xA6 },
- { 840000000, 0xA8 },
- { 842000000, 0xA9 },
- { 845000000, 0xAA },
- { 846000000, 0xAB },
- { 847000000, 0xAD },
- { 848000000, 0xAE },
- { 852000000, 0xAF },
- { 853000000, 0xB0 },
- { 858000000, 0xB1 },
- { 860000000, 0xB2 },
- { 861000000, 0xB3 },
- { 862000000, 0xB4 },
- { 863000000, 0xB6 },
- { 864000000, 0xB8 },
- { 865000000, 0xB9 },
- { 0, 0x00 }, // Table End
+ { 41000000, 0x0F },
+ { 43000000, 0x1C },
+ { 45000000, 0x2F },
+ { 46000000, 0x39 },
+ { 47000000, 0x40 },
+ { 47900000, 0x50 },
+ { 49100000, 0x16 },
+ { 50000000, 0x18 },
+ { 51000000, 0x20 },
+ { 53000000, 0x28 },
+ { 55000000, 0x2B },
+ { 56000000, 0x32 },
+ { 57000000, 0x35 },
+ { 58000000, 0x3E },
+ { 59000000, 0x43 },
+ { 60000000, 0x4E },
+ { 61100000, 0x55 },
+ { 63000000, 0x0F },
+ { 64000000, 0x11 },
+ { 65000000, 0x12 },
+ { 66000000, 0x15 },
+ { 67000000, 0x16 },
+ { 68000000, 0x17 },
+ { 70000000, 0x19 },
+ { 71000000, 0x1C },
+ { 72000000, 0x1D },
+ { 73000000, 0x1F },
+ { 74000000, 0x20 },
+ { 75000000, 0x21 },
+ { 76000000, 0x24 },
+ { 77000000, 0x25 },
+ { 78000000, 0x27 },
+ { 80000000, 0x28 },
+ { 81000000, 0x29 },
+ { 82000000, 0x2D },
+ { 83000000, 0x2E },
+ { 84000000, 0x2F },
+ { 85000000, 0x31 },
+ { 86000000, 0x33 },
+ { 87000000, 0x34 },
+ { 88000000, 0x35 },
+ { 89000000, 0x37 },
+ { 90000000, 0x38 },
+ { 91000000, 0x39 },
+ { 93000000, 0x3C },
+ { 94000000, 0x3E },
+ { 95000000, 0x3F },
+ { 96000000, 0x40 },
+ { 97000000, 0x42 },
+ { 99000000, 0x45 },
+ { 100000000, 0x46 },
+ { 102000000, 0x48 },
+ { 103000000, 0x4A },
+ { 105000000, 0x4D },
+ { 106000000, 0x4E },
+ { 107000000, 0x50 },
+ { 108000000, 0x51 },
+ { 110000000, 0x54 },
+ { 111000000, 0x56 },
+ { 112000000, 0x57 },
+ { 113000000, 0x58 },
+ { 114000000, 0x59 },
+ { 115000000, 0x5C },
+ { 116000000, 0x5D },
+ { 117000000, 0x5F },
+ { 119000000, 0x60 },
+ { 120000000, 0x64 },
+ { 121000000, 0x65 },
+ { 122000000, 0x66 },
+ { 123000000, 0x68 },
+ { 124000000, 0x69 },
+ { 125000000, 0x6C },
+ { 126000000, 0x6D },
+ { 127000000, 0x6E },
+ { 128000000, 0x70 },
+ { 129000000, 0x71 },
+ { 130000000, 0x75 },
+ { 131000000, 0x77 },
+ { 132000000, 0x78 },
+ { 133000000, 0x7B },
+ { 134000000, 0x7E },
+ { 135000000, 0x81 },
+ { 136000000, 0x82 },
+ { 137000000, 0x87 },
+ { 138000000, 0x88 },
+ { 139000000, 0x8D },
+ { 140000000, 0x8E },
+ { 141000000, 0x91 },
+ { 142000000, 0x95 },
+ { 143000000, 0x9A },
+ { 144000000, 0x9D },
+ { 145000000, 0xA1 },
+ { 146000000, 0xA2 },
+ { 147000000, 0xA4 },
+ { 148000000, 0xA9 },
+ { 149000000, 0xAE },
+ { 150000000, 0xB0 },
+ { 151000000, 0xB1 },
+ { 152000000, 0xB7 },
+ { 152600000, 0xBD },
+ { 154000000, 0x20 },
+ { 155000000, 0x22 },
+ { 156000000, 0x24 },
+ { 157000000, 0x25 },
+ { 158000000, 0x27 },
+ { 159000000, 0x29 },
+ { 160000000, 0x2C },
+ { 161000000, 0x2D },
+ { 163000000, 0x2E },
+ { 164000000, 0x2F },
+ { 164700000, 0x30 },
+ { 166000000, 0x11 },
+ { 167000000, 0x12 },
+ { 168000000, 0x13 },
+ { 169000000, 0x14 },
+ { 170000000, 0x15 },
+ { 172000000, 0x16 },
+ { 173000000, 0x17 },
+ { 174000000, 0x18 },
+ { 175000000, 0x1A },
+ { 176000000, 0x1B },
+ { 178000000, 0x1D },
+ { 179000000, 0x1E },
+ { 180000000, 0x1F },
+ { 181000000, 0x20 },
+ { 182000000, 0x21 },
+ { 183000000, 0x22 },
+ { 184000000, 0x24 },
+ { 185000000, 0x25 },
+ { 186000000, 0x26 },
+ { 187000000, 0x27 },
+ { 188000000, 0x29 },
+ { 189000000, 0x2A },
+ { 190000000, 0x2C },
+ { 191000000, 0x2D },
+ { 192000000, 0x2E },
+ { 193000000, 0x2F },
+ { 194000000, 0x30 },
+ { 195000000, 0x33 },
+ { 196000000, 0x35 },
+ { 198000000, 0x36 },
+ { 200000000, 0x38 },
+ { 201000000, 0x3C },
+ { 202000000, 0x3D },
+ { 203500000, 0x3E },
+ { 206000000, 0x0E },
+ { 208000000, 0x0F },
+ { 212000000, 0x10 },
+ { 216000000, 0x11 },
+ { 217000000, 0x12 },
+ { 218000000, 0x13 },
+ { 220000000, 0x14 },
+ { 222000000, 0x15 },
+ { 225000000, 0x16 },
+ { 228000000, 0x17 },
+ { 231000000, 0x18 },
+ { 234000000, 0x19 },
+ { 235000000, 0x1A },
+ { 236000000, 0x1B },
+ { 237000000, 0x1C },
+ { 240000000, 0x1D },
+ { 242000000, 0x1E },
+ { 244000000, 0x1F },
+ { 247000000, 0x20 },
+ { 249000000, 0x21 },
+ { 252000000, 0x22 },
+ { 253000000, 0x23 },
+ { 254000000, 0x24 },
+ { 256000000, 0x25 },
+ { 259000000, 0x26 },
+ { 262000000, 0x27 },
+ { 264000000, 0x28 },
+ { 267000000, 0x29 },
+ { 269000000, 0x2A },
+ { 271000000, 0x2B },
+ { 273000000, 0x2C },
+ { 275000000, 0x2D },
+ { 277000000, 0x2E },
+ { 279000000, 0x2F },
+ { 282000000, 0x30 },
+ { 284000000, 0x31 },
+ { 286000000, 0x32 },
+ { 287000000, 0x33 },
+ { 290000000, 0x34 },
+ { 293000000, 0x35 },
+ { 295000000, 0x36 },
+ { 297000000, 0x37 },
+ { 300000000, 0x38 },
+ { 303000000, 0x39 },
+ { 305000000, 0x3A },
+ { 306000000, 0x3B },
+ { 307000000, 0x3C },
+ { 310000000, 0x3D },
+ { 312000000, 0x3E },
+ { 315000000, 0x3F },
+ { 318000000, 0x40 },
+ { 320000000, 0x41 },
+ { 323000000, 0x42 },
+ { 324000000, 0x43 },
+ { 325000000, 0x44 },
+ { 327000000, 0x45 },
+ { 331000000, 0x46 },
+ { 334000000, 0x47 },
+ { 337000000, 0x48 },
+ { 339000000, 0x49 },
+ { 340000000, 0x4A },
+ { 341000000, 0x4B },
+ { 343000000, 0x4C },
+ { 345000000, 0x4D },
+ { 349000000, 0x4E },
+ { 352000000, 0x4F },
+ { 353000000, 0x50 },
+ { 355000000, 0x51 },
+ { 357000000, 0x52 },
+ { 359000000, 0x53 },
+ { 361000000, 0x54 },
+ { 362000000, 0x55 },
+ { 364000000, 0x56 },
+ { 368000000, 0x57 },
+ { 370000000, 0x58 },
+ { 372000000, 0x59 },
+ { 375000000, 0x5A },
+ { 376000000, 0x5B },
+ { 377000000, 0x5C },
+ { 379000000, 0x5D },
+ { 382000000, 0x5E },
+ { 384000000, 0x5F },
+ { 385000000, 0x60 },
+ { 386000000, 0x61 },
+ { 388000000, 0x62 },
+ { 390000000, 0x63 },
+ { 393000000, 0x64 },
+ { 394000000, 0x65 },
+ { 396000000, 0x66 },
+ { 397000000, 0x67 },
+ { 398000000, 0x68 },
+ { 400000000, 0x69 },
+ { 402000000, 0x6A },
+ { 403000000, 0x6B },
+ { 407000000, 0x6C },
+ { 408000000, 0x6D },
+ { 409000000, 0x6E },
+ { 410000000, 0x6F },
+ { 411000000, 0x70 },
+ { 412000000, 0x71 },
+ { 413000000, 0x72 },
+ { 414000000, 0x73 },
+ { 417000000, 0x74 },
+ { 418000000, 0x75 },
+ { 420000000, 0x76 },
+ { 422000000, 0x77 },
+ { 423000000, 0x78 },
+ { 424000000, 0x79 },
+ { 427000000, 0x7A },
+ { 428000000, 0x7B },
+ { 429000000, 0x7D },
+ { 432000000, 0x7F },
+ { 434000000, 0x80 },
+ { 435000000, 0x81 },
+ { 436000000, 0x83 },
+ { 437000000, 0x84 },
+ { 438000000, 0x85 },
+ { 439000000, 0x86 },
+ { 440000000, 0x87 },
+ { 441000000, 0x88 },
+ { 442000000, 0x89 },
+ { 445000000, 0x8A },
+ { 446000000, 0x8B },
+ { 447000000, 0x8C },
+ { 448000000, 0x8E },
+ { 449000000, 0x8F },
+ { 450000000, 0x90 },
+ { 452000000, 0x91 },
+ { 453000000, 0x93 },
+ { 454000000, 0x94 },
+ { 456000000, 0x96 },
+ { 457800000, 0x98 },
+ { 461000000, 0x11 },
+ { 468000000, 0x12 },
+ { 472000000, 0x13 },
+ { 473000000, 0x14 },
+ { 474000000, 0x15 },
+ { 481000000, 0x16 },
+ { 486000000, 0x17 },
+ { 491000000, 0x18 },
+ { 498000000, 0x19 },
+ { 499000000, 0x1A },
+ { 501000000, 0x1B },
+ { 506000000, 0x1C },
+ { 511000000, 0x1D },
+ { 516000000, 0x1E },
+ { 520000000, 0x1F },
+ { 521000000, 0x20 },
+ { 525000000, 0x21 },
+ { 529000000, 0x22 },
+ { 533000000, 0x23 },
+ { 539000000, 0x24 },
+ { 541000000, 0x25 },
+ { 547000000, 0x26 },
+ { 549000000, 0x27 },
+ { 551000000, 0x28 },
+ { 556000000, 0x29 },
+ { 561000000, 0x2A },
+ { 563000000, 0x2B },
+ { 565000000, 0x2C },
+ { 569000000, 0x2D },
+ { 571000000, 0x2E },
+ { 577000000, 0x2F },
+ { 580000000, 0x30 },
+ { 582000000, 0x31 },
+ { 584000000, 0x32 },
+ { 588000000, 0x33 },
+ { 591000000, 0x34 },
+ { 596000000, 0x35 },
+ { 598000000, 0x36 },
+ { 603000000, 0x37 },
+ { 604000000, 0x38 },
+ { 606000000, 0x39 },
+ { 612000000, 0x3A },
+ { 615000000, 0x3B },
+ { 617000000, 0x3C },
+ { 621000000, 0x3D },
+ { 622000000, 0x3E },
+ { 625000000, 0x3F },
+ { 632000000, 0x40 },
+ { 633000000, 0x41 },
+ { 634000000, 0x42 },
+ { 642000000, 0x43 },
+ { 643000000, 0x44 },
+ { 647000000, 0x45 },
+ { 650000000, 0x46 },
+ { 652000000, 0x47 },
+ { 657000000, 0x48 },
+ { 661000000, 0x49 },
+ { 662000000, 0x4A },
+ { 665000000, 0x4B },
+ { 667000000, 0x4C },
+ { 670000000, 0x4D },
+ { 673000000, 0x4E },
+ { 676000000, 0x4F },
+ { 677000000, 0x50 },
+ { 681000000, 0x51 },
+ { 683000000, 0x52 },
+ { 686000000, 0x53 },
+ { 688000000, 0x54 },
+ { 689000000, 0x55 },
+ { 691000000, 0x56 },
+ { 695000000, 0x57 },
+ { 698000000, 0x58 },
+ { 703000000, 0x59 },
+ { 704000000, 0x5A },
+ { 705000000, 0x5B },
+ { 707000000, 0x5C },
+ { 710000000, 0x5D },
+ { 712000000, 0x5E },
+ { 717000000, 0x5F },
+ { 718000000, 0x60 },
+ { 721000000, 0x61 },
+ { 722000000, 0x62 },
+ { 723000000, 0x63 },
+ { 725000000, 0x64 },
+ { 727000000, 0x65 },
+ { 730000000, 0x66 },
+ { 732000000, 0x67 },
+ { 735000000, 0x68 },
+ { 740000000, 0x69 },
+ { 741000000, 0x6A },
+ { 742000000, 0x6B },
+ { 743000000, 0x6C },
+ { 745000000, 0x6D },
+ { 747000000, 0x6E },
+ { 748000000, 0x6F },
+ { 750000000, 0x70 },
+ { 752000000, 0x71 },
+ { 754000000, 0x72 },
+ { 757000000, 0x73 },
+ { 758000000, 0x74 },
+ { 760000000, 0x75 },
+ { 763000000, 0x76 },
+ { 764000000, 0x77 },
+ { 766000000, 0x78 },
+ { 767000000, 0x79 },
+ { 768000000, 0x7A },
+ { 773000000, 0x7B },
+ { 774000000, 0x7C },
+ { 776000000, 0x7D },
+ { 777000000, 0x7E },
+ { 778000000, 0x7F },
+ { 779000000, 0x80 },
+ { 781000000, 0x81 },
+ { 783000000, 0x82 },
+ { 784000000, 0x83 },
+ { 785000000, 0x84 },
+ { 786000000, 0x85 },
+ { 793000000, 0x86 },
+ { 794000000, 0x87 },
+ { 795000000, 0x88 },
+ { 797000000, 0x89 },
+ { 799000000, 0x8A },
+ { 801000000, 0x8B },
+ { 802000000, 0x8C },
+ { 803000000, 0x8D },
+ { 804000000, 0x8E },
+ { 810000000, 0x90 },
+ { 811000000, 0x91 },
+ { 812000000, 0x92 },
+ { 814000000, 0x93 },
+ { 816000000, 0x94 },
+ { 817000000, 0x96 },
+ { 818000000, 0x97 },
+ { 820000000, 0x98 },
+ { 821000000, 0x99 },
+ { 822000000, 0x9A },
+ { 828000000, 0x9B },
+ { 829000000, 0x9D },
+ { 830000000, 0x9F },
+ { 831000000, 0xA0 },
+ { 833000000, 0xA1 },
+ { 835000000, 0xA2 },
+ { 836000000, 0xA3 },
+ { 837000000, 0xA4 },
+ { 838000000, 0xA6 },
+ { 840000000, 0xA8 },
+ { 842000000, 0xA9 },
+ { 845000000, 0xAA },
+ { 846000000, 0xAB },
+ { 847000000, 0xAD },
+ { 848000000, 0xAE },
+ { 852000000, 0xAF },
+ { 853000000, 0xB0 },
+ { 858000000, 0xB1 },
+ { 860000000, 0xB2 },
+ { 861000000, 0xB3 },
+ { 862000000, 0xB4 },
+ { 863000000, 0xB6 },
+ { 864000000, 0xB8 },
+ { 865000000, 0xB9 },
+ { 0, 0x00 }, /* Table End */
};
static struct SMap2 m_KM_Map[] = {
- { 47900000, 3, 2 },
- { 61100000, 3, 1 },
- { 350000000, 3, 0 },
- { 720000000, 2, 1 },
- { 865000000, 3, 3 },
- { 0, 0x00 }, // Table End
+ { 47900000, 3, 2 },
+ { 61100000, 3, 1 },
+ { 350000000, 3, 0 },
+ { 720000000, 2, 1 },
+ { 865000000, 3, 3 },
+ { 0, 0x00 }, /* Table End */
};
static struct SMap2 m_Main_PLL_Map[] = {
- { 33125000, 0x57, 0xF0 },
- { 35500000, 0x56, 0xE0 },
- { 38188000, 0x55, 0xD0 },
- { 41375000, 0x54, 0xC0 },
- { 45125000, 0x53, 0xB0 },
- { 49688000, 0x52, 0xA0 },
- { 55188000, 0x51, 0x90 },
- { 62125000, 0x50, 0x80 },
- { 66250000, 0x47, 0x78 },
- { 71000000, 0x46, 0x70 },
- { 76375000, 0x45, 0x68 },
- { 82750000, 0x44, 0x60 },
- { 90250000, 0x43, 0x58 },
- { 99375000, 0x42, 0x50 },
- { 110375000, 0x41, 0x48 },
- { 124250000, 0x40, 0x40 },
- { 132500000, 0x37, 0x3C },
- { 142000000, 0x36, 0x38 },
- { 152750000, 0x35, 0x34 },
- { 165500000, 0x34, 0x30 },
- { 180500000, 0x33, 0x2C },
- { 198750000, 0x32, 0x28 },
- { 220750000, 0x31, 0x24 },
- { 248500000, 0x30, 0x20 },
- { 265000000, 0x27, 0x1E },
- { 284000000, 0x26, 0x1C },
- { 305500000, 0x25, 0x1A },
- { 331000000, 0x24, 0x18 },
- { 361000000, 0x23, 0x16 },
- { 397500000, 0x22, 0x14 },
- { 441500000, 0x21, 0x12 },
- { 497000000, 0x20, 0x10 },
- { 530000000, 0x17, 0x0F },
- { 568000000, 0x16, 0x0E },
- { 611000000, 0x15, 0x0D },
- { 662000000, 0x14, 0x0C },
- { 722000000, 0x13, 0x0B },
- { 795000000, 0x12, 0x0A },
- { 883000000, 0x11, 0x09 },
- { 994000000, 0x10, 0x08 },
- { 0, 0x00, 0x00 }, // Table End
+ { 33125000, 0x57, 0xF0 },
+ { 35500000, 0x56, 0xE0 },
+ { 38188000, 0x55, 0xD0 },
+ { 41375000, 0x54, 0xC0 },
+ { 45125000, 0x53, 0xB0 },
+ { 49688000, 0x52, 0xA0 },
+ { 55188000, 0x51, 0x90 },
+ { 62125000, 0x50, 0x80 },
+ { 66250000, 0x47, 0x78 },
+ { 71000000, 0x46, 0x70 },
+ { 76375000, 0x45, 0x68 },
+ { 82750000, 0x44, 0x60 },
+ { 90250000, 0x43, 0x58 },
+ { 99375000, 0x42, 0x50 },
+ { 110375000, 0x41, 0x48 },
+ { 124250000, 0x40, 0x40 },
+ { 132500000, 0x37, 0x3C },
+ { 142000000, 0x36, 0x38 },
+ { 152750000, 0x35, 0x34 },
+ { 165500000, 0x34, 0x30 },
+ { 180500000, 0x33, 0x2C },
+ { 198750000, 0x32, 0x28 },
+ { 220750000, 0x31, 0x24 },
+ { 248500000, 0x30, 0x20 },
+ { 265000000, 0x27, 0x1E },
+ { 284000000, 0x26, 0x1C },
+ { 305500000, 0x25, 0x1A },
+ { 331000000, 0x24, 0x18 },
+ { 361000000, 0x23, 0x16 },
+ { 397500000, 0x22, 0x14 },
+ { 441500000, 0x21, 0x12 },
+ { 497000000, 0x20, 0x10 },
+ { 530000000, 0x17, 0x0F },
+ { 568000000, 0x16, 0x0E },
+ { 611000000, 0x15, 0x0D },
+ { 662000000, 0x14, 0x0C },
+ { 722000000, 0x13, 0x0B },
+ { 795000000, 0x12, 0x0A },
+ { 883000000, 0x11, 0x09 },
+ { 994000000, 0x10, 0x08 },
+ { 0, 0x00, 0x00 }, /* Table End */
};
static struct SMap2 m_Cal_PLL_Map[] = {
- { 33813000, 0xDD, 0xD0 },
- { 36625000, 0xDC, 0xC0 },
- { 39938000, 0xDB, 0xB0 },
- { 43938000, 0xDA, 0xA0 },
- { 48813000, 0xD9, 0x90 },
- { 54938000, 0xD8, 0x80 },
- { 62813000, 0xD3, 0x70 },
- { 67625000, 0xCD, 0x68 },
- { 73250000, 0xCC, 0x60 },
- { 79875000, 0xCB, 0x58 },
- { 87875000, 0xCA, 0x50 },
- { 97625000, 0xC9, 0x48 },
- { 109875000, 0xC8, 0x40 },
- { 125625000, 0xC3, 0x38 },
- { 135250000, 0xBD, 0x34 },
- { 146500000, 0xBC, 0x30 },
- { 159750000, 0xBB, 0x2C },
- { 175750000, 0xBA, 0x28 },
- { 195250000, 0xB9, 0x24 },
- { 219750000, 0xB8, 0x20 },
- { 251250000, 0xB3, 0x1C },
- { 270500000, 0xAD, 0x1A },
- { 293000000, 0xAC, 0x18 },
- { 319500000, 0xAB, 0x16 },
- { 351500000, 0xAA, 0x14 },
- { 390500000, 0xA9, 0x12 },
- { 439500000, 0xA8, 0x10 },
- { 502500000, 0xA3, 0x0E },
- { 541000000, 0x9D, 0x0D },
- { 586000000, 0x9C, 0x0C },
- { 639000000, 0x9B, 0x0B },
- { 703000000, 0x9A, 0x0A },
- { 781000000, 0x99, 0x09 },
- { 879000000, 0x98, 0x08 },
- { 0, 0x00, 0x00 }, // Table End
+ { 33813000, 0xDD, 0xD0 },
+ { 36625000, 0xDC, 0xC0 },
+ { 39938000, 0xDB, 0xB0 },
+ { 43938000, 0xDA, 0xA0 },
+ { 48813000, 0xD9, 0x90 },
+ { 54938000, 0xD8, 0x80 },
+ { 62813000, 0xD3, 0x70 },
+ { 67625000, 0xCD, 0x68 },
+ { 73250000, 0xCC, 0x60 },
+ { 79875000, 0xCB, 0x58 },
+ { 87875000, 0xCA, 0x50 },
+ { 97625000, 0xC9, 0x48 },
+ { 109875000, 0xC8, 0x40 },
+ { 125625000, 0xC3, 0x38 },
+ { 135250000, 0xBD, 0x34 },
+ { 146500000, 0xBC, 0x30 },
+ { 159750000, 0xBB, 0x2C },
+ { 175750000, 0xBA, 0x28 },
+ { 195250000, 0xB9, 0x24 },
+ { 219750000, 0xB8, 0x20 },
+ { 251250000, 0xB3, 0x1C },
+ { 270500000, 0xAD, 0x1A },
+ { 293000000, 0xAC, 0x18 },
+ { 319500000, 0xAB, 0x16 },
+ { 351500000, 0xAA, 0x14 },
+ { 390500000, 0xA9, 0x12 },
+ { 439500000, 0xA8, 0x10 },
+ { 502500000, 0xA3, 0x0E },
+ { 541000000, 0x9D, 0x0D },
+ { 586000000, 0x9C, 0x0C },
+ { 639000000, 0x9B, 0x0B },
+ { 703000000, 0x9A, 0x0A },
+ { 781000000, 0x99, 0x09 },
+ { 879000000, 0x98, 0x08 },
+ { 0, 0x00, 0x00 }, /* Table End */
};
static struct SMap m_GainTaper_Map[] = {
- { 45400000, 0x1F },
- { 45800000, 0x1E },
- { 46200000, 0x1D },
- { 46700000, 0x1C },
- { 47100000, 0x1B },
- { 47500000, 0x1A },
- { 47900000, 0x19 },
- { 49600000, 0x17 },
- { 51200000, 0x16 },
- { 52900000, 0x15 },
- { 54500000, 0x14 },
- { 56200000, 0x13 },
- { 57800000, 0x12 },
- { 59500000, 0x11 },
- { 61100000, 0x10 },
- { 67600000, 0x0D },
- { 74200000, 0x0C },
- { 80700000, 0x0B },
- { 87200000, 0x0A },
- { 93800000, 0x09 },
- { 100300000, 0x08 },
- { 106900000, 0x07 },
- { 113400000, 0x06 },
- { 119900000, 0x05 },
- { 126500000, 0x04 },
- { 133000000, 0x03 },
- { 139500000, 0x02 },
- { 146100000, 0x01 },
- { 152600000, 0x00 },
- { 154300000, 0x1F },
- { 156100000, 0x1E },
- { 157800000, 0x1D },
- { 159500000, 0x1C },
- { 161200000, 0x1B },
- { 163000000, 0x1A },
- { 164700000, 0x19 },
- { 170200000, 0x17 },
- { 175800000, 0x16 },
- { 181300000, 0x15 },
- { 186900000, 0x14 },
- { 192400000, 0x13 },
- { 198000000, 0x12 },
- { 203500000, 0x11 },
- { 216200000, 0x14 },
- { 228900000, 0x13 },
- { 241600000, 0x12 },
- { 254400000, 0x11 },
- { 267100000, 0x10 },
- { 279800000, 0x0F },
- { 292500000, 0x0E },
- { 305200000, 0x0D },
- { 317900000, 0x0C },
- { 330700000, 0x0B },
- { 343400000, 0x0A },
- { 356100000, 0x09 },
- { 368800000, 0x08 },
- { 381500000, 0x07 },
- { 394200000, 0x06 },
- { 406900000, 0x05 },
- { 419700000, 0x04 },
- { 432400000, 0x03 },
- { 445100000, 0x02 },
- { 457800000, 0x01 },
- { 476300000, 0x19 },
- { 494800000, 0x18 },
- { 513300000, 0x17 },
- { 531800000, 0x16 },
- { 550300000, 0x15 },
- { 568900000, 0x14 },
- { 587400000, 0x13 },
- { 605900000, 0x12 },
- { 624400000, 0x11 },
- { 642900000, 0x10 },
- { 661400000, 0x0F },
- { 679900000, 0x0E },
- { 698400000, 0x0D },
- { 716900000, 0x0C },
- { 735400000, 0x0B },
- { 753900000, 0x0A },
- { 772500000, 0x09 },
- { 791000000, 0x08 },
- { 809500000, 0x07 },
- { 828000000, 0x06 },
- { 846500000, 0x05 },
- { 865000000, 0x04 },
- { 0, 0x00 }, // Table End
+ { 45400000, 0x1F },
+ { 45800000, 0x1E },
+ { 46200000, 0x1D },
+ { 46700000, 0x1C },
+ { 47100000, 0x1B },
+ { 47500000, 0x1A },
+ { 47900000, 0x19 },
+ { 49600000, 0x17 },
+ { 51200000, 0x16 },
+ { 52900000, 0x15 },
+ { 54500000, 0x14 },
+ { 56200000, 0x13 },
+ { 57800000, 0x12 },
+ { 59500000, 0x11 },
+ { 61100000, 0x10 },
+ { 67600000, 0x0D },
+ { 74200000, 0x0C },
+ { 80700000, 0x0B },
+ { 87200000, 0x0A },
+ { 93800000, 0x09 },
+ { 100300000, 0x08 },
+ { 106900000, 0x07 },
+ { 113400000, 0x06 },
+ { 119900000, 0x05 },
+ { 126500000, 0x04 },
+ { 133000000, 0x03 },
+ { 139500000, 0x02 },
+ { 146100000, 0x01 },
+ { 152600000, 0x00 },
+ { 154300000, 0x1F },
+ { 156100000, 0x1E },
+ { 157800000, 0x1D },
+ { 159500000, 0x1C },
+ { 161200000, 0x1B },
+ { 163000000, 0x1A },
+ { 164700000, 0x19 },
+ { 170200000, 0x17 },
+ { 175800000, 0x16 },
+ { 181300000, 0x15 },
+ { 186900000, 0x14 },
+ { 192400000, 0x13 },
+ { 198000000, 0x12 },
+ { 203500000, 0x11 },
+ { 216200000, 0x14 },
+ { 228900000, 0x13 },
+ { 241600000, 0x12 },
+ { 254400000, 0x11 },
+ { 267100000, 0x10 },
+ { 279800000, 0x0F },
+ { 292500000, 0x0E },
+ { 305200000, 0x0D },
+ { 317900000, 0x0C },
+ { 330700000, 0x0B },
+ { 343400000, 0x0A },
+ { 356100000, 0x09 },
+ { 368800000, 0x08 },
+ { 381500000, 0x07 },
+ { 394200000, 0x06 },
+ { 406900000, 0x05 },
+ { 419700000, 0x04 },
+ { 432400000, 0x03 },
+ { 445100000, 0x02 },
+ { 457800000, 0x01 },
+ { 476300000, 0x19 },
+ { 494800000, 0x18 },
+ { 513300000, 0x17 },
+ { 531800000, 0x16 },
+ { 550300000, 0x15 },
+ { 568900000, 0x14 },
+ { 587400000, 0x13 },
+ { 605900000, 0x12 },
+ { 624400000, 0x11 },
+ { 642900000, 0x10 },
+ { 661400000, 0x0F },
+ { 679900000, 0x0E },
+ { 698400000, 0x0D },
+ { 716900000, 0x0C },
+ { 735400000, 0x0B },
+ { 753900000, 0x0A },
+ { 772500000, 0x09 },
+ { 791000000, 0x08 },
+ { 809500000, 0x07 },
+ { 828000000, 0x06 },
+ { 846500000, 0x05 },
+ { 865000000, 0x04 },
+ { 0, 0x00 }, /* Table End */
};
static struct SMap m_RF_Cal_DC_Over_DT_Map[] = {
- { 47900000, 0x00 },
- { 55000000, 0x00 },
- { 61100000, 0x0A },
- { 64000000, 0x0A },
- { 82000000, 0x14 },
- { 84000000, 0x19 },
- { 119000000, 0x1C },
- { 124000000, 0x20 },
- { 129000000, 0x2A },
- { 134000000, 0x32 },
- { 139000000, 0x39 },
- { 144000000, 0x3E },
- { 149000000, 0x3F },
- { 152600000, 0x40 },
- { 154000000, 0x40 },
- { 164700000, 0x41 },
- { 203500000, 0x32 },
- { 353000000, 0x19 },
- { 356000000, 0x1A },
- { 359000000, 0x1B },
- { 363000000, 0x1C },
- { 366000000, 0x1D },
- { 369000000, 0x1E },
- { 373000000, 0x1F },
- { 376000000, 0x20 },
- { 379000000, 0x21 },
- { 383000000, 0x22 },
- { 386000000, 0x23 },
- { 389000000, 0x24 },
- { 393000000, 0x25 },
- { 396000000, 0x26 },
- { 399000000, 0x27 },
- { 402000000, 0x28 },
- { 404000000, 0x29 },
- { 407000000, 0x2A },
- { 409000000, 0x2B },
- { 412000000, 0x2C },
- { 414000000, 0x2D },
- { 417000000, 0x2E },
- { 419000000, 0x2F },
- { 422000000, 0x30 },
- { 424000000, 0x31 },
- { 427000000, 0x32 },
- { 429000000, 0x33 },
- { 432000000, 0x34 },
- { 434000000, 0x35 },
- { 437000000, 0x36 },
- { 439000000, 0x37 },
- { 442000000, 0x38 },
- { 444000000, 0x39 },
- { 447000000, 0x3A },
- { 449000000, 0x3B },
- { 457800000, 0x3C },
- { 465000000, 0x0F },
- { 477000000, 0x12 },
- { 483000000, 0x14 },
- { 502000000, 0x19 },
- { 508000000, 0x1B },
- { 519000000, 0x1C },
- { 522000000, 0x1D },
- { 524000000, 0x1E },
- { 534000000, 0x1F },
- { 549000000, 0x20 },
- { 554000000, 0x22 },
- { 584000000, 0x24 },
- { 589000000, 0x26 },
- { 658000000, 0x27 },
- { 664000000, 0x2C },
- { 669000000, 0x2D },
- { 699000000, 0x2E },
- { 704000000, 0x30 },
- { 709000000, 0x31 },
- { 714000000, 0x32 },
- { 724000000, 0x33 },
- { 729000000, 0x36 },
- { 739000000, 0x38 },
- { 744000000, 0x39 },
- { 749000000, 0x3B },
- { 754000000, 0x3C },
- { 759000000, 0x3D },
- { 764000000, 0x3E },
- { 769000000, 0x3F },
- { 774000000, 0x40 },
- { 779000000, 0x41 },
- { 784000000, 0x43 },
- { 789000000, 0x46 },
- { 794000000, 0x48 },
- { 799000000, 0x4B },
- { 804000000, 0x4F },
- { 809000000, 0x54 },
- { 814000000, 0x59 },
- { 819000000, 0x5D },
- { 824000000, 0x61 },
- { 829000000, 0x68 },
- { 834000000, 0x6E },
- { 839000000, 0x75 },
- { 844000000, 0x7E },
- { 849000000, 0x82 },
- { 854000000, 0x84 },
- { 859000000, 0x8F },
- { 865000000, 0x9A },
- { 0, 0x00 }, // Table End
+ { 47900000, 0x00 },
+ { 55000000, 0x00 },
+ { 61100000, 0x0A },
+ { 64000000, 0x0A },
+ { 82000000, 0x14 },
+ { 84000000, 0x19 },
+ { 119000000, 0x1C },
+ { 124000000, 0x20 },
+ { 129000000, 0x2A },
+ { 134000000, 0x32 },
+ { 139000000, 0x39 },
+ { 144000000, 0x3E },
+ { 149000000, 0x3F },
+ { 152600000, 0x40 },
+ { 154000000, 0x40 },
+ { 164700000, 0x41 },
+ { 203500000, 0x32 },
+ { 353000000, 0x19 },
+ { 356000000, 0x1A },
+ { 359000000, 0x1B },
+ { 363000000, 0x1C },
+ { 366000000, 0x1D },
+ { 369000000, 0x1E },
+ { 373000000, 0x1F },
+ { 376000000, 0x20 },
+ { 379000000, 0x21 },
+ { 383000000, 0x22 },
+ { 386000000, 0x23 },
+ { 389000000, 0x24 },
+ { 393000000, 0x25 },
+ { 396000000, 0x26 },
+ { 399000000, 0x27 },
+ { 402000000, 0x28 },
+ { 404000000, 0x29 },
+ { 407000000, 0x2A },
+ { 409000000, 0x2B },
+ { 412000000, 0x2C },
+ { 414000000, 0x2D },
+ { 417000000, 0x2E },
+ { 419000000, 0x2F },
+ { 422000000, 0x30 },
+ { 424000000, 0x31 },
+ { 427000000, 0x32 },
+ { 429000000, 0x33 },
+ { 432000000, 0x34 },
+ { 434000000, 0x35 },
+ { 437000000, 0x36 },
+ { 439000000, 0x37 },
+ { 442000000, 0x38 },
+ { 444000000, 0x39 },
+ { 447000000, 0x3A },
+ { 449000000, 0x3B },
+ { 457800000, 0x3C },
+ { 465000000, 0x0F },
+ { 477000000, 0x12 },
+ { 483000000, 0x14 },
+ { 502000000, 0x19 },
+ { 508000000, 0x1B },
+ { 519000000, 0x1C },
+ { 522000000, 0x1D },
+ { 524000000, 0x1E },
+ { 534000000, 0x1F },
+ { 549000000, 0x20 },
+ { 554000000, 0x22 },
+ { 584000000, 0x24 },
+ { 589000000, 0x26 },
+ { 658000000, 0x27 },
+ { 664000000, 0x2C },
+ { 669000000, 0x2D },
+ { 699000000, 0x2E },
+ { 704000000, 0x30 },
+ { 709000000, 0x31 },
+ { 714000000, 0x32 },
+ { 724000000, 0x33 },
+ { 729000000, 0x36 },
+ { 739000000, 0x38 },
+ { 744000000, 0x39 },
+ { 749000000, 0x3B },
+ { 754000000, 0x3C },
+ { 759000000, 0x3D },
+ { 764000000, 0x3E },
+ { 769000000, 0x3F },
+ { 774000000, 0x40 },
+ { 779000000, 0x41 },
+ { 784000000, 0x43 },
+ { 789000000, 0x46 },
+ { 794000000, 0x48 },
+ { 799000000, 0x4B },
+ { 804000000, 0x4F },
+ { 809000000, 0x54 },
+ { 814000000, 0x59 },
+ { 819000000, 0x5D },
+ { 824000000, 0x61 },
+ { 829000000, 0x68 },
+ { 834000000, 0x6E },
+ { 839000000, 0x75 },
+ { 844000000, 0x7E },
+ { 849000000, 0x82 },
+ { 854000000, 0x84 },
+ { 859000000, 0x8F },
+ { 865000000, 0x9A },
+ { 0, 0x00 }, /* Table End */
};
static struct SMap m_IR_Meas_Map[] = {
- { 200000000, 0x05 },
- { 400000000, 0x06 },
- { 865000000, 0x07 },
- { 0, 0x00 }, // Table End
+ { 200000000, 0x05 },
+ { 400000000, 0x06 },
+ { 865000000, 0x07 },
+ { 0, 0x00 }, /* Table End */
};
static struct SMap2 m_CID_Target_Map[] = {
- { 46000000, 0x04, 18 },
- { 52200000, 0x0A, 15 },
- { 70100000, 0x01, 40 },
- { 136800000, 0x18, 40 },
- { 156700000, 0x18, 40 },
- { 186250000, 0x0A, 40 },
- { 230000000, 0x0A, 40 },
- { 345000000, 0x18, 40 },
- { 426000000, 0x0E, 40 },
- { 489500000, 0x1E, 40 },
- { 697500000, 0x32, 40 },
- { 842000000, 0x3A, 40 },
- { 0, 0x00, 0 }, // Table End
+ { 46000000, 0x04, 18 },
+ { 52200000, 0x0A, 15 },
+ { 70100000, 0x01, 40 },
+ { 136800000, 0x18, 40 },
+ { 156700000, 0x18, 40 },
+ { 186250000, 0x0A, 40 },
+ { 230000000, 0x0A, 40 },
+ { 345000000, 0x18, 40 },
+ { 426000000, 0x0E, 40 },
+ { 489500000, 0x1E, 40 },
+ { 697500000, 0x32, 40 },
+ { 842000000, 0x3A, 40 },
+ { 0, 0x00, 0 }, /* Table End */
};
static struct SRFBandMap m_RF_Band_Map[7] = {
- { 47900000, 46000000, 0, 0},
- { 61100000, 52200000, 0, 0},
- { 152600000, 70100000, 136800000, 0},
- { 164700000, 156700000, 0, 0},
- { 203500000, 186250000, 0, 0},
- { 457800000, 230000000, 345000000, 426000000},
- { 865000000, 489500000, 697500000, 842000000},
+ { 47900000, 46000000, 0, 0},
+ { 61100000, 52200000, 0, 0},
+ { 152600000, 70100000, 136800000, 0},
+ { 164700000, 156700000, 0, 0},
+ { 203500000, 186250000, 0, 0},
+ { 457800000, 230000000, 345000000, 426000000},
+ { 865000000, 489500000, 697500000, 842000000},
};
u8 m_Thermometer_Map_1[16] = {
- 60,62,66,64, 74,72,68,70, 90,88,84,86, 76,78,82,80,
+ 60, 62, 66, 64,
+ 74, 72, 68, 70,
+ 90, 88, 84, 86,
+ 76, 78, 82, 80,
};
u8 m_Thermometer_Map_2[16] = {
- 92,94,98,96, 106,104,100,102, 122,120,116,118, 108,110,114,112,
+ 92, 94, 98, 96,
+ 106, 104, 100, 102,
+ 122, 120, 116, 118,
+ 108, 110, 114, 112,
};
-
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 05/16] DRX-K: Tons of coding-style fixes
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
2011-07-03 16:36 ` [PATCH 01/16] tda18271c2dd: Initial check-in Oliver Endriss
2011-07-03 16:37 ` [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes Oliver Endriss
@ 2011-07-03 16:49 ` Oliver Endriss
2011-07-03 16:51 ` [PATCH 06/16] DRX-K, TDA18271c2: Add build support Oliver Endriss
` (14 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:49 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Tons of coding-style fixes
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/frontends/drxk_hard.c | 4342 +++++++++++++++++--------------
drivers/media/dvb/frontends/drxk_hard.h | 231 +-
2 files changed, 2444 insertions(+), 2129 deletions(-)
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
index e6b1499..fbe24b6 100644
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -37,14 +37,17 @@
static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
static int PowerDownQAM(struct drxk_state *state);
-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode);
-static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode);
-static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz,
+static int SetDVBTStandard(struct drxk_state *state,
+ enum OperationMode oMode);
+static int SetQAMStandard(struct drxk_state *state,
+ enum OperationMode oMode);
+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
s32 tunerFreqOffset);
-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode);
+static int SetDVBTStandard(struct drxk_state *state,
+ enum OperationMode oMode);
static int DVBTStart(struct drxk_state *state);
-static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz,
- s32 tunerFreqOffset);
+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
+ s32 tunerFreqOffset);
static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
static int SwitchAntennaToQAM(struct drxk_state *state);
@@ -58,8 +61,8 @@ static bool IsDVBT(struct drxk_state *state)
static bool IsQAM(struct drxk_state *state)
{
return state->m_OperationMode == OM_QAM_ITU_A ||
- state->m_OperationMode == OM_QAM_ITU_B ||
- state->m_OperationMode == OM_QAM_ITU_C;
+ state->m_OperationMode == OM_QAM_ITU_B ||
+ state->m_OperationMode == OM_QAM_ITU_C;
}
bool IsA1WithPatchCode(struct drxk_state *state)
@@ -75,7 +78,7 @@ bool IsA1WithRomCode(struct drxk_state *state)
#define NOA1ROM 0
#ifndef CHK_ERROR
- #define CHK_ERROR(s) if ((status = s) < 0) break
+#define CHK_ERROR(s) if ((status = s) < 0) break
#endif
#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
@@ -178,7 +181,7 @@ inline u32 MulDiv32(u32 a, u32 b, u32 c)
{
u64 tmp64;
- tmp64 = (u64)a * (u64)b;
+ tmp64 = (u64) a * (u64) b;
do_div(tmp64, c);
return (u32) tmp64;
@@ -190,9 +193,9 @@ inline u32 Frac28a(u32 a, u32 c)
u32 Q1 = 0;
u32 R0 = 0;
- R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
- Q1 = a / c; /* integer part, only the 4 least significant bits
- will be visible in the result */
+ R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
+ Q1 = a / c; /* integer part, only the 4 least significant bits
+ will be visible in the result */
/* division using radix 16, 7 nibbles in the result */
for (i = 0; i < 7; i++) {
@@ -210,94 +213,94 @@ static u32 Log10Times100(u32 x)
{
static const u8 scale = 15;
static const u8 indexWidth = 5;
- u8 i = 0;
+ u8 i = 0;
u32 y = 0;
u32 d = 0;
u32 k = 0;
u32 r = 0;
/*
- log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
- 0 <= n < ((1<<INDEXWIDTH)+1)
- */
+ log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
+ 0 <= n < ((1<<INDEXWIDTH)+1)
+ */
static const u32 log2lut[] = {
- 0, /* 0.000000 */
- 290941, /* 290941.300628 */
- 573196, /* 573196.476418 */
- 847269, /* 847269.179851 */
- 1113620, /* 1113620.489452 */
- 1372674, /* 1372673.576986 */
- 1624818, /* 1624817.752104 */
- 1870412, /* 1870411.981536 */
- 2109788, /* 2109787.962654 */
- 2343253, /* 2343252.817465 */
- 2571091, /* 2571091.461923 */
- 2793569, /* 2793568.696416 */
- 3010931, /* 3010931.055901 */
- 3223408, /* 3223408.452106 */
- 3431216, /* 3431215.635215 */
- 3634553, /* 3634553.498355 */
- 3833610, /* 3833610.244726 */
- 4028562, /* 4028562.434393 */
- 4219576, /* 4219575.925308 */
- 4406807, /* 4406806.721144 */
- 4590402, /* 4590401.736809 */
- 4770499, /* 4770499.491025 */
- 4947231, /* 4947230.734179 */
- 5120719, /* 5120719.018555 */
- 5291081, /* 5291081.217197 */
- 5458428, /* 5458427.996830 */
- 5622864, /* 5622864.249668 */
- 5784489, /* 5784489.488298 */
- 5943398, /* 5943398.207380 */
- 6099680, /* 6099680.215452 */
- 6253421, /* 6253420.939751 */
- 6404702, /* 6404701.706649 */
- 6553600, /* 6553600.000000 */
+ 0, /* 0.000000 */
+ 290941, /* 290941.300628 */
+ 573196, /* 573196.476418 */
+ 847269, /* 847269.179851 */
+ 1113620, /* 1113620.489452 */
+ 1372674, /* 1372673.576986 */
+ 1624818, /* 1624817.752104 */
+ 1870412, /* 1870411.981536 */
+ 2109788, /* 2109787.962654 */
+ 2343253, /* 2343252.817465 */
+ 2571091, /* 2571091.461923 */
+ 2793569, /* 2793568.696416 */
+ 3010931, /* 3010931.055901 */
+ 3223408, /* 3223408.452106 */
+ 3431216, /* 3431215.635215 */
+ 3634553, /* 3634553.498355 */
+ 3833610, /* 3833610.244726 */
+ 4028562, /* 4028562.434393 */
+ 4219576, /* 4219575.925308 */
+ 4406807, /* 4406806.721144 */
+ 4590402, /* 4590401.736809 */
+ 4770499, /* 4770499.491025 */
+ 4947231, /* 4947230.734179 */
+ 5120719, /* 5120719.018555 */
+ 5291081, /* 5291081.217197 */
+ 5458428, /* 5458427.996830 */
+ 5622864, /* 5622864.249668 */
+ 5784489, /* 5784489.488298 */
+ 5943398, /* 5943398.207380 */
+ 6099680, /* 6099680.215452 */
+ 6253421, /* 6253420.939751 */
+ 6404702, /* 6404701.706649 */
+ 6553600, /* 6553600.000000 */
};
if (x == 0)
- return (0);
+ return 0;
/* Scale x (normalize) */
/* computing y in log(x/y) = log(x) - log(y) */
if ((x & ((0xffffffff) << (scale + 1))) == 0) {
for (k = scale; k > 0; k--) {
- if (x & (((u32)1) << scale))
+ if (x & (((u32) 1) << scale))
break;
x <<= 1;
}
} else {
- for (k = scale; k < 31 ; k++) {
- if ((x & (((u32)(-1)) << (scale+1))) == 0)
+ for (k = scale; k < 31; k++) {
+ if ((x & (((u32) (-1)) << (scale + 1))) == 0)
break;
x >>= 1;
- }
+ }
}
/*
- Now x has binary point between bit[scale] and bit[scale-1]
- and 1.0 <= x < 2.0 */
+ Now x has binary point between bit[scale] and bit[scale-1]
+ and 1.0 <= x < 2.0 */
/* correction for divison: log(x) = log(x/y)+log(y) */
- y = k * ((((u32)1) << scale) * 200);
+ y = k * ((((u32) 1) << scale) * 200);
/* remove integer part */
- x &= ((((u32)1) << scale)-1);
+ x &= ((((u32) 1) << scale) - 1);
/* get index */
i = (u8) (x >> (scale - indexWidth));
/* compute delta (x - a) */
- d = x & ((((u32)1) << (scale - indexWidth)) - 1);
+ d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
/* compute log, multiplication (d* (..)) must be within range ! */
y += log2lut[i] +
- ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
+ ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
/* Conver to log10() */
- y /= 108853; /* (log2(10) << scale) */
+ y /= 108853; /* (log2(10) << scale) */
r = (y >> 1);
/* rounding */
- if (y & ((u32)1))
+ if (y & ((u32) 1))
r++;
- return (r);
+ return r;
}
/****************************************************************************/
@@ -306,18 +309,19 @@ static u32 Log10Times100(u32 x)
static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
{
- struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1 }};
+ struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = 1}
+ };
return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
}
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
- struct i2c_msg msg =
- {.addr = adr, .flags = 0, .buf = data, .len = len};
+ struct i2c_msg msg = {
+ .addr = adr, .flags = 0, .buf = data, .len = len };
if (i2c_transfer(adap, &msg, 1) != 1) {
- printk("i2c_write error\n");
+ printk(KERN_ERR "i2c_write error\n");
return -1;
}
return 0;
@@ -326,12 +330,13 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
static int i2c_read(struct i2c_adapter *adap,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
- struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
- .buf = msg, .len = len},
- { .addr = adr, .flags = I2C_M_RD,
- .buf = answ, .len = alen } };
+ struct i2c_msg msgs[2] = { {.addr = adr, .flags = 0,
+ .buf = msg, .len = len},
+ {.addr = adr, .flags = I2C_M_RD,
+ .buf = answ, .len = alen}
+ };
if (i2c_transfer(adap, msgs, 2) != 2) {
- printk("i2c_read error\n");
+ printk(KERN_ERR "i2c_read error\n");
return -1;
}
return 0;
@@ -339,7 +344,7 @@ static int i2c_read(struct i2c_adapter *adap,
static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
{
- u8 adr=state->demod_address, mm1[4], mm2[2], len;
+ u8 adr = state->demod_address, mm1[4], mm2[2], len;
#ifdef I2C_LONG_ADR
flags |= 0xC0;
#endif
@@ -387,7 +392,7 @@ static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
return -1;
if (data)
*data = mm2[0] | (mm2[1] << 8) |
- (mm2[2] << 16) | (mm2[3] << 24);
+ (mm2[2] << 16) | (mm2[3] << 24);
return 0;
}
@@ -409,7 +414,7 @@ static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags)
len = 2;
}
mm[len] = data & 0xff;
- mm[len+1] = (data >>8) & 0xff;
+ mm[len + 1] = (data >> 8) & 0xff;
if (i2c_write(state->i2c, adr, mm, len + 2) < 0)
return -1;
return 0;
@@ -438,10 +443,10 @@ static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags)
len = 2;
}
mm[len] = data & 0xff;
- mm[len+1] = (data >> 8) & 0xff;
- mm[len+2] = (data >> 16) & 0xff;
- mm[len+3] = (data >> 24) & 0xff;
- if (i2c_write(state->i2c, adr, mm, len+4) < 0)
+ mm[len + 1] = (data >> 8) & 0xff;
+ mm[len + 2] = (data >> 16) & 0xff;
+ mm[len + 3] = (data >> 24) & 0xff;
+ if (i2c_write(state->i2c, adr, mm, len + 4) < 0)
return -1;
return 0;
}
@@ -453,22 +458,22 @@ static int WriteBlock(struct drxk_state *state, u32 Address,
#ifdef I2C_LONG_ADR
Flags |= 0xC0;
#endif
- while (BlkSize > 0) {
+ while (BlkSize > 0) {
int Chunk = BlkSize > state->m_ChunkSize ?
- state->m_ChunkSize : BlkSize ;
+ state->m_ChunkSize : BlkSize;
u8 *AdrBuf = &state->Chunk[0];
u32 AdrLength = 0;
- if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
- AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
- AdrBuf[1] = ((Address >> 16) & 0xFF);
- AdrBuf[2] = ((Address >> 24) & 0xFF);
- AdrBuf[3] = ((Address >> 7) & 0xFF);
+ if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
+ AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
+ AdrBuf[1] = ((Address >> 16) & 0xFF);
+ AdrBuf[2] = ((Address >> 24) & 0xFF);
+ AdrBuf[3] = ((Address >> 7) & 0xFF);
AdrBuf[2] |= Flags;
AdrLength = 4;
if (Chunk == state->m_ChunkSize)
Chunk -= 2;
- } else {
+ } else {
AdrBuf[0] = ((Address << 1) & 0xFF);
AdrBuf[1] = (((Address >> 16) & 0x0F) |
((Address >> 18) & 0xF0));
@@ -476,16 +481,16 @@ static int WriteBlock(struct drxk_state *state, u32 Address,
}
memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
status = i2c_write(state->i2c, state->demod_address,
- &state->Chunk[0], Chunk+AdrLength);
- if (status<0) {
- printk("I2C Write error\n");
+ &state->Chunk[0], Chunk + AdrLength);
+ if (status < 0) {
+ printk(KERN_ERR "I2C Write error\n");
break;
}
pBlock += Chunk;
Address += (Chunk >> 1);
BlkSize -= Chunk;
}
- return status;
+ return status;
}
#ifndef DRXK_MAX_RETRIES_POWERUP
@@ -499,14 +504,14 @@ int PowerUpDevice(struct drxk_state *state)
u16 retryCount = 0;
status = i2c_read1(state->i2c, state->demod_address, &data);
- if (status<0)
+ if (status < 0)
do {
data = 0;
if (i2c_write(state->i2c,
state->demod_address, &data, 1) < 0)
- printk("powerup failed\n");
+ printk(KERN_ERR "powerup failed\n");
msleep(10);
- retryCount++ ;
+ retryCount++;
} while (i2c_read1(state->i2c,
state->demod_address, &data) < 0 &&
(retryCount < DRXK_MAX_RETRIES_POWERUP));
@@ -528,33 +533,33 @@ int PowerUpDevice(struct drxk_state *state)
static int init_state(struct drxk_state *state)
{
- u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulVSBIfAgcOutputLevel = 0;
- u32 ulVSBIfAgcMinLevel = 0;
- u32 ulVSBIfAgcMaxLevel = 0x7FFF;
- u32 ulVSBIfAgcSpeed = 3;
-
- u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulVSBRfAgcOutputLevel = 0;
- u32 ulVSBRfAgcMinLevel = 0;
- u32 ulVSBRfAgcMaxLevel = 0x7FFF;
- u32 ulVSBRfAgcSpeed = 3;
- u32 ulVSBRfAgcTop = 9500;
- u32 ulVSBRfAgcCutOffCurrent = 4000;
-
- u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulATVIfAgcOutputLevel = 0;
- u32 ulATVIfAgcMinLevel = 0;
- u32 ulATVIfAgcMaxLevel = 0;
- u32 ulATVIfAgcSpeed = 3;
-
- u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
- u32 ulATVRfAgcOutputLevel = 0;
- u32 ulATVRfAgcMinLevel = 0;
- u32 ulATVRfAgcMaxLevel = 0;
- u32 ulATVRfAgcTop = 9500;
- u32 ulATVRfAgcCutOffCurrent = 4000;
- u32 ulATVRfAgcSpeed = 3;
+ u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
+ u32 ulVSBIfAgcOutputLevel = 0;
+ u32 ulVSBIfAgcMinLevel = 0;
+ u32 ulVSBIfAgcMaxLevel = 0x7FFF;
+ u32 ulVSBIfAgcSpeed = 3;
+
+ u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
+ u32 ulVSBRfAgcOutputLevel = 0;
+ u32 ulVSBRfAgcMinLevel = 0;
+ u32 ulVSBRfAgcMaxLevel = 0x7FFF;
+ u32 ulVSBRfAgcSpeed = 3;
+ u32 ulVSBRfAgcTop = 9500;
+ u32 ulVSBRfAgcCutOffCurrent = 4000;
+
+ u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
+ u32 ulATVIfAgcOutputLevel = 0;
+ u32 ulATVIfAgcMinLevel = 0;
+ u32 ulATVIfAgcMaxLevel = 0;
+ u32 ulATVIfAgcSpeed = 3;
+
+ u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
+ u32 ulATVRfAgcOutputLevel = 0;
+ u32 ulATVRfAgcMinLevel = 0;
+ u32 ulATVRfAgcMaxLevel = 0;
+ u32 ulATVRfAgcTop = 9500;
+ u32 ulATVRfAgcCutOffCurrent = 4000;
+ u32 ulATVRfAgcSpeed = 3;
u32 ulQual83 = DEFAULT_MER_83;
u32 ulQual93 = DEFAULT_MER_93;
@@ -569,7 +574,7 @@ static int init_state(struct drxk_state *state)
/* io_pad_cfg_mode output mode is drive always */
/* io_pad_cfg_drive is set to power 2 (23 mA) */
u32 ulGPIOCfg = 0x0113;
- u32 ulGPIO = 0;
+ u32 ulGPIO = 0;
u32 ulSerialMode = 1;
u32 ulInvertTSClock = 0;
u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
@@ -587,9 +592,9 @@ static int init_state(struct drxk_state *state)
u32 ulAntennaSwitchDVBTDVBC = 0;
state->m_hasLNA = false;
- state->m_hasDVBT= false;
- state->m_hasDVBC= false;
- state->m_hasATV= false;
+ state->m_hasDVBT = false;
+ state->m_hasDVBC = false;
+ state->m_hasATV = false;
state->m_hasOOB = false;
state->m_hasAudio = false;
@@ -600,7 +605,7 @@ static int init_state(struct drxk_state *state)
state->m_bPDownOpenBridge = false;
/* real system clock frequency in kHz */
- state->m_sysClockFreq = 151875;
+ state->m_sysClockFreq = 151875;
/* Timing div, 250ns/Psys */
/* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
@@ -623,23 +628,23 @@ static int init_state(struct drxk_state *state)
/* Init AGC and PGA parameters */
/* VSB IF */
- state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
- state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
- state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
- state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
- state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
+ state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
+ state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
+ state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
+ state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
+ state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
state->m_vsbPgaCfg = 140;
/* VSB RF */
- state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
- state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
- state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
- state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
- state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
- state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
- state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
- state->m_vsbPreSawCfg.reference = 0x07;
- state->m_vsbPreSawCfg.usePreSaw = true;
+ state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
+ state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
+ state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
+ state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
+ state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
+ state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
+ state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
+ state->m_vsbPreSawCfg.reference = 0x07;
+ state->m_vsbPreSawCfg.usePreSaw = true;
state->m_Quality83percent = DEFAULT_MER_83;
state->m_Quality93percent = DEFAULT_MER_93;
@@ -649,90 +654,88 @@ static int init_state(struct drxk_state *state)
}
/* ATV IF */
- state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
- state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
- state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
- state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
- state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
+ state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
+ state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
+ state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
+ state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
+ state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
/* ATV RF */
- state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
- state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
- state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
- state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
- state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
- state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
- state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
- state->m_atvPreSawCfg.reference = 0x04;
- state->m_atvPreSawCfg.usePreSaw = true;
+ state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
+ state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
+ state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
+ state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
+ state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
+ state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
+ state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
+ state->m_atvPreSawCfg.reference = 0x04;
+ state->m_atvPreSawCfg.usePreSaw = true;
/* DVBT RF */
- state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
- state->m_dvbtRfAgcCfg.outputLevel = 0;
- state->m_dvbtRfAgcCfg.minOutputLevel = 0;
- state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
- state->m_dvbtRfAgcCfg.top = 0x2100;
- state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
- state->m_dvbtRfAgcCfg.speed = 1;
+ state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
+ state->m_dvbtRfAgcCfg.outputLevel = 0;
+ state->m_dvbtRfAgcCfg.minOutputLevel = 0;
+ state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
+ state->m_dvbtRfAgcCfg.top = 0x2100;
+ state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
+ state->m_dvbtRfAgcCfg.speed = 1;
/* DVBT IF */
- state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
- state->m_dvbtIfAgcCfg.outputLevel = 0;
- state->m_dvbtIfAgcCfg.minOutputLevel = 0;
- state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
- state->m_dvbtIfAgcCfg.top = 13424;
- state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
- state->m_dvbtIfAgcCfg.speed = 3;
+ state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
+ state->m_dvbtIfAgcCfg.outputLevel = 0;
+ state->m_dvbtIfAgcCfg.minOutputLevel = 0;
+ state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
+ state->m_dvbtIfAgcCfg.top = 13424;
+ state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
+ state->m_dvbtIfAgcCfg.speed = 3;
state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
- state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
- // state->m_dvbtPgaCfg = 140;
+ state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
+ /* state->m_dvbtPgaCfg = 140; */
- state->m_dvbtPreSawCfg.reference = 4;
- state->m_dvbtPreSawCfg.usePreSaw = false;
+ state->m_dvbtPreSawCfg.reference = 4;
+ state->m_dvbtPreSawCfg.usePreSaw = false;
/* QAM RF */
- state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
- state->m_qamRfAgcCfg.outputLevel = 0;
- state->m_qamRfAgcCfg.minOutputLevel = 6023;
- state->m_qamRfAgcCfg.maxOutputLevel = 27000;
- state->m_qamRfAgcCfg.top = 0x2380;
- state->m_qamRfAgcCfg.cutOffCurrent = 4000;
- state->m_qamRfAgcCfg.speed = 3;
+ state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
+ state->m_qamRfAgcCfg.outputLevel = 0;
+ state->m_qamRfAgcCfg.minOutputLevel = 6023;
+ state->m_qamRfAgcCfg.maxOutputLevel = 27000;
+ state->m_qamRfAgcCfg.top = 0x2380;
+ state->m_qamRfAgcCfg.cutOffCurrent = 4000;
+ state->m_qamRfAgcCfg.speed = 3;
/* QAM IF */
- state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
- state->m_qamIfAgcCfg.outputLevel = 0;
- state->m_qamIfAgcCfg.minOutputLevel = 0;
- state->m_qamIfAgcCfg.maxOutputLevel = 9000;
- state->m_qamIfAgcCfg.top = 0x0511;
- state->m_qamIfAgcCfg.cutOffCurrent = 0;
- state->m_qamIfAgcCfg.speed = 3;
- state->m_qamIfAgcCfg.IngainTgtMax = 5119;
+ state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
+ state->m_qamIfAgcCfg.outputLevel = 0;
+ state->m_qamIfAgcCfg.minOutputLevel = 0;
+ state->m_qamIfAgcCfg.maxOutputLevel = 9000;
+ state->m_qamIfAgcCfg.top = 0x0511;
+ state->m_qamIfAgcCfg.cutOffCurrent = 0;
+ state->m_qamIfAgcCfg.speed = 3;
+ state->m_qamIfAgcCfg.IngainTgtMax = 5119;
state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
- state->m_qamPgaCfg = 140;
- state->m_qamPreSawCfg.reference = 4;
- state->m_qamPreSawCfg.usePreSaw = false;
+ state->m_qamPgaCfg = 140;
+ state->m_qamPreSawCfg.reference = 4;
+ state->m_qamPreSawCfg.usePreSaw = false;
state->m_OperationMode = OM_NONE;
state->m_DrxkState = DRXK_UNINITIALIZED;
/* MPEG output configuration */
- state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
- state->m_insertRSByte = false; /* If TRUE; insert RS byte */
- state->m_enableParallel = true; /* If TRUE;
- parallel out otherwise serial */
- state->m_invertDATA = false; /* If TRUE; invert DATA signals */
- state->m_invertERR = false; /* If TRUE; invert ERR signal */
- state->m_invertSTR = false; /* If TRUE; invert STR signals */
- state->m_invertVAL = false; /* If TRUE; invert VAL signals */
- state->m_invertCLK =
- (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
+ state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
+ state->m_insertRSByte = false; /* If TRUE; insert RS byte */
+ state->m_enableParallel = true; /* If TRUE;
+ parallel out otherwise serial */
+ state->m_invertDATA = false; /* If TRUE; invert DATA signals */
+ state->m_invertERR = false; /* If TRUE; invert ERR signal */
+ state->m_invertSTR = false; /* If TRUE; invert STR signals */
+ state->m_invertVAL = false; /* If TRUE; invert VAL signals */
+ state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
- state->m_DVBCStaticCLK =
- (ulDVBCStaticTSClock != 0);
+ state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
/* If TRUE; static MPEG clockrate will be used;
otherwise clockrate will adapt to the bitrate of the TS */
@@ -756,22 +759,22 @@ static int init_state(struct drxk_state *state)
if (ulDemodLockTimeOut < 10000)
state->m_DemodLockTimeOut = ulDemodLockTimeOut;
- // QAM defaults
- state->m_Constellation = DRX_CONSTELLATION_AUTO;
+ /* QAM defaults */
+ state->m_Constellation = DRX_CONSTELLATION_AUTO;
state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
- state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/
- state->m_fecRsPrescale = 1;
+ state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
+ state->m_fecRsPrescale = 1;
state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
state->m_agcFastClipCtrlDelay = 0;
state->m_GPIOCfg = (ulGPIOCfg);
- state->m_GPIO = (ulGPIO == 0 ? 0 : 1);
+ state->m_GPIO = (ulGPIO == 0 ? 0 : 1);
state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1);
state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1);
state->m_AntennaSwitchDVBTDVBC =
- (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1);
+ (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1);
state->m_bPowerDown = false;
state->m_currentPowerMode = DRX_POWER_DOWN;
@@ -793,7 +796,7 @@ static int DRXX_Open(struct drxk_state *state)
do {
/* stop lock indicator process */
CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
/* Check device id */
CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0));
CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A,
@@ -801,24 +804,25 @@ static int DRXX_Open(struct drxk_state *state)
CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0));
CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0));
CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key));
- } while(0);
+ } while (0);
return status;
}
static int GetDeviceCapabilities(struct drxk_state *state)
{
- u16 sioPdrOhwCfg = 0;
+ u16 sioPdrOhwCfg = 0;
u32 sioTopJtagidLo = 0;
int status;
do {
/* driver 0.9.0 */
/* stop lock indicator process */
- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
+ CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA));
- CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0));
+ CHK_ERROR(Read16
+ (state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0));
CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000));
switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
@@ -841,13 +845,13 @@ static int GetDeviceCapabilities(struct drxk_state *state)
return -1;
}
/*
- Determine device capabilities
- Based on pinning v14
- */
+ Determine device capabilities
+ Based on pinning v14
+ */
CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A,
&sioTopJtagidLo, 0));
/* driver 0.9.0 */
- switch((sioTopJtagidLo >> 29) & 0xF) {
+ switch ((sioTopJtagidLo >> 29) & 0xF) {
case 0:
state->m_deviceSpin = DRXK_SPIN_A1;
break;
@@ -862,118 +866,118 @@ static int GetDeviceCapabilities(struct drxk_state *state)
status = -1;
break;
}
- switch ((sioTopJtagidLo>>12)&0xFF) {
+ switch ((sioTopJtagidLo >> 12) & 0xFF) {
case 0x13:
/* typeId = DRX3913K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = false;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = false;
state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = true;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = false;
state->m_hasGPIO1 = false;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x15:
/* typeId = DRX3915K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = false;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x16:
/* typeId = DRX3916K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = false;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x18:
/* typeId = DRX3918K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = false;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x21:
/* typeId = DRX3921K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = true;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x23:
/* typeId = DRX3923K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = true;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x25:
/* typeId = DRX3925K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = true;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
case 0x26:
/* typeId = DRX3926K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
+ state->m_hasLNA = false;
+ state->m_hasOOB = false;
+ state->m_hasATV = true;
state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
+ state->m_hasDVBT = true;
+ state->m_hasDVBC = true;
state->m_hasSAWSW = true;
state->m_hasGPIO2 = true;
state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
+ state->m_hasIRQN = false;
break;
default:
- printk("DeviceID not supported = %02x\n",
- ((sioTopJtagidLo>>12)&0xFF));
+ printk(KERN_ERR "DeviceID not supported = %02x\n",
+ ((sioTopJtagidLo >> 12) & 0xFF));
status = -1;
break;
}
- } while(0);
+ } while (0);
return status;
}
@@ -982,8 +986,6 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
int status;
bool powerdown_cmd;
- //printk("%s\n", __FUNCTION__);
-
/* Write command */
status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd);
if (status < 0)
@@ -992,10 +994,10 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
msleep(1);
powerdown_cmd =
- (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
- ((state->m_HICfgCtrl) &
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
+ (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
+ ((state->m_HICfgCtrl) &
+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
if (powerdown_cmd == false) {
/* Wait until command rdy */
u32 retryCount = 0;
@@ -1006,8 +1008,8 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
retryCount += 1;
status = Read16(state, SIO_HI_RA_RAM_CMD__A,
&waitCmd, 0);
- } while ((status < 0) &&
- (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0));
+ } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
+ && (waitCmd != 0));
if (status == 0)
status = Read16(state, SIO_HI_RA_RAM_RES__A,
@@ -1022,40 +1024,40 @@ static int HI_CfgCommand(struct drxk_state *state)
mutex_lock(&state->mutex);
do {
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_6__A,
state->m_HICfgTimeout));
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_5__A,
state->m_HICfgCtrl));
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_4__A,
state->m_HICfgWakeUpKey));
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_3__A,
state->m_HICfgBridgeDelay));
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A,
state->m_HICfgTimingDiv));
- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A,
+ CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A,
SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY));
CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0));
state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
- } while(0);
+ } while (0);
mutex_unlock(&state->mutex);
return status;
}
static int InitHI(struct drxk_state *state)
{
- state->m_HICfgWakeUpKey = (state->demod_address<<1);
+ state->m_HICfgWakeUpKey = (state->demod_address << 1);
state->m_HICfgTimeout = 0x96FF;
/* port/bridge/power down ctrl */
state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
- return HI_CfgCommand(state);
+ return HI_CfgCommand(state);
}
static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
{
int status = -1;
- u16 sioPdrMclkCfg = 0;
- u16 sioPdrMdxCfg = 0;
+ u16 sioPdrMclkCfg = 0;
+ u16 sioPdrMdxCfg = 0;
do {
/* stop lock indicator process */
@@ -1063,7 +1065,7 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
/* MPEG TS pad configuration */
- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA));
+ CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA));
if (mpegEnable == false) {
/* Set MPEG TS pads to inputmode */
@@ -1075,63 +1077,84 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
SIO_PDR_MCLK_CFG__A, 0x0000));
CHK_ERROR(Write16_0(state,
SIO_PDR_MVAL_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD0_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD1_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD2_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD3_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD4_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD5_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD6_CFG__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD7_CFG__A, 0x0000));
} else {
/* Enable MPEG output */
sioPdrMdxCfg =
- ((state->m_TSDataStrength <<
- SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
+ ((state->m_TSDataStrength <<
+ SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
sioPdrMclkCfg = ((state->m_TSClockkStrength <<
- SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003);
+ SIO_PDR_MCLK_CFG_DRIVE__B) |
+ 0x0003);
CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A,
sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A,
- 0x0000)); // Disable
- CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A,
- 0x0000)); // Disable
+ CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000)); /* Disable */
+ CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000)); /* Disable */
if (state->m_enableParallel == true) {
/* paralel -> enable MD1 to MD7 */
- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A,
- sioPdrMdxCfg));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A,
- sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD1_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD2_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD3_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD4_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD5_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD6_CFG__A,
+ sioPdrMdxCfg));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD7_CFG__A,
+ sioPdrMdxCfg));
} else {
- sioPdrMdxCfg = ((state->m_TSDataStrength <<
- SIO_PDR_MD0_CFG_DRIVE__B) |
- 0x0003);
+ sioPdrMdxCfg = ((state->m_TSDataStrength <<
+ SIO_PDR_MD0_CFG_DRIVE__B)
+ | 0x0003);
/* serial -> disable MD1 to MD7 */
- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A,
- 0x0000));
- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A,
- 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD1_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD2_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD3_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD4_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD5_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD6_CFG__A,
+ 0x0000));
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_MD7_CFG__A,
+ 0x0000));
}
CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A,
sioPdrMclkCfg));
@@ -1142,7 +1165,7 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000));
/* Write nomagic word to enable pdr reg write */
CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000));
- } while(0);
+ } while (0);
return status;
}
@@ -1168,7 +1191,7 @@ static int BLChainCmd(struct drxk_state *state,
nrOfElements));
CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A,
SIO_BL_ENABLE_ON));
- end=jiffies+msecs_to_jiffies(timeOut);
+ end = jiffies + msecs_to_jiffies(timeOut);
do {
msleep(1);
@@ -1177,19 +1200,18 @@ static int BLChainCmd(struct drxk_state *state,
} while ((blStatus == 0x1) &&
((time_is_after_jiffies(end))));
if (blStatus == 0x1) {
- printk("SIO not ready\n");
+ printk(KERN_ERR "SIO not ready\n");
mutex_unlock(&state->mutex);
return -1;
}
- } while(0);
+ } while (0);
mutex_unlock(&state->mutex);
return status;
}
static int DownloadMicrocode(struct drxk_state *state,
- const u8 pMCImage[],
- u32 Length)
+ const u8 pMCImage[], u32 Length)
{
const u8 *pSrc = pMCImage;
u16 Flags;
@@ -1204,25 +1226,31 @@ static int DownloadMicrocode(struct drxk_state *state,
/* down the drain (we don care about MAGIC_WORD) */
Drain = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16); offset += sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
nBlocks = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16); offset += sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
for (i = 0; i < nBlocks; i += 1) {
Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
- (pSrc[2] << 8) | pSrc[3];
- pSrc += sizeof(u32); offset += sizeof(u32);
+ (pSrc[2] << 8) | pSrc[3];
+ pSrc += sizeof(u32);
+ offset += sizeof(u32);
BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
- pSrc += sizeof(u16); offset += sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
Flags = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16); offset += sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
BlockCRC = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16); offset += sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
status = WriteBlock(state, Address, BlockSize, pSrc, 0);
- if (status<0)
+ if (status < 0)
break;
pSrc += BlockSize;
offset += BlockSize;
@@ -1233,32 +1261,33 @@ static int DownloadMicrocode(struct drxk_state *state,
static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
{
int status;
- u16 data = 0;
- u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
+ u16 data = 0;
+ u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
unsigned long end;
if (enable == false) {
- desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
+ desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
}
- status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
+ status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
if (data == desiredStatus) {
/* tokenring already has correct status */
return status;
}
/* Disable/enable dvbt tokenring bridge */
- status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
+ status =
+ Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
- end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
+ end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
do
- CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
- while ((data != desiredStatus) &&
- ((time_is_after_jiffies(end))));
+ CHK_ERROR(Read16_0
+ (state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
+ while ((data != desiredStatus) && ((time_is_after_jiffies(end))));
if (data != desiredStatus) {
- printk("SIO not ready\n");
+ printk(KERN_ERR "SIO not ready\n");
return -1;
}
return status;
@@ -1272,21 +1301,25 @@ static int MPEGTSStop(struct drxk_state *state)
do {
/* Gracefull shutdown (byte boundaries) */
- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode));
+ CHK_ERROR(Read16_0
+ (state, FEC_OC_SNC_MODE__A, &fecOcSncMode));
fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_SNC_MODE__A, fecOcSncMode));
/* Suppress MCLK during absence of data */
- CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode));
+ CHK_ERROR(Read16_0
+ (state, FEC_OC_IPR_MODE__A, &fecOcIprMode));
fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
- CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_IPR_MODE__A, fecOcIprMode));
} while (0);
return status;
}
static int scu_command(struct drxk_state *state,
u16 cmd, u8 parameterLen,
- u16 * parameter, u8 resultLen, u16 * result)
+ u16 *parameter, u8 resultLen, u16 *result)
{
#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
#error DRXK register mapping no longer compatible with this routine!
@@ -1306,7 +1339,7 @@ static int scu_command(struct drxk_state *state,
u8 buffer[34];
int cnt = 0, ii;
- for (ii=parameterLen-1; ii >= 0; ii -= 1) {
+ for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
buffer[cnt++] = (parameter[ii] & 0xFF);
buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
}
@@ -1314,16 +1347,17 @@ static int scu_command(struct drxk_state *state,
buffer[cnt++] = ((cmd >> 8) & 0xFF);
WriteBlock(state, SCU_RAM_PARAM_0__A -
- (parameterLen-1), cnt, buffer, 0x00);
+ (parameterLen - 1), cnt, buffer, 0x00);
/* Wait until SCU has processed command */
- end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME);
+ end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
do {
msleep(1);
- CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd));
- } while (! (curCmd == DRX_SCU_READY) &&
- (time_is_after_jiffies(end)));
+ CHK_ERROR(Read16_0
+ (state, SCU_RAM_COMMAND__A, &curCmd));
+ } while (!(curCmd == DRX_SCU_READY)
+ && (time_is_after_jiffies(end)));
if (curCmd != DRX_SCU_READY) {
- printk("SCU not ready\n");
+ printk(KERN_ERR "SCU not ready\n");
mutex_unlock(&state->mutex);
return -1;
}
@@ -1332,39 +1366,37 @@ static int scu_command(struct drxk_state *state,
s16 err;
int ii;
- for(ii=resultLen-1; ii >= 0; ii -= 1) {
+ for (ii = resultLen - 1; ii >= 0; ii -= 1) {
CHK_ERROR(Read16_0(state,
SCU_RAM_PARAM_0__A - ii,
&result[ii]));
}
/* Check if an error was reported by SCU */
- err = (s16)result[0];
+ err = (s16) result[0];
/* check a few fixed error codes */
if (err == SCU_RESULT_UNKSTD) {
- printk("SCU_RESULT_UNKSTD\n");
+ printk(KERN_ERR "SCU_RESULT_UNKSTD\n");
mutex_unlock(&state->mutex);
return -1;
} else if (err == SCU_RESULT_UNKCMD) {
- printk("SCU_RESULT_UNKCMD\n");
+ printk(KERN_ERR "SCU_RESULT_UNKCMD\n");
mutex_unlock(&state->mutex);
return -1;
}
/* here it is assumed that negative means error,
and positive no error */
else if (err < 0) {
- printk("%s ERROR\n", __FUNCTION__);
+ printk(KERN_ERR "%s ERROR\n", __func__);
mutex_unlock(&state->mutex);
return -1;
}
}
- } while(0);
+ } while (0);
mutex_unlock(&state->mutex);
- if (status<0)
- {
- printk("%s: status = %d\n", __FUNCTION__, status);
- }
+ if (status < 0)
+ printk(KERN_ERR "%s: status = %d\n", __func__, status);
return status;
}
@@ -1374,48 +1406,34 @@ static int SetIqmAf(struct drxk_state *state, bool active)
u16 data = 0;
int status;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active));
- //printk("%s\n", __FUNCTION__);
-
- do
- {
+ do {
/* Configure IQM */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));;
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
if (!active) {
data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
| IQM_AF_STDBY_STDBY_AMP_STANDBY
| IQM_AF_STDBY_STDBY_PD_STANDBY
| IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
- | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
- );
- // break;
- //default:
- // break;
- //}
- } else /* active */ {
+ | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
+ } else { /* active */
+
data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
& (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
& (~IQM_AF_STDBY_STDBY_PD_STANDBY)
& (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
& (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
- );
- // break;
- //default:
- // break;
- //}
+ );
}
- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data));
- }while(0);
+ CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
+ } while (0);
return status;
}
-static int CtrlPowerMode(struct drxk_state *state,
- pDRXPowerMode_t mode)
+static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
{
int status = 0;
- u16 sioCcPwdMode = 0;
+ u16 sioCcPwdMode = 0;
- //printk("%s\n", __FUNCTION__);
/* Check arguments */
if (mode == NULL)
return -1;
@@ -1447,12 +1465,11 @@ static int CtrlPowerMode(struct drxk_state *state,
return 0;
/* For next steps make sure to start from DRX_POWER_UP mode */
- if (state->m_currentPowerMode != DRX_POWER_UP)
- {
+ if (state->m_currentPowerMode != DRX_POWER_UP) {
do {
CHK_ERROR(PowerUpDevice(state));
CHK_ERROR(DVBTEnableOFDMTokenRing(state, true));
- } while(0);
+ } while (0);
}
if (*mode == DRX_POWER_UP) {
@@ -1468,7 +1485,7 @@ static int CtrlPowerMode(struct drxk_state *state,
/* stop all comm_exec */
/* Stop and power down previous standard */
do {
- switch (state->m_OperationMode) {
+ switch (state->m_OperationMode) {
case OM_DVBT:
CHK_ERROR(MPEGTSStop(state));
CHK_ERROR(PowerDownDVBT(state, false));
@@ -1487,20 +1504,20 @@ static int CtrlPowerMode(struct drxk_state *state,
CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A,
SIO_CC_UPDATE_KEY));
- if (*mode != DRXK_POWER_DOWN_OFDM) {
+ if (*mode != DRXK_POWER_DOWN_OFDM) {
state->m_HICfgCtrl |=
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
CHK_ERROR(HI_CfgCommand(state));
}
- } while(0);
+ } while (0);
}
state->m_currentPowerMode = *mode;
- return (status);
+ return status;
}
static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
{
- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM;
+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
u16 cmdResult = 0;
u16 data = 0;
int status;
@@ -1510,12 +1527,14 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
if (data == SCU_COMM_EXEC_ACTIVE) {
/* Send OFDM stop command */
CHK_ERROR(scu_command(state,
- SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_STANDARD_OFDM
+ |
SCU_RAM_COMMAND_CMD_DEMOD_STOP,
0, NULL, 1, &cmdResult));
/* Send OFDM reset command */
CHK_ERROR(scu_command(state,
- SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_STANDARD_OFDM
+ |
SCU_RAM_COMMAND_CMD_DEMOD_RESET,
0, NULL, 1, &cmdResult));
}
@@ -1529,44 +1548,45 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
IQM_COMM_EXEC_B_STOP));
/* powerdown AFE */
- CHK_ERROR(SetIqmAf(state,false));
+ CHK_ERROR(SetIqmAf(state, false));
/* powerdown to OFDM mode */
if (setPowerMode) {
- CHK_ERROR(CtrlPowerMode(state,&powerMode));
+ CHK_ERROR(CtrlPowerMode(state, &powerMode));
}
- } while(0);
+ } while (0);
return status;
}
-static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode)
+static int SetOperationMode(struct drxk_state *state,
+ enum OperationMode oMode)
{
int status = 0;
/*
- Stop and power down previous standard
- TODO investigate total power down instead of partial
- power down depending on "previous" standard.
- */
+ Stop and power down previous standard
+ TODO investigate total power down instead of partial
+ power down depending on "previous" standard.
+ */
do {
/* disable HW lock indicator */
- CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A,
- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
+ CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
if (state->m_OperationMode != oMode) {
- switch (state->m_OperationMode) {
- // OM_NONE was added for start up
+ switch (state->m_OperationMode) {
+ /* OM_NONE was added for start up */
case OM_NONE:
break;
case OM_DVBT:
CHK_ERROR(MPEGTSStop(state));
- CHK_ERROR(PowerDownDVBT(state,true));
+ CHK_ERROR(PowerDownDVBT(state, true));
state->m_OperationMode = OM_NONE;
break;
case OM_QAM_ITU_B:
status = -1;
break;
- case OM_QAM_ITU_A: /* fallthrough */
+ case OM_QAM_ITU_A: /* fallthrough */
case OM_QAM_ITU_C:
CHK_ERROR(MPEGTSStop(state));
CHK_ERROR(PowerDownQAM(state));
@@ -1578,10 +1598,9 @@ static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode)
CHK_ERROR(status);
/*
- Power up new standard
- */
- switch (oMode)
- {
+ Power up new standard
+ */
+ switch (oMode) {
case OM_DVBT:
state->m_OperationMode = oMode;
CHK_ERROR(SetDVBTStandard(state, oMode));
@@ -1589,17 +1608,17 @@ static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode)
case OM_QAM_ITU_B:
status = -1;
break;
- case OM_QAM_ITU_A: /* fallthrough */
+ case OM_QAM_ITU_A: /* fallthrough */
case OM_QAM_ITU_C:
state->m_OperationMode = oMode;
- CHK_ERROR(SetQAMStandard(state,oMode));
+ CHK_ERROR(SetQAMStandard(state, oMode));
break;
default:
status = -1;
}
}
CHK_ERROR(status);
- } while(0);
+ } while (0);
return 0;
}
@@ -1610,7 +1629,7 @@ static int Start(struct drxk_state *state, s32 offsetFreq,
do {
u16 IFreqkHz;
- s32 OffsetkHz = offsetFreq / 1000;
+ s32 OffsetkHz = offsetFreq / 1000;
if (state->m_DrxkState != DRXK_STOPPED &&
state->m_DrxkState != DRXK_DTV_STARTED) {
@@ -1618,31 +1637,32 @@ static int Start(struct drxk_state *state, s32 offsetFreq,
break;
}
state->m_bMirrorFreqSpect =
- (state->param.inversion == INVERSION_ON);
+ (state->param.inversion == INVERSION_ON);
if (IntermediateFrequency < 0) {
- state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
+ state->m_bMirrorFreqSpect =
+ !state->m_bMirrorFreqSpect;
IntermediateFrequency = -IntermediateFrequency;
}
- switch(state->m_OperationMode) {
+ switch (state->m_OperationMode) {
case OM_QAM_ITU_A:
case OM_QAM_ITU_C:
IFreqkHz = (IntermediateFrequency / 1000);
- CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz));
+ CHK_ERROR(SetQAM(state, IFreqkHz, OffsetkHz));
state->m_DrxkState = DRXK_DTV_STARTED;
break;
case OM_DVBT:
IFreqkHz = (IntermediateFrequency / 1000);
CHK_ERROR(MPEGTSStop(state));
- CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz));
+ CHK_ERROR(SetDVBT(state, IFreqkHz, OffsetkHz));
CHK_ERROR(DVBTStart(state));
state->m_DrxkState = DRXK_DTV_STARTED;
break;
default:
break;
}
- } while(0);
+ } while (0);
return status;
}
@@ -1652,7 +1672,8 @@ static int ShutDown(struct drxk_state *state)
return 0;
}
-static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time)
+static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
+ u32 Time)
{
int status;
@@ -1685,9 +1706,11 @@ static int MPEGTSStart(struct drxk_state *state)
do {
/* Allow OC to sync again */
- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode));
+ CHK_ERROR(Read16_0
+ (state, FEC_OC_SNC_MODE__A, &fecOcSncMode));
fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_SNC_MODE__A, fecOcSncMode));
CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1));
} while (0);
return status;
@@ -1699,37 +1722,42 @@ static int MPEGTSDtoInit(struct drxk_state *state)
do {
/* Rate integration settings */
- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000));
- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C));
- CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A));
- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008));
- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006));
- CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680));
- CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080));
- CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C));
+ CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A));
+ CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008));
+ CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_TMD_HI_MARGIN__A, 0x0680));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_TMD_LO_MARGIN__A, 0x0080));
+ CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4));
/* Additional configuration */
- CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0));
- CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2));
- CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12));
+ CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0));
+ CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2));
+ CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12));
} while (0);
return status;
}
-static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
+static int MPEGTSDtoSetup(struct drxk_state *state,
+ enum OperationMode oMode)
{
int status = -1;
- u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
- u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
- u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
- u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
+ u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
+ u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
+ u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
+ u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
+ u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
+ u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
+ u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
u16 fecOcTmdMode = 0;
u16 fecOcTmdIntUpdRate = 0;
- u32 maxBitRate = 0;
+ u32 maxBitRate = 0;
bool staticCLK = false;
do {
@@ -1737,15 +1765,15 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode));
CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A,
&fecOcRegIprMode));
- fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
+ fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
if (state->m_insertRSByte == true) {
/* enable parity symbol forward */
- fecOcRegMode |= FEC_OC_MODE_PARITY__M;
+ fecOcRegMode |= FEC_OC_MODE_PARITY__M;
/* MVAL disable during parity bytes */
fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
/* TS burst length to 204 */
- fecOcDtoBurstLen = 204 ;
+ fecOcDtoBurstLen = 204;
}
/* Check serial or parrallel output */
@@ -1762,20 +1790,20 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
fecOcRcnCtlRate = 0xC00000;
staticCLK = state->m_DVBTStaticCLK;
break;
- case OM_QAM_ITU_A: /* fallthrough */
+ case OM_QAM_ITU_A: /* fallthrough */
case OM_QAM_ITU_C:
fecOcTmdMode = 0x0004;
- fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
+ fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
maxBitRate = state->m_DVBCBitrate;
staticCLK = state->m_DVBCStaticCLK;
break;
default:
status = -1;
- } /* switch (standard) */
+ } /* switch (standard) */
CHK_ERROR(status);
/* Configure DTO's */
- if (staticCLK ) {
+ if (staticCLK) {
u32 bitRate = 0;
/* Rational DTO for MCLK source (static MCLK rate),
@@ -1789,8 +1817,7 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
/* Check user defined bitrate */
bitRate = maxBitRate;
- if (bitRate > 75900000UL)
- { /* max is 75.9 Mb/s */
+ if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
bitRate = 75900000UL;
}
/* Rational DTO period:
@@ -1798,7 +1825,7 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
Result should be floored,
to make sure >= requested bitrate
- */
+ */
fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
* 1000) / bitRate);
if (fecOcDtoPeriod <= 2)
@@ -1822,14 +1849,13 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
fecOcDtoMode));
CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A,
fecOcFctMode));
- CHK_ERROR(Write16_0(state, FEC_OC_MODE__A,
- fecOcRegMode));
+ CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, fecOcRegMode));
CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A,
fecOcRegIprMode));
/* Rate integration settings */
CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A,
- fecOcRcnCtlRate ,0));
+ fecOcRcnCtlRate, 0));
CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A,
fecOcTmdIntUpdRate));
CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A,
@@ -1841,14 +1867,14 @@ static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode)
static int MPEGTSConfigurePolarity(struct drxk_state *state)
{
int status;
- u16 fecOcRegIprInvert = 0;
+ u16 fecOcRegIprInvert = 0;
/* Data mask for the output data byte */
u16 InvertDataMask =
- FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
- FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
- FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
- FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
+ FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
+ FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
+ FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
+ FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
/* Control selective inversion of output bits */
fecOcRegIprInvert &= (~(InvertDataMask));
@@ -1866,7 +1892,7 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
if (state->m_invertCLK == true)
fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
- status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
+ status = Write16_0(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
return status;
}
@@ -1885,10 +1911,10 @@ static int SetAgcRf(struct drxk_state *state,
u16 data = 0;
switch (pAgcCfg->ctrlMode) {
- case DRXK_AGC_CTRL_AUTO:
+ case DRXK_AGC_CTRL_AUTO:
/* Enable RF AGC DAC */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
@@ -1962,19 +1988,21 @@ static int SetAgcRf(struct drxk_state *state,
data));
/* SCU c.o.c. to 0, enabling full control range */
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
- 0));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
+ 0));
/* Write value to output pin */
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A,
- pAgcCfg->outputLevel));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_RF_IACCU_HI__A,
+ pAgcCfg->outputLevel));
break;
- case DRXK_AGC_CTRL_OFF:
+ case DRXK_AGC_CTRL_OFF:
/* Disable RF AGC DAC */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data));
+ CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
/* Disable SCU RF AGC loop */
CHK_ERROR(Read16_0(state,
@@ -1987,15 +2015,15 @@ static int SetAgcRf(struct drxk_state *state,
default:
return -1;
- } /* switch (agcsettings->ctrlMode) */
- } while(0);
+ } /* switch (agcsettings->ctrlMode) */
+ } while (0);
return status;
}
#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
-static int SetAgcIf (struct drxk_state *state,
- struct SCfgAgc *pAgcCfg, bool isDTV)
+static int SetAgcIf(struct drxk_state *state,
+ struct SCfgAgc *pAgcCfg, bool isDTV)
{
u16 data = 0;
int status = 0;
@@ -2003,14 +2031,14 @@ static int SetAgcIf (struct drxk_state *state,
do {
switch (pAgcCfg->ctrlMode) {
- case DRXK_AGC_CTRL_AUTO:
+ case DRXK_AGC_CTRL_AUTO:
/* Enable IF AGC DAC */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data));
+ CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A,
+ CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A,
&data));
/* Enable SCU IF AGC loop */
@@ -2032,7 +2060,7 @@ static int SetAgcIf (struct drxk_state *state,
SCU_RAM_AGC_KI_RED_IAGC_RED__B)
& SCU_RAM_AGC_KI_RED_IAGC_RED__M);
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A ,
+ CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A,
data));
if (IsQAM(state))
@@ -2047,12 +2075,12 @@ static int SetAgcIf (struct drxk_state *state,
pRfAgcSettings->top));
break;
- case DRXK_AGC_CTRL_USER:
+ case DRXK_AGC_CTRL_USER:
/* Enable IF AGC DAC */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data));
+ CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
CHK_ERROR(Read16_0(state,
SCU_RAM_AGC_CONFIG__A, &data));
@@ -2074,12 +2102,12 @@ static int SetAgcIf (struct drxk_state *state,
pAgcCfg->outputLevel));
break;
- case DRXK_AGC_CTRL_OFF:
+ case DRXK_AGC_CTRL_OFF:
/* Disable If AGC DAC */
- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data));
data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data));
+ CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data));
/* Disable SCU IF AGC loop */
CHK_ERROR(Read16_0(state,
@@ -2088,15 +2116,15 @@ static int SetAgcIf (struct drxk_state *state,
CHK_ERROR(Write16_0(state,
SCU_RAM_AGC_CONFIG__A, data));
break;
- } /* switch (agcSettingsIf->ctrlMode) */
+ } /* switch (agcSettingsIf->ctrlMode) */
/* always set the top to support
configurations without if-loop */
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
+ CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
pAgcCfg->top));
- } while(0);
+ } while (0);
return status;
}
@@ -2107,34 +2135,36 @@ static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
*pValue = 0;
- if (status==0) {
+ if (status == 0) {
u16 Level = 0;
if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
if (Level < 14000)
- *pValue = (14000 - Level) / 4 ;
+ *pValue = (14000 - Level) / 4;
else
*pValue = 0;
}
return status;
}
-static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
+static int GetQAMSignalToNoise(struct drxk_state *state,
+ s32 *pSignalToNoise)
{
int status = 0;
do {
/* MER calculation */
- u16 qamSlErrPower = 0; /* accum. error between
+ u16 qamSlErrPower = 0; /* accum. error between
raw and sliced symbols */
- u32 qamSlSigPower = 0; /* used for MER, depends of
+ u32 qamSlSigPower = 0; /* used for MER, depends of
QAM constellation */
- u32 qamSlMer = 0; /* QAM MER */
+ u32 qamSlMer = 0; /* QAM MER */
/* get the register value needed for MER */
- CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower));
+ CHK_ERROR(Read16_0
+ (state, QAM_SL_ERR_POWER__A, &qamSlErrPower));
- switch(state->param.u.qam.modulation) {
+ switch (state->param.u.qam.modulation) {
case QAM_16:
qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
break;
@@ -2154,30 +2184,31 @@ static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
}
if (qamSlErrPower > 0) {
- qamSlMer = Log10Times100(qamSlSigPower) -
- Log10Times100((u32) qamSlErrPower);
+ qamSlMer = Log10Times100(qamSlSigPower) -
+ Log10Times100((u32) qamSlErrPower);
}
*pSignalToNoise = qamSlMer;
- } while(0);
+ } while (0);
return status;
}
-static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
+static int GetDVBTSignalToNoise(struct drxk_state *state,
+ s32 *pSignalToNoise)
{
int status = 0;
- u16 regData = 0;
- u32 EqRegTdSqrErrI = 0;
- u32 EqRegTdSqrErrQ = 0;
- u16 EqRegTdSqrErrExp = 0;
- u16 EqRegTdTpsPwrOfs = 0;
- u16 EqRegTdReqSmbCnt = 0;
- u32 tpsCnt = 0;
- u32 SqrErrIQ = 0;
- u32 a = 0;
- u32 b = 0;
- u32 c = 0;
- u32 iMER = 0;
+ u16 regData = 0;
+ u32 EqRegTdSqrErrI = 0;
+ u32 EqRegTdSqrErrQ = 0;
+ u16 EqRegTdSqrErrExp = 0;
+ u16 EqRegTdTpsPwrOfs = 0;
+ u16 EqRegTdReqSmbCnt = 0;
+ u32 tpsCnt = 0;
+ u32 SqrErrIQ = 0;
+ u32 a = 0;
+ u32 b = 0;
+ u32 c = 0;
+ u32 iMER = 0;
u16 transmissionParams = 0;
do {
@@ -2190,20 +2221,20 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
®Data));
/* Extend SQR_ERR_I operational range */
- EqRegTdSqrErrI = (u32) regData;
+ EqRegTdSqrErrI = (u32) regData;
if ((EqRegTdSqrErrExp > 11) &&
(EqRegTdSqrErrI < 0x00000FFFUL)) {
EqRegTdSqrErrI += 0x00010000UL;
}
- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A,
+ CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A,
®Data));
/* Extend SQR_ERR_Q operational range */
- EqRegTdSqrErrQ = (u32)regData;
+ EqRegTdSqrErrQ = (u32) regData;
if ((EqRegTdSqrErrExp > 11) &&
(EqRegTdSqrErrQ < 0x00000FFFUL))
EqRegTdSqrErrQ += 0x00010000UL;
- CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A,
+ CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_OP_PARAM__A,
&transmissionParams));
/* Check input data for MER */
@@ -2218,7 +2249,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
iMER = 0;
} else {
SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
- EqRegTdSqrErrExp;
+ EqRegTdSqrErrExp;
if ((transmissionParams &
OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
== OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
@@ -2234,12 +2265,13 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
c = 100 * log10 (SqrErrIQ)
- */
+ */
/* log(x) x = 9bits * 9bits->18 bits */
- a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs);
+ a = Log10Times100(EqRegTdTpsPwrOfs *
+ EqRegTdTpsPwrOfs);
/* log(x) x = 16bits * 7bits->23 bits */
- b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt);
+ b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
/* log(x) x = (16bits + 16bits) << 15 ->32 bits */
c = Log10Times100(SqrErrIQ);
@@ -2251,7 +2283,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
iMER = 0;
}
*pSignalToNoise = iMER;
- } while(0);
+ } while (0);
return status;
}
@@ -2259,7 +2291,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
{
*pSignalToNoise = 0;
- switch(state->m_OperationMode) {
+ switch (state->m_OperationMode) {
case OM_DVBT:
return GetDVBTSignalToNoise(state, pSignalToNoise);
case OM_QAM_ITU_A:
@@ -2277,24 +2309,23 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
/* SNR Values for quasi errorfree reception rom Nordig 2.2 */
int status = 0;
- static s32 QE_SN[] =
- {
- 51, // QPSK 1/2
- 69, // QPSK 2/3
- 79, // QPSK 3/4
- 89, // QPSK 5/6
- 97, // QPSK 7/8
- 108, // 16-QAM 1/2
- 131, // 16-QAM 2/3
- 146, // 16-QAM 3/4
- 156, // 16-QAM 5/6
- 160, // 16-QAM 7/8
- 165, // 64-QAM 1/2
- 187, // 64-QAM 2/3
- 202, // 64-QAM 3/4
- 216, // 64-QAM 5/6
- 225, // 64-QAM 7/8
- };
+ static s32 QE_SN[] = {
+ 51, /* QPSK 1/2 */
+ 69, /* QPSK 2/3 */
+ 79, /* QPSK 3/4 */
+ 89, /* QPSK 5/6 */
+ 97, /* QPSK 7/8 */
+ 108, /* 16-QAM 1/2 */
+ 131, /* 16-QAM 2/3 */
+ 146, /* 16-QAM 3/4 */
+ 156, /* 16-QAM 5/6 */
+ 160, /* 16-QAM 7/8 */
+ 165, /* 64-QAM 1/2 */
+ 187, /* 64-QAM 2/3 */
+ 202, /* 64-QAM 3/4 */
+ 216, /* 64-QAM 5/6 */
+ 225, /* 64-QAM 7/8 */
+ };
*pQuality = 0;
@@ -2305,12 +2336,12 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
u32 SignalToNoiseRel;
u32 BERQuality;
- CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise));
- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A,
+ CHK_ERROR(GetDVBTSignalToNoise(state, &SignalToNoise));
+ CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
&Constellation));
Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
+ CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
&CodeRate));
CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
@@ -2318,20 +2349,21 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
break;
SignalToNoiseRel = SignalToNoise -
- QE_SN[Constellation * 5 + CodeRate];
+ QE_SN[Constellation * 5 + CodeRate];
BERQuality = 100;
- if (SignalToNoiseRel < -70) *pQuality = 0;
+ if (SignalToNoiseRel < -70)
+ *pQuality = 0;
else if (SignalToNoiseRel < 30)
*pQuality = ((SignalToNoiseRel + 70) *
BERQuality) / 100;
else
*pQuality = BERQuality;
- } while(0);
+ } while (0);
return 0;
};
-static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
+static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
{
int status = 0;
*pQuality = 0;
@@ -2343,13 +2375,13 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise));
- switch(state->param.u.qam.modulation) {
+ switch (state->param.u.qam.modulation) {
case QAM_16:
SignalToNoiseRel = SignalToNoise - 200;
break;
case QAM_32:
SignalToNoiseRel = SignalToNoise - 230;
- break; /* Not in NorDig */
+ break; /* Not in NorDig */
case QAM_64:
SignalToNoiseRel = SignalToNoise - 260;
break;
@@ -2369,17 +2401,17 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
BERQuality) / 100;
else
*pQuality = BERQuality;
- } while(0);
+ } while (0);
return status;
}
static int GetQuality(struct drxk_state *state, s32 *pQuality)
{
- switch(state->m_OperationMode) {
- case OM_DVBT:
+ switch (state->m_OperationMode) {
+ case OM_DVBT:
return GetDVBTQuality(state, pQuality);
- case OM_QAM_ITU_A:
+ case OM_QAM_ITU_A:
return GetDVBCQuality(state, pQuality);
default:
break;
@@ -2422,16 +2454,18 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN));
}
- CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0));
- } while(0);
+ CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0));
+ } while (0);
return status;
}
-static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg)
+static int SetPreSaw(struct drxk_state *state,
+ struct SCfgPreSaw *pPreSawCfg)
{
int status;
- if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M))
+ if ((pPreSawCfg == NULL)
+ || (pPreSawCfg->reference > IQM_AF_PDREF__M))
return -1;
status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
@@ -2439,40 +2473,43 @@ static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg)
}
static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
- u16 romOffset, u16 nrOfElements, u32 timeOut)
+ u16 romOffset, u16 nrOfElements, u32 timeOut)
{
- u16 blStatus = 0;
- u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF);
- u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF);
- int status ;
+ u16 blStatus = 0;
+ u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
+ u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
+ int status;
unsigned long end;
mutex_lock(&state->mutex);
do {
- CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT));
+ CHK_ERROR(Write16_0
+ (state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT));
CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank));
CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset));
CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset));
- CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements));
- CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON));
+ CHK_ERROR(Write16_0
+ (state, SIO_BL_SRC_LEN__A, nrOfElements));
+ CHK_ERROR(Write16_0
+ (state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON));
- end=jiffies+msecs_to_jiffies(timeOut);
+ end = jiffies + msecs_to_jiffies(timeOut);
do {
- CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus));
- } while ((blStatus == 0x1) &&
- time_is_after_jiffies(end));
+ CHK_ERROR(Read16_0
+ (state, SIO_BL_STATUS__A, &blStatus));
+ } while ((blStatus == 0x1) && time_is_after_jiffies(end));
if (blStatus == 0x1) {
- printk("SIO not ready\n");
+ printk(KERN_ERR "SIO not ready\n");
mutex_unlock(&state->mutex);
return -1;
}
- } while(0);
+ } while (0);
mutex_unlock(&state->mutex);
return status;
}
-static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
+static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
{
u16 data = 0;
int status;
@@ -2481,19 +2518,19 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
/* Start measurement */
CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A,
IQM_AF_COMM_EXEC_ACTIVE));
- CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 1));
*count = 0;
- CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data));
+ CHK_ERROR(Read16_0(state, IQM_AF_PHASE0__A, &data));
if (data == 127)
- *count = *count+1;
- CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data));
+ *count = *count + 1;
+ CHK_ERROR(Read16_0(state, IQM_AF_PHASE1__A, &data));
if (data == 127)
- *count = *count+1;
- CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data));
+ *count = *count + 1;
+ CHK_ERROR(Read16_0(state, IQM_AF_PHASE2__A, &data));
if (data == 127)
- *count = *count+1;
- } while(0);
+ *count = *count + 1;
+ } while (0);
return status;
}
@@ -2505,22 +2542,24 @@ static int ADCSynchronization(struct drxk_state *state)
do {
CHK_ERROR(ADCSyncMeasurement(state, &count));
- if (count==1) {
+ if (count == 1) {
/* Try sampling on a diffrent edge */
u16 clkNeg = 0;
- CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg));
- if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
+ CHK_ERROR(Read16_0
+ (state, IQM_AF_CLKNEG__A, &clkNeg));
+ if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
clkNeg |=
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
+ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
} else {
clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
clkNeg |=
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
+ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
}
- CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg));
+ CHK_ERROR(Write16_0
+ (state, IQM_AF_CLKNEG__A, clkNeg));
CHK_ERROR(ADCSyncMeasurement(state, &count));
}
@@ -2532,41 +2571,40 @@ static int ADCSynchronization(struct drxk_state *state)
static int SetFrequencyShifter(struct drxk_state *state,
u16 intermediateFreqkHz,
- s32 tunerFreqOffset,
- bool isDTV)
+ s32 tunerFreqOffset, bool isDTV)
{
bool selectPosImage = false;
- u32 rfFreqResidual = tunerFreqOffset;
+ u32 rfFreqResidual = tunerFreqOffset;
u32 fmFrequencyShift = 0;
bool tunerMirror = !state->m_bMirrorFreqSpect;
u32 adcFreq;
bool adcFlip;
int status;
u32 ifFreqActual;
- u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3);
+ u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
u32 frequencyShift;
bool imageToSelect;
/*
- Program frequency shifter
- No need to account for mirroring on RF
- */
+ Program frequency shifter
+ No need to account for mirroring on RF
+ */
if (isDTV) {
if ((state->m_OperationMode == OM_QAM_ITU_A) ||
(state->m_OperationMode == OM_QAM_ITU_C) ||
(state->m_OperationMode == OM_DVBT))
- selectPosImage = true;
- else
- selectPosImage = false;
+ selectPosImage = true;
+ else
+ selectPosImage = false;
}
if (tunerMirror)
/* tuner doesn't mirror */
ifFreqActual = intermediateFreqkHz +
- rfFreqResidual + fmFrequencyShift;
+ rfFreqResidual + fmFrequencyShift;
else
/* tuner mirrors */
ifFreqActual = intermediateFreqkHz -
- rfFreqResidual - fmFrequencyShift;
+ rfFreqResidual - fmFrequencyShift;
if (ifFreqActual > samplingFrequency / 2) {
/* adc mirrors */
adcFreq = samplingFrequency - ifFreqActual;
@@ -2579,77 +2617,79 @@ static int SetFrequencyShifter(struct drxk_state *state,
frequencyShift = adcFreq;
imageToSelect = state->m_rfmirror ^ tunerMirror ^
- adcFlip ^ selectPosImage;
- state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency);
+ adcFlip ^ selectPosImage;
+ state->m_IqmFsRateOfs =
+ Frac28a((frequencyShift), samplingFrequency);
if (imageToSelect)
state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
/* Program frequency shifter with tuner offset compensation */
/* frequencyShift += tunerFreqOffset; TODO */
- status = Write32(state, IQM_FS_RATE_OFS_LO__A ,
+ status = Write32(state, IQM_FS_RATE_OFS_LO__A,
state->m_IqmFsRateOfs, 0);
return status;
}
static int InitAGC(struct drxk_state *state, bool isDTV)
{
- u16 ingainTgt = 0;
- u16 ingainTgtMin = 0;
- u16 ingainTgtMax = 0;
- u16 clpCyclen = 0;
- u16 clpSumMin = 0;
- u16 clpDirTo = 0;
- u16 snsSumMin = 0;
- u16 snsSumMax = 0;
- u16 clpSumMax = 0;
- u16 snsDirTo = 0;
- u16 kiInnergainMin = 0;
- u16 ifIaccuHiTgt = 0;
+ u16 ingainTgt = 0;
+ u16 ingainTgtMin = 0;
+ u16 ingainTgtMax = 0;
+ u16 clpCyclen = 0;
+ u16 clpSumMin = 0;
+ u16 clpDirTo = 0;
+ u16 snsSumMin = 0;
+ u16 snsSumMax = 0;
+ u16 clpSumMax = 0;
+ u16 snsDirTo = 0;
+ u16 kiInnergainMin = 0;
+ u16 ifIaccuHiTgt = 0;
u16 ifIaccuHiTgtMin = 0;
u16 ifIaccuHiTgtMax = 0;
- u16 data = 0;
- u16 fastClpCtrlDelay = 0;
- u16 clpCtrlMode = 0;
+ u16 data = 0;
+ u16 fastClpCtrlDelay = 0;
+ u16 clpCtrlMode = 0;
int status = 0;
do {
/* Common settings */
- snsSumMax = 1023;
+ snsSumMax = 1023;
ifIaccuHiTgtMin = 2047;
- clpCyclen = 500;
- clpSumMax = 1023;
+ clpCyclen = 500;
+ clpSumMax = 1023;
if (IsQAM(state)) {
/* Standard specific settings */
- clpSumMin = 8;
- clpDirTo = (u16) - 9;
- clpCtrlMode = 0;
- snsSumMin = 8;
- snsDirTo = (u16) - 9;
- kiInnergainMin = (u16) - 1030;
+ clpSumMin = 8;
+ clpDirTo = (u16) -9;
+ clpCtrlMode = 0;
+ snsSumMin = 8;
+ snsDirTo = (u16) -9;
+ kiInnergainMin = (u16) -1030;
} else
status = -1;
CHK_ERROR((status));
if (IsQAM(state)) {
- ifIaccuHiTgtMax = 0x2380;
- ifIaccuHiTgt = 0x2380;
- ingainTgtMin = 0x0511;
- ingainTgt = 0x0511;
- ingainTgtMax = 5119;
+ ifIaccuHiTgtMax = 0x2380;
+ ifIaccuHiTgt = 0x2380;
+ ingainTgtMin = 0x0511;
+ ingainTgt = 0x0511;
+ ingainTgtMax = 5119;
fastClpCtrlDelay =
- state->m_qamIfAgcCfg.FastClipCtrlDelay;
+ state->m_qamIfAgcCfg.FastClipCtrlDelay;
} else {
- ifIaccuHiTgtMax = 0x1200;
- ifIaccuHiTgt = 0x1200;
- ingainTgtMin = 13424;
- ingainTgt = 13424;
- ingainTgtMax = 30000;
+ ifIaccuHiTgtMax = 0x1200;
+ ifIaccuHiTgt = 0x1200;
+ ingainTgtMin = 13424;
+ ingainTgt = 13424;
+ ingainTgtMax = 30000;
fastClpCtrlDelay =
- state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
+ state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
}
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
- fastClpCtrlDelay));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
+ fastClpCtrlDelay));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A,
clpCtrlMode));
@@ -2659,10 +2699,12 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
ingainTgtMin));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
ingainTgtMax));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
- ifIaccuHiTgtMin));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
- ifIaccuHiTgtMax));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
+ ifIaccuHiTgtMin));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
+ ifIaccuHiTgtMax));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0));
@@ -2683,8 +2725,8 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
1023));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A,
(u16) -1023));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A,
- 50));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A,
20));
@@ -2696,8 +2738,10 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
clpDirTo));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A,
snsDirTo));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0));
@@ -2708,7 +2752,8 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_AGC_SNS_CYCLEN__A, 500));
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500));
/* Initialize inner-loop KI gain factors */
@@ -2721,11 +2766,11 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
}
CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data));
- } while(0);
+ } while (0);
return status;
}
-static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr)
+static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
{
int status;
@@ -2748,11 +2793,11 @@ static int DVBTScCommand(struct drxk_state *state,
u16 param0, u16 param1, u16 param2,
u16 param3, u16 param4)
{
- u16 curCmd = 0;
- u16 errCode = 0;
+ u16 curCmd = 0;
+ u16 errCode = 0;
u16 retryCnt = 0;
- u16 scExec = 0;
- int status;
+ u16 scExec = 0;
+ int status;
status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec);
if (scExec != 1) {
@@ -2761,7 +2806,7 @@ static int DVBTScCommand(struct drxk_state *state,
}
/* Wait until sc is ready to receive command */
- retryCnt =0;
+ retryCnt = 0;
do {
msleep(1);
status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
@@ -2775,12 +2820,13 @@ static int DVBTScCommand(struct drxk_state *state,
case OFDM_SC_RA_RAM_CMD_PROC_START:
case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
- status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
+ status =
+ Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
break;
default:
/* Do nothing */
break;
- } /* switch (cmd->cmd) */
+ } /* switch (cmd->cmd) */
/* Write needed parameters and the command */
switch (cmd) {
@@ -2791,11 +2837,13 @@ static int DVBTScCommand(struct drxk_state *state,
case OFDM_SC_RA_RAM_CMD_PROC_START:
case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
+ status =
+ Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
/* All commands using 1 parameters */
case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
case OFDM_SC_RA_RAM_CMD_USER_IO:
- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
+ status =
+ Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
/* All commands using 0 parameters */
case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
case OFDM_SC_RA_RAM_CMD_NULL:
@@ -2805,22 +2853,21 @@ static int DVBTScCommand(struct drxk_state *state,
default:
/* Unknown command */
return -EINVAL;
- } /* switch (cmd->cmd) */
+ } /* switch (cmd->cmd) */
/* Wait until sc is ready processing command */
retryCnt = 0;
- do{
+ do {
msleep(1);
status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
retryCnt++;
- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
+ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
if (retryCnt >= DRXK_MAX_RETRIES)
return -1;
/* Check for illegal cmd */
status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
- if (errCode == 0xFFFF)
- {
+ if (errCode == 0xFFFF) {
/* illegal command */
return -EINVAL;
}
@@ -2834,7 +2881,8 @@ static int DVBTScCommand(struct drxk_state *state,
/* All commands yielding 1 result */
case OFDM_SC_RA_RAM_CMD_USER_IO:
case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
- status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
+ status =
+ Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
/* All commands yielding 0 results */
case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
case OFDM_SC_RA_RAM_CMD_SET_TIMER:
@@ -2847,13 +2895,13 @@ static int DVBTScCommand(struct drxk_state *state,
/* Unknown command */
return -EINVAL;
break;
- } /* switch (cmd->cmd) */
+ } /* switch (cmd->cmd) */
return status;
}
-static int PowerUpDVBT (struct drxk_state *state)
+static int PowerUpDVBT(struct drxk_state *state)
{
- DRXPowerMode_t powerMode = DRX_POWER_UP;
+ enum DRXPowerMode powerMode = DRX_POWER_UP;
int status;
do {
@@ -2862,92 +2910,75 @@ static int PowerUpDVBT (struct drxk_state *state)
return status;
}
-static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled)
+static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
{
- int status;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- if (*enabled == true)
- {
- status = Write16_0(state, IQM_CF_BYPASSDET__A, 0);
- }
- else
- {
- status = Write16_0(state, IQM_CF_BYPASSDET__A, 1);
- }
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
-
- return status;
+ int status;
+
+ if (*enabled == true)
+ status = Write16_0(state, IQM_CF_BYPASSDET__A, 0);
+ else
+ status = Write16_0(state, IQM_CF_BYPASSDET__A, 1);
+
+ return status;
}
- #define DEFAULT_FR_THRES_8K 4000
-static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled)
+
+#define DEFAULT_FR_THRES_8K 4000
+static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
{
- int status;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
-
- if (*enabled == true)
- {
- /* write mask to 1 */
- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
- DEFAULT_FR_THRES_8K);
- }
- else
- {
- /* write mask to 0 */
- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
- }
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
-
- return status;
+ int status;
+
+ if (*enabled == true) {
+ /* write mask to 1 */
+ status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
+ DEFAULT_FR_THRES_8K);
+ } else {
+ /* write mask to 0 */
+ status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
+ }
+
+ return status;
}
-static int DVBTCtrlSetEchoThreshold (struct drxk_state *state,
- struct DRXKCfgDvbtEchoThres_t* echoThres)
+static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
+ struct DRXKCfgDvbtEchoThres_t *echoThres)
{
- u16 data = 0;
+ u16 data = 0;
int status;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
do {
- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data));
-
- switch (echoThres->fftMode)
- {
- case DRX_FFTMODE_2K:
- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) &
- (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
- break;
- case DRX_FFTMODE_8K:
- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) &
- (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
- break;
- default:
- return -1;
- break;
- }
-
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data));
- } while (0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status));
- }
-
- return status;
+ CHK_ERROR(Read16_0
+ (state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data));
+
+ switch (echoThres->fftMode) {
+ case DRX_FFTMODE_2K:
+ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
+ data |=
+ ((echoThres->threshold <<
+ OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
+ & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
+ break;
+ case DRX_FFTMODE_8K:
+ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
+ data |=
+ ((echoThres->threshold <<
+ OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
+ & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_RA_RAM_ECHO_THRES__A, data));
+ } while (0);
+
+ return status;
}
static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
- enum DRXKCfgDvbtSqiSpeed* speed)
+ enum DRXKCfgDvbtSqiSpeed *speed)
{
int status;
@@ -2959,8 +2990,8 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
default:
return -EINVAL;
}
- status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
- (u16) *speed);
+ status = Write16_0(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
+ (u16) *speed);
return status;
}
@@ -2974,33 +3005,27 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
* Called in DVBTSetStandard
*
*/
-static int DVBTActivatePresets (struct drxk_state *state)
+static int DVBTActivatePresets(struct drxk_state *state)
{
- int status;
-
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
-
- struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K};
- struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K};
-
- do {
- bool setincenable = false;
- bool setfrenable = true;
- CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable));
- CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable));
- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k));
- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k));
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
- state->m_dvbtIfAgcCfg.IngainTgtMax));
- } while (0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
-
- return status;
+ int status;
+
+ struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
+ struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
+
+ do {
+ bool setincenable = false;
+ bool setfrenable = true;
+ CHK_ERROR(DVBTCtrlSetIncEnable(state, &setincenable));
+ CHK_ERROR(DVBTCtrlSetFrEnable(state, &setfrenable));
+ CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k));
+ CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k));
+ CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
+ state->m_dvbtIfAgcCfg.IngainTgtMax));
+ } while (0);
+
+ return status;
}
+
/*============================================================================*/
/**
@@ -3011,13 +3036,12 @@ static int DVBTActivatePresets (struct drxk_state *state)
* For ROM code channel filter taps are loaded from the bootloader. For microcode
* the DVB-T taps from the drxk_filters.h are used.
*/
-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode)
+static int SetDVBTStandard(struct drxk_state *state,
+ enum OperationMode oMode)
{
- u16 cmdResult = 0;
- u16 data = 0;
- int status;
-
- //printk("%s\n", __FUNCTION__);
+ u16 cmdResult = 0;
+ u16 data = 0;
+ int status;
PowerUpDVBT(state);
@@ -3025,108 +3049,133 @@ static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode)
/* added antenna switch */
SwitchAntennaToDVBT(state);
/* send OFDM reset command */
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1,
+ &cmdResult));
/* send OFDM setenv command */
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1,
+ &cmdResult));
/* reset datapath for OFDM, processors first */
- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP));
- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP));
- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP ));
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_COMM_EXEC__A,
+ OFDM_SC_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, OFDM_LC_COMM_EXEC__A,
+ OFDM_LC_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP));
/* IQM setup */
/* synchronize on ofdstate->m_festart */
- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1));
/* window size for clipping ADC detection */
- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0));
/* window size for for sense pre-SAW detection */
- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0));
/* sense threshold for sense pre-SAW detection */
- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC));
- CHK_ERROR(SetIqmAf(state,true));
+ CHK_ERROR(Write16_0
+ (state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC));
+ CHK_ERROR(SetIqmAf(state, true));
- CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0));
/* Impulse noise cruncher setup */
- CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */
- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */
- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */
+ CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */
+ CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */
+ CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */
- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16));
- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */
- CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */
- CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600));
- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16));
+ CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */
+ CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */
+ CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600));
+ CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0));
/* virtual clipping threshold for clipping ADC detection */
- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448));
- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */
+ CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448));
+ CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */
CHK_ERROR(BLChainCmd(state,
- DRXK_BL_ROM_OFFSET_TAPS_DVBT,
- DRXK_BLCC_NR_ELEMENTS_TAPS,
- DRXK_BLC_TIMEOUT));
+ DRXK_BL_ROM_OFFSET_TAPS_DVBT,
+ DRXK_BLCC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT));
- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */
+ CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */
CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2));
/* enable power measurement interrupt */
CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1));
- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, IQM_COMM_EXEC__A,
+ IQM_COMM_EXEC_B_ACTIVE));
/* IQM will not be reset from here, sync ADC and update/init AGC */
CHK_ERROR(ADCSynchronization(state));
CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg));
/* Halt SCU to enable safe non-atomic accesses */
- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
- CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ;
- CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true));
+ CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true));
+ CHK_ERROR(SetAgcIf(state, &state->m_dvbtIfAgcCfg, true));
/* Set Noise Estimation notch width and enable DC fix */
- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data));
+ CHK_ERROR(Read16_0
+ (state, OFDM_SC_RA_RAM_CONFIG__A, &data));
data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data));
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_RA_RAM_CONFIG__A, data));
/* Activate SCU to enable SCU commands */
- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
- if (!state->m_DRXK_A3_ROM_CODE)
- {
+ if (!state->m_DRXK_A3_ROM_CODE) {
/* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
- state->m_dvbtIfAgcCfg.FastClipCtrlDelay));
+ CHK_ERROR(Write16_0
+ (state,
+ SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
+ state->
+ m_dvbtIfAgcCfg.FastClipCtrlDelay));
}
/* OFDM_SC setup */
#ifdef COMPILE_FOR_NONRT
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2));
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1));
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2));
#endif
/* FEC setup */
- CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */
+ CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */
#ifdef COMPILE_FOR_NONRT
- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400));
#else
- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000));
#endif
- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001));
/* Setup MPEG bus */
- CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT));
+ CHK_ERROR(MPEGTSDtoSetup(state, OM_DVBT));
/* Set DVBT Presets */
- CHK_ERROR (DVBTActivatePresets (state));
+ CHK_ERROR(DVBTActivatePresets(state));
} while (0);
- if (status<0)
- {
- printk("%s status - %08x\n",__FUNCTION__,status);
- }
+ if (status < 0)
+ printk(KERN_ERR "%s status - %08x\n", __func__, status);
return status;
}
@@ -3139,22 +3188,24 @@ static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode)
*/
static int DVBTStart(struct drxk_state *state)
{
- u16 param1;
-
- int status;
-// DRXKOfdmScCmd_t scCmd;
-
- //printk("%s\n",__FUNCTION__);
- /* Start correct processes to get in lock */
- /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
- do {
- param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
- CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0));
- /* Start FEC OC */
- CHK_ERROR(MPEGTSStart(state));
- CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE));
- } while (0);
- return (status);
+ u16 param1;
+ int status;
+ /* DRXKOfdmScCmd_t scCmd; */
+
+ /* Start correct processes to get in lock */
+ /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
+ do {
+ param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
+ CHK_ERROR(DVBTScCommand
+ (state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
+ OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0,
+ 0, 0));
+ /* Start FEC OC */
+ CHK_ERROR(MPEGTSStart(state));
+ CHK_ERROR(Write16_0
+ (state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE));
+ } while (0);
+ return status;
}
@@ -3166,149 +3217,182 @@ static int DVBTStart(struct drxk_state *state)
* \return DRXStatus_t.
* // original DVBTSetChannel()
*/
-static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset)
+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
+ s32 tunerFreqOffset)
{
- u16 cmdResult = 0;
- u16 transmissionParams = 0;
- u16 operationMode = 0;
- u32 iqmRcRateOfs = 0;
- u32 bandwidth = 0;
- u16 param1;
+ u16 cmdResult = 0;
+ u16 transmissionParams = 0;
+ u16 operationMode = 0;
+ u32 iqmRcRateOfs = 0;
+ u32 bandwidth = 0;
+ u16 param1;
int status;
- //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset);
+ /* printk(KERN_DEBUG "%s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */
do {
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM |
- SCU_RAM_COMMAND_CMD_DEMOD_STOP,
- 0,NULL,1,&cmdResult));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1,
+ &cmdResult));
/* Halt SCU to enable safe non-atomic accesses */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
/* Stop processors */
- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP));
- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, OFDM_SC_COMM_EXEC__A,
+ OFDM_SC_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, OFDM_LC_COMM_EXEC__A,
+ OFDM_LC_COMM_EXEC_STOP));
/* Mandatory fix, always stop CP, required to set spl offset back to
hardware default (is set to 0 by ucode during pilot detection */
- CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, OFDM_CP_COMM_EXEC__A,
+ OFDM_CP_COMM_EXEC_STOP));
/*== Write channel settings to device =====================================*/
/* mode */
- switch(state->param.u.ofdm.transmission_mode) {
+ switch (state->param.u.ofdm.transmission_mode) {
case TRANSMISSION_MODE_AUTO:
default:
operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
/* fall through , try first guess DRX_FFTMODE_8K */
case TRANSMISSION_MODE_8K:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
break;
case TRANSMISSION_MODE_2K:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
break;
}
/* guard */
- switch(state->param.u.ofdm.guard_interval) {
+ switch (state->param.u.ofdm.guard_interval) {
default:
case GUARD_INTERVAL_AUTO:
operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
/* fall through , try first guess DRX_GUARD_1DIV4 */
case GUARD_INTERVAL_1_4:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
break;
case GUARD_INTERVAL_1_32:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
break;
case GUARD_INTERVAL_1_16:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
break;
case GUARD_INTERVAL_1_8:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
break;
}
/* hierarchy */
- switch(state->param.u.ofdm.hierarchy_information) {
+ switch (state->param.u.ofdm.hierarchy_information) {
case HIERARCHY_AUTO:
- case HIERARCHY_NONE:
+ case HIERARCHY_NONE:
default:
operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
/* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
- // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO;
- //break;
- case HIERARCHY_1:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
+ /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
+ /* break; */
+ case HIERARCHY_1:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
break;
- case HIERARCHY_2:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
+ case HIERARCHY_2:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
break;
- case HIERARCHY_4:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
+ case HIERARCHY_4:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
break;
}
/* constellation */
- switch(state->param.u.ofdm.constellation) {
+ switch (state->param.u.ofdm.constellation) {
case QAM_AUTO:
default:
operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
/* fall through , try first guess DRX_CONSTELLATION_QAM64 */
case QAM_64:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
break;
case QPSK:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
break;
case QAM_16:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
break;
}
#if 0
- // No hierachical channels support in BDA
- /* Priority (only for hierarchical channels) */
- switch (channel->priority) {
- case DRX_PRIORITY_LOW :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO);
- break;
- case DRX_PRIORITY_HIGH :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI));
- break;
- case DRX_PRIORITY_UNKNOWN : /* fall through */
- default:
- return (DRX_STS_INVALID_ARG);
- break;
- }
+ /* No hierachical channels support in BDA */
+ /* Priority (only for hierarchical channels) */
+ switch (channel->priority) {
+ case DRX_PRIORITY_LOW:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
+ WR16(devAddr, OFDM_EC_SB_PRIOR__A,
+ OFDM_EC_SB_PRIOR_LO);
+ break;
+ case DRX_PRIORITY_HIGH:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
+ WR16(devAddr, OFDM_EC_SB_PRIOR__A,
+ OFDM_EC_SB_PRIOR_HI));
+ break;
+ case DRX_PRIORITY_UNKNOWN: /* fall through */
+ default:
+ return DRX_STS_INVALID_ARG;
+ break;
+ }
#else
- // Set Priorty high
+ /* Set Priorty high */
transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
- CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI));
+ CHK_ERROR(Write16_0
+ (state, OFDM_EC_SB_PRIOR__A,
+ OFDM_EC_SB_PRIOR_HI));
#endif
/* coderate */
- switch(state->param.u.ofdm.code_rate_HP) {
+ switch (state->param.u.ofdm.code_rate_HP) {
case FEC_AUTO:
default:
operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
/* fall through , try first guess DRX_CODERATE_2DIV3 */
- case FEC_2_3 :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
+ case FEC_2_3:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
break;
- case FEC_1_2 :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
+ case FEC_1_2:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
break;
- case FEC_3_4 :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
+ case FEC_3_4:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
break;
- case FEC_5_6 :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
+ case FEC_5_6:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
break;
- case FEC_7_8 :
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
+ case FEC_7_8:
+ transmissionParams |=
+ OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
break;
}
@@ -3319,95 +3403,147 @@ static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerF
/* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
functions */
- switch(state->param.u.ofdm.bandwidth) {
+ switch (state->param.u.ofdm.bandwidth) {
case BANDWIDTH_AUTO:
case BANDWIDTH_8_MHZ:
bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 3052));
/* cochannel protection for PAL 8 MHz */
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 7));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 7));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 7));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1));
break;
case BANDWIDTH_7_MHZ:
bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 3491));
/* cochannel protection for PAL 7 MHz */
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 8));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 8));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 4));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1));
break;
case BANDWIDTH_6_MHZ:
bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 4073));
/* cochannel protection for NTSC 6 MHz */
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14));
- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 19));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 19));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 14));
+ CHK_ERROR(Write16_0
+ (state,
+ OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1));
break;
}
- if (iqmRcRateOfs == 0)
- {
+ if (iqmRcRateOfs == 0) {
/* Now compute IQM_RC_RATE_OFS
(((SysFreq/BandWidth)/2)/2) -1) * 2^23)
=>
((SysFreq / BandWidth) * (2^21)) - (2^23)
- */
+ */
/* (SysFreq / BandWidth) * (2^28) */
/* assert (MAX(sysClk)/MIN(bandwidth) < 16)
=> assert(MAX(sysClk) < 16*MIN(bandwidth))
=> assert(109714272 > 48000000) = true so Frac 28 can be used */
- iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth);
+ iqmRcRateOfs = Frac28a((u32)
+ ((state->m_sysClockFreq *
+ 1000) / 3), bandwidth);
/* (SysFreq / BandWidth) * (2^21), rounding before truncating */
if ((iqmRcRateOfs & 0x7fL) >= 0x40)
- {
iqmRcRateOfs += 0x80L;
- }
- iqmRcRateOfs = iqmRcRateOfs >> 7 ;
+ iqmRcRateOfs = iqmRcRateOfs >> 7;
/* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
- iqmRcRateOfs = iqmRcRateOfs - (1<<23);
+ iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
}
- iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<<IQM_RC_RATE_OFS_LO__W) |
- IQM_RC_RATE_OFS_LO__M);
- CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs,0));
+ iqmRcRateOfs &=
+ ((((u32) IQM_RC_RATE_OFS_HI__M) <<
+ IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
+ CHK_ERROR(Write32
+ (state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs, 0));
/* Bandwidth setting done */
- // CHK_ERROR(DVBTSetFrequencyShift(demod, channel, tunerOffset));
- CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true));
+ /* CHK_ERROR(DVBTSetFrequencyShift(demod, channel, tunerOffset)); */
+ CHK_ERROR(SetFrequencyShifter
+ (state, IntermediateFreqkHz, tunerFreqOffset,
+ true));
/*== Start SC, write channel settings to SC ===============================*/
/* Activate SCU to enable SCU commands */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
/* Enable SC after setting all other parameters */
- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_STATE__A, 0));
- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, 1));
+ CHK_ERROR(Write16_0(state, OFDM_SC_COMM_STATE__A, 0));
+ CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, 1));
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM |
- SCU_RAM_COMMAND_CMD_DEMOD_START,0,NULL,1,&cmdResult));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_OFDM |
+ SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1,
+ &cmdResult));
/* Write SC parameter registers, set all AUTO flags in operation mode */
- param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
- OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
- OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
- OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
- OFDM_SC_RA_RAM_OP_AUTO_RATE__M );
- status = DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,0,transmissionParams,param1,0,0,0);
+ param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
+ OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
+ OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
+ OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
+ OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
+ status =
+ DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
+ 0, transmissionParams, param1, 0, 0, 0);
if (!state->m_DRXK_A3_ROM_CODE)
- CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed));
+ CHK_ERROR(DVBTCtrlSetSqiSpeed
+ (state, &state->m_sqiSpeed));
- } while(0);
- if (status<0) {
- //printk("%s status - %08x\n",__FUNCTION__,status);
- }
+ } while (0);
return status;
}
@@ -3424,104 +3560,85 @@ static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerF
*/
static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
{
- int status;
- const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
- OFDM_SC_RA_RAM_LOCK_FEC__M );
- const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
- const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ;
-
- u16 ScRaRamLock = 0;
- u16 ScCommExec = 0;
-
- /* driver 0.9.0 */
- /* Check if SC is running */
- status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
- if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
- {
- /* SC not active; return DRX_NOT_LOCKED */
- *pLockStatus = NOT_LOCKED;
- return status;
- }
-
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
-
- status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
-
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock));
-
- if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
- *pLockStatus = MPEG_LOCK;
- } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) {
- *pLockStatus = FEC_LOCK;
- } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) {
- *pLockStatus = DEMOD_LOCK;
- } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) {
- *pLockStatus = NEVER_LOCK;
- } else {
- *pLockStatus = NOT_LOCKED;
- }
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
-
- return status;
+ int status;
+ const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
+ OFDM_SC_RA_RAM_LOCK_FEC__M);
+ const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
+ const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
+
+ u16 ScRaRamLock = 0;
+ u16 ScCommExec = 0;
+
+ /* driver 0.9.0 */
+ /* Check if SC is running */
+ status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
+ if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) {
+ /* SC not active; return DRX_NOT_LOCKED */
+ *pLockStatus = NOT_LOCKED;
+ return status;
+ }
+
+ status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
+
+ if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
+ *pLockStatus = MPEG_LOCK;
+ else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
+ *pLockStatus = FEC_LOCK;
+ else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
+ *pLockStatus = DEMOD_LOCK;
+ else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
+ *pLockStatus = NEVER_LOCK;
+ else
+ *pLockStatus = NOT_LOCKED;
+
+ return status;
}
-static int PowerUpQAM (struct drxk_state *state)
+static int PowerUpQAM(struct drxk_state *state)
{
- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM;
-
+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
+ int status = 0;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- CHK_ERROR(CtrlPowerMode(state, &powerMode));
+ do {
+ CHK_ERROR(CtrlPowerMode(state, &powerMode));
- }while(0);
+ } while (0);
- if (status<0)
- {
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ return status;
}
-/// Power Down QAM
+/** Power Down QAM */
static int PowerDownQAM(struct drxk_state *state)
{
- u16 data = 0;
- u16 cmdResult;
-
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data));
- if (data == SCU_COMM_EXEC_ACTIVE)
- {
- /*
- STOP demodulator
- QAM and HW blocks
- */
- /* stop all comstate->m_exec */
- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP));
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult));
- }
- /* powerdown AFE */
- CHK_ERROR(SetIqmAf(state, false));
- }
- while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ u16 data = 0;
+ u16 cmdResult;
+ int status = 0;
+
+ do {
+ CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data));
+ if (data == SCU_COMM_EXEC_ACTIVE) {
+ /*
+ STOP demodulator
+ QAM and HW blocks
+ */
+ /* stop all comstate->m_exec */
+ CHK_ERROR(Write16_0
+ (state, QAM_COMM_EXEC__A,
+ QAM_COMM_EXEC_STOP));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_QAM |
+ SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL,
+ 1, &cmdResult));
+ }
+ /* powerdown AFE */
+ CHK_ERROR(SetIqmAf(state, false));
+ } while (0);
+
+ return status;
}
+
/*============================================================================*/
/**
@@ -3539,15 +3656,13 @@ static int SetQAMMeasurement(struct drxk_state *state,
enum EDrxkConstellation constellation,
u32 symbolRate)
{
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode));
-
- u32 fecBitsDesired = 0; /* BER accounting period */
- u32 fecRsPeriodTotal = 0; /* Total period */
- u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
- u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
+ u32 fecBitsDesired = 0; /* BER accounting period */
+ u32 fecRsPeriodTotal = 0; /* Total period */
+ u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
+ u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
int status = 0;
- fecRsPrescale = 1;
+ fecRsPrescale = 1;
do {
@@ -3556,9 +3671,8 @@ static int SetQAMMeasurement(struct drxk_state *state,
(constellation + 1) *
SyncLoss (== 1) *
ViterbiLoss (==1)
- */
- switch (constellation)
- {
+ */
+ switch (constellation) {
case DRX_CONSTELLATION_QAM16:
fecBitsDesired = 4 * symbolRate;
break;
@@ -3579,12 +3693,12 @@ static int SetQAMMeasurement(struct drxk_state *state,
}
CHK_ERROR(status);
- fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
- fecBitsDesired *= 500; /* meas. period [ms] */
+ fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
+ fecBitsDesired *= 500; /* meas. period [ms] */
/* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
/* fecRsPeriodTotal = fecBitsDesired / 1632 */
- fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/
+ fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
/* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
@@ -3593,105 +3707,144 @@ static int SetQAMMeasurement(struct drxk_state *state,
status = -1;
}
CHK_ERROR(status);
- fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) /
- fecRsPrescale;
+ fecRsPeriod =
+ ((u16) fecRsPeriodTotal +
+ (fecRsPrescale >> 1)) / fecRsPrescale;
/* write corresponding registers */
- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod));
- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale));
- CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_MEASUREMENT_PERIOD__A,
+ fecRsPeriod));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_MEASUREMENT_PRESCALE__A,
+ fecRsPrescale));
+ CHK_ERROR(Write16_0
+ (state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod));
} while (0);
- if (status<0) {
- printk("%s: status - %08x\n",__FUNCTION__,status);
- }
+ if (status < 0)
+ printk(KERN_ERR "%s: status - %08x\n", __func__, status);
+
return status;
}
-static int SetQAM16 (struct drxk_state *state)
+static int SetQAM16(struct drxk_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- /* QAM Equalizer Setup */
- /* Equalizer */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517));
- /* Decision Feedback Equalizer */
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
-
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
-
- /* QAM Slicer Settings */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16));
-
- /* QAM Loop Controller Coeficients */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24));
-
-
- /* QAM FSM Tracking Parameters */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127));
- }while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ int status = 0;
+
+ do {
+ /* QAM Equalizer Setup */
+ /* Equalizer */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517));
+ /* Decision Feedback Equalizer */
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
+
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
+
+ /* QAM Slicer Settings */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM16));
+
+ /* QAM Loop Controller Coeficients */
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_COARSE__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_COARSE__A, 32));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
+
+
+ /* QAM State Machine (FSM) Thresholds */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24));
+
+
+ /* QAM FSM Tracking Parameters */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A,
+ (u16) 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A,
+ (u16) 220));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A,
+ (u16) 25));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A,
+ (u16) 6));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A,
+ (u16) -24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A,
+ (u16) -65));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A,
+ (u16) -127));
+ } while (0);
+
+ return status;
}
/*============================================================================*/
@@ -3701,93 +3854,126 @@ static int SetQAM16 (struct drxk_state *state)
* \param demod instance of demod.
* \return DRXStatus_t.
*/
-static int SetQAM32 (struct drxk_state *state)
+static int SetQAM32(struct drxk_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- /* QAM Equalizer Setup */
- /* Equalizer */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707));
-
- /* Decision Feedback Equalizer */
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
-
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
-
- /* QAM Slicer Settings */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32));
-
-
- /* QAM Loop Controller Coeficients */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0));
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10));
-
-
- /* QAM FSM Tracking Parameters */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86));
- }while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ int status = 0;
+
+ do {
+ /* QAM Equalizer Setup */
+ /* Equalizer */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707));
+
+ /* Decision Feedback Equalizer */
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
+
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
+
+ /* QAM Slicer Settings */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM32));
+
+
+ /* QAM Loop Controller Coeficients */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_COARSE__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_COARSE__A, 16));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0));
+
+
+ /* QAM State Machine (FSM) Thresholds */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10));
+
+
+ /* QAM FSM Tracking Parameters */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A,
+ (u16) 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A,
+ (u16) 140));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A,
+ (u16) -8));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A,
+ (u16) -16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A,
+ (u16) -26));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A,
+ (u16) -56));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A,
+ (u16) -86));
+ } while (0);
+
+ return status;
}
/*============================================================================*/
@@ -3797,92 +3983,125 @@ static int SetQAM32 (struct drxk_state *state)
* \param demod instance of demod.
* \return DRXStatus_t.
*/
-static int SetQAM64 (struct drxk_state *state)
+static int SetQAM64(struct drxk_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- /* QAM Equalizer Setup */
- /* Equalizer */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609));
-
- /* Decision Feedback Equalizer */
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
-
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
-
- /* QAM Slicer Settings */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64));
-
-
- /* QAM Loop Controller Coeficients */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15));
-
-
- /* QAM FSM Tracking Parameters */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80));
- }while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ int status = 0;
+
+ do {
+ /* QAM Equalizer Setup */
+ /* Equalizer */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609));
+
+ /* Decision Feedback Equalizer */
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
+
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
+
+ /* QAM Slicer Settings */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM64));
+
+
+ /* QAM Loop Controller Coeficients */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_COARSE__A, 100));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_COARSE__A, 48));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
+
+
+ /* QAM State Machine (FSM) Thresholds */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15));
+
+
+ /* QAM FSM Tracking Parameters */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A,
+ (u16) 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A,
+ (u16) 141));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A,
+ (u16) 7));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A,
+ (u16) 0));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A,
+ (u16) -15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A,
+ (u16) -45));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A,
+ (u16) -80));
+ } while (0);
+
+ return status;
}
/*============================================================================*/
@@ -3894,92 +4113,125 @@ static int SetQAM64 (struct drxk_state *state)
*/
static int SetQAM128(struct drxk_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- /* QAM Equalizer Setup */
- /* Equalizer */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238));
-
- /* Decision Feedback Equalizer */
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
-
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
-
-
- /* QAM Slicer Settings */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128));
-
-
- /* QAM Loop Controller Coeficients */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0));
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12));
-
- /* QAM FSM Tracking Parameters */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23));
- }while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ int status = 0;
+
+ do {
+ /* QAM Equalizer Setup */
+ /* Equalizer */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238));
+
+ /* Decision Feedback Equalizer */
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
+
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
+
+
+ /* QAM Slicer Settings */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM128));
+
+
+ /* QAM Loop Controller Coeficients */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_COARSE__A, 120));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_COARSE__A, 60));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_COARSE__A, 64));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0));
+
+
+ /* QAM State Machine (FSM) Thresholds */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12));
+
+ /* QAM FSM Tracking Parameters */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A,
+ (u16) 8));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A,
+ (u16) 65));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A,
+ (u16) 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A,
+ (u16) 3));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A,
+ (u16) -1));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A,
+ (u16) -12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A,
+ (u16) -23));
+ } while (0);
+
+ return status;
}
/*============================================================================*/
@@ -3991,91 +4243,124 @@ static int SetQAM128(struct drxk_state *state)
*/
static int SetQAM256(struct drxk_state *state)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
- int status = 0;
- do
- {
- /* QAM Equalizer Setup */
- /* Equalizer */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385));
-
- /* Decision Feedback Equalizer */
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6));
- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
-
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
-
- /* QAM Slicer Settings */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256));
-
-
- /* QAM Loop Controller Coeficients */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110));
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12));
-
-
- /* QAM FSM Tracking Parameters */
-
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0));
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8));
- }while(0);
-
- if (status<0)
- {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
- }
- return status;
+ int status = 0;
+
+ do {
+ /* QAM Equalizer Setup */
+ /* Equalizer */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385));
+
+ /* Decision Feedback Equalizer */
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6));
+ CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0));
+
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3));
+
+ /* QAM Slicer Settings */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM256));
+
+
+ /* QAM Loop Controller Coeficients */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16));
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CP_COARSE__A, 250));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CI_COARSE__A, 125));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF_COARSE__A, 48));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10));
+
+
+ /* QAM State Machine (FSM) Thresholds */
+
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150));
+ CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110));
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12));
+
+
+ /* QAM FSM Tracking Parameters */
+
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A,
+ (u16) 8));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A,
+ (u16) 74));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A,
+ (u16) 18));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A,
+ (u16) 13));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A,
+ (u16) 7));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A,
+ (u16) 0));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A,
+ (u16) -8));
+ } while (0);
+
+ return status;
}
@@ -4088,20 +4373,23 @@ static int SetQAM256(struct drxk_state *state)
*/
static int QAMResetQAM(struct drxk_state *state)
{
- int status;
- u16 cmdResult;
-
- //printk("%s\n", __FUNCTION__);
- do
- {
- /* Stop QAM comstate->m_exec */
- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP));
+ int status;
+ u16 cmdResult;
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult));
- } while (0);
+ do {
+ /* Stop QAM comstate->m_exec */
+ CHK_ERROR(Write16_0
+ (state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP));
+
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_QAM |
+ SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1,
+ &cmdResult));
+ } while (0);
- /* All done, all OK */
- return status;
+ /* All done, all OK */
+ return status;
}
/*============================================================================*/
@@ -4114,67 +4402,59 @@ static int QAMResetQAM(struct drxk_state *state)
*/
static int QAMSetSymbolrate(struct drxk_state *state)
{
- u32 adcFrequency = 0;
- u32 symbFreq = 0;
- u32 iqmRcRate = 0;
- u16 ratesel = 0;
- u32 lcSymbRate = 0;
- int status;
-
- do
- {
- /* Select & calculate correct IQM rate */
- adcFrequency = (state->m_sysClockFreq * 1000) / 3;
- ratesel = 0;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate));
- //printk("SR %d\n", state->param.u.qam.symbol_rate);
- if (state->param.u.qam.symbol_rate <= 1188750)
- {
- ratesel = 3;
- }
- else if (state->param.u.qam.symbol_rate <= 2377500)
- {
- ratesel = 2;
- }
- else if (state->param.u.qam.symbol_rate <= 4755000)
- {
- ratesel = 1;
- }
- CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel));
-
- /*
- IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
- */
- symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
- if (symbFreq == 0)
- {
- /* Divide by zero */
- return -1;
- }
- iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
- (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
- (1 << 23);
- CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0));
- state->m_iqmRcRate = iqmRcRate;
- /*
- LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
- */
- symbFreq = state->param.u.qam.symbol_rate;
- if (adcFrequency == 0)
- {
- /* Divide by zero */
- return -1;
- }
- lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
- (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16);
- if (lcSymbRate > 511)
- {
- lcSymbRate = 511;
- }
- CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate));
- } while (0);
-
- return status;
+ u32 adcFrequency = 0;
+ u32 symbFreq = 0;
+ u32 iqmRcRate = 0;
+ u16 ratesel = 0;
+ u32 lcSymbRate = 0;
+ int status;
+
+ do {
+ /* Select & calculate correct IQM rate */
+ adcFrequency = (state->m_sysClockFreq * 1000) / 3;
+ ratesel = 0;
+ /* printk(KERN_DEBUG "SR %d\n", state->param.u.qam.symbol_rate); */
+ if (state->param.u.qam.symbol_rate <= 1188750)
+ ratesel = 3;
+ else if (state->param.u.qam.symbol_rate <= 2377500)
+ ratesel = 2;
+ else if (state->param.u.qam.symbol_rate <= 4755000)
+ ratesel = 1;
+ CHK_ERROR(Write16_0(state, IQM_FD_RATESEL__A, ratesel));
+
+ /*
+ IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
+ */
+ symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
+ if (symbFreq == 0) {
+ /* Divide by zero */
+ return -1;
+ }
+ iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
+ (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
+ (1 << 23);
+ CHK_ERROR(Write32
+ (state, IQM_RC_RATE_OFS_LO__A, iqmRcRate, 0));
+ state->m_iqmRcRate = iqmRcRate;
+ /*
+ LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
+ */
+ symbFreq = state->param.u.qam.symbol_rate;
+ if (adcFrequency == 0) {
+ /* Divide by zero */
+ return -1;
+ }
+ lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
+ (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
+ 16);
+ if (lcSymbRate > 511)
+ lcSymbRate = 511;
+ CHK_ERROR(Write16_0
+ (state, QAM_LC_SYMBOL_FREQ__A,
+ (u16) lcSymbRate));
+ } while (0);
+
+ return status;
}
/*============================================================================*/
@@ -4189,30 +4469,26 @@ static int QAMSetSymbolrate(struct drxk_state *state)
static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
{
int status;
- u16 Result[2] = {0,0};
+ u16 Result[2] = { 0, 0 };
- status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result);
- if (status<0)
- {
- printk("%s status = %08x\n",__FUNCTION__,status);
- }
- if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED)
- {
+ status =
+ scu_command(state,
+ SCU_RAM_COMMAND_STANDARD_QAM |
+ SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
+ Result);
+ if (status < 0)
+ printk(KERN_ERR "%s status = %08x\n", __func__, status);
+
+ if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
/* 0x0000 NOT LOCKED */
*pLockStatus = NOT_LOCKED;
- }
- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED)
- {
+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
/* 0x4000 DEMOD LOCKED */
*pLockStatus = DEMOD_LOCK;
- }
- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK)
- {
+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
/* 0x8000 DEMOD + FEC LOCKED (system lock) */
*pLockStatus = MPEG_LOCK;
- }
- else
- {
+ } else {
/* 0xC000 NEVER LOCKED */
/* (system will never be able to lock to the signal) */
/* TODO: check this, intermediate & standard specific lock states are not
@@ -4229,49 +4505,48 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
#define QAM_LOCKRANGE__M 0x10
#define QAM_LOCKRANGE_NORMAL 0x10
-static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset)
+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
+ s32 tunerFreqOffset)
{
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
int status = 0;
u8 parameterLen;
- u16 setEnvParameters[5];
- u16 setParamParameters[4]={0,0,0,0};
- u16 cmdResult;
-
- //printk("%s\n", __FUNCTION__);
+ u16 setEnvParameters[5];
+ u16 setParamParameters[4] = { 0, 0, 0, 0 };
+ u16 cmdResult;
do {
/*
- STEP 1: reset demodulator
- resets FEC DI and FEC RS
- resets QAM block
- resets SCU variables
- */
- CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP));
- CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP));
+ STEP 1: reset demodulator
+ resets FEC DI and FEC RS
+ resets QAM block
+ resets SCU variables
+ */
+ CHK_ERROR(Write16_0
+ (state, FEC_DI_COMM_EXEC__A,
+ FEC_DI_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, FEC_RS_COMM_EXEC__A,
+ FEC_RS_COMM_EXEC_STOP));
CHK_ERROR(QAMResetQAM(state));
/*
- STEP 2: configure demodulator
- -set env
- -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
- */
+ STEP 2: configure demodulator
+ -set env
+ -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
+ */
CHK_ERROR(QAMSetSymbolrate(state));
/* Env parameters */
- setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */
+ setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */
if (state->m_OperationMode == OM_QAM_ITU_C)
- {
- setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */
- }
+ setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */
setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
-// check for LOCKRANGE Extented
- // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL;
+ /* check for LOCKRANGE Extented */
+ /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
parameterLen = 4;
/* Set params */
- switch(state->param.u.qam.modulation)
- {
+ switch (state->param.u.qam.modulation) {
case QAM_256:
state->m_Constellation = DRX_CONSTELLATION_QAM256;
break;
@@ -4293,270 +4568,290 @@ static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFre
break;
}
CHK_ERROR(status);
- setParamParameters[0] = state->m_Constellation; /* constellation */
- setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
+ setParamParameters[0] = state->m_Constellation; /* constellation */
+ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult));
+ CHK_ERROR(scu_command
+ (state,
+ SCU_RAM_COMMAND_STANDARD_QAM |
+ SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4,
+ setParamParameters, 1, &cmdResult));
/* STEP 3: enable the system in a mode where the ADC provides valid signal
setup constellation independent registers */
-// CHK_ERROR (SetFrequency (channel, tunerFreqOffset));
- CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true));
+ /* CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); */
+ CHK_ERROR(SetFrequencyShifter
+ (state, IntermediateFreqkHz, tunerFreqOffset,
+ true));
/* Setup BER measurement */
- CHK_ERROR(SetQAMMeasurement (state,
- state->m_Constellation,
- state->param.u.qam.symbol_rate));
+ CHK_ERROR(SetQAMMeasurement(state,
+ state->m_Constellation,
+ state->param.u.
+ qam.symbol_rate));
/* Reset default values */
- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE));
- CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE));
-
- /* Reset default LC values */
- CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3));
- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4));
- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4));
- CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7));
-
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4));
- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4));
-
- /* Mirroring, QAM-block starting point not inverted */
- CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS));
-
- /* Halt SCU to enable safe non-atomic accesses */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
-
- /* STEP 4: constellation specific setup */
- switch (state->param.u.qam.modulation)
- {
- case QAM_16:
- CHK_ERROR(SetQAM16(state));
- break;
- case QAM_32:
- CHK_ERROR(SetQAM32(state));
- break;
- case QAM_AUTO:
- case QAM_64:
- CHK_ERROR(SetQAM64(state));
- break;
- case QAM_128:
- CHK_ERROR(SetQAM128(state));
- break;
- case QAM_256:
- //printk("SETQAM256\n");
- CHK_ERROR(SetQAM256(state));
- break;
- default:
- return -1;
- break;
- } /* switch */
- /* Activate SCU to enable SCU commands */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
-
-
- /* Re-configure MPEG output, requires knowledge of channel bitrate */
-// extAttr->currentChannel.constellation = channel->constellation;
-// extAttr->currentChannel.symbolrate = channel->symbolrate;
- CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode));
-
- /* Start processes */
- CHK_ERROR(MPEGTSStart(state));
- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE));
- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE));
- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE));
-
- /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM |
- SCU_RAM_COMMAND_CMD_DEMOD_START,0,
- NULL,1,&cmdResult));
-
- /* update global DRXK data container */
-//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17;
-
- /* All done, all OK */
- } while(0);
-
- if (status<0) {
- printk("%s %d\n", __FUNCTION__, status);
- }
- return status;
+ CHK_ERROR(Write16_0
+ (state, IQM_CF_SCALE_SH__A,
+ IQM_CF_SCALE_SH__PRE));
+ CHK_ERROR(Write16_0
+ (state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE));
+
+ /* Reset default LC values */
+ CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7));
+
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4));
+ CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4));
+
+ /* Mirroring, QAM-block starting point not inverted */
+ CHK_ERROR(Write16_0
+ (state, QAM_SY_SP_INV__A,
+ QAM_SY_SP_INV_SPECTRUM_INV_DIS));
+
+ /* Halt SCU to enable safe non-atomic accesses */
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
+
+ /* STEP 4: constellation specific setup */
+ switch (state->param.u.qam.modulation) {
+ case QAM_16:
+ CHK_ERROR(SetQAM16(state));
+ break;
+ case QAM_32:
+ CHK_ERROR(SetQAM32(state));
+ break;
+ case QAM_AUTO:
+ case QAM_64:
+ CHK_ERROR(SetQAM64(state));
+ break;
+ case QAM_128:
+ CHK_ERROR(SetQAM128(state));
+ break;
+ case QAM_256:
+ CHK_ERROR(SetQAM256(state));
+ break;
+ default:
+ return -1;
+ break;
+ } /* switch */
+ /* Activate SCU to enable SCU commands */
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
+
+
+ /* Re-configure MPEG output, requires knowledge of channel bitrate */
+ /* extAttr->currentChannel.constellation = channel->constellation; */
+ /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
+ CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode));
+
+ /* Start processes */
+ CHK_ERROR(MPEGTSStart(state));
+ CHK_ERROR(Write16_0
+ (state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, IQM_COMM_EXEC__A,
+ IQM_COMM_EXEC_B_ACTIVE));
+
+ /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
+ CHK_ERROR(scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM |
+ SCU_RAM_COMMAND_CMD_DEMOD_START, 0,
+ NULL, 1, &cmdResult));
+
+ /* update global DRXK data container */
+ /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
+
+ /* All done, all OK */
+ } while (0);
+
+ if (status < 0)
+ printk(KERN_ERR "%s %d\n", __func__, status);
+
+ return status;
}
-static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode)
+static int SetQAMStandard(struct drxk_state *state,
+ enum OperationMode oMode)
{
#ifdef DRXK_QAM_TAPS
#define DRXK_QAMA_TAPS_SELECT
#include "drxk_filters.h"
#undef DRXK_QAMA_TAPS_SELECT
#else
- int status;
+ int status;
#endif
- //printk("%s\n", __FUNCTION__);
- do
- {
- /* added antenna switch */
- SwitchAntennaToQAM(state);
-
- /* Ensure correct power-up mode */
- CHK_ERROR(PowerUpQAM(state));
- /* Reset QAM block */
- CHK_ERROR(QAMResetQAM(state));
-
- /* Setup IQM */
-
- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP));
- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC));
-
- /* Upload IQM Channel Filter settings by
- boot loader from ROM table */
- switch (oMode)
- {
- case OM_QAM_ITU_A:
- CHK_ERROR(BLChainCmd(state,
- DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
- DRXK_BLCC_NR_ELEMENTS_TAPS,
- DRXK_BLC_TIMEOUT));
- break;
- case OM_QAM_ITU_C:
- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A,
- DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
- DRXK_BLDC_NR_ELEMENTS_TAPS,
- DRXK_BLC_TIMEOUT));
- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A,
- DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
- DRXK_BLDC_NR_ELEMENTS_TAPS,
- DRXK_BLC_TIMEOUT));
- break;
- default:
- status=-EINVAL;
- }
- CHK_ERROR (status);
-
- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A,
- (1 << IQM_CF_OUT_ENA_QAM__B)));
- CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0));
- CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A,
- ((1 << IQM_CF_MIDTAP_RE__B) |
- (1 << IQM_CF_MIDTAP_IM__B))));
-
- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21));
- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0));
- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448));
- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0));
- CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0));
-
- CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1));
- CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1));
- CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1));
- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0));
-
- /* IQM Impulse Noise Processing Unit */
- CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500));
- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000));
- CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1));
- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0));
- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1));
- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1));
- CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1));
-
- /* turn on IQMAF. Must be done before setAgc**() */
- CHK_ERROR(SetIqmAf(state, true));
- CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01));
-
- /* IQM will not be reset from here, sync ADC and update/init AGC */
- CHK_ERROR(ADCSynchronization (state));
-
- /* Set the FSM step period */
- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000));
-
- /* Halt SCU to enable safe non-atomic accesses */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
-
- /* No more resets of the IQM, current standard correctly set =>
- now AGCs can be configured. */
-
- CHK_ERROR(InitAGC(state,true));
- CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg)));
-
- /* Configure AGC's */
- CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true));
- CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true));
-
- /* Activate SCU to enable SCU commands */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
- } while (0);
- return status;
+ do {
+ /* added antenna switch */
+ SwitchAntennaToQAM(state);
+
+ /* Ensure correct power-up mode */
+ CHK_ERROR(PowerUpQAM(state));
+ /* Reset QAM block */
+ CHK_ERROR(QAMResetQAM(state));
+
+ /* Setup IQM */
+
+ CHK_ERROR(Write16_0
+ (state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP));
+ CHK_ERROR(Write16_0
+ (state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC));
+
+ /* Upload IQM Channel Filter settings by
+ boot loader from ROM table */
+ switch (oMode) {
+ case OM_QAM_ITU_A:
+ CHK_ERROR(BLChainCmd(state,
+ DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
+ DRXK_BLCC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT));
+ break;
+ case OM_QAM_ITU_C:
+ CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A,
+ DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
+ DRXK_BLDC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT));
+ CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A,
+ DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
+ DRXK_BLDC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT));
+ break;
+ default:
+ status = -EINVAL;
+ }
+ CHK_ERROR(status);
+
+ CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A,
+ (1 << IQM_CF_OUT_ENA_QAM__B)));
+ CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A,
+ ((1 << IQM_CF_MIDTAP_RE__B) |
+ (1 << IQM_CF_MIDTAP_IM__B))));
+
+ CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21));
+ CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448));
+ CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0));
+
+ CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0));
+
+ /* IQM Impulse Noise Processing Unit */
+ CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500));
+ CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000));
+ CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0));
+ CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1));
+ CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1));
+
+ /* turn on IQMAF. Must be done before setAgc**() */
+ CHK_ERROR(SetIqmAf(state, true));
+ CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01));
+
+ /* IQM will not be reset from here, sync ADC and update/init AGC */
+ CHK_ERROR(ADCSynchronization(state));
+
+ /* Set the FSM step period */
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000));
+
+ /* Halt SCU to enable safe non-atomic accesses */
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD));
+
+ /* No more resets of the IQM, current standard correctly set =>
+ now AGCs can be configured. */
+
+ CHK_ERROR(InitAGC(state, true));
+ CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg)));
+
+ /* Configure AGC's */
+ CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true));
+ CHK_ERROR(SetAgcIf(state, &(state->m_qamIfAgcCfg), true));
+
+ /* Activate SCU to enable SCU commands */
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
+ } while (0);
+ return status;
}
static int WriteGPIO(struct drxk_state *state)
{
- int status;
- u16 value = 0;
-
- do {
- /* stop lock indicator process */
- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
-
- /* Write magic word to enable pdr reg write */
- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A,
- SIO_TOP_COMM_KEY_KEY));
-
- if (state->m_hasSAWSW) {
- /* write to io pad configuration register - output mode */
- CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A,
- state->m_GPIOCfg));
-
- /* use corresponding bit in io data output registar */
- CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value));
- if (state->m_GPIO == 0) {
- value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
- } else {
- value |= 0x8000; /* write one to 15th bit - 1st UIO */
- }
- /* write back to io data output register */
- CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value));
-
- }
- /* Write magic word to disable pdr reg write */
- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000));
- } while (0);
- return status;
+ int status;
+ u16 value = 0;
+
+ do {
+ /* stop lock indicator process */
+ CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
+
+ /* Write magic word to enable pdr reg write */
+ CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A,
+ SIO_TOP_COMM_KEY_KEY));
+
+ if (state->m_hasSAWSW) {
+ /* write to io pad configuration register - output mode */
+ CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A,
+ state->m_GPIOCfg));
+
+ /* use corresponding bit in io data output registar */
+ CHK_ERROR(Read16_0
+ (state, SIO_PDR_UIO_OUT_LO__A, &value));
+ if (state->m_GPIO == 0)
+ value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
+ else
+ value |= 0x8000; /* write one to 15th bit - 1st UIO */
+ /* write back to io data output register */
+ CHK_ERROR(Write16_0
+ (state, SIO_PDR_UIO_OUT_LO__A, value));
+
+ }
+ /* Write magic word to disable pdr reg write */
+ CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000));
+ } while (0);
+ return status;
}
static int SwitchAntennaToQAM(struct drxk_state *state)
{
- int status = -1;
-
- if (state->m_AntennaSwitchDVBTDVBC != 0) {
- if (state->m_GPIO != state->m_AntennaDVBC) {
- state->m_GPIO = state->m_AntennaDVBC;
- status = WriteGPIO(state);
- }
- }
- return status;
+ int status = -1;
+
+ if (state->m_AntennaSwitchDVBTDVBC != 0) {
+ if (state->m_GPIO != state->m_AntennaDVBC) {
+ state->m_GPIO = state->m_AntennaDVBC;
+ status = WriteGPIO(state);
+ }
+ }
+ return status;
}
static int SwitchAntennaToDVBT(struct drxk_state *state)
{
int status = -1;
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
+
if (state->m_AntennaSwitchDVBTDVBC != 0) {
if (state->m_GPIO != state->m_AntennaDVBT) {
state->m_GPIO = state->m_AntennaDVBT;
@@ -4578,40 +4873,41 @@ static int PowerDownDevice(struct drxk_state *state)
int status;
do {
if (state->m_bPDownOpenBridge) {
- // Open I2C bridge before power down of DRXK
+ /* Open I2C bridge before power down of DRXK */
CHK_ERROR(ConfigureI2CBridge(state, true));
}
- // driver 0.9.0
+ /* driver 0.9.0 */
CHK_ERROR(DVBTEnableOFDMTokenRing(state, false));
- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK));
- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY));
+ CHK_ERROR(Write16_0
+ (state, SIO_CC_PWD_MODE__A,
+ SIO_CC_PWD_MODE_LEVEL_CLOCK));
+ CHK_ERROR(Write16_0
+ (state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY));
state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
CHK_ERROR(HI_CfgCommand(state));
- }
- while(0);
+ } while (0);
- if (status<0) {
- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status));
+ if (status < 0)
return -1;
- }
+
return 0;
}
static int load_microcode(struct drxk_state *state, char *mc_name)
{
const struct firmware *fw = NULL;
- int err=0;
+ int err = 0;
err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
if (err < 0) {
printk(KERN_ERR
- ": Could not load firmware file %s.\n", mc_name);
+ "Could not load firmware file %s.\n", mc_name);
printk(KERN_INFO
- ": Copy %s to your hotplug directory!\n", mc_name);
+ "Copy %s to your hotplug directory!\n", mc_name);
return err;
}
- err=DownloadMicrocode(state, fw->data, fw->size);
+ err = DownloadMicrocode(state, fw->data, fw->size);
release_firmware(fw);
return err;
}
@@ -4619,20 +4915,21 @@ static int load_microcode(struct drxk_state *state, char *mc_name)
static int init_drxk(struct drxk_state *state)
{
int status;
- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM;
+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
u16 driverVersion;
- //printk("init_drxk\n");
if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
do {
CHK_ERROR(PowerUpDevice(state));
- CHK_ERROR (DRXX_Open(state));
+ CHK_ERROR(DRXX_Open(state));
/* Soft reset of OFDM-, sys- and osc-clockdomain */
CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A,
- SIO_CC_SOFT_RST_OFDM__M |
- SIO_CC_SOFT_RST_SYS__M |
- SIO_CC_SOFT_RST_OSC__M));
- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY));
+ SIO_CC_SOFT_RST_OFDM__M |
+ SIO_CC_SOFT_RST_SYS__M |
+ SIO_CC_SOFT_RST_OSC__M));
+ CHK_ERROR(Write16_0
+ (state, SIO_CC_UPDATE__A,
+ SIO_CC_UPDATE_KEY));
/* TODO is this needed, if yes how much delay in worst case scenario */
msleep(1);
state->m_DRXK_A3_PATCH_CODE = true;
@@ -4641,59 +4938,79 @@ static int init_drxk(struct drxk_state *state)
/* Bridge delay, uses oscilator clock */
/* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
/* SDA brdige delay */
- state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000;
+ state->m_HICfgBridgeDelay =
+ (u16) ((state->m_oscClockFreq / 1000) *
+ HI_I2C_BRIDGE_DELAY) / 1000;
/* Clipping */
- if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
- {
- state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
+ if (state->m_HICfgBridgeDelay >
+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
+ state->m_HICfgBridgeDelay =
+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
}
/* SCL bridge delay, same as SDA for now */
- state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
+ state->m_HICfgBridgeDelay +=
+ state->m_HICfgBridgeDelay <<
+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
CHK_ERROR(InitHI(state));
/* disable various processes */
#if NOA1ROM
- if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) )
+ if (!(state->m_DRXK_A1_ROM_CODE)
+ && !(state->m_DRXK_A2_ROM_CODE))
#endif
{
- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE));
}
/* disable MPEG port */
CHK_ERROR(MPEGTSDisable(state));
/* Stop AUD and SCU */
- CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP));
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, AUD_COMM_EXEC__A,
+ AUD_COMM_EXEC_STOP));
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A,
+ SCU_COMM_EXEC_STOP));
/* enable token-ring bus through OFDM block for possible ucode upload */
- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON));
+ CHK_ERROR(Write16_0
+ (state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
+ SIO_OFDM_SH_OFDM_RING_ENABLE_ON));
/* include boot loader section */
- CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE));
+ CHK_ERROR(Write16_0
+ (state, SIO_BL_COMM_EXEC__A,
+ SIO_BL_COMM_EXEC_ACTIVE));
CHK_ERROR(BLChainCmd(state, 0, 6, 100));
#if 0
if (state->m_DRXK_A3_PATCH_CODE)
CHK_ERROR(DownloadMicrocode(state,
- DRXK_A3_microcode,
- DRXK_A3_microcode_length));
+ DRXK_A3_microcode,
+ DRXK_A3_microcode_length));
#else
load_microcode(state, "drxk_a3.mc");
#endif
#if NOA1ROM
if (state->m_DRXK_A2_PATCH_CODE)
CHK_ERROR(DownloadMicrocode(state,
- DRXK_A2_microcode,
- DRXK_A2_microcode_length));
+ DRXK_A2_microcode,
+ DRXK_A2_microcode_length));
#endif
/* disable token-ring bus through OFDM block for possible ucode upload */
- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF));
+ CHK_ERROR(Write16_0
+ (state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
+ SIO_OFDM_SH_OFDM_RING_ENABLE_OFF));
/* Run SCU for a little while to initialize microcode version numbers */
- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE));
- CHK_ERROR (DRXX_Open(state));
- // added for test
+ CHK_ERROR(Write16_0
+ (state, SCU_COMM_EXEC__A,
+ SCU_COMM_EXEC_ACTIVE));
+ CHK_ERROR(DRXX_Open(state));
+ /* added for test */
msleep(30);
powerMode = DRXK_POWER_DOWN_OFDM;
@@ -4704,121 +5021,124 @@ static int init_drxk(struct drxk_state *state)
via I2C from SCU RAM.
Not using SCU command interface for SCU register access since no
microcode may be present.
- */
- driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) +
- (((DRXK_VERSION_MAJOR/10) % 10) << 8) +
- ((DRXK_VERSION_MAJOR%10) << 4) +
- (DRXK_VERSION_MINOR%10);
- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion ));
- driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) +
- (((DRXK_VERSION_PATCH/100) % 10) << 8) +
- (((DRXK_VERSION_PATCH/10) % 10) << 4) +
- (DRXK_VERSION_PATCH%10);
- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion ));
-
- printk("DRXK driver version:%d.%d.%d\n",
- DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH);
+ */
+ driverVersion =
+ (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
+ (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
+ ((DRXK_VERSION_MAJOR % 10) << 4) +
+ (DRXK_VERSION_MINOR % 10);
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_DRIVER_VER_HI__A,
+ driverVersion));
+ driverVersion =
+ (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
+ (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
+ (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
+ (DRXK_VERSION_PATCH % 10);
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_DRIVER_VER_LO__A,
+ driverVersion));
+
+ printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
+ DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
+ DRXK_VERSION_PATCH);
/* Dirty fix of default values for ROM/PATCH microcode
Dirty because this fix makes it impossible to setup suitable values
before calling DRX_Open. This solution requires changes to RF AGC speed
to be done via the CTRL function after calling DRX_Open */
- // m_dvbtRfAgcCfg.speed=3;
+ /* m_dvbtRfAgcCfg.speed = 3; */
/* Reset driver debug flags to 0 */
- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0));
+ CHK_ERROR(Write16_0
+ (state, SCU_RAM_DRIVER_DEBUG__A, 0));
/* driver 0.9.0 */
/* Setup FEC OC:
NOTE: No more full FEC resets allowed afterwards!! */
- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP));
- // MPEGTS functions are still the same
+ CHK_ERROR(Write16_0
+ (state, FEC_COMM_EXEC__A,
+ FEC_COMM_EXEC_STOP));
+ /* MPEGTS functions are still the same */
CHK_ERROR(MPEGTSDtoInit(state));
CHK_ERROR(MPEGTSStop(state));
CHK_ERROR(MPEGTSConfigurePolarity(state));
- CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput));
- // added: configure GPIO
+ CHK_ERROR(MPEGTSConfigurePins
+ (state, state->m_enableMPEGOutput));
+ /* added: configure GPIO */
CHK_ERROR(WriteGPIO(state));
- state->m_DrxkState = DRXK_STOPPED;
+ state->m_DrxkState = DRXK_STOPPED;
if (state->m_bPowerDown) {
CHK_ERROR(PowerDownDevice(state));
- state->m_DrxkState = DRXK_POWERED_DOWN;
- }
- else
- state->m_DrxkState = DRXK_STOPPED;
- } while(0);
- //printk("%s=%d\n", __FUNCTION__, status);
- }
- else
- {
- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n"));
+ state->m_DrxkState = DRXK_POWERED_DOWN;
+ } else
+ state->m_DrxkState = DRXK_STOPPED;
+ } while (0);
}
return 0;
}
-static void drxk_c_release(struct dvb_frontend* fe)
+static void drxk_c_release(struct dvb_frontend *fe)
{
- struct drxk_state *state=fe->demodulator_priv;
- printk("%s\n", __FUNCTION__);
+ struct drxk_state *state = fe->demodulator_priv;
+
kfree(state);
}
-static int drxk_c_init (struct dvb_frontend *fe)
+static int drxk_c_init(struct dvb_frontend *fe)
{
- struct drxk_state *state=fe->demodulator_priv;
+ struct drxk_state *state = fe->demodulator_priv;
- if (mutex_trylock(&state->ctlock)==0)
+ if (mutex_trylock(&state->ctlock) == 0)
return -EBUSY;
SetOperationMode(state, OM_QAM_ITU_A);
return 0;
}
-static int drxk_c_sleep(struct dvb_frontend* fe)
+static int drxk_c_sleep(struct dvb_frontend *fe)
{
- struct drxk_state *state=fe->demodulator_priv;
+ struct drxk_state *state = fe->demodulator_priv;
ShutDown(state);
mutex_unlock(&state->ctlock);
return 0;
}
-static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable)
+static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct drxk_state *state = fe->demodulator_priv;
- //printk("drxk_gate %d\n", enable);
+ /* printk(KERN_DEBUG "drxk_gate %d\n", enable); */
return ConfigureI2CBridge(state, enable ? true : false);
}
-static int drxk_set_parameters (struct dvb_frontend *fe,
- struct dvb_frontend_parameters *p)
+static int drxk_set_parameters(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
{
struct drxk_state *state = fe->demodulator_priv;
u32 IF;
- //printk("%s\n", __FUNCTION__);
-
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (fe->ops.tuner_ops.set_params)
fe->ops.tuner_ops.set_params(fe, p);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
- state->param=*p;
+ state->param = *p;
fe->ops.tuner_ops.get_frequency(fe, &IF);
Start(state, 0, IF);
- //printk("%s IF=%d done\n", __FUNCTION__, IF);
+ /* printk(KERN_DEBUG "%s IF=%d done\n", __func__, IF); */
+
return 0;
}
-static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+static int drxk_c_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
{
- //struct drxk_state *state = fe->demodulator_priv;
- //printk("%s\n", __FUNCTION__);
return 0;
}
@@ -4827,31 +5147,31 @@ static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
struct drxk_state *state = fe->demodulator_priv;
u32 stat;
- *status=0;
+ *status = 0;
GetLockStatus(state, &stat, 0);
- if (stat==MPEG_LOCK)
- *status|=0x1f;
- if (stat==FEC_LOCK)
- *status|=0x0f;
- if (stat==DEMOD_LOCK)
- *status|=0x07;
+ if (stat == MPEG_LOCK)
+ *status |= 0x1f;
+ if (stat == FEC_LOCK)
+ *status |= 0x0f;
+ if (stat == DEMOD_LOCK)
+ *status |= 0x07;
return 0;
}
static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
{
- //struct drxk_state *state = fe->demodulator_priv;
- *ber=0;
+ *ber = 0;
return 0;
}
-static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+static int drxk_read_signal_strength(struct dvb_frontend *fe,
+ u16 *strength)
{
struct drxk_state *state = fe->demodulator_priv;
u32 val;
ReadIFAgc(state, &val);
- *strength = val & 0xffff;;
+ *strength = val & 0xffff;
return 0;
}
@@ -4861,7 +5181,7 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
s32 snr2;
GetSignalToNoise(state, &snr2);
- *snr = snr2&0xffff;
+ *snr = snr2 & 0xffff;
return 0;
}
@@ -4875,59 +5195,58 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
return 0;
}
-static int drxk_c_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *sets)
+static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
+ *sets)
{
- sets->min_delay_ms=3000;
- sets->max_drift=0;
- sets->step_size=0;
+ sets->min_delay_ms = 3000;
+ sets->max_drift = 0;
+ sets->step_size = 0;
return 0;
}
-static void drxk_t_release(struct dvb_frontend* fe)
+static void drxk_t_release(struct dvb_frontend *fe)
{
- //struct drxk_state *state=fe->demodulator_priv;
- //printk("%s\n", __FUNCTION__);
- //kfree(state);
+#if 0
+ struct drxk_state *state = fe->demodulator_priv;
+
+ printk(KERN_DEBUG "%s\n", __func__);
+ kfree(state);
+#endif
}
-static int drxk_t_init (struct dvb_frontend *fe)
+static int drxk_t_init(struct dvb_frontend *fe)
{
- struct drxk_state *state=fe->demodulator_priv;
- if (mutex_trylock(&state->ctlock)==0)
+ struct drxk_state *state = fe->demodulator_priv;
+ if (mutex_trylock(&state->ctlock) == 0)
return -EBUSY;
- //printk("%s\n", __FUNCTION__);
SetOperationMode(state, OM_DVBT);
- //printk("%s done\n", __FUNCTION__);
return 0;
}
-static int drxk_t_sleep(struct dvb_frontend* fe)
+static int drxk_t_sleep(struct dvb_frontend *fe)
{
- struct drxk_state *state=fe->demodulator_priv;
+ struct drxk_state *state = fe->demodulator_priv;
mutex_unlock(&state->ctlock);
return 0;
}
-static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+static int drxk_t_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
{
- //struct drxk_state *state = fe->demodulator_priv;
- //printk("%s\n", __FUNCTION__);
return 0;
}
static struct dvb_frontend_ops drxk_c_ops = {
.info = {
- .name = "DRXK DVB-C",
- .type = FE_QAM,
- .frequency_stepsize = 62500,
- .frequency_min = 47000000,
- .frequency_max = 862000000,
- .symbol_rate_min = 870000,
- .symbol_rate_max = 11700000,
- .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
- FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
- },
+ .name = "DRXK DVB-C",
+ .type = FE_QAM,
+ .frequency_stepsize = 62500,
+ .frequency_min = 47000000,
+ .frequency_max = 862000000,
+ .symbol_rate_min = 870000,
+ .symbol_rate_max = 11700000,
+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
.release = drxk_c_release,
.init = drxk_c_init,
.sleep = drxk_c_sleep,
@@ -4946,22 +5265,20 @@ static struct dvb_frontend_ops drxk_c_ops = {
static struct dvb_frontend_ops drxk_t_ops = {
.info = {
- .name = "DRXK DVB-T",
- .type = FE_OFDM,
- .frequency_min = 47125000,
- .frequency_max = 865000000,
- .frequency_stepsize = 166667,
- .frequency_tolerance = 0,
- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
- FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
- FE_CAN_FEC_AUTO |
- FE_CAN_QAM_16 | FE_CAN_QAM_64 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
- FE_CAN_MUTE_TS
- },
+ .name = "DRXK DVB-T",
+ .type = FE_OFDM,
+ .frequency_min = 47125000,
+ .frequency_max = 865000000,
+ .frequency_stepsize = 166667,
+ .frequency_tolerance = 0,
+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QAM_16 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO |
+ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
.release = drxk_t_release,
.init = drxk_t_init,
.sleep = drxk_t_sleep,
@@ -4982,35 +5299,36 @@ struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr,
{
struct drxk_state *state = NULL;
- state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
+ state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
if (!state)
return NULL;
- state->i2c=i2c;
- state->demod_address=adr;
+ state->i2c = i2c;
+ state->demod_address = adr;
mutex_init(&state->mutex);
mutex_init(&state->ctlock);
- memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops));
- memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops));
- state->c_frontend.demodulator_priv=state;
- state->t_frontend.demodulator_priv=state;
+ memcpy(&state->c_frontend.ops, &drxk_c_ops,
+ sizeof(struct dvb_frontend_ops));
+ memcpy(&state->t_frontend.ops, &drxk_t_ops,
+ sizeof(struct dvb_frontend_ops));
+ state->c_frontend.demodulator_priv = state;
+ state->t_frontend.demodulator_priv = state;
init_state(state);
- if (init_drxk(state)<0)
+ if (init_drxk(state) < 0)
goto error;
*fe_t = &state->t_frontend;
return &state->c_frontend;
error:
- printk("drxk: not found\n");
+ printk(KERN_ERR "drxk: not found\n");
kfree(state);
return NULL;
}
+EXPORT_SYMBOL(drxk_attach);
MODULE_DESCRIPTION("DRX-K driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(drxk_attach);
diff --git a/drivers/media/dvb/frontends/drxk_hard.h b/drivers/media/dvb/frontends/drxk_hard.h
index 550df34..700f40c 100644
--- a/drivers/media/dvb/frontends/drxk_hard.h
+++ b/drivers/media/dvb/frontends/drxk_hard.h
@@ -52,7 +52,7 @@ enum OperationMode {
OM_DVBT
};
-typedef enum {
+enum DRXPowerMode {
DRX_POWER_UP = 0,
DRX_POWER_MODE_1,
DRX_POWER_MODE_2,
@@ -72,7 +72,7 @@ typedef enum {
DRX_POWER_MODE_15,
DRX_POWER_MODE_16,
DRX_POWER_DOWN = 255
-}DRXPowerMode_t, *pDRXPowerMode_t;
+};
/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
@@ -164,8 +164,7 @@ struct DRXKCfgDvbtEchoThres_t {
enum DRXFftmode_t fftMode;
} ;
-struct SCfgAgc
-{
+struct SCfgAgc {
enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
u16 outputLevel; /* range dependent on AGC */
u16 minOutputLevel; /* range dependent on AGC */
@@ -173,19 +172,17 @@ struct SCfgAgc
u16 speed; /* range dependent on AGC */
u16 top; /* rf-agc take over point */
u16 cutOffCurrent; /* rf-agc is accelerated if output current
- is below cut-off current */
+ is below cut-off current */
u16 IngainTgtMax;
u16 FastClipCtrlDelay;
};
-struct SCfgPreSaw
-{
+struct SCfgPreSaw {
u16 reference; /* pre SAW reference value, range 0 .. 31 */
bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
};
-struct DRXKOfdmScCmd_t
-{
+struct DRXKOfdmScCmd_t {
u16 cmd; /**< Command number */
u16 subcmd; /**< Sub-command parameter*/
u16 param0; /**< General purpous param */
@@ -208,127 +205,127 @@ struct drxk_state {
struct mutex mutex;
struct mutex ctlock;
- u32 m_Instance; ///< Channel 1,2,3 or 4
+ u32 m_Instance; /**< Channel 1,2,3 or 4 */
- int m_ChunkSize;
+ int m_ChunkSize;
u8 Chunk[256];
- bool m_hasLNA;
- bool m_hasDVBT;
- bool m_hasDVBC;
- bool m_hasAudio;
- bool m_hasATV;
- bool m_hasOOB;
- bool m_hasSAWSW; /**< TRUE if mat_tx is available */
- bool m_hasGPIO1; /**< TRUE if mat_rx is available */
- bool m_hasGPIO2; /**< TRUE if GPIO is available */
- bool m_hasIRQN; /**< TRUE if IRQN is available */
- u16 m_oscClockFreq;
- u16 m_HICfgTimingDiv;
- u16 m_HICfgBridgeDelay;
- u16 m_HICfgWakeUpKey;
- u16 m_HICfgTimeout;
- u16 m_HICfgCtrl;
- s32 m_sysClockFreq ; ///< system clock frequency in kHz
-
- enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started)
- enum OperationMode m_OperationMode; ///< digital standards
- struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC
- struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC
- u16 m_vsbPgaCfg; ///< settings for VSB PGA
- struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense
- s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication
- s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication
- bool m_smartAntInverted;
- bool m_bDebugEnableBridge;
- bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed
- bool m_bPowerDown; ///< Power down when not used
-
- u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint)
-
- bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
- bool m_insertRSByte; /**< If TRUE, insert RS byte */
- bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
- bool m_invertDATA; /**< If TRUE, invert DATA signals */
- bool m_invertERR; /**< If TRUE, invert ERR signal */
- bool m_invertSTR; /**< If TRUE, invert STR signals */
- bool m_invertVAL; /**< If TRUE, invert VAL signals */
- bool m_invertCLK; /**< If TRUE, invert CLK signals */
- bool m_DVBCStaticCLK;
- bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
- be used, otherwise clockrate will
- adapt to the bitrate of the TS */
- u32 m_DVBTBitrate;
- u32 m_DVBCBitrate;
-
- u8 m_TSDataStrength;
- u8 m_TSClockkStrength;
-
- enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/
- u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
- static clockrate is selected */
-
- //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start
- s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
- s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
-
- bool m_disableTEIhandling;
-
- bool m_RfAgcPol;
- bool m_IfAgcPol;
-
- struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC
- struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC
- struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense
- bool m_phaseCorrectionBypass;
- s16 m_atvTopVidPeak;
- u16 m_atvTopNoiseTh;
+ bool m_hasLNA;
+ bool m_hasDVBT;
+ bool m_hasDVBC;
+ bool m_hasAudio;
+ bool m_hasATV;
+ bool m_hasOOB;
+ bool m_hasSAWSW; /**< TRUE if mat_tx is available */
+ bool m_hasGPIO1; /**< TRUE if mat_rx is available */
+ bool m_hasGPIO2; /**< TRUE if GPIO is available */
+ bool m_hasIRQN; /**< TRUE if IRQN is available */
+ u16 m_oscClockFreq;
+ u16 m_HICfgTimingDiv;
+ u16 m_HICfgBridgeDelay;
+ u16 m_HICfgWakeUpKey;
+ u16 m_HICfgTimeout;
+ u16 m_HICfgCtrl;
+ s32 m_sysClockFreq; /**< system clock frequency in kHz */
+
+ enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
+ enum OperationMode m_OperationMode; /**< digital standards */
+ struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
+ struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
+ u16 m_vsbPgaCfg; /**< settings for VSB PGA */
+ struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
+ s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
+ s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
+ bool m_smartAntInverted;
+ bool m_bDebugEnableBridge;
+ bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
+ bool m_bPowerDown; /**< Power down when not used */
+
+ u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
+
+ bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
+ bool m_insertRSByte; /**< If TRUE, insert RS byte */
+ bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
+ bool m_invertDATA; /**< If TRUE, invert DATA signals */
+ bool m_invertERR; /**< If TRUE, invert ERR signal */
+ bool m_invertSTR; /**< If TRUE, invert STR signals */
+ bool m_invertVAL; /**< If TRUE, invert VAL signals */
+ bool m_invertCLK; /**< If TRUE, invert CLK signals */
+ bool m_DVBCStaticCLK;
+ bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
+ be used, otherwise clockrate will
+ adapt to the bitrate of the TS */
+ u32 m_DVBTBitrate;
+ u32 m_DVBCBitrate;
+
+ u8 m_TSDataStrength;
+ u8 m_TSClockkStrength;
+
+ enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
+ u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
+ static clockrate is selected */
+
+ /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
+ s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
+ s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
+
+ bool m_disableTEIhandling;
+
+ bool m_RfAgcPol;
+ bool m_IfAgcPol;
+
+ struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
+ struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
+ struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
+ bool m_phaseCorrectionBypass;
+ s16 m_atvTopVidPeak;
+ u16 m_atvTopNoiseTh;
enum EDrxkSifAttenuation m_sifAttenuation;
- bool m_enableCVBSOutput;
- bool m_enableSIFOutput;
- bool m_bMirrorFreqSpect;
- enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel
- u32 m_CurrSymbolRate; ///< Current QAM symbol rate
- struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC
- struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC
- u16 m_qamPgaCfg; ///< settings for QAM PGA
- struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense
- enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode
- u16 m_fecRsPlen;
- u16 m_fecRsPrescale;
+ bool m_enableCVBSOutput;
+ bool m_enableSIFOutput;
+ bool m_bMirrorFreqSpect;
+ enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
+ u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
+ struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
+ struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
+ u16 m_qamPgaCfg; /**< settings for QAM PGA */
+ struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
+ enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
+ u16 m_fecRsPlen;
+ u16 m_fecRsPrescale;
enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
- u16 m_GPIO;
- u16 m_GPIOCfg;
+ u16 m_GPIO;
+ u16 m_GPIOCfg;
- struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC
- struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC
- struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense
+ struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
+ struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
+ struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
- u16 m_agcFastClipCtrlDelay;
- bool m_adcCompPassed;
- u16 m_adcCompCoef[64];
- u16 m_adcState;
+ u16 m_agcFastClipCtrlDelay;
+ bool m_adcCompPassed;
+ u16 m_adcCompCoef[64];
+ u16 m_adcState;
- u8 *m_microcode;
- int m_microcode_length;
- bool m_DRXK_A1_PATCH_CODE;
- bool m_DRXK_A1_ROM_CODE;
- bool m_DRXK_A2_ROM_CODE;
- bool m_DRXK_A3_ROM_CODE;
- bool m_DRXK_A2_PATCH_CODE;
- bool m_DRXK_A3_PATCH_CODE;
+ u8 *m_microcode;
+ int m_microcode_length;
+ bool m_DRXK_A1_PATCH_CODE;
+ bool m_DRXK_A1_ROM_CODE;
+ bool m_DRXK_A2_ROM_CODE;
+ bool m_DRXK_A3_ROM_CODE;
+ bool m_DRXK_A2_PATCH_CODE;
+ bool m_DRXK_A3_PATCH_CODE;
- bool m_rfmirror;
- u8 m_deviceSpin;
- u32 m_iqmRcRate;
+ bool m_rfmirror;
+ u8 m_deviceSpin;
+ u32 m_iqmRcRate;
- u16 m_AntennaDVBC;
- u16 m_AntennaDVBT;
- u16 m_AntennaSwitchDVBTDVBC;
+ u16 m_AntennaDVBC;
+ u16 m_AntennaDVBT;
+ u16 m_AntennaSwitchDVBTDVBC;
- DRXPowerMode_t m_currentPowerMode;
+ enum DRXPowerMode m_currentPowerMode;
};
#define NEVER_LOCK 0
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 06/16] DRX-K, TDA18271c2: Add build support
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (2 preceding siblings ...)
2011-07-03 16:49 ` [PATCH 05/16] DRX-K: Tons " Oliver Endriss
@ 2011-07-03 16:51 ` Oliver Endriss
2011-07-03 16:53 ` [PATCH 07/16] get_dvb_firmware: Get DRX-K firmware for Digital Devices DVB-CT cards Oliver Endriss
` (13 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:51 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Add both drivers to Makefile and Kconfig.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/frontends/Kconfig | 21 +++++++++++++++++++++
drivers/media/dvb/frontends/Makefile | 3 +++
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 44b816f..32e08e3 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -49,6 +49,27 @@ config DVB_STV6110x
help
A Silicon tuner that supports DVB-S and DVB-S2 modes
+comment "Multistandard (cable + terrestrial) frontends"
+ depends on DVB_CORE
+
+config DVB_DRXK
+ tristate "Micronas DRXK based"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ Micronas DRX-K DVB-C/T demodulator.
+
+ Say Y when you want to support this frontend.
+
+config DVB_TDA18271C2DD
+ tristate "NXP TDA18271C2 silicon tuner"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ NXP TDA18271 silicon tuner.
+
+ Say Y when you want to support this tuner.
+
comment "DVB-S (satellite) frontends"
depends on DVB_CORE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 2f3a6f7..6a6ba05 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -10,6 +10,7 @@ stv0900-objs = stv0900_core.o stv0900_sw.o
au8522-objs = au8522_dig.o au8522_decoder.o
drxd-objs = drxd_firm.o drxd_hard.o
cxd2820r-objs = cxd2820r_core.o cxd2820r_c.o cxd2820r_t.o cxd2820r_t2.o
+drxk-objs := drxk_hard.o
obj-$(CONFIG_DVB_PLL) += dvb-pll.o
obj-$(CONFIG_DVB_STV0299) += stv0299.o
@@ -88,4 +89,6 @@ obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
obj-$(CONFIG_DVB_STV0367) += stv0367.o
obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o
+obj-$(CONFIG_DVB_DRXK) += drxk.o
+obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 07/16] get_dvb_firmware: Get DRX-K firmware for Digital Devices DVB-CT cards
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (3 preceding siblings ...)
2011-07-03 16:51 ` [PATCH 06/16] DRX-K, TDA18271c2: Add build support Oliver Endriss
@ 2011-07-03 16:53 ` Oliver Endriss
2011-07-03 16:55 ` [PATCH 08/16] ngene: Support Digital Devices DuoFlex CT Oliver Endriss
` (12 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:53 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Get DRX-K firmware for Digital Devices DVB-CT cards
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
Documentation/dvb/get_dvb_firmware | 20 +++++++++++++++++++-
1 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/Documentation/dvb/get_dvb_firmware b/Documentation/dvb/get_dvb_firmware
index 3348d31..224d9e6 100644
--- a/Documentation/dvb/get_dvb_firmware
+++ b/Documentation/dvb/get_dvb_firmware
@@ -27,7 +27,7 @@ use IO::Handle;
"or51211", "or51132_qam", "or51132_vsb", "bluebird",
"opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718",
"af9015", "ngene", "az6027", "lme2510_lg", "lme2510c_s7395",
- "lme2510c_s7395_old");
+ "lme2510c_s7395_old", "drxk");
# Check args
syntax() if (scalar(@ARGV) != 1);
@@ -634,6 +634,24 @@ sub lme2510c_s7395_old {
$outfile;
}
+sub drxk {
+ my $url = "http://l4m-daten.de/files/";
+ my $zipfile = "DDTuner.zip";
+ my $hash = "f5a37b9a20a3534997997c0b1382a3e5";
+ my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1);
+ my $drvfile = "DDTuner.sys";
+ my $fwfile = "drxk_a3.mc";
+
+ checkstandard();
+
+ wgetfile($zipfile, $url . $zipfile);
+ verify($zipfile, $hash);
+ unzip($zipfile, $tmpdir);
+ extract("$tmpdir/$drvfile", 0x14dd8, 15634, "$fwfile");
+
+ "$fwfile"
+}
+
# ---------------------------------------------------------------
# Utilities
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 08/16] ngene: Support Digital Devices DuoFlex CT
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (4 preceding siblings ...)
2011-07-03 16:53 ` [PATCH 07/16] get_dvb_firmware: Get DRX-K firmware for Digital Devices DVB-CT cards Oliver Endriss
@ 2011-07-03 16:55 ` Oliver Endriss
2011-07-03 16:56 ` [PATCH 09/16] ngene: Codingstyle fixes Oliver Endriss
` (11 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:55 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
From: Ralph Metzler <rmetzler@digitaldevices.de>
Support Digital Devices DuoFlex CT with ngene.
Signed-off-by: Ralph Metzler <rmetzler@digitaldevices.de>
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/Kconfig | 2 +
drivers/media/dvb/ngene/ngene-cards.c | 176 ++++++++++++++++++++++++++-------
drivers/media/dvb/ngene/ngene-core.c | 15 +++-
drivers/media/dvb/ngene/ngene.h | 3 +
4 files changed, 156 insertions(+), 40 deletions(-)
diff --git a/drivers/media/dvb/ngene/Kconfig b/drivers/media/dvb/ngene/Kconfig
index cec242b..64c8470 100644
--- a/drivers/media/dvb/ngene/Kconfig
+++ b/drivers/media/dvb/ngene/Kconfig
@@ -5,6 +5,8 @@ config DVB_NGENE
select DVB_STV6110x if !DVB_FE_CUSTOMISE
select DVB_STV090x if !DVB_FE_CUSTOMISE
select DVB_LGDT330X if !DVB_FE_CUSTOMISE
+ select DVB_DRXK if !DVB_FE_CUSTOMISE
+ select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE
select MEDIA_TUNER_MT2131 if !MEDIA_TUNER_CUSTOMISE
---help---
Support for Micronas PCI express cards with nGene bridge.
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index fcf4be9..ca2e146 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -40,6 +40,7 @@
#include "lnbh24.h"
#include "lgdt330x.h"
#include "mt2131.h"
+#include "drxk.h"
/****************************************************************************/
@@ -83,6 +84,52 @@ static int tuner_attach_stv6110(struct ngene_channel *chan)
}
+static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct ngene_channel *chan = fe->sec_priv;
+ int status;
+
+ if (enable) {
+ down(&chan->dev->pll_mutex);
+ status = chan->gate_ctrl(fe, 1);
+ } else {
+ status = chan->gate_ctrl(fe, 0);
+ up(&chan->dev->pll_mutex);
+ }
+ return status;
+}
+
+struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, u8 adr);
+
+static int tuner_attach_tda18271(struct ngene_channel *chan)
+{
+ struct i2c_adapter *i2c;
+ struct dvb_frontend *fe;
+
+ i2c = &chan->dev->channel[0].i2c_adapter;
+ if (chan->fe->ops.i2c_gate_ctrl)
+ chan->fe->ops.i2c_gate_ctrl(chan->fe, 1);
+ fe = dvb_attach(tda18271c2dd_attach, chan->fe, i2c, 0x60);
+ if (chan->fe->ops.i2c_gate_ctrl)
+ chan->fe->ops.i2c_gate_ctrl(chan->fe, 0);
+ if (!fe) {
+ printk("No TDA18271 found!\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int tuner_attach_probe(struct ngene_channel *chan)
+{
+ if (chan->demod_type == 0)
+ return tuner_attach_stv6110(chan);
+ if (chan->demod_type == 1)
+ return tuner_attach_tda18271(chan);
+ return -EINVAL;
+}
+
static int demod_attach_stv0900(struct ngene_channel *chan)
{
struct i2c_adapter *i2c;
@@ -130,6 +177,60 @@ static void cineS2_tuner_i2c_lock(struct dvb_frontend *fe, int lock)
up(&chan->dev->pll_mutex);
}
+static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
+{
+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = 1 }};
+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
+}
+
+static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
+ u16 reg, u8 *val)
+{
+ u8 msg[2] = {reg>>8, reg&0xff};
+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
+ .buf = msg, .len = 2},
+ {.addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = 1}};
+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
+}
+
+static int port_has_stv0900(struct i2c_adapter *i2c, int port)
+{
+ u8 val;
+ if (i2c_read_reg16(i2c, 0x68+port/2, 0xf100, &val) < 0)
+ return 0;
+ return 1;
+}
+
+static int port_has_drxk(struct i2c_adapter *i2c, int port)
+{
+ u8 val;
+
+ if (i2c_read(i2c, 0x29+port, &val) < 0)
+ return 0;
+ printk("DRXK@%02x\n", 0x29+port);
+ return 1;
+}
+
+static int demod_attach_drxk(struct ngene_channel *chan,
+ struct i2c_adapter *i2c)
+{
+ struct dvb_frontend *fe;
+
+ chan->fe = fe = dvb_attach(drxk_attach,
+ i2c, 0x29 + (chan->number^2),
+ &chan->fe2);
+ if (!chan->fe) {
+ printk("No DRXK found!\n");
+ return -ENODEV;
+ }
+ fe->sec_priv = chan;
+ chan->gate_ctrl = fe->ops.i2c_gate_ctrl;
+ fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
+ return 0;
+}
+
static int cineS2_probe(struct ngene_channel *chan)
{
struct i2c_adapter *i2c;
@@ -144,43 +245,42 @@ static int cineS2_probe(struct ngene_channel *chan)
else
i2c = &chan->dev->channel[1].i2c_adapter;
- fe_conf = chan->dev->card_info->fe_config[chan->number];
- i2c_msg.addr = fe_conf->address;
-
- /* probe demod */
- i2c_msg.len = 2;
- buf[0] = 0xf1;
- buf[1] = 0x00;
- rc = i2c_transfer(i2c, &i2c_msg, 1);
- if (rc != 1)
- return -ENODEV;
-
- /* demod found, attach it */
- rc = demod_attach_stv0900(chan);
- if (rc < 0 || chan->number < 2)
- return rc;
-
- /* demod #2: reprogram outputs DPN1 & DPN2 */
- i2c_msg.len = 3;
- buf[0] = 0xf1;
- switch (chan->number) {
- case 2:
- buf[1] = 0x5c;
- buf[2] = 0xc2;
- break;
- case 3:
- buf[1] = 0x61;
- buf[2] = 0xcc;
- break;
- default:
- return -ENODEV;
+ if (port_has_stv0900(i2c, chan->number)) {
+ chan->demod_type=0;
+ fe_conf = chan->dev->card_info->fe_config[chan->number];
+ /* demod found, attach it */
+ rc = demod_attach_stv0900(chan);
+ if (rc < 0 || chan->number < 2)
+ return rc;
+
+ /* demod #2: reprogram outputs DPN1 & DPN2 */
+ i2c_msg.addr = fe_conf->address;
+ i2c_msg.len = 3;
+ buf[0] = 0xf1;
+ switch (chan->number)
+ {
+ case 2:
+ buf[1] = 0x5c;
+ buf[2] = 0xc2;
+ break;
+ case 3:
+ buf[1] = 0x61;
+ buf[2] = 0xcc;
+ break;
+ default:
+ return -ENODEV;
+ }
+ rc = i2c_transfer(i2c, &i2c_msg, 1);
+ if (rc != 1) {
+ printk(KERN_ERR DEVICE_NAME ": could not setup DPNx\n");
+ return -EIO;
+ }
+ } else if (port_has_drxk(i2c, chan->number^2)) {
+ chan->demod_type=1;
+ demod_attach_drxk(chan, i2c);
+ } else {
+ printk("No demod found on chan %d\n", chan->number);
}
- rc = i2c_transfer(i2c, &i2c_msg, 1);
- if (rc != 1) {
- printk(KERN_ERR DEVICE_NAME ": could not setup DPNx\n");
- return -EIO;
- }
-
return 0;
}
@@ -337,7 +437,7 @@ static struct ngene_info ngene_info_duoFlexS2 = {
.io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
NGENE_IO_TSOUT},
.demod_attach = {cineS2_probe, cineS2_probe, cineS2_probe, cineS2_probe},
- .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
+ .tuner_attach = {tuner_attach_probe, tuner_attach_probe, tuner_attach_probe, tuner_attach_probe},
.fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
.tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
.lnb = {0x0a, 0x08, 0x0b, 0x09},
@@ -397,7 +497,7 @@ MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
/****************************************************************************/
static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
- enum pci_channel_state state)
+ enum pci_channel_state state)
{
printk(KERN_ERR DEVICE_NAME ": PCI error\n");
if (state == pci_channel_io_perm_failure)
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index 6927c72..c59bf50 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -41,7 +41,7 @@
#include "ngene.h"
-static int one_adapter = 1;
+static int one_adapter = 0;
module_param(one_adapter, int, 0444);
MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
@@ -461,7 +461,7 @@ static u8 TSFeatureDecoderSetup[8 * 5] = {
0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
- 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
+ 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
};
@@ -1443,6 +1443,9 @@ static void release_channel(struct ngene_channel *chan)
chan->ci_dev = NULL;
}
+ if (chan->fe2) {
+ dvb_unregister_frontend(chan->fe2);
+ }
if (chan->fe) {
dvb_unregister_frontend(chan->fe);
dvb_frontend_detach(chan->fe);
@@ -1534,6 +1537,14 @@ static int init_channel(struct ngene_channel *chan)
goto err;
chan->has_demux = true;
}
+ if (chan->fe2) {
+ if (dvb_register_frontend(adapter, chan->fe2) < 0)
+ goto err;
+ chan->fe2->tuner_priv=chan->fe->tuner_priv;
+ memcpy(&chan->fe2->ops.tuner_ops,
+ &chan->fe->ops.tuner_ops,
+ sizeof(struct dvb_tuner_ops));
+ }
if (chan->has_demux) {
ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
index 40fce9e..e8cd93d 100644
--- a/drivers/media/dvb/ngene/ngene.h
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -641,8 +641,11 @@ struct ngene_channel {
int mode;
bool has_adapter;
bool has_demux;
+ int demod_type;
+ int (*gate_ctrl)(struct dvb_frontend *, int);
struct dvb_frontend *fe;
+ struct dvb_frontend *fe2;
struct dmxdev dmxdev;
struct dvb_demux demux;
struct dvb_net dvbnet;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 09/16] ngene: Codingstyle fixes
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (5 preceding siblings ...)
2011-07-03 16:55 ` [PATCH 08/16] ngene: Support Digital Devices DuoFlex CT Oliver Endriss
@ 2011-07-03 16:56 ` Oliver Endriss
2011-07-03 16:57 ` [PATCH 10/16] ngene: Fix return code if no demux was found Oliver Endriss
` (10 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:56 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Codingstyle fixes
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-cards.c | 36 +++++++++++++-------------------
drivers/media/dvb/ngene/ngene-core.c | 14 ++++++------
drivers/media/dvb/ngene/ngene-dvb.c | 4 +-
drivers/media/dvb/ngene/ngene.h | 2 +-
4 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index ca2e146..0d550a9 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -40,6 +40,7 @@
#include "lnbh24.h"
#include "lgdt330x.h"
#include "mt2131.h"
+#include "tda18271c2dd.h"
#include "drxk.h"
@@ -99,9 +100,6 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
return status;
}
-struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c, u8 adr);
-
static int tuner_attach_tda18271(struct ngene_channel *chan)
{
struct i2c_adapter *i2c;
@@ -114,7 +112,7 @@ static int tuner_attach_tda18271(struct ngene_channel *chan)
if (chan->fe->ops.i2c_gate_ctrl)
chan->fe->ops.i2c_gate_ctrl(chan->fe, 0);
if (!fe) {
- printk("No TDA18271 found!\n");
+ printk(KERN_ERR "No TDA18271 found!\n");
return -ENODEV;
}
@@ -180,7 +178,7 @@ static void cineS2_tuner_i2c_lock(struct dvb_frontend *fe, int lock)
static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
{
struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1 }};
+ .buf = val, .len = 1 } };
return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
}
@@ -191,7 +189,7 @@ static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = msg, .len = 2},
{.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1}};
+ .buf = val, .len = 1} };
return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
}
@@ -209,25 +207,22 @@ static int port_has_drxk(struct i2c_adapter *i2c, int port)
if (i2c_read(i2c, 0x29+port, &val) < 0)
return 0;
- printk("DRXK@%02x\n", 0x29+port);
return 1;
}
static int demod_attach_drxk(struct ngene_channel *chan,
struct i2c_adapter *i2c)
{
- struct dvb_frontend *fe;
-
- chan->fe = fe = dvb_attach(drxk_attach,
+ chan->fe = dvb_attach(drxk_attach,
i2c, 0x29 + (chan->number^2),
&chan->fe2);
if (!chan->fe) {
- printk("No DRXK found!\n");
+ printk(KERN_ERR "No DRXK found!\n");
return -ENODEV;
}
- fe->sec_priv = chan;
- chan->gate_ctrl = fe->ops.i2c_gate_ctrl;
- fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
+ chan->fe->sec_priv = chan;
+ chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl;
+ chan->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
return 0;
}
@@ -246,19 +241,18 @@ static int cineS2_probe(struct ngene_channel *chan)
i2c = &chan->dev->channel[1].i2c_adapter;
if (port_has_stv0900(i2c, chan->number)) {
- chan->demod_type=0;
+ chan->demod_type = 0;
fe_conf = chan->dev->card_info->fe_config[chan->number];
/* demod found, attach it */
rc = demod_attach_stv0900(chan);
if (rc < 0 || chan->number < 2)
return rc;
-
+
/* demod #2: reprogram outputs DPN1 & DPN2 */
i2c_msg.addr = fe_conf->address;
i2c_msg.len = 3;
buf[0] = 0xf1;
- switch (chan->number)
- {
+ switch (chan->number) {
case 2:
buf[1] = 0x5c;
buf[2] = 0xc2;
@@ -276,10 +270,10 @@ static int cineS2_probe(struct ngene_channel *chan)
return -EIO;
}
} else if (port_has_drxk(i2c, chan->number^2)) {
- chan->demod_type=1;
+ chan->demod_type = 1;
demod_attach_drxk(chan, i2c);
} else {
- printk("No demod found on chan %d\n", chan->number);
+ printk(KERN_ERR "No demod found on chan %d\n", chan->number);
}
return 0;
}
@@ -497,7 +491,7 @@ MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
/****************************************************************************/
static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
- enum pci_channel_state state)
+ enum pci_channel_state state)
{
printk(KERN_ERR DEVICE_NAME ": PCI error\n");
if (state == pci_channel_io_perm_failure)
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index c59bf50..fa4b3eb 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -41,7 +41,7 @@
#include "ngene.h"
-static int one_adapter = 0;
+static int one_adapter;
module_param(one_adapter, int, 0444);
MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
@@ -1443,9 +1443,9 @@ static void release_channel(struct ngene_channel *chan)
chan->ci_dev = NULL;
}
- if (chan->fe2) {
+ if (chan->fe2)
dvb_unregister_frontend(chan->fe2);
- }
+
if (chan->fe) {
dvb_unregister_frontend(chan->fe);
dvb_frontend_detach(chan->fe);
@@ -1540,10 +1540,10 @@ static int init_channel(struct ngene_channel *chan)
if (chan->fe2) {
if (dvb_register_frontend(adapter, chan->fe2) < 0)
goto err;
- chan->fe2->tuner_priv=chan->fe->tuner_priv;
- memcpy(&chan->fe2->ops.tuner_ops,
- &chan->fe->ops.tuner_ops,
- sizeof(struct dvb_tuner_ops));
+ chan->fe2->tuner_priv = chan->fe->tuner_priv;
+ memcpy(&chan->fe2->ops.tuner_ops,
+ &chan->fe->ops.tuner_ops,
+ sizeof(struct dvb_tuner_ops));
}
if (chan->has_demux) {
diff --git a/drivers/media/dvb/ngene/ngene-dvb.c b/drivers/media/dvb/ngene/ngene-dvb.c
index 0b49432..ba209cb 100644
--- a/drivers/media/dvb/ngene/ngene-dvb.c
+++ b/drivers/media/dvb/ngene/ngene-dvb.c
@@ -133,9 +133,9 @@ void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
}
return 0;
}
- if (chan->users > 0) {
+ if (chan->users > 0)
dvb_dmx_swfilter(&chan->demux, buf, len);
- }
+
return NULL;
}
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
index e8cd93d..90fa136 100644
--- a/drivers/media/dvb/ngene/ngene.h
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -855,7 +855,7 @@ struct ngene_info {
};
#ifdef NGENE_V4L
-struct ngene_format{
+struct ngene_format {
char *name;
int fourcc; /* video4linux 2 */
int btformat; /* BT848_COLOR_FMT_* */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 10/16] ngene: Fix return code if no demux was found
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (6 preceding siblings ...)
2011-07-03 16:56 ` [PATCH 09/16] ngene: Codingstyle fixes Oliver Endriss
@ 2011-07-03 16:57 ` Oliver Endriss
2011-07-03 16:58 ` [PATCH 11/16] ngene: Fix name of Digital Devices PCIe/miniPCIe Oliver Endriss
` (9 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:57 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Fix return code if no demux was found (cineS2_probe).
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-cards.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index 0d550a9..0d879cb 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -274,6 +274,7 @@ static int cineS2_probe(struct ngene_channel *chan)
demod_attach_drxk(chan, i2c);
} else {
printk(KERN_ERR "No demod found on chan %d\n", chan->number);
+ return -ENODEV;
}
return 0;
}
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 11/16] ngene: Fix name of Digital Devices PCIe/miniPCIe
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (7 preceding siblings ...)
2011-07-03 16:57 ` [PATCH 10/16] ngene: Fix return code if no demux was found Oliver Endriss
@ 2011-07-03 16:58 ` Oliver Endriss
2011-07-03 16:59 ` [PATCH 12/16] ngene: Support DuoFlex CT attached to CineS2 and SaTiX-S2 Oliver Endriss
` (8 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:58 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Fix name of Digital Devices PCIe/miniPCIe.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-cards.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index 0d879cb..e6d5176 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -426,9 +426,9 @@ static struct ngene_info ngene_info_cineS2v5 = {
};
-static struct ngene_info ngene_info_duoFlexS2 = {
+static struct ngene_info ngene_info_duoFlex = {
.type = NGENE_SIDEWINDER,
- .name = "Digital Devices DuoFlex S2 miniPCIe",
+ .name = "Digital Devices DuoFlex PCIe or miniPCIe",
.io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
NGENE_IO_TSOUT},
.demod_attach = {cineS2_probe, cineS2_probe, cineS2_probe, cineS2_probe},
@@ -480,8 +480,8 @@ static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2),
NGENE_ID(0x18c3, 0xdb02, ngene_info_satixS2v2),
NGENE_ID(0x18c3, 0xdd00, ngene_info_cineS2v5),
- NGENE_ID(0x18c3, 0xdd10, ngene_info_duoFlexS2),
- NGENE_ID(0x18c3, 0xdd20, ngene_info_duoFlexS2),
+ NGENE_ID(0x18c3, 0xdd10, ngene_info_duoFlex),
+ NGENE_ID(0x18c3, 0xdd20, ngene_info_duoFlex),
NGENE_ID(0x1461, 0x062e, ngene_info_m780),
{0}
};
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 12/16] ngene: Support DuoFlex CT attached to CineS2 and SaTiX-S2
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (8 preceding siblings ...)
2011-07-03 16:58 ` [PATCH 11/16] ngene: Fix name of Digital Devices PCIe/miniPCIe Oliver Endriss
@ 2011-07-03 16:59 ` Oliver Endriss
2011-07-03 17:00 ` [PATCH 13/16] cxd2099: Update to latest version Oliver Endriss
` (7 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 16:59 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Support DuoFlex CT with Digital Devices CineS2 and Mystique SaTiX-S2.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-cards.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index e6d5176..9f72dd8 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -401,7 +401,7 @@ static struct ngene_info ngene_info_satixS2v2 = {
.io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
NGENE_IO_TSOUT},
.demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
- .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
+ .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_probe, tuner_attach_probe},
.fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
.tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
.lnb = {0x0a, 0x08, 0x0b, 0x09},
@@ -416,7 +416,7 @@ static struct ngene_info ngene_info_cineS2v5 = {
.io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
NGENE_IO_TSOUT},
.demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
- .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
+ .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_probe, tuner_attach_probe},
.fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
.tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
.lnb = {0x0a, 0x08, 0x0b, 0x09},
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 13/16] cxd2099: Update to latest version
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (9 preceding siblings ...)
2011-07-03 16:59 ` [PATCH 12/16] ngene: Support DuoFlex CT attached to CineS2 and SaTiX-S2 Oliver Endriss
@ 2011-07-03 17:00 ` Oliver Endriss
2011-07-04 12:17 ` Issa Gorissen
2011-07-03 17:02 ` [PATCH 14/16] cxd2099: Codingstyle fixes Oliver Endriss
` (6 subsequent siblings)
17 siblings, 1 reply; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:00 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
From: Ralph Metzler <rmetzler@digitaldevices.de>
Import latest driver from ddbridge-0.6.1.tar.bz2.
Signed-off-by: Ralph Metzler <rmetzler@digitaldevices.de>
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/staging/cxd2099/cxd2099.c | 250 ++++++++++++++++++++++++-------------
drivers/staging/cxd2099/cxd2099.h | 16 ++-
2 files changed, 178 insertions(+), 88 deletions(-)
diff --git a/drivers/staging/cxd2099/cxd2099.c b/drivers/staging/cxd2099/cxd2099.c
index b49186c..803a592 100644
--- a/drivers/staging/cxd2099/cxd2099.c
+++ b/drivers/staging/cxd2099/cxd2099.c
@@ -1,7 +1,7 @@
/*
* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
*
- * Copyright (C) 2010 DigitalDevices UG
+ * Copyright (C) 2010-2011 Digital Devices GmbH
*
*
* This program is free software; you can redistribute it and/or
@@ -42,13 +42,13 @@ struct cxd {
struct dvb_ca_en50221 en;
struct i2c_adapter *i2c;
- u8 adr;
+ struct cxd2099_cfg cfg;
+
u8 regs[0x23];
u8 lastaddress;
u8 clk_reg_f;
u8 clk_reg_b;
int mode;
- u32 bitrate;
int ready;
int dr;
int slot_stat;
@@ -64,7 +64,7 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 data)
{
u8 m[2] = {reg, data};
- struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
+ struct i2c_msg msg = {.addr=adr, .flags=0, .buf=m, .len=2};
if (i2c_transfer(adapter, &msg, 1) != 1) {
printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n",
@@ -77,7 +77,7 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
static int i2c_write(struct i2c_adapter *adapter, u8 adr,
u8 *data, u8 len)
{
- struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
+ struct i2c_msg msg = {.addr=adr, .flags=0, .buf=data, .len=len};
if (i2c_transfer(adapter, &msg, 1) != 1) {
printk(KERN_ERR "Failed to write to I2C!\n");
@@ -90,9 +90,9 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 *val)
{
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
- .buf = ®, .len = 1 },
+ .buf = ®, .len = 1},
{.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1 } };
+ .buf = val, .len = 1}};
if (i2c_transfer(adapter, msgs, 2) != 2) {
printk(KERN_ERR "error in i2c_read_reg\n");
@@ -105,9 +105,9 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 *data, u8 n)
{
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
- .buf = ®, .len = 1 },
- {.addr = adr, .flags = I2C_M_RD,
- .buf = data, .len = n } };
+ .buf = ®, .len = 1},
+ {.addr = adr, .flags = I2C_M_RD,
+ .buf = data, .len = n}};
if (i2c_transfer(adapter, msgs, 2) != 2) {
printk(KERN_ERR "error in i2c_read\n");
@@ -120,10 +120,10 @@ static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n)
{
int status;
- status = i2c_write_reg(ci->i2c, ci->adr, 0, adr);
+ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
if (!status) {
ci->lastaddress = adr;
- status = i2c_read(ci->i2c, ci->adr, 1, data, n);
+ status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n);
}
return status;
}
@@ -137,24 +137,24 @@ static int read_reg(struct cxd *ci, u8 reg, u8 *val)
static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
- u8 addr[3] = { 2, address&0xff, address>>8 };
+ u8 addr[3] = {2, address & 0xff, address >> 8};
- status = i2c_write(ci->i2c, ci->adr, addr, 3);
+ status=i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
- status = i2c_read(ci->i2c, ci->adr, 3, data, n);
+ status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
return status;
}
static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
- u8 addr[3] = { 2, address&0xff, address>>8 };
+ u8 addr[3] = {2, address & 0xff, address >> 8};
- status = i2c_write(ci->i2c, ci->adr, addr, 3);
+ status=i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status) {
u8 buf[256] = {3};
memcpy(buf+1, data, n);
- status = i2c_write(ci->i2c, ci->adr, buf, n+1);
+ status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
}
return status;
}
@@ -162,39 +162,64 @@ static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
static int read_io(struct cxd *ci, u16 address, u8 *val)
{
int status;
- u8 addr[3] = { 2, address&0xff, address>>8 };
+ u8 addr[3] = {2, address & 0xff, address >> 8};
- status = i2c_write(ci->i2c, ci->adr, addr, 3);
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
- status = i2c_read(ci->i2c, ci->adr, 3, val, 1);
+ status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
return status;
}
static int write_io(struct cxd *ci, u16 address, u8 val)
{
int status;
- u8 addr[3] = { 2, address&0xff, address>>8 };
- u8 buf[2] = { 3, val };
+ u8 addr[3] = {2, address & 0xff, address >> 8};
+ u8 buf[2] = {3, val};
- status = i2c_write(ci->i2c, ci->adr, addr, 3);
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
- status = i2c_write(ci->i2c, ci->adr, buf, 2);
-
+ status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
return status;
}
+#if 0
+static int read_io_data(struct cxd *ci, u8 *data, u8 n)
+{
+ int status;
+ u8 addr[3] = { 2, 0, 0 };
+
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
+ if (!status)
+ status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
+ return 0;
+}
+
+static int write_io_data(struct cxd *ci, u8 *data, u8 n)
+{
+ int status;
+ u8 addr[3] = {2, 0, 0};
+
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
+ if (!status) {
+ u8 buf[256] = {3};
+ memcpy(buf+1, data, n);
+ status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
+ }
+ return 0;
+}
+#endif
static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
int status;
- status = i2c_write_reg(ci->i2c, ci->adr, 0, reg);
- if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
- status = i2c_read_reg(ci->i2c, ci->adr, 1, &ci->regs[reg]);
- ci->regs[reg] = (ci->regs[reg]&(~mask))|val;
+ status=i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
+ if (!status && reg >= 6 && reg <=8 && mask != 0xff)
+ status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
+ ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
if (!status) {
ci->lastaddress = reg;
- status = i2c_write_reg(ci->i2c, ci->adr, 1, ci->regs[reg]);
+ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
}
if (reg == 0x20)
ci->regs[reg] &= 0x7f;
@@ -212,11 +237,11 @@ static int write_block(struct cxd *ci, u8 adr, u8 *data, int n)
int status;
u8 buf[256] = {1};
- status = i2c_write_reg(ci->i2c, ci->adr, 0, adr);
+ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
if (!status) {
ci->lastaddress = adr;
- memcpy(buf+1, data, n);
- status = i2c_write(ci->i2c, ci->adr, buf, n+1);
+ memcpy(buf + 1, data, n);
+ status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
}
return status;
}
@@ -250,12 +275,16 @@ static void cam_mode(struct cxd *ci, int mode)
write_regm(ci, 0x20, 0x80, 0x80);
break;
case 0x01:
+#ifdef BUFFER_MODE
+ if (!ci->en.read_data)
+ return;
printk(KERN_INFO "enable cam buffer mode\n");
/* write_reg(ci, 0x0d, 0x00); */
/* write_reg(ci, 0x0e, 0x01); */
write_regm(ci, 0x08, 0x40, 0x40);
/* read_reg(ci, 0x12, &dummy); */
write_regm(ci, 0x08, 0x80, 0x80);
+#endif
break;
default:
break;
@@ -265,14 +294,14 @@ static void cam_mode(struct cxd *ci, int mode)
-#define CHK_ERROR(s) if ((status = s)) break
+#define CHK_ERROR(s) if( (status = s) ) break
static int init(struct cxd *ci)
{
int status;
mutex_lock(&ci->lock);
- ci->mode = -1;
+ ci->mode=-1;
do {
CHK_ERROR(write_reg(ci, 0x00, 0x00));
CHK_ERROR(write_reg(ci, 0x01, 0x00));
@@ -284,53 +313,84 @@ static int init(struct cxd *ci)
CHK_ERROR(write_reg(ci, 0x08, 0x28));
CHK_ERROR(write_reg(ci, 0x14, 0x20));
- CHK_ERROR(write_reg(ci, 0x09, 0x4D)); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
+ /* CHK_ERROR(write_reg(ci, 0x09, 0x4D));*/ /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
- /* Sync detector */
CHK_ERROR(write_reg(ci, 0x0B, 0x33));
CHK_ERROR(write_reg(ci, 0x0C, 0x33));
CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
- CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
+ CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f));
- CHK_ERROR(write_reg(ci, 0x20, 0x28)); /* Integer Divider, Falling Edge, Internal Sync, */
- CHK_ERROR(write_reg(ci, 0x21, 0x00)); /* MCLKI = TICLK/8 */
- CHK_ERROR(write_reg(ci, 0x22, 0x07)); /* MCLKI = TICLK/8 */
+ if (ci->cfg.clock_mode) {
+ if (ci->cfg.polarity) {
+ CHK_ERROR(write_reg(ci, 0x09, 0x6f));
+ } else {
+ CHK_ERROR(write_reg(ci, 0x09, 0x6d));
+ }
+ CHK_ERROR(write_reg(ci, 0x20, 0x68));
+ CHK_ERROR(write_reg(ci, 0x21, 0x00));
+ CHK_ERROR(write_reg(ci, 0x22, 0x02));
+ } else {
+ if (ci->cfg.polarity) {
+ CHK_ERROR(write_reg(ci, 0x09, 0x4f));
+ } else {
+ CHK_ERROR(write_reg(ci, 0x09, 0x4d));
+ }
+ CHK_ERROR(write_reg(ci, 0x20, 0x28));
+ CHK_ERROR(write_reg(ci, 0x21, 0x00));
+ CHK_ERROR(write_reg(ci, 0x22, 0x07));
+ }
- CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80)); /* Reset CAM state machine */
+ CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80));
+ CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02));
+ CHK_ERROR(write_reg(ci, 0x01, 0x04));
+ CHK_ERROR(write_reg(ci, 0x00, 0x31));
- CHK_ERROR(write_regm(ci, 0x03, 0x02, 02)); /* Enable IREQA Interrupt */
- CHK_ERROR(write_reg(ci, 0x01, 0x04)); /* Enable CD Interrupt */
- CHK_ERROR(write_reg(ci, 0x00, 0x31)); /* Enable TS1,Hot Swap,Slot A */
- CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08)); /* Put TS in bypass */
- ci->cammode = -1;
-#ifdef BUFFER_MODE
+ /* Put TS in bypass */
+ CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));
+ ci->cammode=-1;
cam_mode(ci, 0);
-#endif
- } while (0);
+ } while(0);
mutex_unlock(&ci->lock);
return 0;
}
-
static int read_attribute_mem(struct dvb_ca_en50221 *ca,
int slot, int address)
{
struct cxd *ci = ca->data;
+#if 0
+ if (ci->amem_read) {
+ if (address <=0 || address>1024)
+ return -EIO;
+ return ci->amem[address];
+ }
+
+ mutex_lock(&ci->lock);
+ write_regm(ci, 0x06, 0x00, 0x05);
+ read_pccard(ci, 0, &ci->amem[0], 128);
+ read_pccard(ci, 128, &ci->amem[0], 128);
+ read_pccard(ci, 256, &ci->amem[0], 128);
+ read_pccard(ci, 384, &ci->amem[0], 128);
+ write_regm(ci, 0x06, 0x05, 0x05);
+ mutex_unlock(&ci->lock);
+ return ci->amem[address];
+#else
u8 val;
mutex_lock(&ci->lock);
set_mode(ci, 1);
read_pccard(ci, address, &val, 1);
mutex_unlock(&ci->lock);
+ //printk("%02x:%02x\n", address,val);
return val;
+#endif
}
-
static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
int address, u8 value)
{
@@ -373,20 +433,41 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
+#if 0
+ write_reg(ci, 0x00, 0x21);
+ write_reg(ci, 0x06, 0x1F);
+ write_reg(ci, 0x00, 0x31);
+#else
+#if 0
+ write_reg(ci, 0x06, 0x1F);
+ write_reg(ci, 0x06, 0x2F);
+#else
cam_mode(ci, 0);
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
write_reg(ci, 0x00, 0x31);
write_regm(ci, 0x20, 0x80, 0x80);
write_reg(ci, 0x03, 0x02);
- ci->ready = 0;
- ci->mode = -1;
+ ci->ready=0;
+#endif
+#endif
+ ci->mode=-1;
{
int i;
- for (i = 0; i < 100; i++) {
+#if 0
+ u8 val;
+#endif
+ for (i=0; i<100;i++) {
msleep(10);
+#if 0
+ read_reg(ci, 0x06,&val);
+ printk(KERN_INFO "%d:%02x\n", i, val);
+ if (!(val&0x10))
+ break;
+#else
if (ci->ready)
break;
+#endif
}
}
mutex_unlock(&ci->lock);
@@ -400,12 +481,12 @@ static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
printk(KERN_INFO "slot_shutdown\n");
mutex_lock(&ci->lock);
- /* write_regm(ci, 0x09, 0x08, 0x08); */
- write_regm(ci, 0x20, 0x80, 0x80);
- write_regm(ci, 0x06, 0x07, 0x07);
+ write_regm(ci, 0x09, 0x08, 0x08);
+ write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
+ write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
ci->mode = -1;
mutex_unlock(&ci->lock);
- return 0; /* shutdown(ci); */
+ return 0;
}
static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
@@ -433,7 +514,7 @@ static int campoll(struct cxd *ci)
write_reg(ci, 0x05, istat);
if (istat&0x40) {
- ci->dr = 1;
+ ci->dr=1;
printk(KERN_INFO "DR\n");
}
if (istat&0x20)
@@ -445,22 +526,21 @@ static int campoll(struct cxd *ci)
read_reg(ci, 0x01, &slotstat);
if (!(2&slotstat)) {
if (!ci->slot_stat) {
- ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
+ ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_PRESENT;
write_regm(ci, 0x03, 0x08, 0x08);
}
} else {
if (ci->slot_stat) {
- ci->slot_stat = 0;
+ ci->slot_stat=0;
write_regm(ci, 0x03, 0x00, 0x08);
printk(KERN_INFO "NO CAM\n");
- ci->ready = 0;
+ ci->ready=0;
}
}
- if (istat&8 && ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
- ci->ready = 1;
- ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
- printk(KERN_INFO "READY\n");
+ if (istat&8 && ci->slot_stat==DVB_CA_EN50221_POLL_CAM_PRESENT) {
+ ci->ready=1;
+ ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_READY;
}
}
return 0;
@@ -481,7 +561,7 @@ static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
}
#ifdef BUFFER_MODE
-static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
+static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
u8 msb, lsb;
@@ -498,20 +578,20 @@ static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
mutex_lock(&ci->lock);
read_reg(ci, 0x0f, &msb);
read_reg(ci, 0x10, &lsb);
- len = (msb<<8)|lsb;
+ len=(msb<<8)|lsb;
read_block(ci, 0x12, ebuf, len);
- ci->dr = 0;
+ ci->dr=0;
mutex_unlock(&ci->lock);
return len;
}
-static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
+static int write_data(struct dvb_ca_en50221* ca, int slot, u8 * ebuf, int ecount)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
- printk(KERN_INFO "write_data %d\n", ecount);
+ printk("write_data %d\n", ecount);
write_reg(ci, 0x0d, ecount>>8);
write_reg(ci, 0x0e, ecount&0xff);
write_block(ci, 0x11, ebuf, ecount);
@@ -536,15 +616,15 @@ static struct dvb_ca_en50221 en_templ = {
};
-struct dvb_ca_en50221 *cxd2099_attach(u8 adr, void *priv,
+struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
+ void *priv,
struct i2c_adapter *i2c)
{
struct cxd *ci = 0;
- u32 bitrate = 62000000;
u8 val;
- if (i2c_read_reg(i2c, adr, 0, &val) < 0) {
- printk(KERN_ERR "No CXD2099 detected at %02x\n", adr);
+ if (i2c_read_reg(i2c, cfg->adr, 0, &val)<0) {
+ printk("No CXD2099 detected at %02x\n", cfg->adr);
return 0;
}
@@ -554,21 +634,21 @@ struct dvb_ca_en50221 *cxd2099_attach(u8 adr, void *priv,
memset(ci, 0, sizeof(*ci));
mutex_init(&ci->lock);
+ memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg));
ci->i2c = i2c;
- ci->adr = adr;
- ci->lastaddress = 0xff;
- ci->clk_reg_b = 0x4a;
- ci->clk_reg_f = 0x1b;
- ci->bitrate = bitrate;
+ ci->lastaddress=0xff;
+ ci->clk_reg_b=0x4a;
+ ci->clk_reg_f=0x1b;
memcpy(&ci->en, &en_templ, sizeof(en_templ));
- ci->en.data = ci;
+ ci->en.data=ci;
init(ci);
- printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->adr);
+ printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr);
return &ci->en;
}
+
EXPORT_SYMBOL(cxd2099_attach);
MODULE_DESCRIPTION("cxd2099");
-MODULE_AUTHOR("Ralph Metzler <rjkm@metzlerbros.de>");
+MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
diff --git a/drivers/staging/cxd2099/cxd2099.h b/drivers/staging/cxd2099/cxd2099.h
index bed54ff..cf26c93 100644
--- a/drivers/staging/cxd2099/cxd2099.h
+++ b/drivers/staging/cxd2099/cxd2099.h
@@ -1,7 +1,7 @@
/*
* cxd2099.h: Driver for the CXD2099AR Common Interface Controller
*
- * Copyright (C) 2010 DigitalDevices UG
+ * Copyright (C) 2010-2011 Digital Devices GmbH
*
*
* This program is free software; you can redistribute it and/or
@@ -27,11 +27,21 @@
#include <dvb_ca_en50221.h>
+struct cxd2099_cfg {
+ u32 bitrate;
+ u8 adr;
+ u8 polarity : 1;
+ u8 clock_mode : 1;
+};
+
#if defined(CONFIG_DVB_CXD2099) || \
(defined(CONFIG_DVB_CXD2099_MODULE) && defined(MODULE))
-struct dvb_ca_en50221 *cxd2099_attach(u8 adr, void *priv, struct i2c_adapter *i2c);
+struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
+ void *priv, struct i2c_adapter *i2c);
#else
-static inline struct dvb_ca_en50221 *cxd2099_attach(u8 adr, void *priv, struct i2c_adapter *i2c)
+
+static inline struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
+ void *priv, struct i2c_adapter *i2c);
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 13/16] cxd2099: Update to latest version
2011-07-03 17:00 ` [PATCH 13/16] cxd2099: Update to latest version Oliver Endriss
@ 2011-07-04 12:17 ` Issa Gorissen
0 siblings, 0 replies; 28+ messages in thread
From: Issa Gorissen @ 2011-07-04 12:17 UTC (permalink / raw)
To: Oliver Endriss; +Cc: linux-media, Mauro Carvalho Chehab, Ralph Metzler
On 03/07/2011 19:00, Oliver Endriss wrote:
> @@ -284,53 +313,84 @@ static int init(struct cxd *ci)
> CHK_ERROR(write_reg(ci, 0x08, 0x28));
> CHK_ERROR(write_reg(ci, 0x14, 0x20));
>
> - CHK_ERROR(write_reg(ci, 0x09, 0x4D)); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
> + /* CHK_ERROR(write_reg(ci, 0x09, 0x4D));*/ /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
> CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
>
> - /* Sync detector */
> CHK_ERROR(write_reg(ci, 0x0B, 0x33));
> CHK_ERROR(write_reg(ci, 0x0C, 0x33));
>
> CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
> CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
> CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
> - CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
> + CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f));
>
> - CHK_ERROR(write_reg(ci, 0x20, 0x28)); /* Integer Divider, Falling Edge, Internal Sync, */
> - CHK_ERROR(write_reg(ci, 0x21, 0x00)); /* MCLKI = TICLK/8 */
> - CHK_ERROR(write_reg(ci, 0x22, 0x07)); /* MCLKI = TICLK/8 */
> + if (ci->cfg.clock_mode) {
> + if (ci->cfg.polarity) {
> + CHK_ERROR(write_reg(ci, 0x09, 0x6f));
> + } else {
> + CHK_ERROR(write_reg(ci, 0x09, 0x6d));
> + }
> + CHK_ERROR(write_reg(ci, 0x20, 0x68));
> + CHK_ERROR(write_reg(ci, 0x21, 0x00));
> + CHK_ERROR(write_reg(ci, 0x22, 0x02));
When clock_mode = 1, you set MKCLI to 9MHz. Comments in this code would
be really nice. Used by ddbrige it seems.
> + } else {
> + if (ci->cfg.polarity) {
> + CHK_ERROR(write_reg(ci, 0x09, 0x4f));
> + } else {
> + CHK_ERROR(write_reg(ci, 0x09, 0x4d));
> + }
>
> + CHK_ERROR(write_reg(ci, 0x20, 0x28));
> + CHK_ERROR(write_reg(ci, 0x21, 0x00));
> + CHK_ERROR(write_reg(ci, 0x22, 0x07));
> + }
When clock_mode = 0, input ts is in serial mode C, MCLKI = TICLK / 8 ;
why not set register 0x20 to 0x8 only ? Also, no need to set 0x21 nor
0x22 which are only for serial input mode D. And only used by ngene it
seems. Is TICLK equal to the bitrate variable (62000000) ? If yes, then
MCLKI can only reach a value of ~7,8MHz, which is not the maximum speed
of CAMs. Is this on purpose ? Ngene chip limitation ?
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 14/16] cxd2099: Codingstyle fixes
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (10 preceding siblings ...)
2011-07-03 17:00 ` [PATCH 13/16] cxd2099: Update to latest version Oliver Endriss
@ 2011-07-03 17:02 ` Oliver Endriss
2011-07-03 17:03 ` [PATCH 15/16] ngene: Update for latest cxd2099 Oliver Endriss
` (5 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:02 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Codingstyle fixes.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/staging/cxd2099/cxd2099.c | 75 ++++++++++++++++++-------------------
drivers/staging/cxd2099/cxd2099.h | 6 +-
2 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/drivers/staging/cxd2099/cxd2099.c b/drivers/staging/cxd2099/cxd2099.c
index 803a592..6ec30c1 100644
--- a/drivers/staging/cxd2099/cxd2099.c
+++ b/drivers/staging/cxd2099/cxd2099.c
@@ -64,7 +64,7 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 data)
{
u8 m[2] = {reg, data};
- struct i2c_msg msg = {.addr=adr, .flags=0, .buf=m, .len=2};
+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
if (i2c_transfer(adapter, &msg, 1) != 1) {
printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n",
@@ -77,7 +77,7 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
static int i2c_write(struct i2c_adapter *adapter, u8 adr,
u8 *data, u8 len)
{
- struct i2c_msg msg = {.addr=adr, .flags=0, .buf=data, .len=len};
+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
if (i2c_transfer(adapter, &msg, 1) != 1) {
printk(KERN_ERR "Failed to write to I2C!\n");
@@ -92,7 +92,7 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = ®, .len = 1},
{.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1}};
+ .buf = val, .len = 1} };
if (i2c_transfer(adapter, msgs, 2) != 2) {
printk(KERN_ERR "error in i2c_read_reg\n");
@@ -107,7 +107,7 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr,
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = ®, .len = 1},
{.addr = adr, .flags = I2C_M_RD,
- .buf = data, .len = n}};
+ .buf = data, .len = n} };
if (i2c_transfer(adapter, msgs, 2) != 2) {
printk(KERN_ERR "error in i2c_read\n");
@@ -139,7 +139,7 @@ static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
- status=i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
return status;
@@ -150,7 +150,7 @@ static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
- status=i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
+ status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status) {
u8 buf[256] = {3};
memcpy(buf+1, data, n);
@@ -213,8 +213,8 @@ static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
int status;
- status=i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
- if (!status && reg >= 6 && reg <=8 && mask != 0xff)
+ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
+ if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
if (!status) {
@@ -294,14 +294,14 @@ static void cam_mode(struct cxd *ci, int mode)
-#define CHK_ERROR(s) if( (status = s) ) break
+#define CHK_ERROR(s) if ((status = s)) break
static int init(struct cxd *ci)
{
int status;
mutex_lock(&ci->lock);
- ci->mode=-1;
+ ci->mode = -1;
do {
CHK_ERROR(write_reg(ci, 0x00, 0x00));
CHK_ERROR(write_reg(ci, 0x01, 0x00));
@@ -322,7 +322,7 @@ static int init(struct cxd *ci)
CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
- CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f));
+ CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
if (ci->cfg.clock_mode) {
if (ci->cfg.polarity) {
@@ -352,9 +352,9 @@ static int init(struct cxd *ci)
/* Put TS in bypass */
CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));
- ci->cammode=-1;
+ ci->cammode = -1;
cam_mode(ci, 0);
- } while(0);
+ } while (0);
mutex_unlock(&ci->lock);
return 0;
@@ -366,7 +366,7 @@ static int read_attribute_mem(struct dvb_ca_en50221 *ca,
struct cxd *ci = ca->data;
#if 0
if (ci->amem_read) {
- if (address <=0 || address>1024)
+ if (address <= 0 || address > 1024)
return -EIO;
return ci->amem[address];
}
@@ -386,7 +386,7 @@ static int read_attribute_mem(struct dvb_ca_en50221 *ca,
set_mode(ci, 1);
read_pccard(ci, address, &val, 1);
mutex_unlock(&ci->lock);
- //printk("%02x:%02x\n", address,val);
+ /* printk(KERN_INFO "%02x:%02x\n", address,val); */
return val;
#endif
}
@@ -448,19 +448,19 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
write_reg(ci, 0x00, 0x31);
write_regm(ci, 0x20, 0x80, 0x80);
write_reg(ci, 0x03, 0x02);
- ci->ready=0;
+ ci->ready = 0;
#endif
#endif
- ci->mode=-1;
+ ci->mode = -1;
{
int i;
#if 0
u8 val;
#endif
- for (i=0; i<100;i++) {
+ for (i = 0; i < 100; i++) {
msleep(10);
#if 0
- read_reg(ci, 0x06,&val);
+ read_reg(ci, 0x06, &val);
printk(KERN_INFO "%d:%02x\n", i, val);
if (!(val&0x10))
break;
@@ -514,7 +514,7 @@ static int campoll(struct cxd *ci)
write_reg(ci, 0x05, istat);
if (istat&0x40) {
- ci->dr=1;
+ ci->dr = 1;
printk(KERN_INFO "DR\n");
}
if (istat&0x20)
@@ -526,21 +526,21 @@ static int campoll(struct cxd *ci)
read_reg(ci, 0x01, &slotstat);
if (!(2&slotstat)) {
if (!ci->slot_stat) {
- ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_PRESENT;
+ ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
write_regm(ci, 0x03, 0x08, 0x08);
}
} else {
if (ci->slot_stat) {
- ci->slot_stat=0;
+ ci->slot_stat = 0;
write_regm(ci, 0x03, 0x00, 0x08);
printk(KERN_INFO "NO CAM\n");
- ci->ready=0;
+ ci->ready = 0;
}
}
- if (istat&8 && ci->slot_stat==DVB_CA_EN50221_POLL_CAM_PRESENT) {
- ci->ready=1;
- ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_READY;
+ if (istat&8 && ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
+ ci->ready = 1;
+ ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
}
}
return 0;
@@ -561,7 +561,7 @@ static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
}
#ifdef BUFFER_MODE
-static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount)
+static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
u8 msb, lsb;
@@ -578,20 +578,20 @@ static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount)
mutex_lock(&ci->lock);
read_reg(ci, 0x0f, &msb);
read_reg(ci, 0x10, &lsb);
- len=(msb<<8)|lsb;
+ len = (msb<<8)|lsb;
read_block(ci, 0x12, ebuf, len);
- ci->dr=0;
+ ci->dr = 0;
mutex_unlock(&ci->lock);
return len;
}
-static int write_data(struct dvb_ca_en50221* ca, int slot, u8 * ebuf, int ecount)
+static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
- printk("write_data %d\n", ecount);
+ printk(kern_INFO "write_data %d\n", ecount);
write_reg(ci, 0x0d, ecount>>8);
write_reg(ci, 0x0e, ecount&0xff);
write_block(ci, 0x11, ebuf, ecount);
@@ -623,8 +623,8 @@ struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
struct cxd *ci = 0;
u8 val;
- if (i2c_read_reg(i2c, cfg->adr, 0, &val)<0) {
- printk("No CXD2099 detected at %02x\n", cfg->adr);
+ if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
+ printk(KERN_INFO "No CXD2099 detected at %02x\n", cfg->adr);
return 0;
}
@@ -636,17 +636,16 @@ struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
mutex_init(&ci->lock);
memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg));
ci->i2c = i2c;
- ci->lastaddress=0xff;
- ci->clk_reg_b=0x4a;
- ci->clk_reg_f=0x1b;
+ ci->lastaddress = 0xff;
+ ci->clk_reg_b = 0x4a;
+ ci->clk_reg_f = 0x1b;
memcpy(&ci->en, &en_templ, sizeof(en_templ));
- ci->en.data=ci;
+ ci->en.data = ci;
init(ci);
printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr);
return &ci->en;
}
-
EXPORT_SYMBOL(cxd2099_attach);
MODULE_DESCRIPTION("cxd2099");
diff --git a/drivers/staging/cxd2099/cxd2099.h b/drivers/staging/cxd2099/cxd2099.h
index cf26c93..75459d4 100644
--- a/drivers/staging/cxd2099/cxd2099.h
+++ b/drivers/staging/cxd2099/cxd2099.h
@@ -30,12 +30,12 @@
struct cxd2099_cfg {
u32 bitrate;
u8 adr;
- u8 polarity : 1;
- u8 clock_mode : 1;
+ u8 polarity:1;
+ u8 clock_mode:1;
};
#if defined(CONFIG_DVB_CXD2099) || \
- (defined(CONFIG_DVB_CXD2099_MODULE) && defined(MODULE))
+ (defined(CONFIG_DVB_CXD2099_MODULE) && defined(MODULE))
struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
void *priv, struct i2c_adapter *i2c);
#else
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 15/16] ngene: Update for latest cxd2099
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (11 preceding siblings ...)
2011-07-03 17:02 ` [PATCH 14/16] cxd2099: Codingstyle fixes Oliver Endriss
@ 2011-07-03 17:03 ` Oliver Endriss
2011-07-03 17:04 ` [PATCH 16/16] ngene: Strip dummy packets inserted by the driver Oliver Endriss
` (4 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:03 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
Modifications for latest cxd2099.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-core.c | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index fa4b3eb..df0f0bd 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -1582,11 +1582,18 @@ static int init_channels(struct ngene *dev)
return 0;
}
+static struct cxd2099_cfg cxd_cfg = {
+ .bitrate = 62000,
+ .adr = 0x40,
+ .polarity = 0,
+ .clock_mode = 0,
+};
+
static void cxd_attach(struct ngene *dev)
{
struct ngene_ci *ci = &dev->ci;
- ci->en = cxd2099_attach(0x40, dev, &dev->channel[0].i2c_adapter);
+ ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter);
ci->dev = dev;
return;
}
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 16/16] ngene: Strip dummy packets inserted by the driver
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (12 preceding siblings ...)
2011-07-03 17:03 ` [PATCH 15/16] ngene: Update for latest cxd2099 Oliver Endriss
@ 2011-07-03 17:04 ` Oliver Endriss
2011-07-03 17:54 ` [PATCH 04/16] DRX-K: Shrink size of drxk_map.h Oliver Endriss
` (3 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:04 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
As the CI requires a continuous data stream, the driver inserts dummy
packets when necessary. Do not pass these packets to userspace anymore.
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
---
drivers/media/dvb/ngene/ngene-core.c | 2 +-
drivers/media/dvb/ngene/ngene-dvb.c | 42 +++++++++++++++++++++++++++++-----
drivers/media/dvb/ngene/ngene.h | 2 +
3 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index df0f0bd..f129a93 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -507,7 +507,7 @@ void FillTSBuffer(void *Buffer, int Length, u32 Flags)
{
u32 *ptr = Buffer;
- memset(Buffer, 0xff, Length);
+ memset(Buffer, TS_FILLER, Length);
while (Length > 0) {
if (Flags & DF_SWAP32)
*ptr = 0x471FFF10;
diff --git a/drivers/media/dvb/ngene/ngene-dvb.c b/drivers/media/dvb/ngene/ngene-dvb.c
index ba209cb..fcb16a6 100644
--- a/drivers/media/dvb/ngene/ngene-dvb.c
+++ b/drivers/media/dvb/ngene/ngene-dvb.c
@@ -118,6 +118,16 @@ static void swap_buffer(u32 *p, u32 len)
}
}
+/* start of filler packet */
+static u8 fill_ts[] = { 0x47, 0x1f, 0xff, 0x10, TS_FILLER };
+
+/* #define DEBUG_CI_XFER */
+#ifdef DEBUG_CI_XFER
+static u32 ok;
+static u32 overflow;
+static u32 stripped;
+#endif
+
void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
{
struct ngene_channel *chan = priv;
@@ -126,21 +136,41 @@ void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
if (flags & DF_SWAP32)
swap_buffer(buf, len);
+
if (dev->ci.en && chan->number == 2) {
- if (dvb_ringbuffer_free(&dev->tsin_rbuf) > len) {
- dvb_ringbuffer_write(&dev->tsin_rbuf, buf, len);
- wake_up_interruptible(&dev->tsin_rbuf.queue);
+ while (len >= 188) {
+ if (memcmp(buf, fill_ts, sizeof fill_ts) != 0) {
+ if (dvb_ringbuffer_free(&dev->tsin_rbuf) >= 188) {
+ dvb_ringbuffer_write(&dev->tsin_rbuf, buf, 188);
+ wake_up(&dev->tsin_rbuf.queue);
+#ifdef DEBUG_CI_XFER
+ ok++;
+#endif
+ }
+#ifdef DEBUG_CI_XFER
+ else
+ overflow++;
+#endif
+ }
+#ifdef DEBUG_CI_XFER
+ else
+ stripped++;
+
+ if (ok % 100 == 0 && overflow)
+ printk(KERN_WARNING "%s: ok %u overflow %u dropped %u\n", __func__, ok, overflow, stripped);
+#endif
+ buf += 188;
+ len -= 188;
}
- return 0;
+ return NULL;
}
+
if (chan->users > 0)
dvb_dmx_swfilter(&chan->demux, buf, len);
return NULL;
}
-u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
-
void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
{
struct ngene_channel *chan = priv;
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
index 90fa136..5443dc0 100644
--- a/drivers/media/dvb/ngene/ngene.h
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -789,6 +789,8 @@ struct ngene {
u8 uart_rbuf[UART_RBUF_LEN];
int uart_rp, uart_wp;
+#define TS_FILLER 0x6f
+
u8 *tsout_buf;
#define TSOUT_BUF_SIZE (512*188*8)
struct dvb_ringbuffer tsout_rbuf;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH 04/16] DRX-K: Shrink size of drxk_map.h
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (13 preceding siblings ...)
2011-07-03 17:04 ` [PATCH 16/16] ngene: Strip dummy packets inserted by the driver Oliver Endriss
@ 2011-07-03 17:54 ` Oliver Endriss
2011-07-03 17:55 ` [PATCH 03/16] DRX-K: Initial check-in Oliver Endriss
` (2 subsequent siblings)
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:54 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
As the patch is too large, it is available from here:
http://escape-edv.de/endriss/tmp/dvb-20110703/0004-drxk-Shrink-size-of-drxk_map.h.patch
CU
Oliver
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH 03/16] DRX-K: Initial check-in
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (14 preceding siblings ...)
2011-07-03 17:54 ` [PATCH 04/16] DRX-K: Shrink size of drxk_map.h Oliver Endriss
@ 2011-07-03 17:55 ` Oliver Endriss
2011-07-04 16:41 ` [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Hans von Marwijk
2011-07-11 11:57 ` Devin Heitmueller
17 siblings, 0 replies; 28+ messages in thread
From: Oliver Endriss @ 2011-07-03 17:55 UTC (permalink / raw)
To: linux-media; +Cc: Mauro Carvalho Chehab
As the patch is too large, it is available from here:
http://escape-edv.de/endriss/tmp/dvb-20110703/0003-drxk-Initial-check-in.patch
CU
Oliver
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (15 preceding siblings ...)
2011-07-03 17:55 ` [PATCH 03/16] DRX-K: Initial check-in Oliver Endriss
@ 2011-07-04 16:41 ` Hans von Marwijk
2011-07-07 23:39 ` Oliver Endriss
2011-07-11 11:57 ` Devin Heitmueller
17 siblings, 1 reply; 28+ messages in thread
From: Hans von Marwijk @ 2011-07-04 16:41 UTC (permalink / raw)
To: 'Oliver Endriss', linux-media; +Cc: 'Mauro Carvalho Chehab'
Hi
In which GIT or HG repository can I find these patches.
drivers/media/dvb/ngene/ngene-core.c
...
Regards
Eckhard
> -----Original Message-----
> From: linux-media-owner@vger.kernel.org [mailto:linux-media-owner@vger.kernel.org] On Behalf Of Oliver Endriss
> Sent: 03 July 2011 18:31
> To: linux-media@vger.kernel.org
> Cc: Mauro Carvalho Chehab
> Subject: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
>
> [PATCH 01/16] tda18271c2dd: Initial check-in
> [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes
> [PATCH 03/16] DRX-K: Initial check-in
> [PATCH 04/16] DRX-K: Shrink size of drxk_map.h
> [PATCH 05/16] DRX-K: Tons of coding-style fixes
> [PATCH 06/16] DRX-K, TDA18271c2: Add build support
> [PATCH 07/16] get_dvb_firmware: Get DRX-K firmware for Digital Devices DVB-CT cards
> [PATCH 08/16] ngene: Support Digital Devices DuoFlex CT
> [PATCH 09/16] ngene: Coding style fixes
> [PATCH 10/16] ngene: Fix return code if no demux was found
> [PATCH 11/16] ngene: Fix name of Digital Devices PCIe/miniPCIe
> [PATCH 12/16] ngene: Support DuoFlex CT attached to CineS2 and SaTiX-S2
> [PATCH 13/16] cxd2099: Update to latest version
> [PATCH 14/16] cxd2099: Codingstyle fixes
> [PATCH 15/16] ngene: Update for latest cxd2099
> [PATCH 16/16] ngene: Strip dummy packets inserted by the driver
>
> --
> ----------------------------------------------------------------
> VDR Remote Plugin 0.4.0: http://www.escape-edv.de/endriss/vdr/
> 4 MByte Mod: http://www.escape-edv.de/endriss/dvb-mem-mod/
> Full-TS Mod: http://www.escape-edv.de/endriss/dvb-full-ts-mod/
> ----------------------------------------------------------------
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
` (16 preceding siblings ...)
2011-07-04 16:41 ` [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Hans von Marwijk
@ 2011-07-11 11:57 ` Devin Heitmueller
2011-07-11 16:18 ` Ralph Metzler
17 siblings, 1 reply; 28+ messages in thread
From: Devin Heitmueller @ 2011-07-11 11:57 UTC (permalink / raw)
To: Oliver Endriss; +Cc: linux-media, Mauro Carvalho Chehab, Michael Krufky
On Sun, Jul 3, 2011 at 12:31 PM, Oliver Endriss <o.endriss@gmx.de> wrote:
> [PATCH 01/16] tda18271c2dd: Initial check-in
> [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes
Oliver,
Why the new driver for the 18271c2? There is already such a driver,
and in the past we've rejected multiple drivers for the same chip
unless there is a *very* compelling reason to do such.
The existing 18271 driver supports the C2 and is actively maintained.
Devin
--
Devin J. Heitmueller - Kernel Labs
http://www.kernellabs.com
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 11:57 ` Devin Heitmueller
@ 2011-07-11 16:18 ` Ralph Metzler
2011-07-11 16:27 ` Devin Heitmueller
2011-07-12 18:21 ` Michael Krufky
0 siblings, 2 replies; 28+ messages in thread
From: Ralph Metzler @ 2011-07-11 16:18 UTC (permalink / raw)
To: Devin Heitmueller
Cc: Oliver Endriss, linux-media, Mauro Carvalho Chehab, Michael Krufky
Hi Devin,
Devin Heitmueller writes:
> On Sun, Jul 3, 2011 at 12:31 PM, Oliver Endriss <o.endriss@gmx.de> wrote:
> > [PATCH 01/16] tda18271c2dd: Initial check-in
> > [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes
>
> Oliver,
>
> Why the new driver for the 18271c2? There is already such a driver,
> and in the past we've rejected multiple drivers for the same chip
> unless there is a *very* compelling reason to do such.
>
> The existing 18271 driver supports the C2 and is actively maintained.
>
AFAIR, there were at least 2 reasons.
One was that the existing driver does not accept 2 (or even 4) tuners with the
same address (but behind different demods) on the same I2C bus which
is the case on duoflex C/T addon cards.
The other was that it does not give back the intermediate frequency
which the demod needs. (This is currently done by misusing
get_frequency() but I added a get_if() call in newer internal versions
which should be added to dvb-core/dvb_frontend.h)
Feel free to change ngene/ddbridge to use the existing driver but it
will need some major changes in tda18271_attach() and a few other places.
Regards,
Ralph
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 16:18 ` Ralph Metzler
@ 2011-07-11 16:27 ` Devin Heitmueller
2011-07-11 17:15 ` Ralph Metzler
2011-07-11 17:19 ` Mauro Carvalho Chehab
2011-07-12 18:21 ` Michael Krufky
1 sibling, 2 replies; 28+ messages in thread
From: Devin Heitmueller @ 2011-07-11 16:27 UTC (permalink / raw)
To: Ralph Metzler
Cc: Oliver Endriss, linux-media, Mauro Carvalho Chehab, Michael Krufky
Hi Ralph,
Good to hear from you.
> AFAIR, there were at least 2 reasons.
> One was that the existing driver does not accept 2 (or even 4) tuners with the
> same address (but behind different demods) on the same I2C bus which
> is the case on duoflex C/T addon cards.
Do you mean that you are relying solely on the i2c gates on the
"other" demods being closed so that the tuners associated with the
other inputs do not receive the commands? If so, that would
definitely create the need for some weird locking structure (since
today demods typically do not manage their i2c gates in tandem).
> The other was that it does not give back the intermediate frequency
> which the demod needs. (This is currently done by misusing
> get_frequency() but I added a get_if() call in newer internal versions
> which should be added to dvb-core/dvb_frontend.h)
Generally speaking with other devices the IF is configured for the
tuner depending on the target modulation (there is a tda18271_config
struct passed at attach time containing the IF for various modes).
Then the demod driver is also configured for a particular IF.
Are you changing the IF based on something other than the target
modulation type? Or do you need to vary the IF based on different
frequencies within the same modulation?
> Feel free to change ngene/ddbridge to use the existing driver but it
> will need some major changes in tda18271_attach() and a few other places.
If there are indeed good reasons, then so be it. But it feels like we
are working around deficiencies in the core DVB framework that would
apply to all drivers, and it would be good if we could avoid the
maintenance headaches associated with two different drivers for the
same chip.
Devin
--
Devin J. Heitmueller - Kernel Labs
http://www.kernellabs.com
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 16:27 ` Devin Heitmueller
@ 2011-07-11 17:15 ` Ralph Metzler
2011-07-11 17:32 ` Devin Heitmueller
2011-07-11 17:19 ` Mauro Carvalho Chehab
1 sibling, 1 reply; 28+ messages in thread
From: Ralph Metzler @ 2011-07-11 17:15 UTC (permalink / raw)
To: Devin Heitmueller
Cc: Oliver Endriss, linux-media, Mauro Carvalho Chehab, Michael Krufky
Devin Heitmueller writes:
> Hi Ralph,
>
> Good to hear from you.
>
> > AFAIR, there were at least 2 reasons.
> > One was that the existing driver does not accept 2 (or even 4) tuners with the
> > same address (but behind different demods) on the same I2C bus which
> > is the case on duoflex C/T addon cards.
>
> Do you mean that you are relying solely on the i2c gates on the
> "other" demods being closed so that the tuners associated with the
> other inputs do not receive the commands? If so, that would
> definitely create the need for some weird locking structure (since
> today demods typically do not manage their i2c gates in tandem).
Yes, gate openings are locked against each other in the bridge drivers.
> > The other was that it does not give back the intermediate frequency
> > which the demod needs. (This is currently done by misusing
> > get_frequency() but I added a get_if() call in newer internal versions
> > which should be added to dvb-core/dvb_frontend.h)
>
> Generally speaking with other devices the IF is configured for the
> tuner depending on the target modulation (there is a tda18271_config
> struct passed at attach time containing the IF for various modes).
> Then the demod driver is also configured for a particular IF.
You mean the optional "struct tda18271_std_map *std_map;"?
That would be a possibility. But then you have to handle IF tables for
all kinds of tuners and demods in the bridge driver.
Letting the tuner choose the IF and have a way to tell the demod (a simple
get_if() call) is much easier.
> Are you changing the IF based on something other than the target
> modulation type? Or do you need to vary the IF based on different
> frequencies within the same modulation?
No.
> > Feel free to change ngene/ddbridge to use the existing driver but it
> > will need some major changes in tda18271_attach() and a few other places.
>
> If there are indeed good reasons, then so be it. But it feels like we
> are working around deficiencies in the core DVB framework that would
> apply to all drivers, and it would be good if we could avoid the
> maintenance headaches associated with two different drivers for the
> same chip.
I know. At the time I was also just porting the DRX-K and only wanted
to get it working based on the known to work Windows driver
combination and not wrestle with other problems.
I guess it whould not be too hard to adapt the old driver now.
Another problem that keeps showing up in the existing drivers is that
some tuner/demod combinations let the tuner call gate_ctrl, others
only call it in the demod.
This leads to problems when trying to use them in new combinations.
Either the gate is not opened/closed at all or twice. In the latter
case this can even lead to lockups if also using locking.
Regards,
Ralph
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 17:15 ` Ralph Metzler
@ 2011-07-11 17:32 ` Devin Heitmueller
0 siblings, 0 replies; 28+ messages in thread
From: Devin Heitmueller @ 2011-07-11 17:32 UTC (permalink / raw)
To: Ralph Metzler
Cc: Oliver Endriss, linux-media, Mauro Carvalho Chehab, Michael Krufky
On Mon, Jul 11, 2011 at 1:15 PM, Ralph Metzler <rjkm@metzlerbros.de> wrote:
> > Generally speaking with other devices the IF is configured for the
> > tuner depending on the target modulation (there is a tda18271_config
> > struct passed at attach time containing the IF for various modes).
> > Then the demod driver is also configured for a particular IF.
>
> You mean the optional "struct tda18271_std_map *std_map;"?
> That would be a possibility. But then you have to handle IF tables for
> all kinds of tuners and demods in the bridge driver.
> Letting the tuner choose the IF and have a way to tell the demod (a simple
> get_if() call) is much easier.
The downside of the approach you've suggested is it prevents the tuner
driver from varying the IF based on the demod it is interacting with.
By having the information defined in the bridge driver, the IF can be
defined by the driver developer based on the attached demod. Also, in
some cases the IF needs to different because of the PCB layout (rather
than just the chosen modulation or what demod it is attached to),
which there is no way a tuner driver could know that based solely on
what tuner/demod is being used.
In other words, in some cases the optimal IF for a given hardware
design is determined by cycling through the various possible values
with a spectrum analyzer attached, and that is the sort of
optimization that is defined in the bridge driver where it is known
exactly what product is being used.
> > If there are indeed good reasons, then so be it. But it feels like we
> > are working around deficiencies in the core DVB framework that would
> > apply to all drivers, and it would be good if we could avoid the
> > maintenance headaches associated with two different drivers for the
> > same chip.
>
> I know. At the time I was also just porting the DRX-K and only wanted
> to get it working based on the known to work Windows driver
> combination and not wrestle with other problems.
> I guess it whould not be too hard to adapt the old driver now.
I can certainly appreciate this, as I've done this myself at times.
That said though, for upstream inclusion we generally want to clean up
such issues.
> Another problem that keeps showing up in the existing drivers is that
> some tuner/demod combinations let the tuner call gate_ctrl, others
> only call it in the demod.
> This leads to problems when trying to use them in new combinations.
> Either the gate is not opened/closed at all or twice. In the latter
> case this can even lead to lockups if also using locking.
Yeah, this is a bit of a mess. Whether it's done in the demod or the
tuner is typically dictated by what driver the developer happened to
have copied as skeleton code. There are certainly merits to both
approaches under certain conditions, but the inconsistency across
drivers is very annoying.
Devin
--
Devin J. Heitmueller - Kernel Labs
http://www.kernellabs.com
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 16:27 ` Devin Heitmueller
2011-07-11 17:15 ` Ralph Metzler
@ 2011-07-11 17:19 ` Mauro Carvalho Chehab
1 sibling, 0 replies; 28+ messages in thread
From: Mauro Carvalho Chehab @ 2011-07-11 17:19 UTC (permalink / raw)
To: Devin Heitmueller
Cc: Ralph Metzler, Oliver Endriss, linux-media, Michael Krufky
Hi Ralph and Devin,
Em 11-07-2011 13:27, Devin Heitmueller escreveu:
> Hi Ralph,
>
> Good to hear from you.
>
>> AFAIR, there were at least 2 reasons.
>> One was that the existing driver does not accept 2 (or even 4) tuners with the
>> same address (but behind different demods) on the same I2C bus which
>> is the case on duoflex C/T addon cards.
I2C core has now support for I2C switches, but I never used it.
I'm not against of merging the tda18271c2 at the short term, but the
both driver maintainers need to work on merging them into one driver
at the long term, to avoid duplicated maintenance efforts.
> Do you mean that you are relying solely on the i2c gates on the
> "other" demods being closed so that the tuners associated with the
> other inputs do not receive the commands? If so, that would
> definitely create the need for some weird locking structure (since
> today demods typically do not manage their i2c gates in tandem).
>
>> The other was that it does not give back the intermediate frequency
>> which the demod needs. (This is currently done by misusing
>> get_frequency() but I added a get_if() call in newer internal versions
>> which should be added to dvb-core/dvb_frontend.h)
>
> Generally speaking with other devices the IF is configured for the
> tuner depending on the target modulation (there is a tda18271_config
> struct passed at attach time containing the IF for various modes).
> Then the demod driver is also configured for a particular IF.
Yeah, with the current way, it is possible to make it work, by binding
tda18271 3 times (one for analog, one for DVB-T and another for DVB-C).
Some care should be taken at the frontend, to avoid it to create one
private instance of its management struct for each binding, but it
works fine. The hybrid_tuner_request_state() call does such trick.
It also works fine when analog is enabled.
> Are you changing the IF based on something other than the target
> modulation type? Or do you need to vary the IF based on different
> frequencies within the same modulation?
>
>> Feel free to change ngene/ddbridge to use the existing driver but it
>> will need some major changes in tda18271_attach() and a few other places.
>
> If there are indeed good reasons, then so be it. But it feels like we
> are working around deficiencies in the core DVB framework that would
> apply to all drivers, and it would be good if we could avoid the
> maintenance headaches associated with two different drivers for the
> same chip.
Agreed.
Ralph,
Could you please check if my patches didn't break for ngene/ddbridge?
I don't have any ngene/ddbrige here for testing. In special, I had to
add a fix for drxk module rmmod due to the way dvb_attach() works.
Thanks!
Mauro
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene
2011-07-11 16:18 ` Ralph Metzler
2011-07-11 16:27 ` Devin Heitmueller
@ 2011-07-12 18:21 ` Michael Krufky
1 sibling, 0 replies; 28+ messages in thread
From: Michael Krufky @ 2011-07-12 18:21 UTC (permalink / raw)
To: Ralph Metzler
Cc: Devin Heitmueller, Oliver Endriss, linux-media, Mauro Carvalho Chehab
On Mon, Jul 11, 2011 at 12:18 PM, Ralph Metzler <rjkm@metzlerbros.de> wrote:
> Hi Devin,
>
> Devin Heitmueller writes:
> > On Sun, Jul 3, 2011 at 12:31 PM, Oliver Endriss <o.endriss@gmx.de> wrote:
> > > [PATCH 01/16] tda18271c2dd: Initial check-in
> > > [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes
> >
> > Oliver,
> >
> > Why the new driver for the 18271c2? There is already such a driver,
> > and in the past we've rejected multiple drivers for the same chip
> > unless there is a *very* compelling reason to do such.
> >
> > The existing 18271 driver supports the C2 and is actively maintained.
> >
...not to mention that many bridge drivers are now depending on the
tda18271 tuner module - It's well-tested and proven to work properly
with a variety of different kinda of hardware.
> AFAIR, there were at least 2 reasons.
> One was that the existing driver does not accept 2 (or even 4) tuners with the
> same address (but behind different demods) on the same I2C bus which
> is the case on duoflex C/T addon cards.
This is a limitation with the hybrid_tuner_request_state - When
creating this mechanism, I foresaw this scenario, but didnt have a way
to test any solution. One way we can account for this would be to rev
hybrid_tuner_request_state to optionally take a unique identifier
rather than an i2c bus ID to identify the uniqueness of the tuner
instance...
> The other was that it does not give back the intermediate frequency
> which the demod needs. (This is currently done by misusing
> get_frequency() but I added a get_if() call in newer internal versions
> which should be added to dvb-core/dvb_frontend.h)
Why not add the get_if() call to the existing driver? Improvements
are always welcome :-)
> Feel free to change ngene/ddbridge to use the existing driver but it
> will need some major changes in tda18271_attach() and a few other places.
...the attach is the most insignificant part of the driver. If there
are limitations causing trouble for you, then we should look at those
limitations rather than duplicating a development effort.
Regards,
Mike Krufky
^ permalink raw reply [flat|nested] 28+ messages in thread