* [PATCH net-next 1/6] r8169: adjust some registers
@ 2011-07-05 9:44 Hayes Wang
2011-07-05 9:44 ` [PATCH net-next 2/6] r8169: modify the flow hw reset Hayes Wang
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw)
To: romieu; +Cc: netdev, linux-kernel, Hayes Wang
Define new registers and modify some existing ones.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
---
drivers/net/r8169.c | 30 +++++++++++++++++++++++-------
1 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index fbd6838..701ab6b 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -327,7 +327,7 @@ enum rtl8168_8101_registers {
#define EPHYAR_REG_SHIFT 16
#define EPHYAR_DATA_MASK 0xffff
DLLPR = 0xd0,
-#define PM_SWITCH (1 << 6)
+#define PFM_EN (1 << 6)
DBG_REG = 0xd1,
#define FIX_NAK_1 (1 << 4)
#define FIX_NAK_2 (1 << 3)
@@ -335,6 +335,7 @@ enum rtl8168_8101_registers {
MCU = 0xd3,
#define EN_NDP (1 << 3)
#define EN_OOB_RESET (1 << 2)
+#define NOW_IS_OOB (1 << 7)
EFUSEAR = 0xdc,
#define EFUSEAR_FLAG 0x80000000
#define EFUSEAR_WRITE_CMD 0x80000000
@@ -345,18 +346,31 @@ enum rtl8168_8101_registers {
};
enum rtl8168_registers {
+ LED_FREQ = 0x1a,
+ EEE_LED = 0x1b,
+
+ /* TxConfig */
+#define AUTO_FIFO (1 << 7)
+#define TX_EMPTY (1 << 11)
+
+ /* RxConfig */
+#define RX128_INT_EN (1 << 15) /* 8111c and later */
+#define RX_MULTI_EN (1 << 14) /* 8111c only */
+
ERIDR = 0x70,
ERIAR = 0x74,
#define ERIAR_FLAG 0x80000000
#define ERIAR_WRITE_CMD 0x80000000
#define ERIAR_READ_CMD 0x00000000
#define ERIAR_ADDR_BYTE_ALIGN 4
-#define ERIAR_EXGMAC 0
-#define ERIAR_MSIX 1
-#define ERIAR_ASF 2
#define ERIAR_TYPE_SHIFT 16
-#define ERIAR_BYTEEN 0x0f
-#define ERIAR_BYTEEN_SHIFT 12
+#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
+#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
+#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
+#define ERIAR_MASK_SHIFT 12
+#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
+#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
+#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
EPHY_RXER_NUM = 0x7c,
OCPDR = 0xb0, /* OCP GPHY access */
#define OCPDR_WRITE_CMD 0x80000000
@@ -371,6 +385,7 @@ enum rtl8168_registers {
RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
MISC = 0xf0, /* 8168e only. */
#define TXPLA_RST (1 << 29)
+#define PWM_EN (1 << 22)
};
enum rtl_register_content {
@@ -395,6 +410,7 @@ enum rtl_register_content {
RxCRC = (1 << 19),
/* ChipCmdBits */
+ StopReq = 0x80,
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
@@ -4368,7 +4384,7 @@ static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
- RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
+ RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
}
--
1.7.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH net-next 2/6] r8169: modify the flow hw reset 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang @ 2011-07-05 9:44 ` Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 3/6] r8169: adjust the settings about RxConfig Hayes Wang ` (4 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Replace rtl8169_asic_down with rtl8169_hw_reset. Clear RxConfig bit 0 ~ 3 and do some checking before reset. Remove hw reset which is before hw_start because reset would be done in close or down. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 701ab6b..cdbbe47 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -731,6 +731,8 @@ static int rtl8169_poll(struct napi_struct *napi, int budget); static const unsigned int rtl8169_rx_config = (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); +static void rtl8169_init_ring_indexes(struct rtl8169_private *tp); + static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) { void __iomem *ioaddr = tp->mmio_addr; @@ -1076,13 +1078,6 @@ static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) RTL_W16(IntrStatus, 0xffff); } -static void rtl8169_asic_down(void __iomem *ioaddr) -{ - RTL_W8(ChipCmd, 0x00); - rtl8169_irq_mask_and_ack(ioaddr); - RTL_R16(CPlusCmd); -} - static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; @@ -3352,10 +3347,12 @@ static void rtl_hw_reset(struct rtl8169_private *tp) /* Check that the chip has finished the reset. */ for (i = 0; i < 100; i++) { + udelay(100); if ((RTL_R8(ChipCmd) & CmdReset) == 0) break; - msleep_interruptible(1); } + + rtl8169_init_ring_indexes(tp); } static int __devinit @@ -3737,6 +3734,16 @@ err_pm_runtime_put: goto out; } +static void rtl_rx_close(struct rtl8169_private *tp) +{ + void __iomem *ioaddr = tp->mmio_addr; + u32 rxcfg = RTL_R32(RxConfig); + + rxcfg &= ~(AcceptBroadcast | AcceptMulticast | + AcceptMyPhys | AcceptAllPhys); + RTL_W32(RxConfig, rxcfg); +} + static void rtl8169_hw_reset(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; @@ -3744,19 +3751,20 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) /* Disable interrupts */ rtl8169_irq_mask_and_ack(ioaddr); + rtl_rx_close(tp); + if (tp->mac_version == RTL_GIGA_MAC_VER_27 || tp->mac_version == RTL_GIGA_MAC_VER_28 || tp->mac_version == RTL_GIGA_MAC_VER_31) { while (RTL_R8(TxPoll) & NPQ) udelay(20); + } else { + RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); + udelay(100); } - /* Reset the chipset */ - RTL_W8(ChipCmd, CmdReset); - - /* PCI commit */ - RTL_R8(ChipCmd); + rtl_hw_reset(tp); } static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) @@ -3776,8 +3784,6 @@ static void rtl_hw_start(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); - rtl_hw_reset(tp); - tp->hw_start(dev); netif_start_queue(dev); @@ -4718,7 +4724,6 @@ static void rtl8169_reset_task(struct work_struct *work) rtl8169_tx_clear(tp); - rtl8169_init_ring_indexes(tp); rtl_hw_start(dev); netif_wake_queue(dev); rtl8169_check_link_status(dev, tp, tp->mmio_addr); @@ -5132,7 +5137,7 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) * the chip, so just exit the loop. */ if (unlikely(!netif_running(dev))) { - rtl8169_asic_down(ioaddr); + rtl8169_hw_reset(tp); break; } @@ -5255,7 +5260,7 @@ static void rtl8169_down(struct net_device *dev) spin_lock_irq(&tp->lock); - rtl8169_asic_down(ioaddr); + rtl8169_hw_reset(tp); /* * At this point device interrupts can not be enabled in any function, * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, @@ -5509,7 +5514,7 @@ static void rtl_shutdown(struct pci_dev *pdev) spin_lock_irq(&tp->lock); - rtl8169_asic_down(ioaddr); + rtl8169_hw_reset(tp); spin_unlock_irq(&tp->lock); -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 2/6] r8169: modify the flow hw reset 2011-07-05 9:44 ` [PATCH net-next 2/6] r8169: modify the flow hw reset Hayes Wang @ 2011-07-05 18:55 ` Francois Romieu 2011-07-06 7:48 ` hayeswang 0 siblings, 1 reply; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:55 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : > Replace rtl8169_asic_down with rtl8169_hw_reset. Clear RxConfig > bit 0 ~ 3 and do some checking before reset. Remove hw reset > which is before hw_start because reset would be done in close or > down. The whole description of the changes ought to explain why things are changed. > Signed-off-by: Hayes Wang <hayeswang@realtek.com> > --- > drivers/net/r8169.c | 43 ++++++++++++++++++++++++------------------- > 1 files changed, 24 insertions(+), 19 deletions(-) > > diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c > index 701ab6b..cdbbe47 100644 > --- a/drivers/net/r8169.c > +++ b/drivers/net/r8169.c > @@ -731,6 +731,8 @@ static int rtl8169_poll(struct napi_struct *napi, int budget); > static const unsigned int rtl8169_rx_config = > (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); > > +static void rtl8169_init_ring_indexes(struct rtl8169_private *tp); > + rtl8169_init_ring_indexes is really short. Please move it before its first use and avoid the forward declaration. > static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) > { > void __iomem *ioaddr = tp->mmio_addr; > @@ -1076,13 +1078,6 @@ static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) > RTL_W16(IntrStatus, 0xffff); > } > > -static void rtl8169_asic_down(void __iomem *ioaddr) > -{ > - RTL_W8(ChipCmd, 0x00); > - rtl8169_irq_mask_and_ack(ioaddr); > - RTL_R16(CPlusCmd); > -} > - > static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) > { > void __iomem *ioaddr = tp->mmio_addr; > @@ -3352,10 +3347,12 @@ static void rtl_hw_reset(struct rtl8169_private *tp) > > /* Check that the chip has finished the reset. */ > for (i = 0; i < 100; i++) { > + udelay(100); > if ((RTL_R8(ChipCmd) & CmdReset) == 0) > break; Nit: is it forbidden to perform the read - and thus the implicit PCI flush - before the first 100 us delay ? > - msleep_interruptible(1); > } > + > + rtl8169_init_ring_indexes(tp); > } > > static int __devinit > @@ -3737,6 +3734,16 @@ err_pm_runtime_put: > goto out; > } > > +static void rtl_rx_close(struct rtl8169_private *tp) > +{ > + void __iomem *ioaddr = tp->mmio_addr; > + u32 rxcfg = RTL_R32(RxConfig); > + > + rxcfg &= ~(AcceptBroadcast | AcceptMulticast | > + AcceptMyPhys | AcceptAllPhys); > + RTL_W32(RxConfig, rxcfg); > +} > + Should not error and runt packets be considered too ? <shot in the dark> Is there any relationship with commit ca52efd5490f97f396d3c5863ba714624f272033 ? </shot in the dark> > static void rtl8169_hw_reset(struct rtl8169_private *tp) > { > void __iomem *ioaddr = tp->mmio_addr; > @@ -3744,19 +3751,20 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) > /* Disable interrupts */ > rtl8169_irq_mask_and_ack(ioaddr); > > + rtl_rx_close(tp); > + > if (tp->mac_version == RTL_GIGA_MAC_VER_27 || > tp->mac_version == RTL_GIGA_MAC_VER_28 || > tp->mac_version == RTL_GIGA_MAC_VER_31) { > while (RTL_R8(TxPoll) & NPQ) > udelay(20); > > + } else { > + RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); > + udelay(100); No posted PCI write flush ? Please remove the empty line after the udelay(20). It should not have been there in the first place. > } > > - /* Reset the chipset */ > - RTL_W8(ChipCmd, CmdReset); > - > - /* PCI commit */ > - RTL_R8(ChipCmd); > + rtl_hw_reset(tp); > } > > static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) > @@ -3776,8 +3784,6 @@ static void rtl_hw_start(struct net_device *dev) > { > struct rtl8169_private *tp = netdev_priv(dev); > > - rtl_hw_reset(tp); > - > tp->hw_start(dev); > > netif_start_queue(dev); > @@ -4718,7 +4724,6 @@ static void rtl8169_reset_task(struct work_struct *work) > > rtl8169_tx_clear(tp); > > - rtl8169_init_ring_indexes(tp); > rtl_hw_start(dev); > netif_wake_queue(dev); > rtl8169_check_link_status(dev, tp, tp->mmio_addr); I do not see where the ring indexes will be set when __rtl8169_resume() schedules rtl8169_reset_task. It could hurt. -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH net-next 2/6] r8169: modify the flow hw reset 2011-07-05 18:55 ` Francois Romieu @ 2011-07-06 7:48 ` hayeswang 0 siblings, 0 replies; 13+ messages in thread From: hayeswang @ 2011-07-06 7:48 UTC (permalink / raw) To: 'Francois Romieu'; +Cc: netdev, linux-kernel > -----Original Message----- > From: Francois Romieu [mailto:romieu@fr.zoreil.com] > Sent: Wednesday, July 06, 2011 2:55 AM > To: Hayeswang > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH net-next 2/6] r8169: modify the flow hw reset > > > > > +static void rtl_rx_close(struct rtl8169_private *tp) { > > + void __iomem *ioaddr = tp->mmio_addr; > > + u32 rxcfg = RTL_R32(RxConfig); > > + > > + rxcfg &= ~(AcceptBroadcast | AcceptMulticast | > > + AcceptMyPhys | AcceptAllPhys); > > + RTL_W32(RxConfig, rxcfg); > > +} > > + > > Should not error and runt packets be considered too ? > > <shot in the dark> > Is there any relationship with commit > ca52efd5490f97f396d3c5863ba714624f272033 ? > </shot in the dark> > No, there is no relationship about that. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next 3/6] r8169: adjust the settings about RxConfig 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang 2011-07-05 9:44 ` [PATCH net-next 2/6] r8169: modify the flow hw reset Hayes Wang @ 2011-07-05 9:44 ` Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 4/6] r8169: add ERI functions Hayes Wang ` (3 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Set the init value before reset in probe function. And then just modify the relative bits and keep the init settings. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 63 +++++++++++++++++++++++++++++++++++++------------- 1 files changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index cdbbe47..3aeae68 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -71,7 +71,7 @@ static const int multicast_filter_limit = 32; #define MAX_READ_REQUEST_SHIFT 12 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ -#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define RX_DMA_BURST 7 /* Maximum PCI burst, '7' is Unlimited */ #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ @@ -272,9 +272,6 @@ enum rtl_registers { IntrStatus = 0x3e, TxConfig = 0x40, RxConfig = 0x44, - -#define RTL_RX_CONFIG_MASK 0xff7e1880u - RxMissed = 0x4c, Cfg9346 = 0x50, Config0 = 0x51, @@ -727,10 +724,6 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); static void rtl8169_down(struct net_device *dev); static void rtl8169_rx_clear(struct rtl8169_private *tp); static int rtl8169_poll(struct napi_struct *napi, int budget); - -static const unsigned int rtl8169_rx_config = - (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); - static void rtl8169_init_ring_indexes(struct rtl8169_private *tp); static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) @@ -3337,6 +3330,45 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) } } +static void rtl_init_rxcfg(struct rtl8169_private *tp) +{ + void __iomem *ioaddr = tp->mmio_addr; + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_01: + case RTL_GIGA_MAC_VER_02: + case RTL_GIGA_MAC_VER_03: + case RTL_GIGA_MAC_VER_04: + case RTL_GIGA_MAC_VER_05: + case RTL_GIGA_MAC_VER_06: + case RTL_GIGA_MAC_VER_10: + case RTL_GIGA_MAC_VER_11: + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_13: + case RTL_GIGA_MAC_VER_14: + case RTL_GIGA_MAC_VER_15: + case RTL_GIGA_MAC_VER_16: + case RTL_GIGA_MAC_VER_17: + RTL_W32(RxConfig, (RX_FIFO_THRESH << RxCfgFIFOShift) | + (RX_DMA_BURST << RxCfgDMAShift)); + break; + case RTL_GIGA_MAC_VER_18: + case RTL_GIGA_MAC_VER_19: + case RTL_GIGA_MAC_VER_20: + case RTL_GIGA_MAC_VER_21: + case RTL_GIGA_MAC_VER_22: + case RTL_GIGA_MAC_VER_23: + case RTL_GIGA_MAC_VER_24: + RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | + (RX_DMA_BURST << RxCfgDMAShift)); + break; + default: + RTL_W32(RxConfig, RX128_INT_EN | + (RX_DMA_BURST << RxCfgDMAShift)); + break; + } +} + static void rtl_hw_reset(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; @@ -3459,6 +3491,11 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (!pci_is_pcie(pdev)) netif_info(tp, probe, dev, "not PCI Express\n"); + /* Identify chip attached to board */ + rtl8169_get_mac_version(tp, dev, cfg->default_ver); + + rtl_init_rxcfg(tp); + RTL_W16(IntrMask, 0x0000); rtl_hw_reset(tp); @@ -3467,9 +3504,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) pci_set_master(pdev); - /* Identify chip attached to board */ - rtl8169_get_mac_version(tp, dev, cfg->default_ver); - /* * Pretend we are using VLANs; This bypasses a nasty bug where * Interrupts stop flowing on high load on 8110SCd controllers. @@ -3770,10 +3804,6 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; - u32 cfg = rtl8169_rx_config; - - cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK); - RTL_W32(RxConfig, cfg); /* Set DMA burst size and Interframe Gap Time */ RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | @@ -5343,8 +5373,7 @@ static void rtl_set_rx_mode(struct net_device *dev) spin_lock_irqsave(&tp->lock, flags); - tmp = rtl8169_rx_config | rx_mode | - (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK); + tmp = RTL_R32(RxConfig) | rx_mode; if (tp->mac_version > RTL_GIGA_MAC_VER_06) { u32 data = mc_filter[0]; -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/6] r8169: adjust the settings about RxConfig 2011-07-05 9:44 ` [PATCH net-next 3/6] r8169: adjust the settings about RxConfig Hayes Wang @ 2011-07-05 18:55 ` Francois Romieu 0 siblings, 0 replies; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:55 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : [...] > diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c > index cdbbe47..3aeae68 100644 > --- a/drivers/net/r8169.c > +++ b/drivers/net/r8169.c > @@ -71,7 +71,7 @@ static const int multicast_filter_limit = 32; > > #define MAX_READ_REQUEST_SHIFT 12 > #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ > -#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ > +#define RX_DMA_BURST 7 /* Maximum PCI burst, '7' is Unlimited */ > #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ > #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ > #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ > @@ -272,9 +272,6 @@ enum rtl_registers { > IntrStatus = 0x3e, > TxConfig = 0x40, > RxConfig = 0x44, > - > -#define RTL_RX_CONFIG_MASK 0xff7e1880u > - Nit: could you remove RxCfgFIFOShift and add something like #define RXCFG_FIFO_SHIFT 13 /* No threshold before first PCI xfer. */ #define RXCFG_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) #define RXCFG_DMA_SHIFT 8 /* Unlimited maximum PCI burst. */ #define RXCFG_DMA_BURST (7 << RXCFG_DMA_SHIFT) (and move both RX128_INT_EN and RX_MULTI_EN near RxConfig in patch #1) -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next 4/6] r8169: add ERI functions 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang 2011-07-05 9:44 ` [PATCH net-next 2/6] r8169: modify the flow hw reset Hayes Wang 2011-07-05 9:44 ` [PATCH net-next 3/6] r8169: adjust the settings about RxConfig Hayes Wang @ 2011-07-05 9:44 ` Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E Hayes Wang ` (2 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Add the ERI functions which would be used by the new chips. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 3aeae68..fa2c139 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -1046,6 +1046,49 @@ static u32 rtl_csi_read(void __iomem *ioaddr, int addr) return value; } +static +void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) +{ + unsigned int i; + + BUG_ON((addr & 3) || (mask == 0)); + RTL_W32(ERIDR, val); + RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); + + for (i = 0; i < 100; i++) { + udelay(100); + if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) + break; + } +} + +static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) +{ + unsigned int i; + u32 value = ~0x00; + + RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); + + for (i = 0; i < 100; i++) { + udelay(100); + if (RTL_R32(ERIAR) & ERIAR_FLAG) { + value = RTL_R32(ERIDR); + break; + } + } + + return value; +} + +static void +rtl_eri_write_w0w1(void __iomem *ioaddr, int addr, u32 mask, u32 m, u32 p, int type) +{ + u32 val; + + val = rtl_eri_read(ioaddr, addr, type); + rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); +} + static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) { u8 value = 0xff; -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 4/6] r8169: add ERI functions 2011-07-05 9:44 ` [PATCH net-next 4/6] r8169: add ERI functions Hayes Wang @ 2011-07-05 18:55 ` Francois Romieu 0 siblings, 0 replies; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:55 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : [...] > @@ -1046,6 +1046,49 @@ static u32 rtl_csi_read(void __iomem *ioaddr, int addr) > return value; > } > > +static > +void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) > +{ > + unsigned int i; > + > + BUG_ON((addr & 3) || (mask == 0)); > + RTL_W32(ERIDR, val); > + RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); > + > + for (i = 0; i < 100; i++) { > + udelay(100); > + if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) > + break; I'd rather reverse those if possible : implicit posted write flushing read, then udelay. -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang ` (2 preceding siblings ...) 2011-07-05 9:44 ` [PATCH net-next 4/6] r8169: add ERI functions Hayes Wang @ 2011-07-05 9:44 ` Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 6/6] r8169: support RTL8111E-VL Hayes Wang 2011-07-05 18:53 ` [PATCH net-next 1/6] r8169: adjust some registers Francois Romieu 5 siblings, 1 reply; 13+ messages in thread From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Only 8111E needs enable RxConfig bit 0 ~ 3 when suspending or shutdowning when supporting wake on lan. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index fa2c139..01da16a 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -3266,8 +3266,10 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) rtl_writephy(tp, 0x1f, 0x0000); rtl_writephy(tp, MII_BMCR, 0x0000); - RTL_W32(RxConfig, RTL_R32(RxConfig) | - AcceptBroadcast | AcceptMulticast | AcceptMyPhys); + if (tp->mac_version == RTL_GIGA_MAC_VER_32 || + tp->mac_version == RTL_GIGA_MAC_VER_33) + RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | + AcceptMulticast | AcceptMyPhys); return; } -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E 2011-07-05 9:44 ` [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E Hayes Wang @ 2011-07-05 18:55 ` Francois Romieu 0 siblings, 0 replies; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:55 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : > Only 8111E needs enable RxConfig bit 0 ~ 3 when suspending or > shutdowning when supporting wake on lan. Nit: if it only applies to the non-VL 8111E, it could make sense to apply it after the 8168E-VL support patch and outline this fact in the comment. Your call. -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next 6/6] r8169: support RTL8111E-VL 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang ` (3 preceding siblings ...) 2011-07-05 9:44 ` [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E Hayes Wang @ 2011-07-05 9:44 ` Hayes Wang 2011-07-05 18:56 ` Francois Romieu 2011-07-05 18:53 ` [PATCH net-next 1/6] r8169: adjust some registers Francois Romieu 5 siblings, 1 reply; 13+ messages in thread From: Hayes Wang @ 2011-07-05 9:44 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Support RTL8111E-VL Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 188 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 181 insertions(+), 7 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 01da16a..bee9e49 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -41,6 +41,7 @@ #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" +#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" #ifdef RTL8169_DEBUG @@ -133,6 +134,7 @@ enum mac_version { RTL_GIGA_MAC_VER_31, RTL_GIGA_MAC_VER_32, RTL_GIGA_MAC_VER_33, + RTL_GIGA_MAC_VER_34, RTL_GIGA_MAC_NONE = 0xff, }; @@ -216,7 +218,9 @@ static const struct { [RTL_GIGA_MAC_VER_32] = _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1), [RTL_GIGA_MAC_VER_33] = - _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2) + _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2), + [RTL_GIGA_MAC_VER_34] = + _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3) }; #undef _R @@ -1151,6 +1155,39 @@ static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) rtl_writephy(tp, MII_BMCR, val & 0xffff); } +static void rtl_link_chg_patch(struct rtl8169_private *tp) +{ + void __iomem *ioaddr = tp->mmio_addr; + struct net_device *dev = tp->dev; + + if (!netif_running(dev)) + return; + + if (tp->mac_version == RTL_GIGA_MAC_VER_34) { + if (RTL_R8(PHYstatus) & _1000bpsF) { + rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, + 0x00000011, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, + 0x00000005, ERIAR_EXGMAC); + } else if (RTL_R8(PHYstatus) & _100bps) { + rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, + 0x0000001f, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, + 0x00000005, ERIAR_EXGMAC); + } else { + rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, + 0x0000001f, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, + 0x0000003f, ERIAR_EXGMAC); + } + /* Reset packet filter */ + rtl_eri_write_w0w1(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, + 0x00, ERIAR_EXGMAC); + rtl_eri_write_w0w1(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, + 0x01, ERIAR_EXGMAC); + } +} + static void __rtl8169_check_link_status(struct net_device *dev, struct rtl8169_private *tp, void __iomem *ioaddr, bool pm) @@ -1159,6 +1196,7 @@ static void __rtl8169_check_link_status(struct net_device *dev, spin_lock_irqsave(&tp->lock, flags); if (tp->link_ok(ioaddr)) { + rtl_link_chg_patch(tp); /* This is to cancel a scheduled suspend if there's one. */ if (pm) pm_request_resume(&tp->pci_dev->dev); @@ -1687,6 +1725,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, int mac_version; } mac_info[] = { /* 8168E family. */ + { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, @@ -2664,7 +2703,7 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) rtl_patchphy(tp, 0x0d, 1 << 5); } -static void rtl8168e_hw_phy_config(struct rtl8169_private *tp) +static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { /* Enable Delay cap */ @@ -2737,6 +2776,91 @@ static void rtl8168e_hw_phy_config(struct rtl8169_private *tp) rtl_writephy(tp, 0x0d, 0x0000); } +static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) +{ + static const struct phy_reg phy_reg_init[] = { + /* Enable Delay cap */ + { 0x1f, 0x0004 }, + { 0x1f, 0x0007 }, + { 0x1e, 0x00ac }, + { 0x18, 0x0006 }, + { 0x1f, 0x0002 }, + { 0x1f, 0x0000 }, + { 0x1f, 0x0000 }, + + /* Channel estimation fine tune */ + { 0x1f, 0x0003 }, + { 0x09, 0xa20f }, + { 0x1f, 0x0000 }, + { 0x1f, 0x0000 }, + + /* Green Setting */ + { 0x1f, 0x0005 }, + { 0x05, 0x8b5b }, + { 0x06, 0x9222 }, + { 0x05, 0x8b6d }, + { 0x06, 0x8000 }, + { 0x05, 0x8b76 }, + { 0x06, 0x8000 }, + { 0x1f, 0x0000 } + }; + + rtl_apply_firmware(tp); + + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + + /* For 4-corner performance improve */ + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b80); + rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); + + /* PHY auto speed down */ + rtl_writephy(tp, 0x1f, 0x0004); + rtl_writephy(tp, 0x1f, 0x0007); + rtl_writephy(tp, 0x1e, 0x002D); + rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); + + /* improve 10M EEE waveform */ + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b86); + rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); + + /* Improve 2-pair detection performance */ + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b85); + rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); + + /* EEE setting */ + rtl_eri_write_w0w1(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0003, + 0x0000, ERIAR_EXGMAC); + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b85); + rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); + rtl_writephy(tp, 0x1f, 0x0004); + rtl_writephy(tp, 0x1f, 0x0007); + rtl_writephy(tp, 0x1e, 0x0020); + rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_writephy(tp, 0x0d, 0x0007); + rtl_writephy(tp, 0x0e, 0x003c); + rtl_writephy(tp, 0x0d, 0x4007); + rtl_writephy(tp, 0x0e, 0x0000); + rtl_writephy(tp, 0x0d, 0x0000); + + /* Green feature */ + rtl_writephy(tp, 0x1f, 0x0003); + rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); + rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); + rtl_writephy(tp, 0x1f, 0x0000); +} + static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { @@ -2856,7 +2980,10 @@ static void rtl_hw_phy_config(struct net_device *dev) break; case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: - rtl8168e_hw_phy_config(tp); + rtl8168e_1_hw_phy_config(tp); + break; + case RTL_GIGA_MAC_VER_34: + rtl8168e_2_hw_phy_config(tp); break; default: @@ -3235,6 +3362,7 @@ static void r8168_phy_power_down(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_28: case RTL_GIGA_MAC_VER_31: rtl_writephy(tp, 0x0e, 0x0200); + case RTL_GIGA_MAC_VER_34: default: rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); break; @@ -3364,6 +3492,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_31: case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: + case RTL_GIGA_MAC_VER_34: ops->down = r8168_pll_power_down; ops->up = r8168_pll_power_up; break; @@ -3838,6 +3967,9 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) while (RTL_R8(TxPoll) & NPQ) udelay(20); + } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) { + while (!(RTL_R32(TxConfig) & TX_EMPTY)) + udelay(100); } else { RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); udelay(100); @@ -4245,9 +4377,9 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) rtl_enable_clock_request(pdev); } -static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) +static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) { - static const struct ephy_info e_info_8168e[] = { + static const struct ephy_info e_info_8168e_1[] = { { 0x00, 0x0200, 0x0100 }, { 0x00, 0x0000, 0x0004 }, { 0x06, 0x0002, 0x0001 }, @@ -4265,7 +4397,7 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) rtl_csi_access_enable_2(ioaddr); - rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e)); + rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -4280,6 +4412,45 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); } +static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) +{ + static const struct ephy_info e_info_8168e_2[] = { + { 0x09, 0x0000, 0x0080 }, + { 0x19, 0x0000, 0x0224 } + }; + + rtl_csi_access_enable_1(ioaddr); + + rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); + rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); + rtl_eri_write_w0w1(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x10, + ERIAR_EXGMAC); + rtl_eri_write_w0w1(ioaddr, 0xd4, ERIAR_MASK_0011, 0xff00, 0x0c00, + ERIAR_EXGMAC); + + RTL_W8(MaxTxPacketSize, 0x27); + + rtl_disable_clock_request(pdev); + + RTL_W32(TxConfig, RTL_R32(TxConfig) | AUTO_FIFO); + RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); + + /* Adjust EEE LED frequency */ + RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); + + RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); + RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); + RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); +} + static void rtl_hw_start_8168(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); @@ -4368,7 +4539,10 @@ static void rtl_hw_start_8168(struct net_device *dev) case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: - rtl_hw_start_8168e(ioaddr, pdev); + rtl_hw_start_8168e_1(ioaddr, pdev); + break; + case RTL_GIGA_MAC_VER_34: + rtl_hw_start_8168e_2(ioaddr, pdev); break; default: -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 6/6] r8169: support RTL8111E-VL 2011-07-05 9:44 ` [PATCH net-next 6/6] r8169: support RTL8111E-VL Hayes Wang @ 2011-07-05 18:56 ` Francois Romieu 0 siblings, 0 replies; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:56 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : [...] > + rtl_writephy(tp, 0x1e, 0x002D); ^^ 2d :o) Some rtl_eri_write probably deserve to be tabulated. It can wait though. -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 1/6] r8169: adjust some registers 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang ` (4 preceding siblings ...) 2011-07-05 9:44 ` [PATCH net-next 6/6] r8169: support RTL8111E-VL Hayes Wang @ 2011-07-05 18:53 ` Francois Romieu 5 siblings, 0 replies; 13+ messages in thread From: Francois Romieu @ 2011-07-05 18:53 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : > Define new registers and modify some existing ones. > > Signed-off-by: Hayes Wang <hayeswang@realtek.com> > --- > drivers/net/r8169.c | 30 +++++++++++++++++++++++------- > 1 files changed, 23 insertions(+), 7 deletions(-) > > diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c > index fbd6838..701ab6b 100644 > --- a/drivers/net/r8169.c > +++ b/drivers/net/r8169.c > @@ -327,7 +327,7 @@ enum rtl8168_8101_registers { > #define EPHYAR_REG_SHIFT 16 > #define EPHYAR_DATA_MASK 0xffff > DLLPR = 0xd0, > -#define PM_SWITCH (1 << 6) > +#define PFM_EN (1 << 6) > DBG_REG = 0xd1, > #define FIX_NAK_1 (1 << 4) > #define FIX_NAK_2 (1 << 3) > @@ -335,6 +335,7 @@ enum rtl8168_8101_registers { > MCU = 0xd3, > #define EN_NDP (1 << 3) > #define EN_OOB_RESET (1 << 2) > +#define NOW_IS_OOB (1 << 7) ^^^ there should be a tab, not a space. Nit : 3, 2, 7 is a bit surprizing. 7, 3, 2 ? @@ -345,18 +346,31 @@ enum rtl8168_8101_registers { }; enum rtl8168_registers { + LED_FREQ = 0x1a, + EEE_LED = 0x1b, + + /* TxConfig */ +#define AUTO_FIFO (1 << 7) +#define TX_EMPTY (1 << 11) Eventually move these close to the existing TxConfig register as : +#define TXCFG_AUTO_FIFO (1 << 7) /* 8168e (?) */ +#define TXCFG_EMPTY (1 << 11) /* 8168e (?) */ -- Ueimor ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2011-07-06 7:49 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-07-05 9:44 [PATCH net-next 1/6] r8169: adjust some registers Hayes Wang 2011-07-05 9:44 ` [PATCH net-next 2/6] r8169: modify the flow hw reset Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-06 7:48 ` hayeswang 2011-07-05 9:44 ` [PATCH net-next 3/6] r8169: adjust the settings about RxConfig Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 4/6] r8169: add ERI functions Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 5/6] r8169: fix wake on lan setting for 8111E Hayes Wang 2011-07-05 18:55 ` Francois Romieu 2011-07-05 9:44 ` [PATCH net-next 6/6] r8169: support RTL8111E-VL Hayes Wang 2011-07-05 18:56 ` Francois Romieu 2011-07-05 18:53 ` [PATCH net-next 1/6] r8169: adjust some registers Francois Romieu
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