[PATCH 1/4] drm/i915: disable turbo on ValleyView for now

[PATCH 1/4] drm/i915: disable turbo on ValleyView for now

[Jesse Barnes]

We'll probably need new init functions and will need to test it.

v2: fix impossible GEN6 && GEN7 condition, move to Daniel's new init function

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aee389c..58f4b02 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9541,7 +9541,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
@@ -9632,7 +9632,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_drps(dev);
-	if (IS_GEN6(dev) || IS_GEN7(dev))
+	if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
 		gen6_disable_rps(dev);
 
 	if (IS_IRONLAKE_M(dev))
-- 
1.7.4.1

[PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC

[Jesse Barnes]

When the PCH split occurred, we dropped support for separate hsync and
vsync disable in the VGA DAC.  So add a PCH specific DPMS function that
just uses the port enable bit for controlling DPMS states.

Before this fix, when anything other than a full DPMS off occurred,
the VGA port would be left enabled and scanning out while all the other
heads would turn off as expected.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |   42 ++++++++++++++++++++++++++++---------
 1 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 70b0f1a..bdaefff 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -55,18 +55,36 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
 			    struct intel_crt, base);
 }
 
-static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
+static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 temp, reg;
+	u32 temp;
 
-	if (HAS_PCH_SPLIT(dev))
-		reg = PCH_ADPA;
-	else
-		reg = ADPA;
+	temp = I915_READ(PCH_ADPA);
+	temp &= ~ADPA_DAC_ENABLE;
+
+	switch (mode) {
+	case DRM_MODE_DPMS_ON:
+		temp |= ADPA_DAC_ENABLE;
+		break;
+	case DRM_MODE_DPMS_STANDBY:
+	case DRM_MODE_DPMS_SUSPEND:
+	case DRM_MODE_DPMS_OFF:
+		/* Just leave port enable cleared */
+		break;
+	}
+
+	I915_WRITE(PCH_ADPA, temp);
+}
+
+static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 temp;
 
-	temp = I915_READ(reg);
+	temp = I915_READ(ADPA);
 	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 	temp &= ~ADPA_DAC_ENABLE;
 
@@ -85,7 +103,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
 		break;
 	}
 
-	I915_WRITE(reg, temp);
+	I915_WRITE(ADPA, temp);
 }
 
 static int intel_crt_mode_valid(struct drm_connector *connector,
@@ -516,8 +534,7 @@ static void intel_crt_reset(struct drm_connector *connector)
  * Routines for controlling stuff on the analog port
  */
 
-static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
-	.dpms = intel_crt_dpms,
+static struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
 	.mode_fixup = intel_crt_mode_fixup,
 	.prepare = intel_encoder_prepare,
 	.commit = intel_encoder_commit,
@@ -602,6 +619,11 @@ void intel_crt_init(struct drm_device *dev)
 		connector->interlace_allowed = 1;
 	connector->doublescan_allowed = 0;
 
+	if (HAS_PCH_SPLIT(dev))
+		intel_crt_helper_funcs.dpms = pch_crt_dpms;
+	else
+		intel_crt_helper_funcs.dpms = intel_crt_dpms;
+
 	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
-- 
1.7.4.1

[PATCH 3/4] drm/i915: allow PCH PWM override on IVB

[Jesse Barnes]

On IVB, there are two sets of panel backlight regs: one in the CPU and
one in the PCH.  The CPU ones aren't generally used, so on IVB make sure
we allow the PCH regs to actually control the backlight.

v2: remove unused pwm variable (Daniel)
    move to init_hw function so we override on resume too

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 58f4b02..33aaad3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9530,6 +9530,19 @@ static void i915_disable_vga(struct drm_device *dev)
 	POSTING_READ(vga_reg);
 }
 
+static void ivb_pch_pwm_override(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * IVB has CPU eDP backlight regs too, set things up to let the
+	 * PCH regs control the backlight
+	 */
+	I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
+	I915_WRITE(BLC_PWM_CPU_CTL, 0);
+	I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
+}
+
 void intel_modeset_init_hw(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9545,6 +9558,9 @@ void intel_modeset_init_hw(struct drm_device *dev)
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
+
+	if (IS_IVYBRIDGE(dev))
+		ivb_pch_pwm_override(dev);
 }
 
 void intel_modeset_init(struct drm_device *dev)
-- 
1.7.4.1

[PATCH 4/4] drm/i915: force CPU eDP onto pipe 3 on IVB

[Jesse Barnes]

This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 drivers/gpu/drm/i915/intel_dp.c      |    4 ++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..0b5f843 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6225,6 +6225,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 			   fp == I915_READ(PCH_FP0(1))) {
 			intel_crtc->use_pll_a = false;
 			DRM_DEBUG_KMS("using pipe b dpll\n");
+		} else if (is_cpu_edp) {
+			DRM_DEBUG_KMS("CPU eDP, no PCH PLL needed\n");
 		} else {
 			DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
 			return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6346b29..89b326f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2417,6 +2417,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 	}
 
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+
+	if (IS_IVYBRIDGE(dev) && output_reg == DP_A)
+		intel_encoder->crtc_mask = (1 << 2);
+
 	connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;
 
-- 
1.7.4.1

Re: [PATCH 4/4] drm/i915: force CPU eDP onto pipe 3 on IVB

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 308 bytes --]

On Wed, 11 Apr 2012 09:23:36 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.

Ignore this one, it's too ugly to live.  I'll put something better
together now...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC

[Daniel Vetter]

On Wed, Apr 11, 2012 at 09:23:34AM -0700, Jesse Barnes wrote:
> When the PCH split occurred, we dropped support for separate hsync and
> vsync disable in the VGA DAC.  So add a PCH specific DPMS function that
> just uses the port enable bit for controlling DPMS states.
> 
> Before this fix, when anything other than a full DPMS off occurred,
> the VGA port would be left enabled and scanning out while all the other
> heads would turn off as expected.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_crt.c |   42 ++++++++++++++++++++++++++++---------
>  1 files changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 70b0f1a..bdaefff 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -55,18 +55,36 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
>  			    struct intel_crt, base);
>  }
>  
> -static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
> +static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
>  {
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 temp, reg;
> +	u32 temp;
>  
> -	if (HAS_PCH_SPLIT(dev))
> -		reg = PCH_ADPA;
> -	else
> -		reg = ADPA;
> +	temp = I915_READ(PCH_ADPA);
> +	temp &= ~ADPA_DAC_ENABLE;
> +
> +	switch (mode) {
> +	case DRM_MODE_DPMS_ON:
> +		temp |= ADPA_DAC_ENABLE;
> +		break;
> +	case DRM_MODE_DPMS_STANDBY:
> +	case DRM_MODE_DPMS_SUSPEND:
> +	case DRM_MODE_DPMS_OFF:
> +		/* Just leave port enable cleared */
> +		break;
> +	}
> +
> +	I915_WRITE(PCH_ADPA, temp);
> +}
> +
> +static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
> +{
> +	struct drm_device *dev = encoder->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 temp;
>  
> -	temp = I915_READ(reg);
> +	temp = I915_READ(ADPA);
>  	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
>  	temp &= ~ADPA_DAC_ENABLE;
>  
> @@ -85,7 +103,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
>  		break;
>  	}
>  
> -	I915_WRITE(reg, temp);
> +	I915_WRITE(ADPA, temp);
>  }
>  
>  static int intel_crt_mode_valid(struct drm_connector *connector,
> @@ -516,8 +534,7 @@ static void intel_crt_reset(struct drm_connector *connector)
>   * Routines for controlling stuff on the analog port
>   */
>  
> -static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
> -	.dpms = intel_crt_dpms,
> +static struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
>  	.mode_fixup = intel_crt_mode_fixup,
>  	.prepare = intel_encoder_prepare,
>  	.commit = intel_encoder_commit,
> @@ -602,6 +619,11 @@ void intel_crt_init(struct drm_device *dev)
>  		connector->interlace_allowed = 1;
>  	connector->doublescan_allowed = 0;
>  
> +	if (HAS_PCH_SPLIT(dev))
> +		intel_crt_helper_funcs.dpms = pch_crt_dpms;
> +	else
> +		intel_crt_helper_funcs.dpms = intel_crt_dpms;

I like the clean split of this, but the static struct frobbing really
itches me. Can you either split up intel_crt_helper_funcs into a gmch and
pch_split version or add a dpms function pointer to struct intel_crt?

Patch 1&3 of this series are queued for -next, thanks.
-Daniel

> +
>  	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
>  	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
>  
> -- 
> 1.7.4.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC

[Jesse Barnes]

Like this?

>From fee9f6fbf2230f96b9195baf32fd67b243969a14 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed, 11 Apr 2012 09:23:34 -0700
Subject: [PATCH] drm/i915: IBX+ doesn't have separate vsync/hsync controls on
 the VGA DAC

When the PCH split occurred, we dropped support for separate hsync and
vsync disable in the VGA DAC.  So add a PCH specific DPMS function that
just uses the port enable bit for controlling DPMS states.

Before this fix, when anything other than a full DPMS off occurred,
the VGA port would be left enabled and scanning out while all the other
heads would turn off as expected.

v2: duplicate encoder helper vtable into pch and gmch versions (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |   54 ++++++++++++++++++++++++++++++-------
 1 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 70b0f1a..fb516e9 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -55,18 +55,36 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
 			    struct intel_crt, base);
 }
 
-static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
+static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 temp, reg;
+	u32 temp;
 
-	if (HAS_PCH_SPLIT(dev))
-		reg = PCH_ADPA;
-	else
-		reg = ADPA;
+	temp = I915_READ(PCH_ADPA);
+	temp &= ~ADPA_DAC_ENABLE;
+
+	switch (mode) {
+	case DRM_MODE_DPMS_ON:
+		temp |= ADPA_DAC_ENABLE;
+		break;
+	case DRM_MODE_DPMS_STANDBY:
+	case DRM_MODE_DPMS_SUSPEND:
+	case DRM_MODE_DPMS_OFF:
+		/* Just leave port enable cleared */
+		break;
+	}
+
+	I915_WRITE(PCH_ADPA, temp);
+}
 
-	temp = I915_READ(reg);
+static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 temp;
+
+	temp = I915_READ(ADPA);
 	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 	temp &= ~ADPA_DAC_ENABLE;
 
@@ -85,7 +103,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
 		break;
 	}
 
-	I915_WRITE(reg, temp);
+	I915_WRITE(ADPA, temp);
 }
 
 static int intel_crt_mode_valid(struct drm_connector *connector,
@@ -516,12 +534,20 @@ static void intel_crt_reset(struct drm_connector *connector)
  * Routines for controlling stuff on the analog port
  */
 
-static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
-	.dpms = intel_crt_dpms,
+static const struct drm_encoder_helper_funcs pch_encoder_funcs = {
+	.mode_fixup = intel_crt_mode_fixup,
+	.prepare = intel_encoder_prepare,
+	.commit = intel_encoder_commit,
+	.mode_set = intel_crt_mode_set,
+	.dpms = pch_crt_dpms,
+};
+
+static const struct drm_encoder_helper_funcs gmch_encoder_funcs = {
 	.mode_fixup = intel_crt_mode_fixup,
 	.prepare = intel_encoder_prepare,
 	.commit = intel_encoder_commit,
 	.mode_set = intel_crt_mode_set,
+	.dpms = intel_crt_dpms,
 };
 
 static const struct drm_connector_funcs intel_crt_connector_funcs = {
@@ -567,6 +593,7 @@ void intel_crt_init(struct drm_device *dev)
 	struct intel_crt *crt;
 	struct intel_connector *intel_connector;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	const struct drm_encoder_helper_funcs *encoder_helper_funcs;
 
 	/* Skip machines without VGA that falsely report hotplug events */
 	if (dmi_check_system(intel_no_crt))
@@ -602,7 +629,12 @@ void intel_crt_init(struct drm_device *dev)
 		connector->interlace_allowed = 1;
 	connector->doublescan_allowed = 0;
 
-	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
+	if (HAS_PCH_SPLIT(dev))
+		encoder_helper_funcs = &pch_encoder_funcs;
+	else
+		encoder_helper_funcs = &gmch_encoder_funcs;
+
+	drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs);
 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
 	drm_sysfs_connector_add(connector);
-- 
1.7.5.4

Re: [PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC

[Chris Wilson]

On Tue, 17 Apr 2012 15:06:33 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Like this?
> 
> From fee9f6fbf2230f96b9195baf32fd67b243969a14 Mon Sep 17 00:00:00 2001
> From: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed, 11 Apr 2012 09:23:34 -0700
> Subject: [PATCH] drm/i915: IBX+ doesn't have separate vsync/hsync controls on
>  the VGA DAC
> 
> When the PCH split occurred, we dropped support for separate hsync and
> vsync disable in the VGA DAC.  So add a PCH specific DPMS function that
> just uses the port enable bit for controlling DPMS states.
> 
> Before this fix, when anything other than a full DPMS off occurred,
> the VGA port would be left enabled and scanning out while all the other
> heads would turn off as expected.
> 
> v2: duplicate encoder helper vtable into pch and gmch versions (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

With s/intel_crt_dpms/gmch_crt_dpms/ and
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48491

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC

[Daniel Vetter]

On Tue, Apr 17, 2012 at 11:18:46PM +0100, Chris Wilson wrote:
> On Tue, 17 Apr 2012 15:06:33 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Like this?
> > 
> > From fee9f6fbf2230f96b9195baf32fd67b243969a14 Mon Sep 17 00:00:00 2001
> > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Date: Wed, 11 Apr 2012 09:23:34 -0700
> > Subject: [PATCH] drm/i915: IBX+ doesn't have separate vsync/hsync controls on
> >  the VGA DAC
> > 
> > When the PCH split occurred, we dropped support for separate hsync and
> > vsync disable in the VGA DAC.  So add a PCH specific DPMS function that
> > just uses the port enable bit for controlling DPMS states.
> > 
> > Before this fix, when anything other than a full DPMS off occurred,
> > the VGA port would be left enabled and scanning out while all the other
> > heads would turn off as expected.
> > 
> > v2: duplicate encoder helper vtable into pch and gmch versions (Daniel)
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> With s/intel_crt_dpms/gmch_crt_dpms/ and
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48491
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for next with the gmch_ color applied, thanks for the patch&review.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48